Chip package thermal failure prediction method based on digital twinning

Abstract

The application discloses a chip packaging thermal failure prediction method based on digital twinning, relates to the technical field of chip packaging, and comprises the following steps: analyzing a chip packaging design file, establishing a connection relationship of packaging thermal nodes and thermal paths, limiting a same-family packaging parameter range, generating a thermal path digital twinning initial body and a packaging parameter range table; expanding the thermal path digital twinning initial body by using the packaging parameter range table, constructing an initial packaging digital twinning body set, and forming a representative packaging digital twinning body through random orthogonal decomposition and Krylov dynamic modal filtering; performing heat transfer deduction from a junction to a heat dissipation boundary on the representative packaging digital twinning body, extracting a hot spot, an interlayer temperature difference, a solder joint thermal cycle and a main transfer path, and generating a packaging thermal field sequence. The application compares the temperature field inversion of the candidate failure unit with the position sequence, the expansion direction and the main transfer path of the thermal anomaly residual, so that the structural positioning capability and the result interpretability of the chip packaging thermal failure prediction are improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a method for predicting thermal failure in chip packaging based on digital twins. Background Technology

[0002] With the increasing integration of chips and the development of multi-chip packaging, heterogeneous integration, and 3D packaging technologies, the heat transfer paths in chip packaging structures have become more complex. Multi-level thermal coupling relationships exist between chip junctions, solder joint arrays, packaging substrates, molding layers, thermal interface materials, and heat dissipation structures. Current chip packaging thermal reliability analyses typically establish a thermal analysis object based on the packaging geometry, material thermal parameters, power consumption distribution, and heat dissipation boundary conditions. They then evaluate the temperature distribution, hotspot locations, interlayer temperature differences, and solder joint thermal cycling states of the packaging structure during operation through finite element simulation, thermal network calculations, temperature cycling tests, and power cycling tests, thereby providing a basis for packaging structure design and thermal reliability assessment.

[0003] However, existing thermal failure prediction methods mostly rely on hotspot temperatures, junction temperature margins, or overall temperature field changes as criteria. These methods typically only reflect areas of concentrated heat within the package structure and struggle to differentiate whether thermal anomalies are caused by localized overheating in the junction region, thermal fatigue at solder joints, material interface delamination, molding compound cracking, or degradation of the thermal interface material. Furthermore, conventional finite element method (FEM) simulations require calculating numerous combinations of package parameters individually, resulting in significant computational overhead. Additionally, the differences in thermal paths and heat propagation behaviors between different package designs are prone to repetition, making it difficult to accurately correlate prediction results with specific candidate failure elements and the order of failure. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a chip packaging thermal failure prediction method based on digital twins to solve the problem of difficulty in reverse locating the source of failure and the sequence of failures in chip packaging thermal anomalies.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: This invention provides a method for predicting thermal failure in chip packaging based on digital twins, comprising: Analyze the chip package design file, establish the connection relationship between package hot nodes and hot paths, limit the parameter range of the same package family, and generate the initial digital twin of hot paths and the package parameter range table; The initial thermal path digital twin is expanded using a package parameter range table to construct an initial package digital twin set. Representative package digital twins are then formed through random orthogonal decomposition and Krylov dynamic mode screening. Heat transfer from the junction region to the heat dissipation boundary is simulated for representative packaged digital twins, and hot spots, interlayer temperature difference, solder joint thermal cycle and main transfer path are extracted to generate packaged thermal field sequence; The thermal field sequence of the package is separated into the dominant thermal diffusion mode and the thermal anomaly residual, and the thermal anomaly residual is extrapolated along the time series to generate the thermal field interpretation result of the package. Candidate failure units in the thermal field interpretation results are located by identifying the thermal path connection relationship, the temperature field of the candidate failure units is inverted and compared with the thermal anomaly residual to generate thermal failure prediction results.

[0007] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the step of establishing the connection relationship between packaging hot nodes and hot paths specifically includes: Analyze the layout layer, package stack-up, power distribution, material properties and heat dissipation boundaries in the chip package design file, identify the spatial location of the package structure parts, and generate a package structure coordinate set; The package structure coordinate set is used to divide the junction nodes, interlayer nodes, solder joint nodes, interface nodes and heat dissipation nodes, and thermal parameters are added to each node to generate a package thermal node set. Connect the packaged thermal node set along the heat transfer direction from the chip junction region to the heat dissipation structure, and distinguish between the heat conduction path, contact path, solder joint path and heat dissipation path to generate thermal path connection relationship.

[0008] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the generation of the initial digital twin of the thermal path and the packaging parameter range table specifically includes, The hot node set, hot path connection relationship and hot parameters of each node are mapped to the coordinate set of the package structure to generate the initial digital twin of the hot path. Select parameters of family-packaged chips that have passed reliability verification, and remove parameter records that do not meet the package design rules to obtain a valid family-packaged parameter set; The effective family of package parameters is divided according to the package level, solder joint structure, material system and heat dissipation path, and the boundary values ​​and commonly used value sequences of each type of parameter are extracted to generate a package parameter range table.

[0009] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the construction of the initial package digital twin set specifically includes, Extract the packaging layer thickness, solder joint geometry, thermal interface material parameters, and heat dissipation path parameters from the packaging parameter range table, and match each type of parameter to the interlayer node, solder joint node, interface node, and heat dissipation node in the initial thermal path digital twin to obtain the parameter replacement list. According to the parameter replacement list, multiple sets of parameters are replaced in the initial digital twin of the thermal path to maintain the consistency of chip junction power consumption, material hierarchy relationship and heat dissipation boundary, generate multiple package digital twins, and mark the parameter source, node change position and thermal path change position of each package digital twin to form an initial package digital twin set.

[0010] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the random orthogonal decomposition specifically includes: The thermal path difference matrix is ​​obtained by extracting the changes in package layer thickness, solder joint array, thermal interface material, and heat dissipation path from the initial package digital twin set; Random sampling and orthogonal decomposition of the thermal path difference matrix are performed to extract non-overlapping thermal path difference directions, resulting in an orthogonal feature set; The repetitive hot path changes in the initial encapsulated digital twin set are compressed according to the orthogonal feature set to form a representative space.

[0011] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the random orthogonal decomposition specifically includes: The thermal path difference matrix is ​​obtained by extracting the changes in package layer thickness, solder joint array, thermal interface material, and heat dissipation path from the initial package digital twin set; Random sampling and orthogonal decomposition of the thermal path difference matrix are performed to extract non-overlapping thermal path difference directions, resulting in an orthogonal feature set; The repetitive hot path changes in the initial encapsulated digital twin set are compressed according to the orthogonal feature set to form a representative space.

[0012] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the generation of the packaging thermal field sequence specifically includes: Chip junction power consumption and heat dissipation boundary conditions are applied to a representative packaged digital twin, and the temperature changes of each packaged thermal node are calculated along the thermal path connection relationship to obtain the node temperature timing. Extract the highest temperature node, the highest temperature moment, the temperature difference between adjacent layers, the periodic temperature fluctuation of the solder joint, and the dominant flow direction from the junction to the heat dissipation node from the node temperature time series to obtain hot spots, interlayer temperature difference, solder joint thermal cycle, and main transfer path. The hot spots, interlayer temperature difference, solder joint thermal cycle and main transfer path are arranged in time slice order to generate the package thermal field sequence.

[0013] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the generation of packaging thermal field interpretation results specifically includes: The encapsulated thermal field sequence is arranged into a thermal field matrix in chronological order, and the temperature diffusion pattern that appears stably in the long term is extracted to obtain the dominant thermal diffusion mode. By subtracting the dominant thermal diffusion mode from the thermal field matrix, separating the local high temperature region, the interlayer temperature difference abrupt change region, and the solder joint thermal cycle concentration region, the thermal anomaly residual is obtained. The spatial position change of the thermal anomaly residual is tracked along the continuous time slice, and the residual expansion direction, residual expansion rate, and residual persistence region are extracted to obtain the future thermal field evolution sequence. The normal heat transfer baseline, abnormal heat source location, and abnormal expansion trend are defined by the dominant heat diffusion mode, thermal anomaly residual, and future thermal field evolution sequence, respectively, to generate the encapsulated thermal field interpretation results.

[0014] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the method for locating candidate failure units in the packaging thermal field interpretation results specifically includes: Map the thermal anomaly residuals in the thermal field interpretation results to the thermal path connection relationship to determine the thermal node, adjacent thermal path and physical location of the thermal anomaly residuals in the package; When the thermal anomaly residual remains in the chip junction region, the chip junction region candidate failure unit is determined; when the thermal anomaly residual appears repeatedly along the solder joint array, the solder joint candidate failure unit is determined; when the thermal anomaly residual is concentrated at the material interface, the interface candidate failure unit is determined. When the thermal anomaly residual extends from the edge of the molding layer, candidate failure elements of the molding layer are determined. When the thermal anomaly residual is located in the thermal interface material and changes the main transmission path, candidate failure elements of the thermal interface material are determined. Combine each candidate failure element with its corresponding thermal anomaly residual to generate a list of candidate failure elements.

[0015] As a preferred embodiment of the chip packaging thermal failure prediction method based on digital twins described in this invention, the generation of thermal failure prediction results specifically includes: Extract the power consumption map, material thermal conductivity distribution, heat dissipation boundary conditions, heat transfer coefficient distribution and thermal path connection relationship corresponding to the candidate failure units in the candidate failure unit list, and generate the candidate failure unit inversion condition set; The temperature field response caused by the candidate failure element is reconstructed by the inversion condition set of the candidate failure element, and the inversion temperature field is obtained. The inversion hot spot location, the inversion interlayer temperature difference distribution and the inversion heat main transfer path are extracted from the inversion temperature field to obtain the inversion thermal response characteristics. By comparing the positional order, expansion direction, and main propagation path of the inverted thermal response characteristics with the thermal anomaly residuals, the positional consistency results, directional consistency results, and path consistency results are obtained. When the location consistency result, direction consistency result, and path consistency result all point to the same candidate failure unit, it is determined as the failure source unit; When the failure source unit corresponds to the chip junction region, solder joint array, material interface, molding layer edge and thermal interface material, the local overheating type, solder joint thermal fatigue type, interface delamination type, molding layer thermal cracking type and thermal interface material degradation type are determined respectively. Based on the earliest occurrence location of the thermal anomaly residual, the earliest pointing location of the inverted temperature field, and the thermal path location of the failure source unit, the order of each failure type is arranged to generate thermal failure prediction results.

[0016] The beneficial effects of this invention are as follows: By analyzing chip packaging design documents to establish the connection relationship between packaging thermal nodes and thermal paths, the chip junction region, interlayer structure, solder joints, material interfaces, and heat dissipation structure are all incorporated into the same initial digital twin of the thermal path. This enables thermal failure prediction to move beyond judging the overall temperature field and instead provides a basis for tracing the source of failure along the thermal path. Expanding the initial digital twin of the thermal path through the packaging parameter range table and using random orthogonal decomposition and Krylov dynamic mode to screen representative packaging digital twins can reduce repeated thermal path changes and repeated heat propagation behaviors, avoiding inefficient traversal of all packaging parameter combinations. By performing heat transfer deduction on representative packaging digital twins, the heat transfer process from the chip junction region to the heat dissipation boundary can be fully characterized. By separating the dominant heat diffusion mode and thermal anomaly residuals, normal heat transfer benchmarks can be distinguished from local thermal anomalies. By inverting the temperature field of candidate failure units and comparing it with the positional order, expansion direction, and main transmission path of thermal anomaly residuals, the failure type and failure sequence of the failure source unit can be determined, thereby improving the structural localization capability and interpretability of chip packaging thermal failure prediction. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Fig. 1 This is a flowchart of a chip packaging thermal failure prediction method based on digital twins.

[0019] Fig. 2 This is a schematic diagram illustrating the initial construction and encapsulation parameter mapping of the hot path digital twin.

[0020] Fig. 3 This is a schematic diagram of the selection of representative packaged digital twins and the generation of packaged thermal field sequences.

[0021] Fig. 4 This is a schematic diagram for interpreting thermal anomaly residuals and predicting candidate failure elements. Detailed Implementation

[0022] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0024] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0025] Reference Figs. 1-4 This is one embodiment of the present invention, which provides a chip packaging thermal failure prediction method based on digital twins, including the following steps: S1. Parse the chip package design file, establish the connection relationship between package hot nodes and hot paths, limit the parameter range of the same package family, and generate the initial digital twin of hot paths and the package parameter range table.

[0026] S1.1. Parse the layout file, package stack-up file, chip power consumption file, material parameter file, and thermal boundary file of the chip package to be predicted.

[0027] The layout file is a GDSII format file exported during the chip packaging layout design stage, used to record the planar coordinates of the chip junction region, the back of the chip, and the package interconnect area; the package stack-up file is a stack-up structure table formed during the package substrate design stage, used to record the layer order and thickness of the adhesive layer, redistribution layer, solder joint, package substrate, molding layer, thermal interface material, and heat dissipation structure; the chip power consumption file is a power consumption map obtained from chip power consumption analysis, used to record the power consumption distribution of the chip junction region on the planar coordinates; the material parameter file is a material thermal parameter file recorded in the package material specification and bill of materials, used to record thermal conductivity, heat capacity, and density; and the heat dissipation boundary file is a thermal design condition file, used to record the ambient temperature, heat transfer method, and boundary heat transfer parameters of the outer surface of the heat dissipation structure.

[0028] Extract the planar coordinate range of the chip junction area and the back of the chip from the layout file. Extract the layer order and thickness of the adhesive layer, redistribution layer, solder joint, packaging substrate, molding layer, thermal interface material and heat dissipation structure from the package stack-up file. Extract the power consumption distribution of the chip junction area from the chip power consumption file. Extract the thermal conductivity, heat capacity and density from the material parameter file. Extract the boundary heat transfer parameters of the outer surface of the heat dissipation structure from the heat dissipation boundary file. Unify the above contents to the same three-dimensional coordinate reference according to the coordinate origin and stack-up direction in the chip package design file to generate the package structure coordinate set.

[0029] The package structure is divided into junction nodes, interlayer nodes, solder joint nodes, interface nodes, and heat dissipation nodes according to the coordinate set. Junction nodes correspond to the power consumption distribution position of the chip junction region, interlayer nodes correspond to the layer center position of the back of the chip, the bonding layer, the redistribution layer, the package substrate, and the molding layer, solder joint nodes correspond to the center position of the solder joint array, interface nodes correspond to the contact surface position of different materials, and heat dissipation nodes correspond to the external heat transfer position of the thermal interface material and the heat dissipation structure. Power consumption and heat capacity are added to junction nodes, thickness, thermal conductivity, heat capacity and density are added to interlayer nodes, solder joint height, solder joint diameter, thermal conductivity and heat capacity are added to solder joint nodes, contact position and contact material properties are added to interface nodes, and heat dissipation boundary parameters are added to heat dissipation nodes to generate a package thermal node set.

[0030] S1.2. Connect the packaged thermal node set along the heat transfer direction from the chip junction region to the heat dissipation structure. Determine the connection between adjacent packaged thermal nodes within the same material as the heat conduction path, the connection between packaged thermal nodes on both sides of the contact surface of different materials as the contact path, the connection between the chip junction region and the packaged substrate through the solder joint node as the solder joint path, and the connection between the heat dissipation node and the outer surface of the heat dissipation structure as the heat dissipation path. Record the starting packaged thermal node, ending packaged thermal node, path length, heat transfer area, and corresponding material thermal conductivity for the heat conduction path, contact path, and solder joint path, respectively, and generate the thermal path connection relationship.

[0031] For the heat conduction path and solder joint path, the path thermal resistance is calculated using the thermal resistance expression derived from Fourier's law of heat conduction under steady-state one-dimensional heat transfer conditions. Fourier's law of heat conduction states that heat flow is directly proportional to thermal conductivity, heat transfer area, and temperature difference, and inversely proportional to heat transfer length. After defining the ratio of temperature difference to heat flow as thermal resistance, the path thermal resistance of the heat conduction path and solder joint path is obtained, expressed as: ; in, Indicates the first The packaged hot node to the first Path thermal resistance between each packaged thermal node; Indicates the first The packaged hot node to the first Path length between each encapsulated thermal node along the heat transfer direction; Indicates the first The packaged hot node to the first Thermal conductivity of the material between each encapsulated thermal node; Indicates the first The packaged hot node to the first The heat transfer area between each encapsulated thermal node perpendicular to the heat transfer direction.

[0032] S1.3. Map the package hot node set, hot path connection relationships, thermal parameters of each node, and path thermal resistance to the package structure coordinate set, so that each package hot node has spatial location, material properties, and thermal parameters, and each hot path has connection objects, path type, and path thermal resistance, generating an initial digital twin of the hot path. The initial digital twin of the hot path retains the geometric hierarchy and heat transfer relationships of the chip package structure, and can serve as the structural parent of subsequent initial package digital twin sets.

[0033] Select package thickness, solder joint size, material thermal conductivity, thermal interface material thickness, and heat dissipation structure size from chip family packages that have passed reliability verification. Reliability verification includes verification results showing no failures under temperature cycling, power cycling, and high-temperature operating conditions. Remove parameter records that violate package design rules, which include consistent package layer order, solder joint size falling within the allowable range of the package process, material thermal conductivity consistent with the material parameter file, thermal interface material thickness meeting mounting requirements, and heat dissipation structure size meeting chip package outline limitations, to obtain an effective set of package family parameters.

[0034] It should be noted that the allowable range of the packaging process is obtained from the packaging process card, packaging design rules and reliability verification records of the same packaged chip. The allowable range of solder joint spacing is 0.40mm to 1.00mm, the allowable range of solder joint diameter is 0.20mm to 0.60mm, the allowable range of package layer thickness is 0.05mm to 1.20mm, the allowable range of thermal interface material thickness is 0.02mm to 0.20mm, and the allowable range of heat dissipation structure thickness is 0.50mm to 3.00mm. The thermal conductivity of the material does not adopt a fixed allowable range. The thermal conductivity of the material is based on the measured value of the corresponding material in the material parameter file or the nominal value in the specification.

[0035] Effective family-based package parameter sets are divided according to package level, solder joint structure, material system, and heat dissipation path. Specifically, the thickness of the chip back, adhesive layer, redistribution layer, package substrate, and molding compound are classified into the package level category; the solder joint spacing, solder joint diameter, and solder joint height are classified into the solder joint structure category; the thermal conductivity of the adhesive layer, redistribution layer, solder joint, package substrate, molding compound, thermal interface material, and heat dissipation structure are classified into the material system category; and the thermal interface material thickness, heat dissipation structure thickness, and heat dissipation boundary dimensions are classified into the heat dissipation path category. Boundary values ​​and commonly used value sequences for package thickness, solder joint size, material thermal conductivity, thermal interface material thickness, and heat dissipation structure dimensions are extracted respectively.

[0036] Among them, the boundary values ​​are the minimum and maximum values ​​of the same type of parameter in the effective family package parameter set; the commonly used value sequence is the top 3 values ​​that appear in the effective family package parameter set in descending order of frequency. When the same type of parameter is a continuous value, it is first merged into a value segment according to the packaging process tolerance, and then the center value of the top 3 value segments with the largest number of samples is taken as the commonly used value sequence; the package thickness boundary values ​​are 0.05mm and 1.20mm, the solder joint size boundary values ​​are 0.20mm and 1.00mm, the thermal interface material thickness boundary values ​​are 0.02mm and 0.20mm, and the heat dissipation structure thickness boundary values ​​are 0.50mm and 3.00mm, generating a package parameter range table; each type of parameter in the package parameter range table corresponds to the interlayer node, solder joint node, interface node, or heat dissipation node in the initial digital twin of the thermal path.

[0037] S2. The initial thermal path digital twin is expanded using the encapsulation parameter range table to construct an initial set of encapsulated digital twins. Representative encapsulated digital twins are then formed through random orthogonal decomposition and Krylov dynamic mode screening.

[0038] S2.1. Extract the package layer thickness, solder joint geometry, thermal interface material parameters, and heat dissipation path parameters from the package parameter range table. The package layer thickness includes the thickness values ​​of the chip back side, adhesive layer, redistribution layer, package substrate, and molding compound layer; the solder joint geometry includes the solder joint spacing, solder joint diameter, and solder joint height values; the thermal interface material parameters include the thermal interface material thickness and thermal conductivity values; the heat dissipation path parameters include the heat dissipation structure thickness, heat dissipation boundary dimensions, and heat dissipation structure thermal conductivity values.

[0039] The encapsulation layer thickness is matched to the interlayer nodes in the initial digital twin of the thermal path, the solder joint geometry is matched to the solder joint nodes, the thermal interface material parameters are matched to the interface nodes, and the heat dissipation path parameters are matched to the heat dissipation nodes, resulting in a parameter replacement list. Each record in the parameter replacement list includes the parameter category, parameter name, value source, replacement node, and affected thermal path, enabling the encapsulation parameter range table to directly apply to the initial digital twin of the thermal path.

[0040] S2.2. Perform multiple sets of parameter replacements on the initial digital twin of the thermal path according to the parameter replacement list. Each set of parameter replacements maintains consistency in chip junction power consumption, material layer relationships, and heat dissipation boundaries, only changing the package layer thickness, solder joint geometry, thermal interface material parameters, and heat dissipation path parameters, so that the differences between digital twins of different packages come from the package parameter range table rather than from changes in external operating conditions.

[0041] For each set of initial thermal path digital twins after parameter replacement, the spatial location of affected package hot nodes, the path length of affected thermal paths, the heat transfer area, and the path thermal resistance are recalculated, generating multiple package digital twins. Each package digital twin is labeled with the parameter source, node change location, and thermal path change location, forming an initial set of package digital twins. This initial set of package digital twins covers the parameter range of the same package family while maintaining comparable chip junction power consumption and heat dissipation boundaries, avoiding misinterpreting differences in operating conditions as differences in package structure.

[0042] S2.3. Extract the package layer thickness variation, solder joint array variation, thermal interface material variation, and heat dissipation path variation from the initial package digital twin set to obtain the thermal path difference matrix. The package layer thickness variation is determined by the thickness variation of interlayer nodes and the corresponding thermal path length variation; the solder joint array variation is determined by the spacing, diameter, and height of solder joint nodes and the corresponding thermal resistance variation of solder joint paths; the thermal interface material variation is determined by the thickness and thermal conductivity variation of interface nodes and the corresponding contact path variation; the heat dissipation path variation is determined by the thickness of the heat dissipation structure of the heat dissipation node, the heat dissipation boundary size, and the thermal resistance variation of the heat dissipation path. Each row of the thermal path difference matrix corresponds to a package digital twin, and each column corresponds to a thermal path variation. The thermal path difference matrix is ​​used as the processing object for random orthogonal decomposition.

[0043] Before randomly sampling the thermal path difference matrix, the boundary values ​​in the package parameter range table are used to make each column of the thermal path difference matrix dimensionless, so that the changes in package layer thickness, solder joint array, thermal interface material and heat dissipation path are on the same numerical scale. The dimensionless thermal path difference matrix retains the thermal path change order of each package digital twin, which serves as the source of the random sampling matrix.

[0044] Random sampling first retains sample rows containing minimum boundary values, maximum boundary values, and commonly used value sequences. Then, supplementary sample rows are randomly selected from the remaining sample rows until the sample rows in the sampling matrix cover the changes in package level class, solder joint structure class, material system class, and heat dissipation path class, and the number of rows in the sampling matrix is ​​not less than the number of columns in the thermal path difference matrix. The random sampling process records the extraction sequence number, parameter source, and corresponding package digital twin number of each sample row to obtain the sampling matrix.

[0045] When performing orthogonal decomposition on the sampling matrix, the heat path change columns are processed sequentially according to the column order of the sampling matrix. First, the current heat path change column is projected and subtracted from the already retained orthogonal directions. Then, the remaining directions after projection subtraction are used as the new heat path difference directions. When the current heat path change column can be represented by the already retained orthogonal directions, the current heat path change column is no longer retained. When the current heat path change column cannot be represented by the already retained orthogonal directions, the remaining directions corresponding to the current heat path change column are retained, thus obtaining the orthogonal feature set.

[0046] The different thermal path difference directions in the orthogonal feature set correspond to thermal transfer differences dominated by changes in package layer thickness, changes in solder joint array, changes in thermal interface material, and changes in heat dissipation path, respectively. By compressing repetitive thermal path changes in the initial package digital twin set using the orthogonal feature set, a representative space is formed, which can retain the main directions of thermal path changes and reduce repetitive package digital twins.

[0047] S2.4. Establish a heat transfer state sequence for each packaged digital twin in the representative space. The heat transfer state sequence is arranged according to the heat transfer direction from the chip junction to the heat dissipation structure, and includes the junction temperature rise response, interlayer heat transfer response, solder joint thermal cycling response, and heat dissipation boundary response. The junction temperature rise response is determined by the junction node power consumption and junction node heat capacity; the interlayer heat transfer response is determined by the interlayer node temperature change and the thermal resistance of the heat conduction path; the solder joint thermal cycling response is determined by the temperature fluctuation of the solder joint node within a continuous power cycle; and the heat dissipation boundary response is determined by the heat dissipation node temperature change and boundary heat transfer parameters. The heat transfer state sequence, as the processing object of Krylov dynamic mode screening, can reflect the dynamic differences of each packaged digital twin in the heat transfer evolution.

[0048] When using Krylov subspace to characterize the evolution direction of the heat transfer state sequence, the first time slice of the heat transfer state sequence is used as the initial state vector, and candidate direction vectors are generated sequentially according to the state progression relationship between consecutive time slices. For each candidate direction vector generated, the candidate direction vector is orthogonalized with the already retained direction vectors, and the remaining directions that cannot be represented by the already retained direction vectors are retained, thus obtaining the Krylov direction set.

[0049] The heat transfer state sequence of each packaged digital twin is projected onto a set of Krylov directions. The response amplitude of each Krylov direction in all time slices is counted, and the Krylov direction with the largest response amplitude is selected as the dominant thermal response direction. The packaged hot node with the largest response amplitude is located along the dominant thermal response direction to obtain the propagation position of the dominant thermal response. The expansion direction of the dominant thermal response is obtained according to the movement order of the packaged hot node with the largest response amplitude in adjacent time slices. The duration of the dominant thermal response is obtained according to the start time slice and end time slice of the continuous occurrence of the dominant thermal response.

[0050] For any two packaged digital twins, when the dominant thermal responses have the same propagation location, the same direction of expansion, and the same or adjacent duration, the packaged digital twin with greater differences in thermal paths is retained, and packaged digital twins with duplicate thermal propagation behaviors are deleted. When the dominant thermal responses correspond to different thermal path connections or different packaged thermal nodes, the corresponding packaged digital twins are retained. After Krylov dynamic modal screening, representative packaged digital twins are formed, ensuring that the representative packaged digital twins both come from the packaged parameter range table and can reflect different thermal propagation behaviors.

[0051] S3. Perform heat transfer simulation from junction region to heat dissipation boundary on representative packaged digital twins, extract hot spots, interlayer temperature difference, solder joint thermal cycle and main transfer path, and generate packaged thermal field sequence.

[0052] S3.1. Maintain consistency in the package hot nodes, hot path connection relationships, path thermal resistance, chip junction power consumption, material hierarchy relationships, and heat dissipation boundary conditions in the representative package digital twin; map the chip junction power consumption to the junction node, map the heat dissipation boundary conditions to the heat dissipation node, and map the path thermal resistance to the heat conduction path, contact path, solder joint path, and heat dissipation path between adjacent package hot nodes to form a heat transfer simulation object.

[0053] Based on the power time slices in the chip power consumption file, chip junction power consumption and heat dissipation boundary conditions are applied to the heat transfer simulation object. Temperature changes at junction nodes, interlayer nodes, solder joint nodes, interface nodes, and heat dissipation nodes are calculated along the thermal path connections to obtain the node temperature timing sequence. Each record in the node temperature timing sequence includes a time slice, package hot node number, package hot node spatial location, package hot node temperature, and adjacent thermal path number.

[0054] When calculating the temperature change of the packaged hot node, the transient energy conservation relationship of the thermal network is adopted. This relationship is derived from the path thermal resistance obtained by Fourier's law of heat conduction and the thermal capacity of the packaged hot node, and is used to describe the temperature change of the packaged hot node between adjacent time slices. The expression is: ; in, Indicates the first The thermal capacity of each packaged thermal node; Indicates the first Each packaged hot node in time slice Temperature; Indicates the first Each packaged hot node in the next time slice Temperature; Indicates the time interval between adjacent time slices; Indicates the first Each packaged hot node in time slice The power consumption of the chip junction region; Indicates the relationship with the first The adjacent hot node of the first encapsulation Each packaged hot node in time slice Temperature; Indicates the first The packaged hot node to the first Path thermal resistance between each packaged thermal node; Indicates the relationship with the first The number of packaged hot nodes connected to each packaged hot node.

[0055] S3.2. Based on the node temperature time sequence, hot spots and interlayer temperature differences are extracted. First, the temperatures of all packaged hot nodes are compared within each time slice. The packaged hot node with the highest temperature is selected as the highest temperature node, and its spatial location and corresponding time slice are recorded to obtain the hot spot location and temperature. Then, according to the hierarchical order of the packaged structure coordinate set, the temperature difference between adjacent interlayer nodes within the same time slice is taken as the adjacent interlayer temperature difference value to obtain the interlayer temperature difference. Hot spots and interlayer temperature differences reflect the location of local temperature concentration and the location of heat transfer obstruction between adjacent packaged layers, respectively, which can provide a clearly located temperature basis for subsequent thermal anomaly residual separation.

[0056] Solder joint thermal cycling is extracted based on node temperature timing. Following the continuous power cycles in the chip power consumption file, the highest temperature, lowest temperature, heating period, and cooling period of each solder joint node within the same continuous power cycle are recorded. The difference between the highest and lowest temperatures is used as the periodic temperature fluctuation of the solder joint node, thus obtaining the solder joint thermal cycle. The solder joint thermal cycle originates from the temperature fluctuations of the solder joint node as the chip junction power consumption cycle changes, reflecting the thermal fatigue-driven characteristics of the solder joint path during power loading and unloading.

[0057] S3.3. Extract the main transfer path based on node temperature time series and path thermal resistance. Calculate the heat flow between adjacent packaged hot nodes within each time slice, and arrange the thermal paths in descending order of absolute heat flow value. Select the thermal path chain that runs continuously from the junction node to the heat dissipation node with the same heat flow direction as the dominant flow direction from the junction to the heat dissipation node, thus obtaining the main transfer path.

[0058] The expression for heat flow is derived from the definition of path thermal resistance, and the expression is: in, Indicates the first The packaged hot node to the first The time slice between each packaged hot node Heat flow.

[0059] By arranging hotspots, interlayer temperature differences, solder joint thermal cycles, and main heat transfer paths in time slice order, a package thermal field sequence is generated. The package thermal field sequence retains the temperature concentration, interlayer heat transfer, solder joint periodic temperature fluctuations, and dominant heat flow direction of the representative packaged digital twin during the heat transfer process from the junction region to the heat dissipation boundary.

[0060] S4. Separate the packaged thermal field sequence into the dominant thermal diffusion mode and the thermal anomaly residual, and extrapolate the thermal anomaly residual along the time series to generate the packaged thermal field interpretation result.

[0061] S4.1. Extract the node temperature timing, hotspot location, hotspot temperature, interlayer temperature difference, solder joint thermal cycling, and main heat transfer path from the package thermal field sequence, and arrange the node temperature timing according to the time slice order; using the package hot node number as the row index and the time slice as the column index, fill in the temperature of each package hot node in the corresponding position for each time slice to form a thermal field matrix. Each column in the thermal field matrix represents the package thermal field distribution within a time slice, and each row in the thermal field matrix represents the temperature trajectory of a package hot node over time. The thermal field matrix preserves the heat transfer process from the chip junction region to the heat dissipation boundary of the representative package digital twin.

[0062] Orthogonal decomposition of the thermal field matrix is ​​performed to extract the long-term stable temperature diffusion pattern, yielding the dominant thermal diffusion mode. Orthogonal decomposition originates from the orthogonal projection method in linear algebra, which separates long-term temperature variation components along a fixed spatial direction from short-term local variation components in the thermal field matrix. In this embodiment, the spatial orthogonal direction with the largest projection amplitude is selected along the main propagation path from the chip junction region to the heat dissipation boundary. This spatial orthogonal direction is then normalized, and the thermal field matrix is ​​projected onto the normalized spatial orthogonal direction to obtain the dominant thermal diffusion mode, expressed as: ; in, This represents the thermal field matrix, where the matrix elements are the temperatures of the encapsulated thermal nodes. This represents the spatial orthogonal direction obtained by orthogonal decomposition of the thermal field matrix, used to represent the temperature diffusion direction that occurs stably and long-term along the chip junction region to the heat dissipation boundary. express Transpose of; This represents the dominant thermal diffusion mode, with the matrix elements being the dominant temperature components.

[0063] S4.2. Subtract the dominant thermal diffusion mode from the thermal field matrix, separate the temperature components that deviate from the normal heat transfer reference, and obtain the thermal anomaly residual.

[0064] The thermal anomaly residual is obtained using matrix differencing, and its expression is: ; in, This represents the thermal anomaly residual, where the matrix elements are the temperature deviations of the encapsulated thermal nodes relative to the dominant thermal diffusion mode. This represents the thermal field matrix.

[0065] The thermal field matrix has the same packaged thermal node row index and time slice column index as the dominant thermal diffusion mode. The thermal anomaly residual after matrix difference still corresponds one-to-one with the spatial position and time slice of the packaged thermal node, which can locate local high temperature areas, interlayer temperature difference abrupt change areas and solder joint thermal cycle concentration areas.

[0066] The location of abnormal heat sources is extracted based on thermal anomaly residuals, interlayer temperature differences, and solder joint thermal cycling. First, the packaged hot node with the largest thermal anomaly residual value is located within each time slice to determine the local high-temperature zone. Then, the changes in the difference of the thermal anomaly residuals corresponding to adjacent interlayer nodes are compared to determine the interlayer temperature difference abrupt change zone. Finally, the fluctuation amplitude of the thermal anomaly residuals at the solder joint nodes is compared within continuous power cycles to determine the solder joint thermal cycling concentration zone. The local high-temperature zone, the interlayer temperature difference abrupt change zone, and the solder joint thermal cycling concentration zone together constitute the spatial distribution of the thermal anomaly residuals, enabling the distinction between the normal diffused thermal field and the local abnormal thermal field.

[0067] S4.3. Track the spatial location changes of thermal anomaly residuals along consecutive time slices, and extract the residual propagation direction, residual propagation rate, and residual persistence region. The residual propagation direction is determined according to the movement order of the thermal node encapsulated by the maximum value of the thermal anomaly residual in adjacent time slices; the residual persistence region is determined according to the range of encapsulated thermal nodes where the thermal anomaly residual repeatedly appears in consecutive time slices. The residual propagation rate is calculated based on the spatial distance and time interval between the thermal nodes encapsulated by the maximum value of the thermal anomaly residual in adjacent time slices, and the expression is: ; in, Indicates time slice Time slice The residual expansion rate between; Indicates time slice Maximum residual value of thermal anomaly encapsulated hot node and time slice The maximum residual value of thermal anomalies encapsulates the spatial distance between thermal nodes; This indicates the time interval between adjacent time slices.

[0068] The temporal evolution trajectories of thermal anomaly residuals are arranged according to their propagation direction, propagation rate, and duration to obtain the future thermal field evolution sequence. Starting from the last time slice of the encapsulated thermal field sequence, the future thermal field evolution sequence determines the adjacent encapsulated thermal nodes where the thermal anomaly residual continues to move, based on the propagation direction. It also determines the time slices in which the thermal anomaly residual reaches these adjacent encapsulated thermal nodes based on the propagation rate and the time interval between adjacent time slices, and identifies the range of encapsulated thermal nodes where the thermal anomaly residual persists within consecutive time slices, based on the duration of the residual. The future thermal field evolution sequence reflects the process of the thermal anomaly residual expanding from local temperature deviations to adjacent encapsulated thermal nodes along the thermal path connections.

[0069] The dominant temperature component of the same packaged thermal node in the same time slice within the dominant thermal diffusion mode is used as the normal heat transfer reference temperature. Combined with the main transfer path in the packaged thermal field sequence, the normal heat transfer direction is determined, generating a normal heat transfer reference. The abnormal heat source location is determined by the packaged thermal node that deviates from the normal heat transfer reference temperature in the thermal anomaly residual, the corresponding time slice, and the corresponding spatial location. Local high temperature areas, interlayer temperature difference abrupt change areas, and solder joint thermal cycle concentration areas are written into the abnormal heat source location. The abnormal expansion trend is determined by the residual expansion direction, residual expansion rate, and residual persistence area in the future thermal field evolution sequence. The expansion process of the abnormal heat source location to adjacent packaged thermal nodes is recorded in the order of time slices. The normal heat transfer reference, abnormal heat source location, and abnormal expansion trend are mapped to the packaged thermal node number, packaged thermal node spatial location, and thermal path connection relationship to generate the packaged thermal field interpretation result.

[0070] S5. Locate candidate failure units in the thermal field interpretation results through thermal path connection relationships, invert the temperature field of candidate failure units and compare with thermal anomaly residuals to generate thermal failure prediction results.

[0071] S5.1. Extract the normal heat transfer baseline, abnormal heat source location, abnormal expansion trend, dominant heat diffusion mode, thermal anomaly residual, and future thermal field evolution sequence from the package thermal field interpretation results. Retrieve the thermal path connection relationships and map the package thermal node number, spatial location, and time slice corresponding to the thermal anomaly residual to the thermal path connection relationships to determine the package thermal node, adjacent thermal paths, and physical location of the thermal anomaly residual. Physical locations include chip junction regions, solder joint arrays, material interfaces, molding compound edges, and thermal interface material locations; adjacent thermal paths include heat conduction paths, contact paths, solder joint paths, and heat dissipation paths. This processing transforms the package thermal field interpretation results from temperature deviation results into specific thermal path locations within the package structure, avoiding the risk of failure based solely on hotspot temperatures.

[0072] Candidate failure units are determined based on the package hot nodes, adjacent thermal paths, and physical locations where thermal anomaly residuals are located. When the thermal anomaly residual remains at the junction node corresponding to the chip junction region within a continuous time slice, a chip junction candidate failure unit is determined; when the thermal anomaly residual repeatedly appears along the solder joint nodes corresponding to the solder joint array within a continuous power cycle, a solder joint candidate failure unit is determined; when the thermal anomaly residual is concentrated at the interface nodes corresponding to different material contact surfaces, an interface candidate failure unit is determined; when the thermal anomaly residual extends from the interlayer node corresponding to the edge of the molding compound to adjacent interlayer nodes, a molding compound candidate failure unit is determined; when the thermal anomaly residual is located at the interface node corresponding to the thermal interface material and changes the main propagation path, a thermal interface material candidate failure unit is determined. A candidate failure unit list is generated based on the correspondence between candidate failure units, thermal anomaly residuals, package hot nodes, adjacent thermal paths, and physical locations.

[0073] S5.2. For each candidate failure unit in the candidate failure unit list, extract the corresponding power consumption map, material thermal conductivity distribution, heat dissipation boundary conditions, heat transfer coefficient distribution, and thermal path connection relationships to generate a candidate failure unit inversion condition set. The power consumption map comes from the chip power consumption file, the material thermal conductivity distribution comes from the material parameter file, the heat dissipation boundary conditions and heat transfer coefficient distribution come from the heat dissipation boundary file, and the thermal path connection relationships come from the heat conduction path, contact path, solder joint path, and heat dissipation path. Each item in the candidate failure unit inversion condition set corresponds to the package hot node, adjacent thermal path, and physical location of the candidate failure unit, giving the temperature field inversion of the candidate failure unit a clear data source and structural endpoint.

[0074] The inverted temperature field is obtained by reconstructing the temperature field response caused by candidate failure elements through the inversion condition set of candidate failure elements. When reconstructing the temperature field response caused by candidate failure elements, the hot node of the package containing the candidate failure element is used as the starting point for inversion. The power consumption map, material thermal conductivity distribution, heat dissipation boundary conditions, heat transfer coefficient distribution, and thermal path connection relationships in the candidate failure element inversion condition set are kept consistent. The temperature change from the candidate failure element to the adjacent package hot node is calculated along the adjacent thermal paths of the candidate failure element, and the inverted temperature of each package hot node is recorded in time slice order. Each record in the inverted temperature field includes the time slice, package hot node number, package hot node spatial location, inverted temperature, and adjacent thermal path number.

[0075] S5.3. Extract the inversion hotspot locations, inversion interlayer temperature difference distribution, and inversion main heat transfer paths from the inversion temperature field to obtain the inversion thermal response characteristics. The inversion hotspot locations are the packaging hot nodes with the highest inversion temperature within the same time slice in the inversion temperature field; the inversion interlayer temperature difference distribution is the distribution of inversion temperature differences between adjacent interlayer nodes within the same time slice; the inversion main heat transfer path is the heat path chain in the inversion temperature field extending from the packaging hot node where the candidate failure unit is located to the heat dissipation node with the same heat flow direction. The inversion thermal response characteristics and the thermal anomaly residuals have the same packaging hot node numbering, packaging hot node spatial location, and time slice representation, allowing for direct comparison of positional order, expansion direction, and main transfer path.

[0076] The positional order, expansion direction, and main propagation path of the retrieved thermal response characteristics and thermal anomaly residuals are compared to obtain positional consistency, directional consistency, and path consistency results. When comparing the positional order, the order in which the retrieved hotspot locations appear on the time slice is correlated with the order in which the encapsulated hot nodes containing the maximum value of the thermal anomaly residuals appear on the time slice, resulting in positional consistency. When comparing the expansion direction, the movement direction of the retrieved hotspot locations along adjacent encapsulated hot nodes is correlated with the residual expansion direction in the anomaly expansion trend, resulting in directional consistency. When comparing the main propagation path, the main propagation path of the retrieved heat is correlated with the adjacent hot paths containing the thermal anomaly residuals and the main propagation path, resulting in path consistency.

[0077] S5.4. When the position consistency result, direction consistency result, and path consistency result all point to the same candidate failure unit, the same candidate failure unit is determined as the failure source unit. When the failure source unit corresponds to a candidate failure unit in the chip junction region, the local overheating type is determined; when the failure source unit corresponds to a candidate failure unit in the solder joint, the solder joint thermal fatigue type is determined; when the failure source unit corresponds to a candidate failure unit in the interface, the interface delamination type is determined; when the failure source unit corresponds to a candidate failure unit in the molding compound, the molding compound thermal cracking type is determined; when the failure source unit corresponds to a candidate failure unit in the thermal interface material, the thermal interface material degradation type is determined.

[0078] The failure types are ordered according to the earliest occurrence location of the thermal anomaly residual, the earliest pointing location of the inverted temperature field, and the thermal path location of the failure source unit. When ordering the failure types, the initial candidate order is determined first by the earliest occurrence time slice of the thermal anomaly residual. When multiple failure source units share the same earliest occurrence time slice of the thermal anomaly residual, the initial candidate order is determined by the earliest pointing time slice of the inverted temperature field. Finally, when multiple failure source units share the same earliest pointing time slice of the inverted temperature field, the initial candidate order is determined by the sequential position of the failure source units in the heat transfer direction from the chip junction region to the heat dissipation node. This process ensures that the failure sequence is jointly defined by the time slice, the inverted temperature field, and the thermal path location, preventing the inability to sort multiple candidate failure units when they occur simultaneously.

[0079] The failure source element, failure type, inverted temperature field, failure sequence, earliest occurrence location of thermal anomaly residuals, earliest pointing location of the inverted temperature field, and thermal path location of the failure source element are incorporated into the thermal failure prediction results. The thermal failure prediction results include the initial failure location, failure type, failure propagation path, hotspot migration process, critical thermal paths, inverted temperature field, and corresponding packaging parameter combinations. These packaging parameter combinations are derived from the parameter sources, node change locations, and thermal path change locations of the representative packaged digital twin. The thermal failure prediction results reflect the complete process of the representative packaged digital twin, from thermal field sequence generation, thermal anomaly residual separation, candidate failure element location, to inverted temperature field comparison.

[0080] In summary, this invention establishes the connection relationships between packaged thermal nodes and thermal paths by analyzing chip package design documents. This allows chip junctions, interlayer structures, solder joints, material interfaces, and heat dissipation structures to be incorporated into the same initial digital twin of the thermal path. This enables thermal failure prediction to move beyond simply judging the overall temperature field and to provide a basis for tracing the source of failure along the thermal path. By expanding the initial digital twin of the thermal path through a package parameter range table and using stochastic orthogonal decomposition and Krylov dynamic mode filtering to select representative package digital twins, repeated thermal path changes and repeated heat propagation behaviors can be reduced, avoiding inefficient traversal of all package parameter combinations. By performing heat transfer simulation on representative package digital twins, the heat transfer process from the chip junction to the heat dissipation boundary can be fully characterized. By separating the dominant heat diffusion mode and thermal anomaly residuals, normal heat transfer benchmarks can be distinguished from local thermal anomalies. By inverting the temperature field of candidate failure units and comparing it with the positional order, expansion direction, and main transmission path of thermal anomaly residuals, the failure type and failure sequence of the failure source units can be determined, thereby improving the structural localization capability and interpretability of chip package thermal failure prediction.

[0081] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A method for predicting thermal failure in chip packaging based on digital twins, characterized in that: include, Analyze the chip package design file, establish the connection relationship between package hot nodes and hot paths, limit the parameter range of the same package family, and generate the initial digital twin of hot paths and the package parameter range table; The initial thermal path digital twin is expanded using a package parameter range table to construct an initial package digital twin set. Representative package digital twins are then formed through random orthogonal decomposition and Krylov dynamic mode screening. Heat transfer from the junction region to the heat dissipation boundary is simulated for representative packaged digital twins, and hot spots, interlayer temperature difference, solder joint thermal cycle and main transfer path are extracted to generate packaged thermal field sequence; The thermal field sequence of the package is separated into the dominant thermal diffusion mode and the thermal anomaly residual, and the thermal anomaly residual is extrapolated along the time series to generate the thermal field interpretation result of the package. Candidate failure units in the thermal field interpretation results are located by identifying the thermal path connection relationship, the temperature field of the candidate failure units is inverted and compared with the thermal anomaly residual to generate thermal failure prediction results.

2. The chip packaging thermal failure prediction method based on digital twin as described in claim 1, characterized in that: The establishment of the connection relationship between the encapsulated hot nodes and hot paths specifically includes, Analyze the layout layer, package stack-up, power distribution, material properties and heat dissipation boundaries in the chip package design file, identify the spatial location of the package structure parts, and generate a package structure coordinate set; The package structure coordinate set is used to divide the junction nodes, interlayer nodes, solder joint nodes, interface nodes and heat dissipation nodes, and thermal parameters are added to each node to generate a package thermal node set. Connect the packaged thermal node set along the heat transfer direction from the chip junction region to the heat dissipation structure, and distinguish between the heat conduction path, contact path, solder joint path and heat dissipation path to generate thermal path connection relationship.

3. The chip packaging thermal failure prediction method based on digital twin as described in claim 2, characterized in that: The generated initial digital twin of the thermal path and the encapsulation parameter range table specifically include, The hot node set, hot path connection relationship and hot parameters of each node are mapped to the coordinate set of the package structure to generate the initial digital twin of the hot path. Select parameters of family-packaged chips that have passed reliability verification, and remove parameter records that do not meet the package design rules to obtain a valid family-packaged parameter set; The effective family of package parameters is divided according to the package level, solder joint structure, material system and heat dissipation path, and the boundary values ​​and commonly used value sequences of each type of parameter are extracted to generate a package parameter range table.

4. The chip packaging thermal failure prediction method based on digital twin as described in claim 3, characterized in that: The construction of the initial encapsulated digital twin set specifically includes, Extract the packaging layer thickness, solder joint geometry, thermal interface material parameters, and heat dissipation path parameters from the packaging parameter range table, and match each type of parameter to the interlayer node, solder joint node, interface node, and heat dissipation node in the initial thermal path digital twin to obtain the parameter replacement list. According to the parameter replacement list, multiple sets of parameters are replaced in the initial digital twin of the thermal path to maintain the consistency of chip junction power consumption, material hierarchy relationship and heat dissipation boundary, generate multiple package digital twins, and mark the parameter source, node change position and thermal path change position of each package digital twin to form an initial package digital twin set.

5. The chip packaging thermal failure prediction method based on digital twin as described in claim 4, characterized in that: The random orthogonal decomposition specifically includes, The thermal path difference matrix is ​​obtained by extracting the changes in package layer thickness, solder joint array, thermal interface material, and heat dissipation path from the initial package digital twin set; Random sampling and orthogonal decomposition of the thermal path difference matrix are performed to extract non-overlapping thermal path difference directions, resulting in an orthogonal feature set; The repetitive hot path changes in the initial encapsulated digital twin set are compressed according to the orthogonal feature set to form a representative space.

6. The chip packaging thermal failure prediction method based on digital twin as described in claim 5, characterized in that: The Krylov dynamic modality screening specifically includes, A heat transfer state sequence is established for each packaged digital twin in the representative space, the heat transfer state sequence including junction temperature rise response, interlayer heat transfer response, solder joint thermal cycling response and heat dissipation boundary response; The evolution direction of the heat transfer state sequence is characterized by Krylov subspace, the dominant thermal response is extracted, and the encapsulated digital twins with repeated heat propagation behavior are removed according to the propagation location, expansion direction and duration to form a representative encapsulated digital twin.

7. The chip packaging thermal failure prediction method based on digital twin as described in claim 6, characterized in that: The generation of the encapsulation thermal field sequence specifically includes, Chip junction power consumption and heat dissipation boundary conditions are applied to a representative packaged digital twin, and the temperature changes of each packaged thermal node are calculated along the thermal path connection relationship to obtain the node temperature timing. Extract the highest temperature node, the highest temperature moment, the temperature difference between adjacent layers, the periodic temperature fluctuation of the solder joint, and the dominant flow direction from the junction to the heat dissipation node from the node temperature time series to obtain hot spots, interlayer temperature difference, solder joint thermal cycle, and main transfer path. The hot spots, interlayer temperature difference, solder joint thermal cycle and main transfer path are arranged in time slice order to generate the package thermal field sequence.

8. The chip packaging thermal failure prediction method based on digital twin as described in claim 7, characterized in that: The generated packaging thermal field interpretation results specifically include, The encapsulated thermal field sequence is arranged into a thermal field matrix in chronological order, and the temperature diffusion pattern that appears stably in the long term is extracted to obtain the dominant thermal diffusion mode. By subtracting the dominant thermal diffusion mode from the thermal field matrix, separating the local high temperature region, the interlayer temperature difference abrupt change region, and the solder joint thermal cycle concentration region, the thermal anomaly residual is obtained. The spatial position change of the thermal anomaly residual is tracked along the continuous time slice, and the residual expansion direction, residual expansion rate, and residual persistence region are extracted to obtain the future thermal field evolution sequence. The normal heat transfer baseline, abnormal heat source location, and abnormal expansion trend are defined by the dominant heat diffusion mode, thermal anomaly residual, and future thermal field evolution sequence, respectively, to generate the encapsulated thermal field interpretation results.

9. The chip packaging thermal failure prediction method based on digital twin as described in claim 8, characterized in that: The candidate failure units in the positioning and packaging thermal field interpretation results specifically include, Map the thermal anomaly residuals in the thermal field interpretation results to the thermal path connection relationship to determine the thermal node, adjacent thermal path and physical location of the thermal anomaly residuals in the package; When the thermal anomaly residual remains in the chip junction region, the chip junction region candidate failure unit is determined; when the thermal anomaly residual appears repeatedly along the solder joint array, the solder joint candidate failure unit is determined; when the thermal anomaly residual is concentrated at the material interface, the interface candidate failure unit is determined. When the thermal anomaly residual extends from the edge of the molding layer, candidate failure elements of the molding layer are determined. When the thermal anomaly residual is located in the thermal interface material and changes the main transmission path, candidate failure elements of the thermal interface material are determined. Combine each candidate failure element with its corresponding thermal anomaly residual to generate a list of candidate failure elements.

10. The chip packaging thermal failure prediction method based on digital twin as described in claim 9, characterized in that: The generated thermal failure prediction results specifically include, Extract the power consumption map, material thermal conductivity distribution, heat dissipation boundary conditions, heat transfer coefficient distribution and thermal path connection relationship corresponding to the candidate failure units in the candidate failure unit list, and generate the candidate failure unit inversion condition set; The temperature field response caused by the candidate failure element is reconstructed by the inversion condition set of the candidate failure element, and the inversion temperature field is obtained. The inversion hot spot location, the inversion interlayer temperature difference distribution and the inversion heat main transfer path are extracted from the inversion temperature field to obtain the inversion thermal response characteristics. By comparing the positional order, expansion direction, and main propagation path of the inverted thermal response characteristics with the thermal anomaly residuals, the positional consistency results, directional consistency results, and path consistency results are obtained. When the location consistency result, direction consistency result, and path consistency result all point to the same candidate failure unit, it is determined as the failure source unit; When the failure source unit corresponds to the chip junction region, solder joint array, material interface, molding layer edge and thermal interface material, the local overheating type, solder joint thermal fatigue type, interface delamination type, molding layer thermal cracking type and thermal interface material degradation type are determined respectively. Based on the earliest occurrence location of the thermal anomaly residual, the earliest pointing location of the inverted temperature field, and the thermal path location of the failure source unit, the order of each failure type is arranged to generate thermal failure prediction results.

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