A static timing analysis method, apparatus and electronic device

Abstract

This application provides a static timing analysis method, apparatus, and electronic device, applied in the field of computer technology. After acquiring multiple process corners, the method performs static timing analysis on the target circuit module based on each process corner, obtaining the timing violation paths and corresponding timing margin values ​​for each process corner. It then determines the worst-case timing margin value for each timing violation path and, based on the worst-case timing margin value, determines a subset of process corners from among the multiple process corners. The number of process corners in the subset is less than the total number of process corners. This method can simplify the required process corners, reduce the number of process corners ultimately used for circuit design, reduce computational resource consumption during timing analysis, and significantly shorten the timing verification cycle, thus helping to improve design iteration efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, specifically to a static timing analysis method, apparatus, and electronic device. Background Technology

[0002] In the field of integrated circuit design, in order to address the impact of process deviations, operating voltage fluctuations and temperature changes in semiconductor manufacturing on the timing performance of integrated circuits, it is usually necessary to establish multiple process corners composed of parameters such as process, voltage and temperature, and to perform timing verification on the integrated circuit design under each process corner to ensure that the integrated circuit can meet timing requirements under various extreme operating conditions.

[0003] Related technologies often employ a multi-process corner exhaustive analysis method to verify the timing performance of integrated circuits. This involves performing static timing analysis on the integrated circuit for each process corner, checking whether each timing path in the integrated circuit exhibits any violations at each process corner.

[0004] However, with the evolution of semiconductor process technology and the widespread adoption of multi-voltage domain strategies in complex system-on-chip designs, the number of process corners that need to be considered has increased exponentially. Exhaustively traversing all process corners consumes a large amount of computing resources and significantly prolongs the timing verification cycle, which severely restricts the efficiency of design iteration. Summary of the Invention

[0005] In view of this, this application aims to provide a static timing analysis method, apparatus and electronic device to solve the problem in the related art of exhaustively traversing all process corners for timing performance analysis, which leads to the consumption of a large amount of computing resources and a significant extension of the timing verification cycle, thus severely restricting the efficiency of design iteration.

[0006] Firstly, this application provides a static timing analysis method, including: Obtain multiple process corners; Static timing analysis is performed on the target circuit module based on each process corner to obtain the timing violation path and the timing margin value corresponding to the timing violation path of the target circuit module under each process corner. The target circuit module is used to implement the preset function of the integrated circuit. Determine the worst-case timing margin value for each timing violation path; Based on the worst-case timing margin value, a subset of process corners is determined from the plurality of process corners, wherein the number of process corners in the subset is less than the total number of the plurality of process corners.

[0007] In one alternative implementation, determining a subset of process corners among the plurality of process corners based on the worst-case timing margin value includes: Determine the process corner corresponding to the worst timing margin value for each timing violation path; Count the number of worst-case timing margin values ​​corresponding to each process corner; The process corners with a non-zero number of worst-case timing margin values ​​among the multiple process corners are integrated into a process corner subset.

[0008] In one optional implementation, determining the worst-case timing margin value corresponding to each timing violation path includes: The timing margin value of each timing violation path under each process corner is calculated separately to obtain the set of timing margin values ​​corresponding to each timing violation path; For each timing violation path, the timing margin value with the largest absolute value is determined from the set of timing margin values ​​corresponding to that timing violation path as the worst-case timing margin value.

[0009] In one alternative implementation, the integrated circuit includes a plurality of functional circuits, the plurality of functional circuits including the target functional circuit, and the timing characteristics of the target functional circuit can characterize the worst-case timing characteristics of the plurality of functional circuits.

[0010] In an optional implementation, the method provided by the first aspect of this application further includes: performing static timing analysis on other functional circuits besides the target functional circuit based on each process corner in the process corner subset.

[0011] In one alternative implementation, determining a subset of process corners among the plurality of process corners based on the worst-case timing margin value includes: Determine the process corner corresponding to the worst timing margin value for each timing violation path; Count the number of worst-case timing margin values ​​corresponding to each process corner; The process corners whose worst timing margin value is greater than a preset threshold are integrated into a process corner subset.

[0012] In an optional implementation, the method provided by the first aspect of this application further includes: obtaining a first timing margin value for the target timing violation path at a target process angle and a second timing margin value at a subset of the process angles. Wherein, the target process angle is a process angle in which the number of worst-case timing margin values ​​is not zero and is less than or equal to the preset number threshold, and the target timing violation path corresponds to the worst-case timing margin value under the target process angle; The difference between the second timing margin value and the first timing margin value is used as the timing uncertainty corresponding to the target timing violation path.

[0013] In one alternative implementation, the timing violation path includes a time violation hold path or a time violation establish path.

[0014] Secondly, this application provides a static timing analysis apparatus, comprising: The first acquisition unit is used to acquire multiple process corners; The first analysis unit is used to perform static timing analysis on the target circuit module based on each process corner, to obtain the timing violation path of the target circuit module under each process corner and the timing margin value corresponding to the timing violation path. The target circuit module is used to implement the preset function of the integrated circuit. The determination unit is used to determine the worst-case timing margin value corresponding to each timing violation path; A filtering unit is configured to determine a subset of process corners from the plurality of process corners based on the worst-case timing margin value, wherein the subset of process corners covers all timing violation paths and the number of process corners in the subset is less than the total number of the plurality of process corners.

[0015] Thirdly, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executed by the processor, wherein the processor executes the computer program to implement the steps of the static timing analysis method as described in any embodiment of the first aspect of this application.

[0016] Based on the above, the static timing analysis method provided in this application, after obtaining multiple process corners, performs static timing analysis on the target circuit module based on each process corner, obtains the timing violation path of the target circuit module under each process corner and the timing margin value corresponding to the timing violation path, determines the worst-case timing margin value corresponding to each timing violation path, and determines a subset of process corners among multiple process corners based on the worst-case timing margin value. The number of process corners in the subset is less than the total number of multiple process corners. Therefore, the static timing analysis method provided in this application can simplify the required process corners, reduce the number of process corners finally used for circuit design, reduce the computational resource consumption in the timing analysis process, and significantly shorten the timing verification cycle, which helps to improve the efficiency of design iteration. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1This is a flowchart of a static timing analysis method provided in an embodiment of this application.

[0019] Figure 2 This is a flowchart of another static timing analysis method provided in the embodiments of this application.

[0020] Figure 3 This is a structural block diagram of a static timing analysis device provided in an embodiment of this application.

[0021] Figure 4 This is a structural block diagram of another static timing analysis device provided in the embodiments of this application.

[0022] Figure 5 This is a structural block diagram of another static timing analysis device provided in the embodiments of this application.

[0023] Figure 6 This is a structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] As mentioned earlier, in the field of integrated circuit design, to address the impact of process deviations, operating voltage fluctuations, and temperature variations in semiconductor manufacturing on the timing performance of integrated circuits, timing verification is typically performed on the integrated circuit design under multiple process corners to ensure that the integrated circuit meets timing requirements under various extreme operating conditions. Especially in the static timing analysis of very large-scale digital integrated circuits (VLSI), to ensure that the integrated circuit can still pass timing approval under various manufacturing process deviations, operating voltage fluctuations, and temperature variations, the commonly used approach is multi-corner analysis. Specifically, by combining process deviation models, voltage fluctuation extremes, temperature extremes, and extreme value models of interconnect parasitic parameters, a set of process corners covering extreme cases is constructed. Static timing analysis is then performed on the integrated circuit based on each process corner, i.e., exhaustive verification of all process corner combinations, checking for violations in setup and hold times one by one.

[0026] However, with the evolution of semiconductor process technology and the widespread adoption of multi-voltage domain strategies in complex system-on-chip designs, the number of process corners that need to be considered has increased exponentially. Exhaustively traversing all process corners consumes a large amount of computing resources and significantly prolongs the timing verification cycle, which severely restricts the efficiency of design iteration.

[0027] To address the aforementioned issues, this application provides a static timing analysis method that reduces process corners based on the worst-case margin value of timing violation paths. This eliminates redundant process corners that cannot contribute to the worst-case margin value while ensuring the integrity of timing verification. Consequently, the number of process corners in the final subset used for subsequent static timing analysis is significantly less than the original total. By simplifying the required process corners while covering all timing violation paths, the number of process corners ultimately used for circuit design is reduced. This lowers the computational resource consumption during timing analysis and significantly shortens the timing verification cycle, thereby improving design iteration efficiency.

[0028] The static timing analysis method provided in this application is applied to electronic devices, which may be electronic design automation tools, servers, workstations, or other processing platforms capable of performing static timing analysis tasks. See also... Figure 1 As shown, the static timing analysis method provided in this application embodiment may include the following steps.

[0029] S100, obtain multiple process corners.

[0030] In the field of integrated circuit design, a process corner refers to a combination of boundary conditions used during semiconductor manufacturing to simulate the impact of variations in parameters such as process, voltage, and temperature on integrated circuit performance. This can be a simple combination of a process model and voltage / temperature parameters, or it can be further superimposed with interconnect parasitic parameter models. For example, a process corner can include a slow transistor model combined with low voltage and high temperature, or a fast transistor model combined with high voltage and low temperature. It can also combine models of maximum and minimum capacitance values, or the maximum or minimum value of the resistance-capacitance product.

[0031] As an optional implementation, a set of process corners to be traversed can be generated based on standard cell library files, parasitic parameter files, and the project's voltage and temperature configurations. More generally, the methods for obtaining process corners can include, but are not limited to: manual configuration by designers, automatic enumeration by scripts, reading from the project configuration database by the approval platform, or output from the preceding analysis process, etc., which will not be detailed here.

[0032] Combining the composition of process corners before and after the analysis reveals that the number of process corners increases significantly with the number of multi-voltage domains. This indicates that when the design scale expands and the power supply strategy becomes more complex, directly exhaustively analyzing all process corners would incur a significant computational burden. By first obtaining the complete set of process corners and then performing violation coverage analysis, the problem can be transformed into identifying redundant process corners from the original complete set. It should be noted that the more process corners obtained in this step, the more representative the coverage of violation paths will be for the subsequently selected subset of process corners.

[0033] S110. Perform static timing analysis on the target circuit module based on each process corner to obtain the timing violation path of the target circuit module under each process corner and the timing margin value corresponding to the timing violation path.

[0034] It is understandable that, based on different specific functional implementations, an integrated circuit may include multiple functional circuits. Each functional circuit is used to implement a preset function of the integrated circuit. For example, the preset function may be a processor core function, cache control function, bus interconnect function, interface control function, or other digital logic function. Therefore, as an optional implementation, the target circuit module mentioned in this embodiment can be any functional circuit in the integrated circuit. For example, it may be a circuit module in the integrated circuit that requires individual process corner selection. In another optional implementation, the target circuit module may be a representative module that reflects the overall timing risk of the integrated circuit. In other words, the target circuit module selected among the multiple circuit modules included in the integrated circuit has timing characteristics that can characterize the worst-case timing characteristics of all circuit modules within the integrated circuit. For example, it may be a high-density standard cell module, a long interconnect module, etc., in the integrated circuit. By first performing process corner selection on the target circuit module, the workload of repeatedly traversing redundant process corners over a larger scope can be reduced, thereby forming a technical path of global verification supported by local analysis.

[0035] Static Timing Analysis (STA) is an input-independent timing verification technique that aims to find the worst-case delay of sequential logic circuits by traversing all timing paths in an integrated circuit and checking whether setup and hold times meet requirements. This analysis method is primarily based on process corner-limited operating conditions, analyzing the maximum and minimum sequential logic path delays to determine whether the design can operate under the required process corners. This analysis method is very convenient, especially in large integrated circuit architectures, as it can significantly reduce simulation workload and time costs. STA, combined with formal verification, ensures the timing correctness of digital systems. The main purpose of STA is to improve the system's operating frequency and increase system stability by reducing metastability and the synthesis, mapping, placement, and routing results of control logic, thereby reducing logic and routing delays and ultimately increasing the operating frequency.

[0036] More importantly, STA analysis can traverse every timing path in the integrated circuit architecture. Therefore, after obtaining multiple process corners, this method first performs static timing analysis on the target circuit module based on each process corner, obtaining the corresponding static timing analysis results. Based on the timing delay of each timing path within the target circuit module recorded in the static timing analysis results, the timing violation paths of the target circuit module under each process corner and the timing margin values ​​corresponding to the timing violation paths are selected. As for the specific analysis process of performing static timing analysis on the target circuit module under each process corner, relevant technologies can be referenced, and will not be detailed here.

[0037] In practical applications, static timing analysis mainly includes two parts: setup time and hold time. Setup time refers to the shortest period of time during which input data must remain stable before the arrival of the clock's valid edge. If a timing path fails to meet this condition, it is considered a setup time violation path, and its timing margin is negative. Hold time refers to the shortest period of time during which input data must remain stable after the arrival of the clock's valid edge. If a timing path fails to meet this condition, it is considered a hold time violation path, and its hold time margin is also negative. In this embodiment, both the hold time margin and the setup time margin are uniformly defined as timing margin values, used to characterize the degree of deviation of the corresponding path from meeting the timing constraints.

[0038] The timing violation paths described in this application's embodiments can be either setup time violation paths or hold time violation paths. Generally, setup time violations typically occur in slow, high-delay process corners, and these violations can be corrected by frequency reduction. Therefore, setup time checks can be ignored in fast process corners and only performed in slow process corners. In contrast, while hold time violations typically occur in fast, low-delay process corners, some violations can still occur in slow process corners. Furthermore, hold time violations cannot be corrected by subsequent methods, so hold time checks are usually performed in all process corners. In practical applications, the number of process corners used for hold time checks is far greater than the number used for setup time checks, resulting in more redundant process corners for hold time checks. Therefore, the static timing analysis method provided in this application's embodiments can primarily be used to reduce the number of process corners used for hold time checks. Of course, the same reduction can also be applied to the number of process corners used for setup time checks; the specific operation process is the same.

[0039] Based on the above, static timing analysis is performed on the target circuit module for each process corner to obtain the static timing analysis results of the target circuit module under each process corner. Furthermore, from each static timing analysis result, the timing violation paths of the target circuit module under each process corner, and the timing margin values ​​corresponding to each timing violation path, are extracted. Assume that the set of multiple process corners obtained in S100 is represented as: Cs1: (C1, C2, ..., Cn), where C1-Cn represent different process corners, and n>1. After this step, the results obtained by performing static timing analysis on the target circuit module for each process corner can be expressed as: C1: [p1(S11), p2(S21), ..., pm(Sm1)], C2: [p1(S11), p2(S21), ..., pm(Sm1)], ..., Cn: [p1(S11), p2(S21), ..., pm(Sm1)], where p1-pm represents the timing violation path under each process corner, m≥0, and S11-Sm1 represents the timing margin value corresponding to the timing violation path.

[0040] S120. Determine the worst-case timing margin value for each timing violation path.

[0041] As mentioned earlier, timing margin values ​​represent the timing deviation between hold time and set-up time, and are typically negative. In other words, the larger the absolute value of the timing margin, the greater the deviation from timing constraints. Based on this, this embodiment defines the timing margin value with the largest absolute value as the worst-case timing margin value. After determining the timing violation path and its corresponding timing margin value for each process corner in the aforementioned steps, using the timing violation path as the selection criterion, for each timing violation path, the timing margin values ​​of all violation paths in each process corner can be counted first to obtain the timing margin value set corresponding to each timing violation path. It can be understood that some timing paths only exhibit violations in some process corners, and do not form violations in other process corners. Therefore, the number of timing margin values ​​included in the timing margin value set corresponding to each timing violation path is not the same. Subsequently, the worst-case value, i.e., the worst-case timing margin value, is found in the corresponding margin value set for each timing violation path. By adopting this path-by-path comparison method, the original exhaustive coverage problem for all process corners can be transformed into the problem of identifying the most stringent operating conditions for each violation path.

[0042] Following the previous example, the set of timing margin values ​​corresponding to a timing violation path can be represented as: p1(S11, S12, ..., S1m), p2(S21, S22, ..., S2m), ..., pm(Sm1, Sm2, ..., Smm). For each timing violation path, the timing margin value with the largest absolute value in its corresponding timing margin value set is determined as the worst-case timing margin value corresponding to that timing violation path.

[0043] S130. Determine a subset of process corners among multiple process corners based on the worst-case timing margin value.

[0044] The number of process corners in the final determined process corner subset of this application embodiment is less than the total number of multiple process corners obtained in S100, that is, the number of process corners can be reduced. As mentioned above, static timing analysis is performed according to the limiting conditions of process corners. Based on the timing violation paths obtained from static timing analysis and the worst timing margin values ​​corresponding to the timing violation paths, there is a unique correspondence between them and the process corners. Based on this, as an optional implementation method, when screening the process corner subset, the process corner corresponding to the worst timing margin value of each timing violation path can be determined first. After traversing all timing violation paths, the process corners corresponding to the worst timing margin values ​​of each timing violation path can be obtained. Further horizontal statistics are performed, that is, the number of worst timing margin values ​​corresponding to each process corner is counted. It can be understood that in practical applications, there may be cases where all timing violation paths do not have the worst timing margin value under a certain process corner. In this case, the number of worst timing margin values ​​corresponding to that process corner is zero. Based on this, after completing the statistics of all process corners, the process corners with a non-zero number of worst timing margin values ​​are integrated into a process corner subset.

[0045] It is understandable that the number of worst-case timing margin values ​​corresponding to a process corner is not zero, which can be interpreted as the process corner corresponding to at least one worst-case timing margin value for a path. Based on this principle, a subset of process corners is determined, ensuring that each retained process corner has an irreplaceable representative role in the worst-case state of at least one violation path. Process corners that are removed do not bear the worst-case state carrying function in the existing path set and can therefore be considered redundant. Excluding these redundant process corners will not affect the comprehensive evaluation of timing paths. This is because if the worst-case timing violation under a certain process corner (a process corner in the process corner subset) can be overcome through violation repair, then timing violations under other non-worst-case states can naturally be repaired as well. The process corner subset selection scheme provided in this embodiment has a relatively direct selection logic, does not rely on complex optimization models, and does not require applying additional weights to different paths, making it easy to implement in engineering scripts. Furthermore, identifying indispensable process corners using a simple and stable statistical method helps reduce the implementation complexity of the selection process itself and synergistically enhances the convergence efficiency of the overall timing analysis process.

[0046] In some embodiments, the number of process corners can be significantly reduced after the above screening. For example, in a real-world project, the hold-time check originally required traversing 48 process corners. This screening method eliminated 20 redundant process corners, ultimately retaining 28 process corners for subsequent analysis. Although the total number of process corners, design complexity, and screening results may vary across different projects, this example demonstrates that screening based on the worst-case margin value attribution can significantly compress the size of the analysis corners without changing the target path set.

[0047] More importantly, this embodiment includes all process corners with a non-zero number of worst-case timing margin values ​​as elements of the process corner subset. This ensures that the final process corner subset covers all timing violation paths. That is, for each extracted timing violation path, at least one process corner in the process corner subset corresponds to its worst-case timing margin value, or can be considered the process corner assigned to the most severe violation state of that path. In other words, the selection criterion for the process corner subset is not simply retaining process corners with a large number of violations, but rather retaining process corners that are representative of the worst-case state of the path. This avoids missing some paths that only exhibit extreme violations in a few process corners by selecting solely based on the total number of violations. Through this selection logic that combines path coverage and worst-case value assignment, the burden of subsequent analysis can be reduced while ensuring the coverage of the approval process.

[0048] Furthermore, after determining the process corner subset, static timing analysis can be performed on other functional circuits in the integrated circuit besides the target functional circuit based on each process corner in the obtained process corner subset. Since the target functional circuit is the functional circuit with the worst timing characteristics among all functional circuits in the integrated circuit, the process corner subset can cover all scenarios in which the worst timing margin value of the target functional circuit is generated, and can naturally meet the testing needs of other functional circuits. Since the number of process corners in the process corner subset is less than the total number of process corners obtained in S100, that is, the number of process corners that need to be verified is reduced, which can greatly reduce the overall time required for static timing analysis of other functional circuits and improve analysis efficiency.

[0049] In summary, the static timing analysis method provided in this application can simplify the required process corners while covering all timing violation paths, thereby reducing the number of process corners ultimately used for circuit design, reducing the computational resource consumption during timing analysis, and significantly shortening the timing verification cycle, which helps to improve design iteration efficiency.

[0050] This application also provides another static timing analysis method, see [link to relevant documentation]. Figure 2 As shown in the figure, the static timing analysis method provided in this application includes the following steps.

[0051] S200, obtain multiple process corners.

[0052] As an optional implementation method, the specific implementation process of S200 can be referred to Figure 1 The details of S100 in the illustrated embodiment will not be repeated here.

[0053] S210. Perform static timing analysis on the target circuit module based on each process corner to obtain the timing violation path of the target circuit module under each process corner and the timing margin value corresponding to the timing violation path.

[0054] As an optional implementation method, the specific implementation process of S210 can be referred to Figure 1 The details of S110 in the illustrated embodiment will not be repeated here.

[0055] S220. Determine the worst-case timing margin value for each timing violation path.

[0056] As an optional implementation method, the specific implementation process of S220 can be referred to Figure 1 The details of S120 in the illustrated embodiment will not be repeated here.

[0057] S230. Determine the process corner corresponding to the worst timing margin value when each timing violation path occurs, and count the number of worst timing margin values ​​corresponding to each process corner.

[0058] As mentioned earlier, static timing analysis is performed according to the constraints of process corners. The timing violation paths and their corresponding worst-case timing margin values ​​obtained from static timing analysis have a unique correspondence with process corners. Therefore, when selecting a subset of process corners, we can first determine the process corner corresponding to the worst-case timing margin value for each timing violation path. After traversing all timing violation paths, we can obtain the process corners corresponding to the worst-case timing margin values ​​for each path. Further, we can count the number of worst-case timing margin values ​​corresponding to each process corner. It's understandable that in practical applications, there might be instances where all timing violation paths do not exhibit a worst-case timing margin value under a certain process corner; in such cases, the number of worst-case timing margin values ​​corresponding to that process corner is zero. Conversely, if the number of worst-case timing margin values ​​corresponding to a process corner is not zero, it can be understood that that process corner corresponds to at least one path with a worst-case timing margin value.

[0059] S240. Integrate the process corners whose number of worst timing margin values ​​is greater than a preset threshold into a process corner subset.

[0060] The static timing analysis method provided in this embodiment further filters the process corners ultimately assigned to the process corner subset by setting a preset quantity threshold, thereby further reducing the number of process corners included in the subset. This excludes process corners whose worst-case timing margin values ​​are not zero but are few in number. Based on this, the preset quantity threshold provided in this embodiment can be understood as a lower limit for measuring the contribution of a process corner to determine whether it is worth retaining. If a process corner is not completely redundant but only provides a worst-case timing margin value for a very small number of paths, it can be considered for further exclusion in some application scenarios to achieve higher analysis efficiency. This design allows process corner compression to go beyond simply eliminating process corners that occur zero times. Instead, it allows for finer-grained adjustments based on the project's need for a balance between coverage and efficiency, thus potentially reducing the number of process corners to be analyzed while minimizing coverage loss.

[0061] Those skilled in the art will understand that the preset threshold is not limited to a fixed integer, but can also be dynamically adjusted based on the total number of violation paths, design scale, module type, or approval stage. For example, it can be set to an integer such as 1, 2, or 3, or it can be set to a threshold calculated as a certain percentage of the total number of violation paths.

[0062] As another alternative implementation, different thresholds can be set for different types of paths, or different threshold standards can be used for setup time violation paths and hold time violation paths, thereby providing a more flexible compression mechanism in engineering practice, which further helps to address the problem of the expansion of process corners in multi-voltage domain scenarios.

[0063] It is understandable that after executing S230 and S240, a subset of process corners determined based on the worst-case timing margin value is obtained. According to this embodiment, the number of process corners included in the subset of process corners is still less than the total number of process corners obtained in S100. However, the obtained subset of process corners can no longer cover all timing violation paths. Therefore, in order to meet the requirements of sufficient verification, it is necessary to further process the timing violation paths that are not covered by the subset of process corners.

[0064] S250, Obtain the first timing margin value of the target timing violation path under the target process corner and the second timing margin value under the process corner subset.

[0065] Based on the foregoing, this embodiment defines the process corners where the number of worst timing margin values ​​is not zero and is less than or equal to a preset threshold as target process corners, that is, process corners where the number of worst timing margin values ​​is not zero but has not been merged into a subset of process corners. Accordingly, the timing violation paths with worst timing margin values ​​under the target process corners are defined as target timing violation paths.

[0066] The first timing margin value of the target timing violation path under the target process corner is also known as the worst-case timing margin value corresponding to the target timing violation path. It is understood that any timing path may have timing violations under multiple process corners. The target timing violation path experiences the most severe timing violation under the target process corner. Simultaneously, it may also experience timing violations under any process corner in the process corner subset. Of course, the timing margin value when a timing violation occurs under a process corner subset will definitely be less than the worst-case timing margin value of the target timing violation path, i.e., the aforementioned first timing margin value. In this embodiment, the timing margin value when the target timing violation path experiences a timing violation under a process corner subset is defined as the second timing margin value. It should be noted that if the target timing violation path experiences timing violations under multiple process corners in the process corner subset, i.e., there are multiple timing margin values ​​under the process corner subset, then the timing margin value with the largest absolute value among the multiple timing margin values ​​is taken as the second timing margin value.

[0067] S260. The difference between the second timing margin value and the first timing margin value is taken as the timing uncertainty corresponding to the target timing violation path.

[0068] Timing uncertainty refers to the additional timing constraints added to compensate for the margin deviation caused when some timing violation paths are not covered by the selected subset of process corners due to process corner reduction. As mentioned above, the absolute value of the worst-case timing margin for the target timing violation path under the target process corner is always smaller than the absolute value of the timing margin under other process corners. Based on this, the difference between the second timing margin value and the first timing margin value (i.e., the worst-case timing margin value of the target timing violation path) can be used to quantify the severity loss caused by removing the target process corner. Specifically, the difference between the second timing margin value and the first timing margin value should be positive, and can be used as the additional timing uncertainty to be added in the subsequent analysis of the target timing violation path. By artificially compensating for this severity difference, the analysis results on the retained process corner subset can be closer to the original worst-case state including the removed process corners.

[0069] Specifically, if a target timing violation path has a first timing margin of -0.10 nanoseconds at the target process corner, and a second timing margin of -0.06 nanoseconds obtainable within the process corner subset, then the difference between the two, i.e., 0.04 nanoseconds, can be used as the timing uncertainty of the target timing violation path. Subsequently, a corresponding uncertainty can be added to the constraint model of the target timing violation path to ensure that the analysis results remain sufficiently conservative.

[0070] In addition to the difference compensation method, those skilled in the art can also analyze the causes of the target timing violation path and modify the path structure to reduce the number of times the worst timing margin value occurs under the target process corner to 0, thereby indirectly completing further elimination.

[0071] In summary, the static timing analysis method provided in this embodiment can further compress the process corner subset to improve the efficiency of static timing analysis, while providing a compensation mechanism for excluded paths, thereby maintaining high timing reliability and meeting the analysis needs of different scenarios.

[0072] The static timing analysis apparatus provided by this invention is described below. This apparatus belongs to the same conceptual framework as the static timing analysis method provided in the embodiments of this application. It can execute the static timing analysis method provided in any embodiment of this application and possesses the corresponding functional modules and beneficial effects for executing the static timing analysis method. Technical details not described in detail in this embodiment can be found in the static timing analysis method provided in the embodiments of this application, and will not be repeated here.

[0073] See Figure 3 The static timing analysis apparatus provided in this application includes: The first acquisition unit 10 is used to acquire multiple process corners; The first analysis unit 20 is used to perform static timing analysis on the target circuit module based on each process corner, to obtain the timing violation path of the target circuit module under each process corner and the timing margin value corresponding to the timing violation path. The target circuit module is used to implement the preset function of the integrated circuit. Determining unit 30 is used to determine the worst-case timing margin value corresponding to each timing violation path; The filtering unit 40 is used to determine a subset of process corners from multiple process corners based on the worst-case timing margin value. The number of process corners in the subset is less than the total number of multiple process corners.

[0074] In one alternative implementation, the filtering unit 40 specifically includes the following when determining a subset of process corners among multiple process corners based on the worst-case timing margin value: Determine the process corner corresponding to the worst timing margin value for each timing violation path; Count the number of worst-case timing margin values ​​corresponding to each process corner; The process corners with a non-zero number of worst-case timing margin values ​​among multiple process corners are integrated into a process corner subset.

[0075] In one optional implementation, the determining unit 30, when determining the worst-case timing margin value corresponding to each timing violation path, specifically includes: The timing margin value of each timing violation path is calculated at each process corner to obtain the set of timing margin values ​​corresponding to each timing violation path. For each timing violation path, the timing margin value with the largest absolute value is determined from the set of timing margin values ​​corresponding to that timing violation path as the worst-case timing margin value.

[0076] This application also provides another static timing analysis device, see [link to previous document]. Figure 4 The static timing analysis apparatus provided in this embodiment further includes: The second analysis unit 50 is used to perform static timing analysis on other functional circuits besides the target functional circuit based on each process corner in the process corner subset.

[0077] This application provides another static timing analysis device, see [link to previous document]. Figure 5 As shown, in Figure 3 Based on the embodiment shown, it also includes a second acquisition unit 60 and a marking unit 70.

[0078] It should be noted that in the static timing analysis device provided in this embodiment, the filtering unit 40 is used for: Determine the process corner corresponding to the worst timing margin value for each timing violation path; Count the number of worst-case timing margin values ​​corresponding to each process corner; Process corners with a number of worst timing margin values ​​greater than a preset threshold are integrated into a process corner subset.

[0079] The second acquisition unit 60 is used to acquire the first timing margin value of the target timing violation path under the target process corner and the second timing margin value under the process corner subset. Wherein, the target process corner is the process corner where the number of corresponding worst timing margin values ​​is not zero and is less than or equal to a preset number threshold, and the target timing violation path corresponds to the worst timing margin value under the target process corner; The marking unit 70 is used to take the difference between the second timing margin value and the first timing margin value as the timing uncertainty corresponding to the target timing violation path.

[0080] Below, for reference Figure 6 The electronic device provided in this embodiment of the invention may include: at least one processor 100, at least one communication interface 200, at least one memory 300, and at least one communication bus 400. In this embodiment of the invention, the number of processor 100, communication interface 200, memory 300, and communication bus 400 is at least one, and the processor 100, communication interface 200, and memory 300 communicate with each other through communication bus 400; obviously, Figure 6 The communication connections shown for the processor 100, communication interface 200, memory 300, and communication bus 400 are optional. Optionally, the communication interface 200 can be an interface of a communication module, such as the interface of a GSM module; the processor 100 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present invention.

[0081] The memory 300 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0082] Specifically, the processor 100 is used to execute the application program in the memory to implement the steps of the static timing analysis method described above.

[0083] In some embodiments, this embodiment also provides a computer-readable storage medium, such as a floppy disk, optical disk, hard disk, flash memory, USB flash drive, SD (Secure Digital Memory Card), MMC (Multimedia Card), etc., in which one or more instructions implementing the above steps are stored. When these one or more instructions are executed by one or more processors, the processors perform the static timing analysis method described above. For specific implementation details, please refer to the foregoing description; further elaboration is not provided here.

[0084] In addition to the methods and apparatus described above, embodiments of this application may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the static timing analysis methods according to various embodiments of this application as described above.

[0085] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this application. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0086] Those skilled in the art will understand that the contents disclosed herein can be varied and modified in many ways. For example, the various devices or components described above can be implemented in hardware, or in software, firmware, or a combination of some or all of the three.

[0087] Furthermore, while this disclosure makes various references to certain elements of systems according to embodiments of this disclosure, any number of different elements may be used and operated on clients and / or servers. Elements are merely illustrative, and different aspects of the system and method may use different elements.

[0088] This disclosure uses flowcharts to illustrate the steps of a method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes.

[0089] Those skilled in the art will understand that all or part of the steps in the above methods can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium, such as a read-only memory. Optionally, all or part of the steps in the above embodiments can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiments can be implemented in hardware or as a software functional module. This disclosure is not limited to any particular combination of hardware and software.

[0090] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0091] The foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it. While several exemplary embodiments of the present disclosure have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined by the claims. It should be understood that the foregoing description is intended to illustrate the present disclosure and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A static time series analysis method, characterized in that, include: Obtain multiple process corners; Static timing analysis is performed on the target circuit module based on each process corner to obtain the timing violation path and the timing margin value corresponding to the timing violation path of the target circuit module under each process corner. The target circuit module is used to implement the preset function of the integrated circuit. Determine the worst-case timing margin value for each timing violation path; Based on the worst-case timing margin value, a subset of process corners is determined from the plurality of process corners, wherein the number of process corners in the subset is less than the total number of the plurality of process corners.

2. The method according to claim 1, characterized in that, Based on the worst-case timing margin value, a subset of process corners is determined from the plurality of process corners, including: Determine the process corner corresponding to the worst timing margin value for each timing violation path; Count the number of worst-case timing margin values ​​corresponding to each process corner; The process corners with a non-zero number of worst-case timing margin values ​​among the multiple process corners are integrated into a process corner subset.

3. The method according to claim 1, characterized in that, The step of determining the worst-case timing margin value corresponding to each timing violation path includes: The timing margin value of each timing violation path under each process corner is calculated separately to obtain the set of timing margin values ​​corresponding to each timing violation path; For each timing violation path, the timing margin value with the largest absolute value is determined from the set of timing margin values ​​corresponding to that timing violation path as the worst-case timing margin value.

4. The method according to claim 1, characterized in that, The integrated circuit includes multiple functional circuits, including a target functional circuit, and the timing characteristics of the target functional circuit can characterize the worst-case timing characteristics of the multiple functional circuits.

5. The method according to claim 4, characterized in that, The method further includes: performing static timing analysis on other functional circuits besides the target functional circuit based on each process corner in the process corner subset.

6. The method according to claim 1, characterized in that, Based on the worst-case timing margin value, a subset of process corners is determined from the plurality of process corners, including: Determine the process corner corresponding to the worst timing margin value for each timing violation path; Count the number of worst-case timing margin values ​​corresponding to each process corner; The process corners whose worst timing margin value is greater than a preset threshold are integrated into a process corner subset.

7. The method according to claim 6, characterized in that, The method further includes: obtaining a first timing margin value for the target timing violation path under the target process corner and a second timing margin value under the subset of process corners. Wherein, the target process angle is a process angle in which the number of worst-case timing margin values ​​is not zero and is less than or equal to the preset number threshold, and the target timing violation path corresponds to the worst-case timing margin value under the target process angle; The difference between the second timing margin value and the first timing margin value is used as the timing uncertainty corresponding to the target timing violation path.

8. The method according to any one of claims 1 to 7, characterized in that, The timing violation paths include either a time-keeping violation path or a time-establishment violation path.

9. A static timing analysis device, characterized in that, include: The first acquisition unit is used to acquire multiple process corners; The first analysis unit is used to perform static timing analysis on the target circuit module based on each process corner, to obtain the timing violation path of the target circuit module under each process corner and the timing margin value corresponding to the timing violation path. The target circuit module is used to implement the preset function of the integrated circuit. The determination unit is used to determine the worst-case timing margin value corresponding to each timing violation path; A filtering unit is used to determine a subset of process corners from the plurality of process corners based on the worst-case timing margin value, wherein the number of process corners in the subset is less than the total number of the plurality of process corners.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executed by the processor, characterized in that, When the processor executes the computer program, it implements the steps of the static timing analysis method as described in any one of claims 1 to 8.

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