A method and apparatus for routing path allocation in a multi-fpga system

Abstract

This application provides a routing path allocation method and device for a multi-FPGA system, applied in the field of electronic design automation technology. The method smooths and aggregates the path delays of routing paths to obtain a differentiable global smooth maximum delay. Combining the contribution weight of the path delay, the continuous edge load of physical edges, and the traversal relationship between the routing path and the physical edge, a chain-law derivative is performed on the global smooth maximum delay to obtain an analytical gradient cost. This analytical gradient cost characterizes the marginal impact of changes in physical edge load on the global timing objective. The analytical gradient cost guides the path search of the signal network, enabling the path search to allocate routing paths based on the influence of physical edges on the global timing objective. This facilitates the coordination of routing paths for different signal networks and significantly reduces the need for repeated path adjustments based on the local state of physical edges.

Description

Technical Field

[0001] This application relates to the field of electronic design automation technology, specifically to a wiring path allocation method and device for a multi-FPGA system. Background Technology

[0002] Multi-FPGA systems (MFS) are widely used for large-scale language model inference, high-performance computing, and pre-silicon verification of advanced chips due to their parallel computing capabilities and reconfigurability. A typical MFS divides and maps a high-density design netlist onto multiple physical FPGA chips. Signals are transmitted between different FPGAs through physical interconnect channels, and the routing paths of the signal nets can pass through one or more physical edges. Inter-chip communication latency mainly includes the physical hop count latency caused by the routing path from the source to the sink, and the scheduling latency caused by the time-division multiplexing (TDM) channels, which are important factors affecting the system's operating frequency.

[0003] Currently, routing path allocation in multi-FPGA systems typically employs shortest path search or negotiation-based routing methods. These methods set edge costs based on physical edge transmission delays, channel occupancy, or congestion levels, and then search for routing paths for the signal network according to these edge costs. When physical edges become congested or the routing results do not meet expectations, the edge costs can be adjusted, and the path search can be restarted. Furthermore, existing methods can iteratively optimize the allocation of routing paths and channel resources within a fixed physical interconnect graph.

[0004] However, the maximum latency across the entire network is determined by multiple cabling paths from different signal networks, involving comparisons between different cabling paths within the same signal network as well as comparisons between different signal networks. When cabling paths or physical edge loads change, the bottleneck path generating the maximum latency across the entire network may also change. Since the maximum latency across the entire network is determined by comparing the maximum values ​​among multiple cabling paths, existing path evaluation methods struggle to form a continuous and stable global timing evaluation basis when the bottleneck path changes. Existing methods mainly set edge costs based on the current transmission delay or congestion level of the physical edge, which fails to reflect the impact of changes in physical edge load on the maximum latency across the entire network, resulting in insufficient correlation between the edge costs used in path search and the global timing objective.

[0005] Therefore, a new routing path allocation scheme for multi-FPGA systems is needed. Summary of the Invention

[0006] In view of this, embodiments of this specification provide a routing path allocation method and device for a multi-FPGA system, which solves the problem that existing routing path allocation methods mainly rely on the local state of physical edges for path search, making it difficult to coordinate the routing paths of different signal networks, resulting in the inability to effectively reduce the maximum latency of the entire network.

[0007] The embodiments in this specification provide the following technical solutions: This specification provides an embodiment of a routing path allocation method for a multi-FPGA system, including: Obtain a physical interconnection diagram, a netlist to be routed, and a set of routing paths. The physical interconnection diagram includes physical edges and the edge capacity corresponding to the physical edges. The set of routing paths includes the routing paths of the signal nets in the netlist to be routed. Based on the set of wiring paths, the edge load corresponding to the physical edge is obtained, and the edge load is the number of signal networks passing through the corresponding physical edge; Based on the edge load and the edge capacity, the physical single-hop delay corresponding to the physical edge is obtained; Determine the relationship between the wiring path and the physical edge; Based on the physical single-hop delay and the traversal relationship, the path delay corresponding to the wiring path is obtained; The path delay is smoothed and aggregated using a logarithmic exponent and a function to obtain the global smoothed maximum delay and the contribution weight corresponding to the path delay. The contribution weight represents the degree of contribution of the path delay to the global smoothed maximum delay. The edge load is processed to become a continuous edge load; Using the continuous edge load as the derivative variable, and based on the contribution weight and the traversal relationship, perform chain-like differentiation on the global smoothing maximum delay to obtain the analytical gradient cost corresponding to the physical edge; Based on the analytical gradient cost, a path search is performed on the signal nets in the netlist to be routed in the physical interconnect graph to obtain the target routing path set.

[0008] Furthermore, the smooth aggregation of the path delay using a logarithmic exponent and a function includes: The path delays of the same signal network are first smoothed and aggregated to obtain the smoothed network delays corresponding to the signal network. A second smoothing aggregation is performed on the smoothed network delay to obtain the global smoothed maximum delay.

[0009] Furthermore, based on the path delay of the same signal network and the smoothing network delay, the path delay is exponentially normalized to obtain the intra-network normalized weight, which corresponds to the path delay. Based on the smoothing network delay and the global smoothing maximum delay, the smoothing network delay is exponentially normalized to obtain system-level normalized weights, which correspond to the signal network. The contribution weight is obtained by multiplying the intra-network normalized weight and the corresponding system-level normalized weight.

[0010] Further, the step of performing path search on the signal nets in the netlist to be routed in the physical interconnect graph based on the analytical gradient cost includes: Based on the physical single-hop delay and the analytical gradient cost, construct the composite edge cost corresponding to the physical edge: ; in, This represents the cost of the composite edge corresponding to physical edge e; This represents the physical single-hop delay corresponding to physical edge e; Let represent the analytical gradient cost corresponding to the physical edge e; λ represents the tradeoff coefficient that balances the scale difference between physical delay and gradient cost. The cost of the composite edge is determined as the path search weight of the physical edge; Path search is performed based on the path search weights.

[0011] Further, performing path search based on the path search weight includes: Divide the signal networks in the netlist to be wired into multiple batches; At the start of the first batch, the analytical gradient cost is obtained based on the set of routing paths, and the composite edge cost is updated. At the beginning of each subsequent batch, the composite edge cost is updated using the analytical gradient cost obtained at the end of the previous batch. The updated composite edge cost is determined as the path search weight; Within the batch, the path search weight remains unchanged, and path search is performed sequentially on the signal network in the batch; Update the wiring path set based on the results of the path search; The analytical gradient cost is updated based on the updated set of routing paths, and the analytical gradient cost is used for the next batch of composite edge cost updates.

[0012] Furthermore, the step of dividing the signal networks in the netlist to be wired into multiple batches includes: The contribution weights of the wiring paths for the same signal network are summed to obtain the sum of the contribution weights corresponding to the signal network. The signal networks are sorted from largest to smallest based on the sum of their contribution weights; The signal network is divided into multiple batches according to the sorting results.

[0013] Further, performing path search based on the path search weight includes: Based on the edge load and the edge capacity, the time-division multiplexing ratio corresponding to the physical edge is obtained; The contribution weights of the wiring paths for the same signal network are summed to obtain the sum of the contribution weights corresponding to the signal network. Based on the sum of the contribution weights, the signal network is divided into critical networks and non-critical networks; During the path search of the non-critical network, the path search weight of the physical edges with a time-division multiplexing ratio greater than 1 is set to infinity; When performing path search on the critical network, the path search weight of physical edges with a time-division multiplexing ratio greater than 1 remains unchanged.

[0014] Furthermore, the method also includes: After completing the multiple batches, the target maximum path delay is determined based on the target wiring path set; The target number of bottleneck networks is determined based on the target maximum path delay, where the target number of bottleneck networks is the number of signal networks that reach the target maximum path delay. Select a signal network from the target wiring path set, and re-execute the path search according to the path search weight to obtain candidate wiring paths; Replace the wiring path of the signal network with the candidate wiring path to obtain a set of candidate wiring paths; The candidate maximum path delay is determined based on the set of candidate wiring paths; The number of candidate bottleneck networks is determined based on the candidate maximum path delay, where the number of candidate bottleneck networks is the number of signal networks that reach the candidate maximum path delay. When the candidate maximum path delay is greater than the target maximum path delay, or the number of candidate bottleneck networks is greater than the target number of bottleneck networks, the candidate cabling path set is discarded. Otherwise, update the target routing path set based on the candidate routing path set.

[0015] Furthermore, the analytical gradient cost is determined in the following way: Based on the described relationship, determine the associated path that passes through the physical edge from the wiring path; The sum of the contribution weights corresponding to the associated paths is obtained by summing the contribution weights corresponding to the physical edges. Based on the edge capacity and the preset delay coefficient, the delay change rate is obtained, whereby the delay change rate represents the change in physical single-hop delay when the continuous edge load undergoes a unit change. The analytical gradient cost is obtained by multiplying the sum of the contribution weights by the rate of change of delay.

[0016] This specification also provides an electronic device, characterized in that it includes: At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform: the aforementioned wiring path allocation method for a multi-FPGA system.

[0017] Compared with the prior art, the technical effects that can be achieved by at least one of the above-mentioned technical solutions adopted in the embodiments of this specification include at least the following: 1. By smoothly aggregating path delays and performing chain-like differentiation on the global smooth maximum delay, the analytical gradient cost corresponding to the physical edge is obtained, thereby quantifying the impact of physical edge load changes on the global smooth maximum delay and providing a basis for selecting physical edges during path search. 2. By using analytical gradient cost to guide the path search of the signal network, the dependence of the path search on the local state of the physical edge is reduced, which is beneficial to coordinating the wiring paths of different signal networks and significantly reducing the maximum latency of the entire network. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of a routing path allocation method for a multi-FPGA system according to a specific embodiment of this application; Figure 2 This is a schematic diagram of the structure of an electronic device according to a specific embodiment of this application. Detailed Implementation

[0020] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0021] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that the following description covers various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0023] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0024] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0025] Regarding existing routing path allocation schemes for multi-FPGA systems, such as the prior art mentioned in the background section, through problem analysis and exploration of solutions, it was found that: Negotiated cabling (PathFinder) schemes mainly set congestion penalties based on the current occupancy of physical edges and gradually adjust cabling paths by removing and re-routing. This type of scheme is easily affected by the local state of physical edges, making it difficult to predict the impact of local path adjustments on the overall network timing. Its congestion penalty parameters usually need to be adjusted according to the system scale, and its adaptability to physical interconnection graphs of different scales is limited. While system-level optimization schemes under fixed topology can jointly adjust cabling paths and time-division multiplexing resources, they still mainly rely on heuristic search. When cabling paths or physical edge loads change, such schemes are difficult to form a continuous and stable global time-series evaluation basis, and path search results are easily affected by the current path distribution and local resource occupancy status.

[0026] In view of this, through research and exploration of improvements, it was found that when adjusting routing paths and time-division multiplexing resources on the existing physical resource map, as the number of FPGAs and physical channels increases, the number of available routing paths and resource allocation combinations also increases, and the existing heuristic methods are difficult to coordinate the global timing target with the path allocation result.

[0027] Based on this, this specification proposes a routing path allocation scheme for a multi-FPGA system: by smoothly aggregating the path delays of routing paths, a differentiable global smooth maximum delay is obtained; combining the contribution weight of the path delay, the continuous edge load of the physical edge, and the traversal relationship between the routing path and the physical edge, a chain-like derivative is performed on the global smooth maximum delay to obtain an analytical gradient cost, which is used to characterize the marginal impact of changes in physical edge load on the global timing objective; the path search of the signal network is guided according to the analytical gradient cost, so that the path search can allocate routing paths based on the impact of physical edges on the global timing objective, which is beneficial to coordinating the routing paths of different signal networks and significantly reduces the situation of repeated path adjustments based on the local state of physical edges.

[0028] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0029] like Figure 1 As shown in the embodiments of this specification, a routing path allocation method for a multi-FPGA system is provided, including: Step S10: Obtain the physical interconnect diagram, netlist to be routed, and set of routing paths for the Multi-FPGA System (MFS).

[0030] Specifically, the physical interconnection graph is used to represent the physical interconnection relationships between FPGAs in a multi-FPGA system. In one implementation, the physical interconnection graph is an undirected graph, represented as follows: In this diagram, V represents the node set, where each node corresponds to one FPGA, and E represents the physical edge set, where each physical edge represents a physical interconnection channel between FPGAs. Each physical edge corresponds to an edge capacity, which represents the number of parallel physical channels for that physical edge. The netlist to be routed includes signal networks that need to be allocated routing paths in the physical interconnection diagram; the routing path set includes the routing paths of the signal networks, used to determine the usage status of the physical edges.

[0031] Step S20: Determine edge load, physical single-hop delay, traversal relationship, and path delay.

[0032] Specifically, the number of signal networks passing through the physical edge is counted based on the set of routing paths to obtain the edge load corresponding to the physical edge; the physical single-hop delay corresponding to the physical edge is obtained based on the edge load and edge capacity; the traversal relationship between the routing path and the physical edge is determined, and the physical single-hop delay corresponding to the physical edge traversed by the routing path is summarized based on the traversal relationship to obtain the path delay corresponding to the routing path; the edge load is used for subsequent continuous processing, and the traversal relationship and path delay are used for subsequent determination of analytical gradient cost.

[0033] Step S30: Smooth the aggregated path delay to obtain the global smoothed maximum delay and contribution weight.

[0034] Specifically, the path delay is smoothly aggregated using the log-sum-exp (LSE) function, which transforms the maximum delay determined by multiple routing paths into the global smooth maximum delay. The contribution weights corresponding to the path delays are obtained, which represent the degree of contribution of the path delays to the global smooth maximum delay and are used for subsequent chain-law differentiation.

[0035] Step S40: Continuize the edge load and perform chain-like differentiation on the global smoothing maximum delay by combining the contribution weight and the traversal relationship to obtain the analytical gradient cost.

[0036] Specifically, the discrete edge loads are made continuous to obtain continuous edge loads; using the continuous edge loads as the derivative variables, the global smoothing maximum delay is chained according to the contribution weights and the relationship between the routing path and the physical edge to obtain the analytical gradient cost corresponding to the physical edge; the analytical gradient cost is used to represent the impact of changes in the edge load of the physical edge on the global smoothing maximum delay.

[0037] Step S50: Perform path search based on analytical gradient cost to obtain the target wiring path set.

[0038] Specifically, the analytical gradient cost is used as the path evaluation criterion for physical edges in the physical interconnect graph, and a path search is performed on the signal network in the netlist to be routed based on the analytical gradient cost. The routing path of the signal network is determined based on the path search results, and the target routing path set is obtained.

[0039] This embodiment achieves smooth aggregation of path delays, transforming the total network delay determined by multiple routing paths into a smooth target that can be derived using chain rule differentiation. Based on contribution weights and traversal relationships, the analytical gradient cost corresponding to each physical edge is obtained, reflecting the impact of physical edge load changes on the global timing objective. This provides an evaluation basis for selecting physical edges during path search, thereby reducing the dependence of path search on the local state of physical edges. This facilitates the coordination of routing paths in different signal networks, reduces the total network delay, and improves the overall timing performance of multi-FPGA systems.

[0040] In some implementations, after obtaining the analytical gradient cost corresponding to the physical edge, topology reconfiguration (Retopo) can be performed. The analytical gradient cost characterizes the impact of the edge load change of the corresponding physical edge on the global smoothing maximum latency. During the topology reconfiguration process, the analytical gradient cost is used as the topology reconfiguration weight of the physical edge, and the physical channels to be adjusted are determined according to the topology reconfiguration weight. The physical channels to be adjusted may include at least one of physical channels to be added and physical channels to be deleted.

[0041] Specifically, the physical constraints of the multi-FPGA system are obtained. These physical constraints include the maximum input / output capacity and reconfiguration margin of the nodes. Under these physical constraints, the locations for adding or deleting physical channels are determined based on the global timing impact represented by the analytical gradient cost.

[0042] For physical channels to be added, the corresponding physical channels are added to the physical interconnection graph; for physical channels to be deleted, the corresponding physical channels are deleted from the physical interconnection graph. The physical interconnection graph is updated according to the adjusted physical channels to obtain the reconstructed physical interconnection graph, which includes the updated physical edges and their corresponding edge capacities.

[0043] After obtaining the reconstructed physical interconnection diagram, the reconstructed physical interconnection diagram is used as the physical interconnection diagram for path search. Path search is performed on the signal network in the netlist to be wired in the reconstructed physical interconnection diagram to obtain the corresponding set of wiring paths.

[0044] In this embodiment, the analytical gradient cost is used simultaneously to determine the physical channels to be adjusted and to perform path search, so that topology reconstruction and cabling path allocation adopt the same global timing evaluation criteria, which helps to improve the consistency between physical channel adjustment results and cabling path allocation results.

[0045] In some implementations, the Log-Sum-Exp (LSE) function is used to smooth the maximum path delay within the same signal network and the maximum network delay between different signal networks layer by layer. For signal network n, the wiring path from the source end to the sink end t of the signal network is obtained. and according to the path delay corresponding to the wiring path. Perform the first smoothing aggregation; the intra-network smoothing formula is:

[0046] in, Denotes the set of terminals of signal network n; This represents the wiring path of signal network n from the source end to the sink end t; Indicates the path delay corresponding to the wiring path; Indicates the LSE smoothing parameter; This represents the smoothing network delay corresponding to signal network n.

[0047] By performing a first smooth aggregation on the path delays of the same signal network, the maximum path delay of multiple wiring paths within the signal network is represented as the smooth network delay, which is then used for a second smooth aggregation.

[0048] After obtaining the smoothed network delays corresponding to all signal networks, a second smoothing aggregation is performed on the smoothed network delays. The inter-network smoothing formula is as follows:

[0049] Where N represents the set of all signal networks; This represents the smoothing network delay corresponding to signal network n; Indicates the maximum delay for global smoothing; The second smoothing aggregation takes the smoothing network delay corresponding to each signal network as the processing object, and is used to represent the maximum network delay between different signal networks as the global smoothing maximum delay.

[0050] When smoothing parameter Global smoothing maximum delay as it approaches infinity Converging point by point to the original maximum latency of the entire network When the smoothing parameter When taking finite positive values, the global smoothing maximum delay is differentiable everywhere with respect to the delay of each path, and is still... The upper bound of the smoothing parameter. Preferably, the smoothing parameter. Take an empirical value of 0.05, and adjust the exponent term. A maximum value shift is performed to ensure the numerical stability of exponential operations.

[0051] This embodiment replaces the two nested maximum values ​​in the maximum delay of the entire network layer by layer with the LSE function, and performs intra-network smoothing on the maximum path delay of each path within the same signal network, and inter-network smoothing on the maximum network delay between different signal networks, thereby obtaining a continuously differentiable global smoothed maximum delay. This provides a processing basis for subsequently determining the contribution weight of path delay and performing chain-like differentiation on the global smoothed maximum delay.

[0052] Based on the above embodiments, and building upon the aforementioned two-stage smoothing aggregation, softmax normalization is applied to the path delay and smoothing network delay. This applies to the routing path of the signal network n from the source to the sink t. According to the path delay of the wiring path The path delays of other wiring paths within the signal network are used to determine the normalized weights within the network according to the following formula:

[0053] Based on the smoothing network delay corresponding to signal network n The system-level normalized weights, along with the smoothing network delays corresponding to other signal networks, are determined according to the following formula:

[0054] in, This represents the normalized weight within the network corresponding to the cabling path; This represents the system-level normalized weights corresponding to signal network n; Let N represent the set of terminals of signal network n; N represents the set of all signal networks.

[0055] The contribution weight of the corresponding path delay is obtained by multiplying the normalized weight within the network with the corresponding system-level normalized weight. The contribution weight reflects both the criticality of the wiring path within its signal network and the criticality of the signal network within the system, and is used to subsequently determine the analytical gradient cost corresponding to the physical edge.

[0056] It should be noted that the aforementioned maximum value shifting process can be used during exponent normalization to maintain the numerical stability of exponent calculation.

[0057] This embodiment performs exponential normalization processing both within the signal network and across all signal networks, so that the contribution weight of path delay includes both intra-network criticality and system-level criticality. This allows for the differentiation of the contribution of different routing paths to the global smooth maximum delay and provides a weight basis for each routing path in subsequent chain-like differentiation.

[0058] In some implementations, after obtaining the physical single-hop delay and analytical gradient cost corresponding to the physical edge, the composite edge cost corresponding to the physical edge is constructed: ; in, This represents the cost of the composite edge corresponding to physical edge e; This represents the physical single-hop delay corresponding to physical edge e; Let represent the analytical gradient cost corresponding to the physical edge e; λ represents the tradeoff coefficient that balances the scale difference between physical delay and gradient cost. Physical single-hop delay reflects the actual transmission delay of a signal passing through a physical edge, while analytical gradient cost reflects the impact of changes in physical edge load on the global smooth maximum delay. Since the physical single-hop delay and analytical gradient cost have different scales, a trade-off coefficient is used... The analytical gradient cost is scaled, and the scaled analytical gradient cost is added to the physical single-hop delay to obtain the composite edge cost corresponding to the physical edge.

[0059] Preferably, the tradeoff coefficient An empirical value of 75 is used to balance the scale difference between physical delay and gradient cost.

[0060] After obtaining the composite edge cost corresponding to the physical edge in the physical interconnection graph, the composite edge cost is determined as the path search weight of the corresponding physical edge.

[0061] In one implementation, Dijkstra's shortest path algorithm can be used to perform path search. During the path search process, candidate routing paths are evaluated according to the path search weights of physical edges, and the routing path of the signal network is determined from the candidate routing paths. This allows the actual transmission delay of physical edges and the impact of changes in physical edge load on the global smooth maximum delay to both participate in the selection of routing paths.

[0062] This embodiment constructs a composite edge cost by combining physical single-hop delay and analytical gradient cost, so that the path search weight simultaneously reflects the actual transmission delay of the physical edge and the impact of edge load changes on the global timing target. This allows the routing path selection of the signal network to take into account both local transmission cost and global timing impact, which helps to reduce the single dependence of path search on the current occupancy state of the physical edge and improve the overall timing performance of multi-FPGA systems.

[0063] In some implementations, all signal nets in the netlist to be wired are divided into multiple batches. The path search is performed sequentially according to the batches. The execution flow for each batch is as follows: At the start of this batch, the analytical gradient cost of the final state from the previous batch is used. Recalculate the composite edge cost In the first batch, a round of fast global routing can be performed to obtain the initial set of routing paths.

[0064] The edge load of the physical edge and the continuous edge load are determined based on the initial set of routing paths, and the analytical gradient cost and composite edge cost corresponding to the physical edge are calculated. The composite edge cost is used as the path search weight for the first batch.

[0065] For any batch after the first batch, at the beginning of the batch, the analytical gradient cost recalculated at the end of the previous batch is used; based on the analytical gradient cost and the physical single-hop delay, the composite edge cost is recalculated, and the composite edge cost is determined as the path search weight of the current batch.

[0066] Within the current batch, the path search weights of the physical edges remain unchanged, and path searches are performed sequentially on the signal networks in the current batch. In one implementation, Dijkstra's shortest path algorithm is used to determine the routing paths of each signal network in the current batch according to fixed path search weights. After all signal networks in the current batch have completed their path searches, the routing path set is updated based on the routing paths of all signal networks, and the edge loads of the physical edges and the continuation edge loads are re-determined based on the updated routing path set.

[0067] After the current batch ends, the analytical gradient cost corresponding to the physical edge is recalculated based on the updated routing path set. The recalculated analytical gradient cost is used to update the composite edge cost at the beginning of the next batch. Multiple batches are completed in the above manner, so that a fixed composite edge cost is used for path search within a batch, and the composite edge cost is updated based on the latest routing path set between batches.

[0068] This embodiment reduces the computational overhead of immediately recalculating all physical edge costs after performing path search on a single signal network by fixing the composite edge cost within a batch. By updating the analytical gradient cost based on all current routing paths after the batch ends, the composite edge cost updated at the start of the next batch reflects the path allocation results of the completed batch. This approach balances the timeliness of edge cost updates with the processing efficiency of batch path search and helps reduce the need for repeated teardowns and rerouting based on local congestion.

[0069] In some implementations, after obtaining the contribution weights corresponding to the wiring paths, the contribution weights are aggregated according to the signal network to which the wiring paths belong. For signal network n, the wiring paths from the source end to each sink end of the signal network are obtained, and the contribution weights corresponding to the wiring paths are summed to obtain the sum of the contribution weights corresponding to the signal network (i.e., system-level criticality). Since the contribution weights are determined by the product of the intra-network normalized weights and the system-level normalized weights, the sum of the contribution weights corresponding to the wiring paths of the same signal network and the system-level normalized weights of the signal network are considered equal. Correspondingly.

[0070] After obtaining the sum of contribution weights for each signal network, all signal networks are sorted from largest to smallest according to the sum of contribution weights, so that signal networks with larger sums of contribution weights are placed before those with smaller sums of contribution weights. Signal networks are selected sequentially along the sorting results, and the selected signal networks are divided into multiple batches, ensuring that the order of the signal networks within each batch and within each batch maintains the order corresponding to the sorting results.

[0071] When performing batch global routing, multiple batches are processed sequentially according to batch order. The first batch calculates the analytical gradient cost and composite edge cost based on the initial routing path set. At the beginning of each subsequent batch, the composite edge cost is updated using the analytical gradient cost obtained at the end of the previous batch, and the updated composite edge cost is determined as the path search weight. Signal networks with a larger sum of contribution weights are placed in earlier batches and can perform path search first after the composite edge cost is updated; signal networks with a smaller sum of contribution weights are placed in subsequent batches and regain their path search weights based on the updated routing path set of the previous batches.

[0072] This embodiment sorts signal networks in descending order based on system-level criticality and divides them into multiple batches according to the sorting results. This prioritizes signal networks that contribute significantly to global smoothing of the maximum delay by performing path search using the updated composite edge cost. This approach can preferentially allocate timing convergence pressure to signal networks that affect global timing, which is beneficial for prioritizing the improvement of routing paths for bottleneck signal networks and promoting the convergence of the maximum delay of the entire network.

[0073] In some implementations, the set of signal networks passing through physical edge e is determined based on the set of wiring paths. The number of signal networks in the signal network set As the edge load of physical edge e, and with The number of parallel physical channels for physical edge e is represented by the ratio of edge load to edge capacity. The ratio of edge load to edge capacity represents the time-division multiplexing (TDM) ratio corresponding to physical edge e. The TDM scheduling delay corresponding to the physical edge is determined by the following formula:

[0074] The physical single-hop delay corresponding to physical edge e is determined by the following formula:

[0075] in, This represents the TDM scheduling delay corresponding to physical edge e; This represents the physical single-hop delay corresponding to physical edge e; Set constants for the hardware.

[0076] Preferably, .

[0077] when When the number of signal networks passing through physical edge e exceeds the number of parallel physical channels of the physical edge, the physical edge needs to use TDM to transmit multiple signal networks.

[0078] After determining the time-division multiplexing ratio corresponding to the physical edge, the contribution weights corresponding to the path delay of the signal network to which the cabling path belongs are used. For any signal network, the contribution weights corresponding to the cabling paths of that signal network are summed to obtain the sum of contribution weights corresponding to that signal network (i.e., system-level criticality). The sum of contribution weights is then compared with the system-level normalized weight of the signal network. Correspondingly, a value is used to characterize the contribution of the signal network to the global smoothing maximum delay. Signal networks with a large sum of contribution weights and a system-level criticality close to 1 are classified as critical networks, while signal networks with a small sum of contribution weights are classified as non-critical networks.

[0079] During path search for non-critical networks, physical edges with a time-division multiplexing ratio (TDM) greater than 1 are identified, and their path search weights are temporarily set to infinity during the Dijkstra path search performed on these non-critical networks. These physical edges do not participate in the candidate cabling path search for non-critical networks, allowing non-critical networks to select physical edges where TDM multiplexing has not occurred or where the TDM multiplexing level is low. This infinity setting only takes effect during the path search for the corresponding non-critical network.

[0080] When performing path search on the critical network, the infinity setting is not applied to physical edges with a time-division multiplexing ratio greater than 1. The original path search weights of these physical edges remain unchanged, allowing the critical network to still search for wiring paths passing through them. The critical network can select the corresponding physical edge based on its original path search weights, while non-critical networks will detour through other available physical channels. This prioritizes physical edges with higher time-division multiplexing ratios for signaling networks that have a greater impact on global timing.

[0081] This embodiment employs different physical edge usage strategies for critical and non-critical networks based on the sum of the time-division multiplexing ratio (TDM) and contribution weight. This guides non-critical networks to avoid physical edges with a TDM greater than 1, while preserving path selection space for critical networks to use corresponding physical edges. This approach helps reduce the occupation of high-TDM physical edges by non-critical networks, alleviates TDM scheduling delays for critical networks, and improves the timing utilization efficiency of fixed physical resources without adjusting the physical interconnection topology.

[0082] In some implementations, after completing multiple batches of path searches, the currently obtained set of target routing paths is determined as the current solution for strictly backtracking iterative redistribution, and candidate updates are evaluated according to a non-loss criterion. This applies to the routing paths of a signal network n from the source to the sink t. The path delay of the wiring path is determined according to the following formula:

[0083] in, This represents the physical single-hop delay corresponding to physical edge e.

[0084] Based on the path delays of each cabling path within the same signal network, the network delay corresponding to signal network n is determined using the following formula:

[0085] in, Let represent the set of terminals of signal network n. Based on the network delays corresponding to all signal networks, the target maximum path delay corresponding to the target cabling path set is determined according to the following formula:

[0086] Here, N represents the set of all signal networks. Signal networks whose network delay reaches the target maximum path delay are identified as target bottleneck networks, and the number of target bottleneck networks is counted to obtain the target bottleneck network count. The target maximum path delay and the target bottleneck network count together constitute the evaluation result of the current solution.

[0087] Select a signal network from the target routing path set, remove the original routing path of the selected signal network, and re-execute the path search based on the current path search weight to obtain candidate routing paths. Write the candidate routing paths into the temporary candidate state, replacing the original routing paths of the selected signal network, to obtain a candidate routing path set. In the temporary candidate state, determine the network delay corresponding to each signal network using the same calculation method as the target routing path set, and determine the maximum candidate path delay and the number of candidate bottleneck networks corresponding to the candidate routing path set.

[0088] Let the maximum path delay corresponding to the candidate routing path set be denoted as . The maximum path delay corresponding to the target routing path set is denoted as... When the following equation is satisfied, it indicates that the set of candidate routing paths increases the maximum path delay of the current solution:

[0089] When the candidate maximum path delay is greater than the target maximum path delay, discard the candidate routing path set and restore the original routing path of the selected signal network. When the candidate maximum path delay does not increase, but the number of candidate bottleneck networks is greater than the number of target bottleneck networks, also discard the candidate routing path set and restore the target routing path set.

[0090] When the candidate maximum path delay is not greater than the target maximum path delay and the number of candidate bottleneck networks is not greater than the number of target bottleneck networks, the candidate routing path set is accepted and the target routing path set is updated according to the candidate routing path set.

[0091] In one implementation, after receiving the set of candidate routing paths, the analytical gradient cost is recalculated based on the updated set of target routing paths. and composite edge cost Then, the updated composite edge cost is used to evaluate the next candidate update.

[0092] This embodiment employs a non-loss criterion to simultaneously evaluate the maximum path delay and the number of bottleneck networks in the candidate routing path set. If a candidate update leads to an increase in the maximum path delay or the number of bottleneck networks, the target routing path set before the update is restored. Candidate updates are accepted when the corresponding indicators have not deteriorated. This approach limits the adverse impact of iterative rerouting on the current timing results, helps maintain the non-deteriorating trend of the maximum delay and the number of bottleneck networks across the entire network, and promotes timing convergence after routing.

[0093] In some implementations, for a physical edge e, the set of signal networks passing through the physical edge is represented as... ,definition Let be the number of networks that pass through edge e.

[0094] Intra-network smoothing and inter-network smoothing from Reverse chain derivative to Substitute:

[0095] in, This indicates the indicator function corresponding to the routing path. When passing through physical edge e, the indicator function takes a value of 1; when the wiring path When the path does not pass through physical edge e, the indicator function takes a value of 0. Based on the indicator function, associated paths that pass through physical edge e can be filtered from the set of wiring paths.

[0096] For the selected associated paths, the product of the system-level normalized weight corresponding to signal network n and the network-level normalized weight corresponding to the associated path is taken as the contribution weight of the associated path. These contribution weights are then summed to obtain the sum of the contribution weights corresponding to physical edge e. This sum of contribution weights reflects both the criticality of the wiring path passing through physical edge e within its respective signal network and the criticality of that signal network within all signal networks.

[0097] This embodiment uses a continuous approximation to represent the relationship between physical single-hop delay and continuous edge load. Based on edge capacity... and preset delay coefficient The rate of change of delay is determined by the following formula:

[0098] Preset delay factor 0.7 can be taken.

[0099] Multiplying the sum of the contribution weights corresponding to physical edge e by the rate of change of delay yields a closed-form expression for the analytical gradient cost:

[0100] Among them, analytical gradient cost This represents the maximum global smooth delay increment caused by increasing the edge load of physical edge e by one unit, and serves as the basis for global temporal evaluation of the physical edge in subsequent path search. Analytical gradient cost. The computational complexity is ,in, It represents the number of physical edges in the physical interconnect graph, and the incremental update after routing within a single batch is in near-linear time.

[0101] This embodiment obtains the analytical gradient cost corresponding to the physical edge by filtering the routing paths associated with the physical edge through relational filtering and multiplying the sum of the contribution weights of the associated paths by the rate of change of the physical single-hop delay. This allows the marginal impact of the physical edge load change on the global smooth maximum delay to be directly calculated through a closed expression. The incremental update after routing in a single batch is completed in near-linear time, which helps to reduce the computational overhead of edge-level cost updates in large-scale multi-FPGA systems.

[0102] Based on the same inventive concept, this application also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform: a wiring path allocation method for a multi-FPGA system as described in any embodiment of this application.

[0103] like Figure 2 As shown in the schematic diagram of the electronic device 500 in this application, the electronic device 500 is merely an example and should not be construed as limiting the function and scope of use of the embodiments of this application.

[0104] The electronic device 500 may include: at least one processor 510; and a memory 520 communicatively connected to the at least one processor; wherein the memory 520 stores instructions executable by the at least one processor 510, the instructions being executed by the at least one processor 510 to enable the at least one processor 510 to perform: the wiring path allocation method for a multi-FPGA system according to any embodiment of this application.

[0105] It should be noted that the electronic device 500 can be represented in the form of a general-purpose computing device, such as a server device.

[0106] In practice, the components of electronic device 500 may include, but are not limited to: at least one processor 510, at least one memory 520, and a bus 530 connecting different system components (including memory 520 and processor 510), wherein bus 530 may include a data bus, an address bus, and a control bus.

[0107] In implementation, memory 520 may include volatile memory, such as random access memory (RAM) 5201 and / or cache memory 5202, and may further include read-only memory (ROM) 5203.

[0108] The memory 520 may also include a program tool 5205 having a set (at least one) of program modules 5204, including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0109] The processor 510 performs various functional applications and data processing by running computer programs stored in the memory 520.

[0110] Electronic device 500 can also communicate with one or more external devices 540 (e.g., keyboard, pointing device, etc.). This communication can be performed through input / output (I / O) interface 550. Furthermore, electronic device 500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public network, such as the Internet) via network adapter 560, which communicates with other modules in electronic device 500 via bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems.

[0111] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the descriptions of the embodiments described later are relatively simple, and relevant parts can be referred to the descriptions of the foregoing embodiments.

[0112] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A routing path allocation method for a multi-FPGA system, characterized in that, include: Obtain a physical interconnection diagram, a netlist to be routed, and a set of routing paths. The physical interconnection diagram includes physical edges and the edge capacity corresponding to the physical edges. The set of routing paths includes the routing paths of the signal nets in the netlist to be routed. Based on the set of wiring paths, the edge load corresponding to the physical edge is obtained, and the edge load is the number of signal networks passing through the corresponding physical edge; Based on the edge load and the edge capacity, the physical single-hop delay corresponding to the physical edge is obtained; Determine the relationship between the wiring path and the physical edge; Based on the physical single-hop delay and the traversal relationship, the path delay corresponding to the wiring path is obtained; The path delay is smoothed and aggregated using a logarithmic exponent and a function to obtain the global smoothed maximum delay and the contribution weight corresponding to the path delay. The contribution weight represents the degree of contribution of the path delay to the global smoothed maximum delay. The edge load is processed to become a continuous edge load; Using the continuous edge load as the derivative variable, and based on the contribution weight and the traversal relationship, perform chain-like differentiation on the global smoothing maximum delay to obtain the analytical gradient cost corresponding to the physical edge; Based on the analytical gradient cost, a path search is performed on the signal nets in the netlist to be routed in the physical interconnect graph to obtain the target routing path set.

2. The routing path allocation method for a multi-FPGA system according to claim 1, characterized in that, The method of smoothing and aggregating the path delay using a logarithmic exponent and a function includes: The path delays of the same signal network are first smoothed and aggregated to obtain the smoothed network delays corresponding to the signal network. A second smoothing aggregation is performed on the smoothed network delay to obtain the global smoothed maximum delay.

3. The routing path allocation method for a multi-FPGA system according to claim 2, characterized in that, Based on the path delay of the same signal network and the smoothing network delay, the path delay is exponentially normalized to obtain the intra-network normalized weight, which corresponds to the path delay. Based on the smoothing network delay and the global smoothing maximum delay, the smoothing network delay is exponentially normalized to obtain system-level normalized weights, which correspond to the signal network. The contribution weight is obtained by multiplying the intra-network normalized weight and the corresponding system-level normalized weight.

4. The routing path allocation method for a multi-FPGA system according to claim 1, characterized in that, The step of performing path search on the signal nets in the netlist to be routed in the physical interconnect graph based on the analytical gradient cost includes: Based on the physical single-hop delay and the analytical gradient cost, construct the composite edge cost corresponding to the physical edge: ； in, This represents the cost of the composite edge corresponding to physical edge e; This represents the physical single-hop delay corresponding to physical edge e; Let represent the analytical gradient cost corresponding to the physical edge e; λ represents the tradeoff coefficient that balances the scale difference between physical delay and gradient cost. The cost of the composite edge is determined as the path search weight of the physical edge; Path search is performed based on the path search weights.

5. The routing path allocation method for a multi-FPGA system according to claim 4, characterized in that, The step of performing path search based on the path search weight includes: Divide the signal networks in the netlist to be wired into multiple batches; At the start of the first batch, the analytical gradient cost is obtained based on the set of routing paths, and the composite edge cost is updated. At the beginning of each subsequent batch, the composite edge cost is updated using the analytical gradient cost obtained at the end of the previous batch. The updated composite edge cost is determined as the path search weight; Within the batch, the path search weight remains unchanged, and path search is performed sequentially on the signal network in the batch; Update the wiring path set based on the results of the path search; The analytical gradient cost is updated based on the updated set of routing paths, and the analytical gradient cost is used for the next batch of composite edge cost updates.

6. The routing path allocation method for a multi-FPGA system according to claim 5, characterized in that, The step of dividing the signal networks in the netlist to be wired into multiple batches includes: The contribution weights of the wiring paths for the same signal network are summed to obtain the sum of the contribution weights corresponding to the signal network. The signal networks are sorted from largest to smallest based on the sum of their contribution weights; The signal network is divided into multiple batches according to the sorting results.

7. The routing path allocation method for a multi-FPGA system according to claim 4, characterized in that, The step of performing path search based on the path search weight includes: Based on the edge load and the edge capacity, the time-division multiplexing ratio corresponding to the physical edge is obtained; The contribution weights of the wiring paths for the same signal network are summed to obtain the sum of the contribution weights corresponding to the signal network. Based on the sum of the contribution weights, the signal network is divided into critical networks and non-critical networks; During the path search of the non-critical network, the path search weight of the physical edges with a time-division multiplexing ratio greater than 1 is set to infinity; When performing path search on the critical network, the path search weight of physical edges with a time-division multiplexing ratio greater than 1 remains unchanged.

8. The routing path allocation method for a multi-FPGA system according to claim 5, characterized in that, The method further includes: After completing the multiple batches, the target maximum path delay is determined based on the target wiring path set; The target number of bottleneck networks is determined based on the target maximum path delay, where the target number of bottleneck networks is the number of signal networks that reach the target maximum path delay. Select a signal network from the target wiring path set, and re-execute the path search according to the path search weight to obtain candidate wiring paths; Replace the wiring path of the signal network with the candidate wiring path to obtain a set of candidate wiring paths; The candidate maximum path delay is determined based on the set of candidate wiring paths; The number of candidate bottleneck networks is determined based on the candidate maximum path delay, where the number of candidate bottleneck networks is the number of signal networks that reach the candidate maximum path delay. When the candidate maximum path delay is greater than the target maximum path delay, or the number of candidate bottleneck networks is greater than the target number of bottleneck networks, the candidate cabling path set is discarded. Otherwise, update the target routing path set based on the candidate routing path set.

9. The routing path allocation method for a multi-FPGA system according to claim 1, characterized in that, The analytical gradient cost is determined in the following way: Based on the described relationship, determine the associated path that passes through the physical edge from the wiring path; The sum of the contribution weights corresponding to the associated paths is obtained by summing the contribution weights corresponding to the physical edges. Based on the edge capacity and the preset delay coefficient, the delay change rate is obtained, whereby the delay change rate represents the change in physical single-hop delay when the continuous edge load undergoes a unit change. The analytical gradient cost is obtained by multiplying the sum of the contribution weights by the rate of change of delay.

10. An electronic device, characterized in that, include: At least one processor; And a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform: the wiring path allocation method for a multi-FPGA system as described in any one of claims 1 to 9.

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