Method, system and computer device for automatic identification of potential paths of a circuit

Abstract

This invention provides an automatic identification method, system, and computer device for potential circuit paths. The method includes: abstracting the state of each physical element in the actual circuit connection diagram of the circuit system into a state value of a corresponding three-value resistor, and constructing a state vector of the circuit system; inputting the state vector into a potential circuit identification neural network model, and outputting a functional output value of the circuit system; and determining whether each function of the circuit system is normal and whether potential paths exist based on the functional output value. By converting physical element data into three-value resistors that can be accurately numerically represented, different states of different physical elements are accurately mapped, achieving precise characterization of different states of different physical elements in circuit design; enabling accurate automated analysis and efficient identification of potential paths in large and complex circuit system designs, eliminating errors from manual identification, and improving the accuracy of potential path detection.

Description

Technical Field

[0001] This invention relates to the field of circuit testing, and more specifically to an automatic identification method, system, and computer device for potential circuit paths. Background Technology

[0002] In the design of launch vehicle electrical systems, potential pathways exist, such as unexpected current paths and abnormal timing sequences. These potential pathways are design flaws that can seriously affect the reliability of the launch vehicle. Therefore, it is necessary to identify potential pathways to ensure that there are no unexpected current paths or abnormal timing sequences in the design, thereby improving the overall system reliability and safety. Thus, potential pathway identification is crucial for rocket electrical system design.

[0003] Currently, there are two main types of Sneakircuit Analysis (SCA) techniques both domestically and internationally: comprehensive SCA and simplified SCA. Comprehensive SCA attempts to reveal all functions and behaviors within a system. Its drawbacks include the need for network tree generation and topology identification algorithms adapted to the system scale, and the fact that comprehensive SCA can only be performed after design completion and before product manufacturing. Even if potential paths are discovered, the cost of modifying the entire system design is enormous. For example, relying on manual identification of potential paths requires analyzing circuit diagrams and wiring tables, manually acquiring topology data, identifying paths, compiling thread lists, obtaining component lists, performing function-path mapping according to functional specifications, manually checking each path during potential path identification, generating Fault Mode and Effects Analysis (FMEA), and finally producing an analysis report. According to NASA standard SAE ARP4761, the average time taken is >50 hours per system. For instance, NASA research report FAC-TR-2020-001 indicates that satellite power system analysis takes an average of 89 hours. These factors limit the widespread adoption of Sneakircuit analysis techniques.

[0004] Simplified SCA (Simplified Path Analysis) is divided into two types: latent path analysis and design defect analysis. Latent path analysis searches for all paths between the "source" and "target" points and applies two types of cues to identify potential paths. Design defect analysis, on the other hand, uses component-level cues to identify design defects. These design defects are not directly related to the source / target relationship, and design defect analysis serves as a supplement to latent path analysis. Both have been successfully applied in relevant fields. However, SCA has also encountered problems in its application, such as the enormous workload and error-prone nature of inputting data into electronic systems; difficulties in obtaining cue lists; difficulties in modeling complex components; and the generation of false latent path reports. Summary of the Invention

[0005] This invention provides an automatic identification method, system, and computer device for potential circuit paths, which can solve the technical problems of complex identification process, large workload, low identification efficiency, and low identification accuracy in the prior art.

[0006] To achieve the above objectives, in a first aspect, embodiments of the present invention provide an automatic identification method for potential circuit paths, comprising:

[0007] The state of each physical element in the actual circuit connection diagram of the circuit system is abstracted into a state value of the corresponding three-value resistor state, and the state vector of the circuit system is constructed.

[0008] Input the state vector into the potential circuit recognition neural network model, and output the functional output value of the circuit system.

[0009] Based on the functional output values, determine whether each function of the circuit system is normal, and whether there are any potential pathways.

[0010] Specifically, the states of each physical component in the actual circuit connection diagram of the circuit system are abstracted into a state value of the corresponding three-value resistor state, and the state vector of the circuit system is constructed, including:

[0011] A three-value resistor model is adopted. Based on the three-value resistor state mapping rules of each physical element and the connection topology of each physical element in the actual circuit connection diagram, each physical element is abstracted into a state value of the three-value resistor state.

[0012] The circuit system state vector is constructed based on the state values ​​of all physical components. The dimension of the circuit system state vector is the same as the number of physical components.

[0013] Specifically, the automatic identification method for potential paths in this circuit also includes the step of constructing a three-value resistor state mapping rule:

[0014] The parameter information of each physical component is standardized based on the component list of the circuit system to obtain the type and parameters of each physical component;

[0015] Based on the component type and parameters of each physical element, the three-value resistor model abstracts each physical element into a three-value resistor, resulting in the three-value resistor state mapping rule for each physical element. The three-value resistor states include open circuit state, physical element state during circuit system operation, and open circuit state.

[0016] Specifically, the method for automatically identifying potential paths in a circuit also includes:

[0017] Design data on circuit connection relationships are extracted from the circuit schematic of the self-circuit system through image processing and topology analysis.

[0018] The wiring diagram of the circuit system is analyzed to obtain the actual wiring data;

[0019] By merging the circuit connection design data and the actual wiring data, the actual circuit connection diagram of the circuit system is obtained;

[0020] Construct a list of physical components, which includes a unique identifier for each physical component in the actual circuit connection diagram, as well as a physical component association matrix, which refers to the other physical components or nodes to which a physical component is connected.

[0021] Specifically, the state vector is input into the latent circuit recognition neural network model, and the output circuit system's functional output values ​​include:

[0022] The number of neurons in the input layer of the latent circuit recognition neural network model is set to the number of all physical components of the circuit system, and the number of neurons in the output layer of the latent circuit recognition neural network model is set to the number of functions of all physical components of the circuit system; wherein, each function to be implemented by the circuit system is extracted from the functional specification document of the circuit system;

[0023] The state vector is input into the latent circuit recognition neural network model, and the output values ​​of each function that the circuit system is to achieve are output.

[0024] Specifically, based on the functional output values, it is determined whether each function of the circuit system is normal and whether there are any potential pathways, including:

[0025] The status of a function is determined based on its function type and output value during normal operation of the circuit system; the function type of each function is either a normal function or an emergency function.

[0026] If the function is functioning normally, when the function output value is greater than or equal to the first output threshold, it is determined that the function is functioning normally and is at a low risk level.

[0027] When the function output value is less than the first output threshold but greater than or equal to the second output threshold, it is determined to be a function warning, which is a medium-risk level.

[0028] When the function output value is less than the second output threshold and greater than or equal to the third output threshold, it is determined to be a function failure, indicating a potential path risk, which is classified as a high-risk level.

[0029] When the function output value is less than the third output threshold, the function is determined to be completely failed, which is a serious risk level.

[0030] If the function is an emergency function, and the function output value is not greater than the third output threshold, the function is determined to be safe and at a low risk level.

[0031] When the function output value is greater than the third output threshold, the function is determined to be at risk, and is classified as low risk.

[0032] Specifically, the method for automatically identifying potential paths in a circuit also includes:

[0033] Based on the functional and physical component association matrix and connection topology, the functions with faults and functions with risks are traced backward. Through the intersection analysis and sensitivity positioning of physical components, the specific component combinations and potential paths that lead to the functions with faults and functions with risks are identified, and a potential path report is generated. The potential path report includes the function output value, judgment result, risk level, potential path list, potential path description, fault cause tracing, and suspect component list.

[0034] A risk level assessment report is generated based on the risk level.

[0035] Repair recommendations for the circuit system are generated based on potential pathway reports and risk level assessment reports.

[0036] Secondly, embodiments of the present invention provide an automatic identification system for potential circuit paths, comprising:

[0037] The ternary resistor construction unit is used to abstract the state of each physical element in the actual circuit connection diagram of the circuit system into a state value of the corresponding ternary resistor state, and to construct the state vector of the circuit system.

[0038] The recognition unit is used to input the state vector into the potential circuit recognition neural network model and output the functional output value of the circuit system.

[0039] The intelligent judgment unit is used to determine whether each function of the circuit system is normal and whether there are any potential pathways based on the function output value.

[0040] Specifically, the three-value resistor building unit is used for:

[0041] A three-value resistor model is adopted. Based on the three-value resistor state mapping rules of each physical element and the connection topology of each physical element in the actual circuit connection diagram, each physical element is abstracted into a state value of the three-value resistor state.

[0042] The circuit system state vector is constructed based on the state values ​​of all physical components. The dimension of the circuit system state vector is the same as the number of physical components.

[0043] Specifically, the automatic identification system for potential pathways of the circuit also includes a mapping rule construction unit for:

[0044] The parameter information of each physical component is standardized based on the component list of the circuit system to obtain the type and parameters of each physical component;

[0045] Based on the component type and parameters of each physical element, the three-value resistor model abstracts each physical element into a three-value resistor, resulting in the three-value resistor state mapping rule for each physical element. The three-value resistor states include open circuit state, physical element state during circuit system operation, and open circuit state.

[0046] Specifically, the automatic identification system for potential circuit paths also includes an actual circuit connection diagram construction unit, used for:

[0047] Design data on circuit connection relationships are extracted from the circuit schematic of the self-circuit system through image processing and topology analysis.

[0048] The wiring diagram of the circuit system is analyzed to obtain the actual wiring data;

[0049] By merging the circuit connection design data and the actual wiring data, the actual circuit connection diagram of the circuit system is obtained;

[0050] Construct a list of physical components, which includes a unique identifier for each physical component in the actual circuit connection diagram, as well as a physical component association matrix, which refers to the other physical components or nodes to which a physical component is connected.

[0051] Thirdly, embodiments of the present invention provide a computer-readable storage medium that stores one or more programs, which, when executed by a computer device, enable the automatic identification of potential pathways for circuits that allow the computer device to execute any of the foregoing items.

[0052] Fourthly, embodiments of the present invention provide a computer device, comprising:

[0053] A processor; and a method for automatically identifying potential pathways of a circuit that, when executed, causes the processor to perform any of the foregoing.

[0054] The above technical solution has the following beneficial effects: by converting the collected data of various basic physical components into a state value of a three-value resistor that can be accurately numerically represented, the different states of different physical components can be accurately mapped, thereby achieving accurate representation of the different states of different physical components in circuit design; then, it is used as input to the potential circuit identification neural network model for intelligent analysis, thereby achieving accurate and automated analysis and efficient identification of potential paths in large and complex circuit systems, eliminating errors in manual identification, improving the accuracy of potential path investigation, and reducing workload. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a flowchart of an automatic identification method for potential circuit paths according to an embodiment of the present invention;

[0057] Figure 2 This is a schematic diagram of the structure of an automatic identification system for potential circuit paths according to an embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of the neural network feedforward structure according to an embodiment of the present invention;

[0059] Figure 4 This is the principle for determining the value of 𝛼 in the embodiments of the present invention;

[0060] Figure 5 This is the algorithm training process according to an embodiment of the present invention;

[0061] Figure 6 This is the functional decision process of an embodiment of the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] like Figure 1 As shown, in conjunction with embodiments of the present invention, an automatic identification method for potential circuit paths is provided, comprising:

[0064] S101: Abstract the state of each physical element in the actual circuit connection diagram of the circuit system into a state value of the corresponding three-value resistor state, and construct the state vector of the circuit system;

[0065] S102: Input the state vector into the latent circuit recognition neural network model and output the functional output value of the circuit system;

[0066] S103: Based on the function output value, determine whether each function of the circuit system is normal and whether there are any potential paths.

[0067] By converting various collected basic physical component data into one state value of the ternary resistance state that can be accurately numerically characterized, different states of different physical components can be accurately mapped, thereby realizing the accurate characterization of different states of different physical components in circuit design; then the state value is used as the input of the latent circuit identification neural network model for intelligent analysis, so as to realize the accurate automatic analysis and efficient identification of whether there is a latent path in a large and complex circuit system, eliminate the error of manual identification, improve the troubleshooting accuracy of latent paths, and reduce the workload.

[0068] Preferably, S101: abstracting the state of each physical component in the actual circuit connection diagram of the circuit system into a corresponding state value of the ternary resistance state, and constructing a state vector of the circuit system, comprising:

[0069] Using a ternary resistance model, according to the ternary resistance state mapping rule of each physical component, and based on the connection topology of each physical component in the actual circuit connection diagram, each physical component is abstracted into one state value in the ternary resistance state;

[0070] The circuit system state vector is constructed based on the state values of all physical components, and the dimension of the circuit system state vector is the same as the number of physical components.

[0071] The parameters and type of each physical component are obtained by processing the component list, a ternary resistance model is adopted, and the ternary state mapping rule of each component is defined. Based on the connection topology (that is, how to connect) of each physical component in the actual circuit connection diagram, the physical component is abstracted, that is, mapped to one state value in the ternary resistance state {0, L, 1} according to the ternary state mapping rule; wherein the ternary resistance satisfies 0<L<1, where 0 represents a short-circuit state, L represents a load state and satisfies 0<L<1, and 1 represents an open-circuit state.

[0072] For the construction of the system state vector, assuming that the circuit system has n physical components, and each physical component corresponds to one state value of the ternary resistance state, then the state of the circuit system can be represented by an n-dimensional vector, and each value is 0, 1 or L, which means that each physical component can only be in one physical state at the same time; determined by the ternary resistance, the half-fault state can be accurately characterized without losing the real state information of the physical component.

[0073] Preferably, the automatic identification method for the latent path of the circuit further comprises S104: a step of constructing a ternary resistance state mapping rule:

[0074] Standardize the parameter information of each physical component according to the component list of the circuit system to obtain the type and parameter of each physical component;

[0075] Through the ternary resistance model, each physical element is abstracted into a ternary resistance according to the element type and parameter of each physical element, so as to obtain the ternary resistance state mapping rule of each physical element. The ternary resistance states include a short-circuit state, a state of the physical element during operation of the circuit system, and an open-circuit state.

[0076] According to the parameters and type of each physical element and the physical characteristics of the physical element, a ternary resistance model is adopted to define the ternary state mapping rule of each element. Based on the connection topology (that is, the connection mode) of each physical element in the actual circuit connection diagram, the ternary state mapping rule means that the physical element is abstracted, that is, mapped to a ternary resistance state {0, L, 1}; where the ternary resistance satisfies 0<L<1, 0 represents the short-circuit state, L represents the load state and satisfies 0<L<1, and 1 represents the open-circuit state. L is dynamically optimized through historical load data, and the L value is calculated by the formula L= dynamic calculation, is the measured current of the physical element, is the rated current; L is a real number between 0 and 1.

[0077] For example, the relay state mapping rule means that the closed state is mapped to 0, the open state is mapped to 1, and when L represents the half-pull-in state, it is calculated based on the ratio of the actual current to the rated current;

[0078] The fuse state mapping rule means that the short-circuit state is 0, the normal state is mapped to L=0.6, and the open state is mapped to 1;

[0079] The switch state mapping rule means that the closed state is mapped to 0, the open state is mapped to 1, and the poor contact state is mapped to L=0.5;

[0080] The diode state mapping rule means that the conducting state is mapped to 0, the open state is mapped to 1, and L represents the leakage state, which is calculated based on the magnitude of the leakage current;

[0081] The specific mapping rules of different physical elements and the calculation method of the L value can be defined respectively according to the physical characteristics of the elements. Such state values with unified structure and different parameters not only ensure the standardization of the input of the subsequent neural network model, which is beneficial to the processing of the neural network, but also take into account the physical differences of different physical elements.

[0082] Abstracting each physical element into a plurality of state values can reflect the physical differences of different physical elements, which are used as the input of the circuit identification neural network model, so as to improve the identification accuracy of the latent path.

[0083] Preferably, the method for automatically identifying a latent path in a circuit further comprises:

[0084] S105: Extract circuit connection design data from the circuit schematic of the circuit system through image processing and topology analysis;

[0085] Specifically, the component list and physical component-node connections (i.e., topology) of a circuit system are automatically extracted from circuit schematic images such as PDFs and pictures. The steps are as follows:

[0086] The input circuit schematic image undergoes preprocessing, such as binarization, noise reduction, and tilt correction, to obtain a preprocessed image. Within the preprocessed image, component detection and identification are performed, including component type and pin endpoint location, wire extraction, and detection of key points such as nodes and intersections. A topology analysis phase is then conducted, including connectivity analysis of wire-component pin matching, assigning a unique ID to each electrical common point (node) to implement node numbering, constructing a physical component-node association matrix, generating a connection list, and finally generating a component list.

[0087] Preprocessing refers to converting the file into a high-resolution bit image using a parsing library (such as PDFium or PyMuPDF). Image grayscale and binarization refer to converting color / grayscale images into black-and-white binary images to distinguish between the background (white) and the foreground (lines, symbols). Denoising refers to removing isolated noise points using median filtering or morphological opening operations. Tilt correction refers to finding horizontal / vertical reference lines in the drawing using Hough line detection, calculating the tilt angle, and rotating to correct it.

[0088] Component detection and recognition employ a strategy combining template matching and deep learning-based object detection. A pre-built component symbol template library (relays, switches, fuses, resistors, capacitors, diodes, etc.) is established, with each template containing shape contours, pin positions, and orientation information. Template matching involves using normalized cross-correlation (NCC) to match templates for standardized circuit diagrams, locating component positions and types. For symbol deformations or hand-drawn diagrams, object detection models such as YOLOv8 are used. The training dataset can be generated by applying random affine transformations and adding noise to standard templates, eliminating the need for extensive manual annotation. Pin endpoint extraction involves calculating the precise pixel coordinates of the pin endpoints in the image for each identified component, based on its type and orientation (e.g., the two pins of a relay are located at the left and right ends of the component's bounding box).

[0089] Erosion is performed on a binary image to reduce the width of the wires to a single pixel (skeletonization), often using the Zhang-Suen thinning algorithm. Wire tracing involves starting from the endpoints of the wire skeleton and traversing all pixels using depth-first search (DFS) to record the wire path. Branch point detection identifies a wire branch point (i.e., a node) when a pixel has three or more connected components within its eight-neighborhood. This process leads to wire extraction.

[0090] A solid dot marking at a wire intersection indicates an electrical connection; otherwise, it's a jumper (no connection). A component pin connection is defined as a connection where the distance between the wire endpoint and the component pin endpoint is less than a threshold (e.g., 10 pixels). This enables key point detection and extraction.

[0091] The topology analysis phase includes:

[0092] Connectivity analysis and matching, specifically wire and pin matching, involves calculating the Euclidean distance from each wire's endpoint to the endpoints of all component pins, and selecting the pin with the closest distance as the connection object. Forming a connection pair involves recording a triplet of (component ID, pin number, node ID). All pins on the same node belong to the same electrical common point.

[0093] The algorithm iterates through all connected pairs, assigning the same node number (N1, N2, ...) to sets of interconnected pins. It constructs an undirected graph where nodes are "pins" and edges are "wire connections," using a union-find dataset to label connected components.

[0094] Construct a component-node association matrix. Assume the system has P component pins (each two-pin component contributes 2 rows, multi-pin components are represented by the actual number of pins) and M nodes. Construct a matrix A with dimensions P×M. The value rules are: A[i][j]=1 indicates the i-th pin is connected to node j, A[i][j]=0 indicates no connection. Simultaneously, store the mapping table from pins to component IDs for easy reverse lookup.

[0095] Generate a netlist (connection list) and output it in text format. For example, for component K1 (relay), pin 1, node N1, pin 2, node N2; for component F1 (fuse), pin A, node N2, pin B, node N3..., where the connection on node N refers to K1 (pin 2) and F1 (pin A).

[0096] Wiring tables typically include wire numbers, starting component pins, and ending component pins. Cross-validation involves comparing the connection relationships obtained from image processing with the wiring table's analysis results. If conflicts exist (e.g., the image shows a connection but the wiring table does not), the wiring table takes precedence (as it represents the original design data). Using wiring tables (Excel / CSV format) as input improves reliability.

[0097] When poor image quality (such as blurriness or occlusion) causes some connections to be unrecognizable, the wiring table data is used to complete the identification; conversely, certain details missing from the wiring table (such as node positions) can be supplemented by the image. This achieves complementary enhancement.

[0098] S106: Analyze the wiring table of the circuit system to obtain the actual wiring data;

[0099] S107: Combine the circuit connection design data and the actual wiring data to obtain the actual circuit connection diagram of the circuit system;

[0100] S108: Construct a list of physical components, which includes a unique identifier for each physical component in the actual circuit connection diagram, as well as a physical component association matrix, which refers to the other physical components or nodes to which the physical components are connected.

[0101] A node is an electrical connection point in a circuit topology (a common electrical point where the pins of two or more components in a circuit are connected to each other). All component pins connected to the same node have the same potential. Each node is assigned a unique identifier (such as N1, N2, ...).

[0102] Unique identifiers can represent different physical components, facilitating searching and marking throughout the process. After extracting the association mapping relationship between the physical component and its connected nodes based on the physical component's unique identifier, a physical component association matrix or connection list is formed. When a functional problem is discovered, the specific issue can be located based on the physical component and its corresponding physical component association matrix.

[0103] Specifically, a physical component association matrix, also known as a physical component-node association matrix (or "component-node association matrix" or "branch-node association matrix"), is used. This matrix describes the connection relationship between the pins of each component in the system and the electrical nodes. Rows correspond to each component pin in the circuit system (or can be considered as the component itself; this can be simplified for two-pin components), and columns correspond to each electrical node in the circuit system. Element values ​​are: +1 indicates that current flows into the node from the component pin (or is conventionally defined as positive), -1 indicates that current flows out of the node from the component pin, and 0 indicates that the component pin is not connected to the node. Since only the connection relationship needs to be known and the current direction does not need to be analyzed, it is simplified to an element value of 1 indicating that the component pin is connected to the node, and 0 indicating no connection. The matrix dimension is as follows: Assume there are N physical components in the system, each component has an average of p pins (commonly p=2 for two-pin components, relays may have multiple pins). The total number of pins is P. Assume there are M electrical nodes in the system. Then the dimension of the component-node connection matrix is ​​P×M (or N×M, if each component is simplified to an endpoint, but the accuracy is lower). For clarity, this patent uses a P×M matrix.

[0104] Row indexes represent unique row numbers for each pin of each component. Column indexes represent unique column numbers (e.g., N1, N2, ..., Nm) for each electrical node.

[0105] The physical component list is a table, as shown in Table 1, which records the necessary fields for each component.

[0106] Table 1

[0107] The connection information obtained from the circuit schematic recognition module and the wiring table parsing module is used to construct a physical component association matrix through the following steps:

[0108] Node numbering refers to traversing all wire connection points in the circuit diagram (including component pin connections, wire junctions, power / ground wires) and assigning a unique node identifier (N1, N2, ...) to each electrical common point. Component pin mapping refers to determining the node ID to which each pin of each component is connected. Constructing the initial matrix refers to creating an all-zero matrix with the number of rows equal to the total number of pins and the number of columns equal to the total number of nodes. Filling the matrix refers to setting matrix element A[i][j] = 1 for each pin i connected to node j. Storing the mapping relationship refers to saving a table of correspondences between component IDs, pin IDs, and matrix row numbers for easy reverse lookup.

[0109] Table 2 shows a simple circuit example. The positive terminal of the battery (B1) is connected to the switch (S1), the switch is connected to the resistor (R1), and the resistor returns to the negative terminal of the battery. There are three components in total, with four pins. In the component list, for B1: pin + and S1, pin 1 and R1, pin A and B node assignments; N1, the connection point between the battery positive terminal and switch pin 1; N2, the connection point between switch pin 2 and resistor pin A; N3, the connection point between resistor pin B and battery negative terminal, pin-to-node mapping.

[0110] Table 2

[0111] Table 3

[0112] The physical component association matrix (simplified 0 / 1 matrix) is shown in Table 3. This matrix fully describes the connection relationships between all pins and nodes. This matrix allows for easy lookup of which pins are connected to a given node (vertical view) and which node a given pin is connected to (horizontal view).

[0113] The algorithm for finding potential pathway-related components based on this matrix is ​​as follows:

[0114] When the intelligent judgment system detects a certain function (such as...) Overcurrent protection) output abnormality ( When it is necessary to locate the component affecting this function, the following steps can be taken to perform reverse tracing using the association matrix:

[0115] Identify the critical nodes or critical paths corresponding to this function (predefined in the function-node mapping library). For example, the overcurrent protection function involves the current detection point node N_detect and the comparator output node N_comp.

[0116] Extract all pins connected to N_detect from the correlation matrix, i.e., all rows in the matrix where the value of that column is 1.

[0117] Find the corresponding component ID based on the pin to obtain the candidate component set.

[0118] By combining the three-valued state vector, components with abnormal states (l ≠ normal expected value) are selected as candidates for root cause of failure.

[0119] Further expansion using the correlation matrix means starting from the pin of the faulty component, finding other nodes connected to it, and then finding the associated components on these nodes to form a complete anomaly subgraph, which is used to explain the current path of potential pathways.

[0120] This correlation matrix is ​​not directly input into the neural network, but is used to verify the rationality of the three-valued state vector (e.g., the logical consistency of the state of all components at a certain node), to assist in interpreting the neural network's decision results, and to locate specific faulty components. It also generates anomaly path descriptions in the maintenance report.

[0121] The circuit connection design data and actual wiring data are combined to obtain the actual circuit connection diagram of the circuit system. This diagram reflects the true state of the circuit design, especially in cases of potential paths, ensuring that potential paths are not overlooked during subsequent potential path identification. Preferably, S102: The state vector is input into the potential circuit identification neural network model, and the functional output values ​​of the circuit system are output, including:

[0122] The number of neurons in the input layer of the latent circuit recognition neural network model is set to the number of all physical components of the circuit system, and the number of neurons in the output layer of the latent circuit recognition neural network model is set to the number of functions of all physical components of the circuit system; wherein, each function to be implemented by the circuit system is extracted from the functional specification document of the circuit system;

[0123] The state vector is input into the latent circuit recognition neural network model, and the output values ​​of each function that the circuit system is to achieve are output.

[0124] Because each value in the state vector of a circuit system lies between 0 and 1, for a specific physical component, L can be understood as multiple continuous values. For example, as a relay contact begins to oxidize, the contact resistance gradually increases from 0Ω to 10Ω. L gradually changes from 0.0 to 0.2, 0.5, and 0.8, which can finely characterize the health degradation process of the physical component. This can improve the learning accuracy and generalization ability of the neural network model for circuit recognition. Furthermore, the neural network model for potential circuit recognition can capture this gradual trend, enabling early warning of functional failures.

[0125] Preferably, S103: Based on the functional output value, determining whether each function of the circuit system is normal and whether there are potential pathways further includes:

[0126] The status of a function is determined based on its function type and output value during normal operation of the circuit system; the function type of each function is either a normal function or an emergency function.

[0127] If the function is functioning normally, when the function output value is greater than or equal to the first output threshold, it is determined to be functioning normally and is at a low risk level.

[0128] When the function output value is less than the first output threshold and greater than or equal to the second output threshold, it is judged as a function warning, which is a medium risk level.

[0129] When the functional output value is less than the second output threshold and greater than or equal to the third output threshold, it is determined to be a functional failure, indicating a potential path risk, and is classified as a high-risk level.

[0130] When the function output value is less than the third output threshold, the function is determined to be completely failed, which is a serious risk level.

[0131] If the function is an emergency function, and the function output value is not greater than the third output threshold, the function is determined to be safe and at a low risk level.

[0132] When the function output value is greater than the third output threshold, the function is determined to be at risk, and is classified as low risk.

[0133] Specifically, a function can be either a normal function or an emergency function; it cannot be both. Normal function determination refers to the process of assessing the status of functions that should continuously operate and perform under normal operating conditions in a circuit system. A normal function can be understood as what the circuit system should do during operation; normal function determination is about judging how well these tasks are being performed.

[0134] A simplified representation of the functional decision process is as follows: Figure 6As shown, the neural network output vector of the potential circuit recognition neural network model contains the output values ​​of each function. Traversing the output values ​​of each function yields the function output. The system performs a function type determination to determine whether it is an emergency function. If yes, it proceeds to the emergency function judgment; otherwise, it proceeds to the normal function judgment.

[0135] For example, for normal functions, the function output value A value ≥0.8 indicates normal function, is considered low-risk, and requires no intervention.

[0136] 0.5≤function output value A value less than 0.8 indicates a functional warning, which is considered medium risk and indicates a significant anomaly requiring investigation.

[0137] 0.2≤function output value If the value is less than 0.5, it is considered a functional failure, indicating a high risk and abnormal function, requiring immediate action.

[0138] If the function is determined to be completely failed, it is a serious risk and should be dealt with immediately; if the function is completely failed (e.g., the overcurrent protection is completely lost), the consequences are more serious than those of a normal fault.

[0139] Record all decision results for normal functioning.

[0140] For emergency functions, the function output value A value ≤0.2 is considered a safe state; function output value. If the value is greater than 0.2, a risk is identified, the risk is recorded, and a warning is issued; this function is normally in standby mode. Function output value. It is close to 0 and is only activated in emergency situations.

[0141] Record all decisions made regarding emergency response capabilities.

[0142] Output value in the output function At the same time, it also outputs the function's output value. The confidence level is used to assess the reliability of the results; high confidence (>0.9) indicates extremely high reliability; medium confidence (0.7-0.9) indicates good reliability; and low confidence (<0.7) suggests a design review. The confidence level represents the neural network's output value for that function. The reliability level. The functional output value corresponding to low confidence. This should trigger a manual review.

[0143] That is, the functional output value of the circuit system during normal operation. The value is close to 1, for example, the main power supply function needs to be implemented under normal circumstances, so the function output value is close to 1. When the value is close to 1, the function is considered to be normal.

[0144] When a circuit system is running, emergency functions should be in a standby state (not activated) and should only be activated in an emergency. Therefore, it is desirable for their output value to be close to 0. For example, the emergency shutdown function should not be activated under normal circumstances, so when the neural network output is close to 0, it is considered that the function is in a normal state.

[0145] For normal functions, if a function is judged as a malfunction or warning but should function correctly, there may be a potential pathway (leading to function loss or degradation). For emergency functions, if a function should not be activated but is judged as risky, there may be a potential pathway (leading to accidental activation).

[0146] More simply and strictly speaking, when the output value of a function deviates from its expected target and the deviation exceeds a threshold, that is, the output value of a normal function is less than the first threshold and the output value of an emergency function is greater than the third threshold, then it can be determined that the function has a potential pathway.

[0147] Preferably, the automatic identification method for potential paths in the circuit further includes:

[0148] S109: Based on the correlation matrix of each function and physical component in the circuit system and the connection topology of each physical component, reverse trace the functions with faults and functions with risks. Through intersection analysis and sensitivity positioning of physical components, identify the specific component combinations and potential paths that lead to the functions with faults and functions with risks, and form a potential path report. The potential path report includes the function output value, judgment result, risk level, potential path list, potential path description, fault cause tracing, and suspect component list.

[0149] The specific implementation definition of reverse tracing is as follows:

[0150] Starting with a functional anomaly (output value below or above a threshold), the process of tracing back along the circuit topology to find the component combinations that may cause the anomaly.

[0151] Implementation steps:

[0152] 1. Identify critical nodes for abnormal functions: Each function is pre-associated with one or more critical electrical nodes. For example, for overcurrent protection, the critical nodes include the current sampling point N_sense, the comparator output N_comp, and the trigger output N_trigger.

[0153] The main power supply function reaches the key nodes: power input terminal N_in and output terminal N_out.

[0154] 2. Using the physical component association matrix: Starting from the key node, query all pins corresponding to that node in the association matrix to obtain the components directly connected to that node.

[0155] 3. Breadth-first expansion: Starting from these components, find adjacent nodes along their other pins, and then query other components on these nodes to form an influence subgraph.

[0156] 4. Obtain the three-valued state of these components: Extract the x_i value of each candidate component from the system state vector.

[0157] 5. Screening abnormal components: Compare the actual three-value state of a component with its expected normal state (e.g., a relay is expected to be closed at 0, and a fuse is expected to be normally at 0.6). Components with deviations exceeding the threshold are marked as suspected components.

[0158] The specific implementation definition of intersection analysis is as follows:

[0159] When multiple functions malfunction simultaneously, identify the sets of influencing components for each function, find their intersection, and thus pinpoint the common root cause of the failure. Implementation steps:

[0160] 1. For each abnormal function f_k, perform reverse tracing to obtain its suspected element set S_k.

[0161] 2. Calculate the intersection of the sets of suspected components with all abnormal functions: C = S_1 ∩ S_2 ∩ … ∩ S_t

[0162] 3. If the intersection is not empty, then these components are very likely to be the common source of failure.

[0163] 4. If the intersection is empty, consider the union or second-order intersection (common nodes on the connection paths between components). Example: If overcurrent protection failure (suspected components: K2, D2) and voltage stability failure (suspected components D2, R3) occur simultaneously, and the intersection is {D2}, then diode D2 is very likely the common fault point.

[0164] The specific implementation definition of sensitivity localization:

[0165] By quantitatively analyzing the impact of each component's state change on the functional output value, the most sensitive component, i.e., the component with the greatest impact on the functional output, is identified. Implementation steps:

[0166] 1. Perturbation method

[0167] For each element in the candidate element set, its three-valued state is slightly perturbed within the range of [0,1] (e.g., ±0.05), and then re-input into the neural network to calculate the change in the function output value Y_k.

[0168] 2. Calculate sensitivity

[0169] Sen(i) = |ΔY_k / Δx_i

[0170] 3. Sort

[0171] Components are sorted from most sensitive to least sensitive, and those with the highest sensitivity are the most likely to fail.

[0172] 4. Output

[0173] The report lists suspected components and their sensitivity scores for engineers to prioritize their inspection.

[0174] It does not require retraining the model; forward propagation calculations can be performed on the already trained model, which is fast.

[0175] Table 4 shows the specific content of the potential pathway report (corresponding to S109) and the fields that should be included in the report.

[0176] Table 4

[0177] The logic for generating repair suggestions (corresponding to S120)

[0178] The repair recommendations are not general, but are generated from a predefined rule base based on each specific potential path, taking into account the type of the faulty component, abnormal state value, and topological location.

[0179] Examples of rule bases are shown in Table 5.

[0180] Table 5

[0181] The process for generating repair suggestions is as follows:

[0182] 1. For each potential pathway, extract the suspected element and its three-valued state.

[0183] 2. Match suggestions from the rule base based on the component type and l value range.

[0184] 3. Based on the topology path, provide the specific replacement component number (e.g., "Replace relay K2").

[0185] 4. If multiple related pathways exist, it is recommended to merge them and output the duplicates.

[0186] The final output example is:

[0187] For potential path P001, the faulty components are relay K2 (l=0.4, half-closed) and diode D2 (l=0.2, leakage).

[0188] It is recommended to replace K2 and D2 immediately; connect a 0.1μF capacitor in parallel across D2; monitor the current in the K2 coil.

[0189] S110: Generate a risk level assessment report based on the risk level;

[0190] S120: Generate repair recommendations for the circuit system based on potential pathway reports and risk level assessment reports.

[0191] The repair recommendations are automatically generated for each identified potential path, taking into account its faulty physical component, abnormal path, and risk level. These recommendations can include replacing physical components, adjusting parameters, modifying design, and adding monitoring, and are presented to engineers in a structured manner, rather than being general suggestions. It provides a complete record and explanation of the entire decision-making process, enabling engineers to quickly understand the status of the circuit system and take action, greatly improving practicality and efficiency.

[0192] For example, the overcurrent protection function was detected. The output value is 0.12, indicating the existence of a potential pathway.

[0193] The tracing results show that the faulty components are relay K2 (half-engaged, l=0.4) and diode D2 (leakage, l=0.2).

[0194] The abnormal path is: solar panel, K2, D2, overcurrent detection point;

[0195] Targeted modification suggestions generated:

[0196] Immediately replace relay K2 with a certain model and diode D2 with a certain model.

[0197] The recommended design improvement is to connect a 0.1μF high-frequency capacitor in parallel across D2 to suppress leakage current spikes.

[0198] The recommended approach to enhance monitoring is to add a current sensor to the K2 coil circuit to monitor the engagement status in real time.

[0199] The recommended maintenance plan is to test the reverse leakage current of D2 every 3 months and record the degradation trend.

[0200] like Figure 2 As shown, in conjunction with embodiments of the present invention, an automatic identification system for potential circuit paths is provided, comprising:

[0201] The three-value resistor construction unit 21 is used to abstract the state of each physical element in the actual circuit connection diagram of the circuit system into a state value of the corresponding three-value resistor state, and construct the state vector of the circuit system.

[0202] an identification unit 22, configured to input the state vector into the latent circuit identification neural network model, and output a functional output value of the circuit system;

[0203] an intelligent judgment unit 23, configured to judge, according to the functional output value, whether each function of the circuit system is normal and whether a latent path exists.

[0204] By converting a variety of collected basic physical component data into one state value of a tri-valued resistance state that can be accurately represented numerically, different states of different physical components can be accurately mapped, so as to realize accurate characterization of different states of different physical components in circuit design; then, the state value is used as the input of the latent circuit identification neural network model for intelligent analysis, thereby realizing accurate automatic analysis and efficient identification of whether latent paths exist in large and complex circuit systems, eliminating errors in manual identification, improving the troubleshooting accuracy of latent paths, and also reducing the workload.

[0205] Preferably, the tri-valued resistance construction unit 21 is specifically configured to:

[0206] adopt a tri-valued resistance model, and abstract each physical component into one state value in the tri-valued resistance state according to the tri-valued resistance state mapping rule of each physical component and based on the connection topology of each physical component in the actual circuit connection diagram;

[0207] construct a circuit system state vector based on the state values of all physical components, wherein the dimension of the circuit system state vector is the same as the number of physical components.

[0208] process the component list to obtain the parameters and type of each physical component, adopt a tri-valued resistance model, and define the tri-valued state mapping rule for each component. Based on the connection topology (that is, how it is connected) of each physical component in the actual circuit connection diagram, the physical component is abstracted, that is, mapped to one state value in the tri-valued resistance state {0, L, 1} according to the tri-valued state mapping rule; wherein the tri-valued resistance satisfies 0<L<1, 0 represents a short-circuit state, L represents a load state and satisfies 0<L<1, and 1 represents an open-circuit state.

[0209] For the construction of the system state vector, assuming that the circuit system has n physical components, and each physical component corresponds to one state value of the tri-valued resistance state, then the state of the circuit system can be represented by an n-dimensional vector, each value of which is 0, 1 or L, which means that each physical component can only be in one physical state at the same time; determined by the tri-valued resistance, the half-fault state can be accurately characterized, and the real state information of the physical component will not be lost.

[0210] Preferably, the automatic identification system for a latent path of the circuit further comprises a mapping rule construction unit, configured to:

[0211] Standardize the parameter information of each physical element according to the element list of the circuit system to obtain the type and parameter of each physical element;

[0212] Using the ternary resistance model, each physical element is abstracted into a ternary resistor according to the element type and parameter of each physical element, so as to obtain the ternary resistance state mapping rule for each physical element. The ternary resistance states include an open-circuit state, the state of the physical element during operation of the circuit system, and a broken-circuit state.

[0213] According to the parameters and type of each physical element, and based on the physical characteristics of the physical element, the ternary resistance model is adopted to define the ternary state mapping rule for each element. Based on the connection topology (that is, the connection manner) of each physical element in the actual circuit connection diagram, the ternary state mapping rule means that the physical element is abstracted, i.e., mapped to a ternary resistance state {0, L, 1}; wherein the ternary resistor satisfies 0<L<1, 0 represents a short-circuit state, L represents a load state and satisfies 0<L<1, and 1 represents an open-circuit state. L is dynamically optimized through historical load data, and the L value is calculated by the formula L= dynamic calculation, is the measured current of the physical element, is the rated current; L is a real number between 0 and 1.

[0214] For example, the relay state mapping rule means that the closed state is mapped to 0, the open state is mapped to 1, and when L represents a half-pull-in state, it is calculated based on the ratio of the actual current to the rated current;

[0215] The fuse state mapping rule means that the open-circuit state is 0, the normal state is mapped to L=0.6, and the blown state is mapped to 1;

[0216] The switch state mapping rule means that the closed state is mapped to 0, the open state is mapped to 1, and the poor contact state is mapped to L=0.5;

[0217] The diode state mapping rule means that the conducting state is mapped to 0, the open-circuit state is mapped to 1, and L represents a leakage state, which is calculated based on the magnitude of the leakage current;

[0218] The specific mapping rules for different physical elements and the calculation method of the L value can be defined respectively according to the physical characteristics of the elements. Such state values with a unified structure and different parameters not only ensure the standardization of the input of the subsequent neural network model, which is beneficial to the processing of the neural network, but also take into account the physical differences of different physical elements.

[0219] Abstracting each physical element into multiple state values can truly reflect the physical differences of different physical elements, which are used as the input of the circuit identification neural network model to improve the identification accuracy of potential paths.

[0220] Preferably, the automatic identification system for potential circuit paths further includes an actual circuit connection diagram construction unit, used for:

[0221] Design data on circuit connection relationships are extracted from the circuit schematic of the self-circuit system through image processing and topology analysis.

[0222] The wiring diagram of the circuit system is analyzed to obtain the actual wiring data;

[0223] By merging the circuit connection design data and the actual wiring data, the actual circuit connection diagram of the circuit system is obtained;

[0224] Construct a list of physical components, which includes a unique identifier for each physical component in the actual circuit connection diagram, as well as a physical component association matrix, which refers to the other physical components or nodes to which a physical component is connected.

[0225] A node is an electrical connection point in a circuit topology (a common electrical point where the pins of two or more components in a circuit are connected to each other). All component pins connected to the same node have the same potential. Each node is assigned a unique identifier (such as N1, N2, ...).

[0226] Unique identifiers can represent different physical components, facilitating searching and marking throughout the process. After extracting the association mapping relationship between the physical component and its connected nodes based on the physical component's unique identifier, a physical component association matrix or connection list is formed. When a functional problem is discovered, the specific issue can be located based on the physical component and its corresponding physical component association matrix.

[0227] By merging the circuit connection design data and the actual wiring data, the actual circuit connection diagram of the circuit system is obtained. The actual circuit connection diagram can reflect the true situation of the circuit design, especially when there are potential paths. This will prevent potential paths in the design from being overlooked during the subsequent identification of potential paths.

[0228] Preferably, the identification unit 22 is specifically used for:

[0229] The number of neurons in the input layer of the latent circuit recognition neural network model is set to the number of all physical components of the circuit system, and the number of neurons in the output layer of the latent circuit recognition neural network model is set to the number of functions of all physical components of the circuit system; wherein, each function to be implemented by the circuit system is extracted from the functional specification document of the circuit system;

[0230] The state vector is input into the latent circuit recognition neural network model, and the output values ​​of each function that the circuit system is to achieve are output.

[0231] Because each value in the state vector of a circuit system lies between 0 and 1, for a specific physical component, L can be understood as multiple continuous values. For example, as a relay contact begins to oxidize, the contact resistance gradually increases from 0Ω to 10Ω. L gradually changes from 0.0 to 0.2, 0.5, and 0.8, which can finely characterize the health degradation process of the physical component. This can improve the learning accuracy and generalization ability of the neural network model for circuit recognition. Furthermore, the neural network model for potential circuit recognition can capture this gradual trend, enabling early warning of functional failures.

[0232] Preferably, the intelligent judgment unit 23 is specifically used for:

[0233] The status of a function is determined based on its function type and output value during normal operation of the circuit system; the function type of each function is either a normal function or an emergency function.

[0234] If the function is functioning normally, when the function output value is greater than or equal to the first output threshold, it is determined to be functioning normally and is at a low risk level.

[0235] When the function output value is less than the first output threshold and greater than or equal to the second output threshold, it is judged as a function warning, which is a medium risk level.

[0236] When the functional output value is less than the second output threshold and greater than or equal to the third output threshold, it is determined to be a functional failure, indicating a potential path risk, and is classified as a high-risk level.

[0237] When the function output value is less than the third output threshold, the function is determined to be completely failed, which is a serious risk level.

[0238] If the function is an emergency function, and the function output value is not greater than the third output threshold, the function is determined to be safe and at a low risk level.

[0239] When the function output value is greater than the third output threshold, the function is determined to be at risk, and is classified as low risk.

[0240] Specifically, a function can be either a normal function or an emergency function; it cannot be both. Normal function determination refers to the process of assessing the status of functions that should continuously operate and perform under normal operating conditions in a circuit system. A normal function can be understood as what the circuit system should do during operation; normal function determination is about judging how well these tasks are being performed.

[0241] A simplified representation of the functional decision process is as follows: Figure 6 As shown, the neural network output vector of the potential circuit recognition neural network model contains the output values ​​of each function. Traversing the output values ​​of each function yields the function output. The system performs a function type determination to determine whether it is an emergency function. If yes, it proceeds to the emergency function judgment; otherwise, it proceeds to the normal function judgment.

[0242] For example, for normal functions, the function output value A value ≥0.8 indicates normal function, is considered low-risk, and requires no intervention.

[0243] 0.5≤function output value A value less than 0.8 indicates a functional warning, which is considered medium risk and indicates a significant anomaly requiring investigation.

[0244] 0.2≤function output value If the value is less than 0.5, it is considered a functional failure, indicating a high risk and abnormal function, requiring immediate action.

[0245] If the function is determined to be completely failed, it is a serious risk and should be dealt with immediately; if the function is completely failed (e.g., the overcurrent protection is completely lost), the consequences are more serious than those of a normal fault.

[0246] Record all decision results for normal functioning.

[0247] For emergency functions, the function output value A value ≤0.2 is considered a safe state; function output value. If the value is greater than 0.2, a risk is identified, the risk is recorded, and a warning is issued; this function is normally in standby mode. Function output value. It is close to 0 and is only activated in emergency situations.

[0248] Record all decisions made regarding emergency response capabilities.

[0249] Output value in the output function At the same time, it also outputs the function's output value. The confidence level is used to assess the reliability of the results; high confidence (>0.9) indicates extremely high reliability; medium confidence (0.7-0.9) indicates good reliability; and low confidence (<0.7) suggests a design review. The confidence level represents the neural network's output value for that function. The reliability level. The functional output value corresponding to low confidence. This should trigger a manual review.

[0250] That is, the functional output value of the circuit system during normal operation. The value is close to 1, for example, the main power supply function needs to be implemented under normal circumstances, so the function output value is close to 1. When the value is close to 1, the function is considered to be normal.

[0251] When a circuit system is running, emergency functions should be in a standby state (not activated) and should only be activated in an emergency. Therefore, it is desirable for their output value to be close to 0. For example, the emergency shutdown function should not be activated under normal circumstances, so when the neural network output is close to 0, it is considered that the function is in a normal state.

[0252] For normal functions, if a function is judged as a malfunction or warning but should function correctly, there may be a potential pathway (leading to function loss or degradation). For emergency functions, if a function should not be activated but is judged as risky, there may be a potential pathway (leading to accidental activation).

[0253] More simply and strictly speaking, when the output value of a function deviates from its expected target and the deviation exceeds a threshold, that is, the output value of a normal function is less than the first threshold and the output value of an emergency function is greater than the third threshold, then it can be determined that the function has a potential pathway.

[0254] Preferably, the automatic identification system for potential paths of the circuit further includes a feedback unit, specifically used for:

[0255] Based on the functional and physical component association matrix and connection topology, the functions with faults and functions with risks are traced backward. Through the intersection analysis and sensitivity positioning of physical components, the specific component combinations and potential paths that lead to the functions with faults and functions with risks are identified, and a potential path report is generated. The potential path report includes the function output value, judgment result, risk level, potential path list, potential path description, fault cause tracing, and suspect component list.

[0256] A risk level assessment report is generated based on the risk level.

[0257] Repair recommendations for the circuit system are generated based on potential pathway reports and risk level assessment reports.

[0258] The repair recommendations are automatically generated for each identified potential path, taking into account its faulty physical component, abnormal path, and risk level. These recommendations can include replacing physical components, adjusting parameters, modifying design, and adding monitoring, and are presented to engineers in a structured manner, rather than being general suggestions. It provides a complete record and explanation of the entire decision-making process, enabling engineers to quickly understand the status of the circuit system and take action, greatly improving practicality and efficiency.

[0259] For example, the overcurrent protection function was detected. The output value is 0.12, indicating the existence of a potential pathway.

[0260] The tracing results show that the faulty components are relay K2 (half-engaged, l=0.4) and diode D2 (leakage, l=0.2).

[0261] The abnormal path is: solar panel, K2, D2, overcurrent detection point;

[0262] Targeted modification suggestions generated:

[0263] Immediately replace relay K2 with a certain model and diode D2 with a certain model.

[0264] The recommended design improvement is to connect a 0.1μF high-frequency capacitor in parallel across D2 to suppress leakage current spikes.

[0265] The recommended approach to enhance monitoring is to add a current sensor to the K2 coil circuit to monitor the engagement status in real time.

[0266] The recommended maintenance plan is to test the reverse leakage current of D2 every 3 months and record the degradation trend.

[0267] In summary, this method first trains a neural network model using existing circuit system design functions and the relationship between switch combinations, resulting in a potential circuit identification neural network model. The state vector, composed of the three-valued states of the physical components of the circuit system, is then input into the potential circuit identification neural network model, and the output is the probability value of the desired function (functional output value). The existence of potential paths is identified through this functional output value. This approach enables efficient identification of potential paths in large and complex circuit system designs, solving the problems of complexity and high labor intensity associated with traditional potential path analysis.

[0268] like Figure 3 As shown, the potential circuit identification neural network model is a three-layer feedforward neural network, which goes through three layers from input to output: input layer, hidden layer and output layer (not shown in the figure). The number of neurons in the input layer is equal to the number of physical components n in the circuit system, the number of neurons in the hidden layer (intermediate layer) is p, and the number of neurons in the output layer is equal to the number of designed functions m, which is the state that the function should achieve (0 or 1, indicating whether the circuit system should achieve the function when it is running).

[0269] In the input layer, the number of neurons is equal to the number of physical components n in the circuit system; each neuron corresponds to a state value of a three-valued resistor state of a physical component; the input state vector is normalized to ensure numerical stability.

[0270] For the hidden layer, the formula for calculating the number of neurons is as follows: ,like Figure 4 As shown, the selection is based on the value of the system complexity n. For values ​​n < 20, the system is considered simple; therefore, choose... =5 to 6, 20 ≤ n ≤ 50 is a medium-sized system, choose... =7 to 8, n>50 is a complex system, choose =9 to 18; this range ensures that the neural network can fully learn the complex mapping relationships of the three-valued resistance model without overfitting due to excessive parameterization; through training validation, the training error is less than 0.05, and when the error meets the target, it indicates... Choose the appropriate option; if it's not suitable, adjust it. ±1 retraining.

[0271] The hidden layer output is: ; In the formula This represents the connection weights from neuron i in the input layer to neuron j in the intermediate layer; This represents the input to the i-th neuron;

[0272] For the output layer, the number of neurons equals the number of functions m; each neuron corresponds to the probability of realizing a function; the output layer outputs: ; ; This represents the connection weights from intermediate layer neuron j to output layer neuron k; where, based on the functional specification analysis, the functions that the circuit system needs to achieve are determined, and m kinetic energy values ​​that need to be achieved are defined. Under normal circumstances, each function should be achieved (output 1) or not achieved (output 0).

[0273] Establish a weight initialization strategy, with the following characteristics:

[0274] Initialize the weight matrix , The values ​​are random numbers within the range [-0.5, 0.5]. If the weights are initialized to 0, all neurons will learn the same features, and the network will degenerate into a single neuron, significantly reducing its learning ability. The randomness of [-0.5, 0.5] ensures that each neuron learns different features, and the network has rich representational capabilities.

[0275] First, the weights are initialized, that is, all weights are initialized to uniformly distributed random numbers in the interval [-0.5, 0.5] to ensure the stability of network training and initial gradients, and avoid the problems of gradient vanishing and gradient exploding.

[0276] like Figure 5 The image shows a simplified diagram of the network model training process. The detailed training process for the network model is as follows:

[0277] 1. Input training samples;

[0278] 2. Forward propagation calculation output : , ;

[0279] 3. Output layer gradient: ;

[0280] 4. Error result judgment:

[0281] When the calculation error E Determine if E is greater than 0.01; if not, generate a verification report.

[0282] If so, then execute: , , , Where the learning rate is 0.1 and the activation function is f. t For LeakyReLU;

[0283] 5. Backpropagation to update weights:

[0284] Hidden layer gradient: ;

[0285] Weight update: ;

[0286] 6. Iterative loop; updating formula via weights. , Iterative optimization model; in the algorithm For function The target output.

[0287] By employing the aforementioned dedicated network architecture, accurate input-output mapping is achieved, and overfitting can be avoided. Through optimized training algorithms, rapid convergence and global optima are realized.

[0288] In conjunction with embodiments of the present invention, a computer-readable storage medium is provided, which stores one or more programs, and when the one or more programs are executed by a computer device, an automatic identification method for potential paths of circuits that cause the computer device to perform any of the foregoing.

[0289] In conjunction with embodiments of the present invention, a computer device is provided, comprising:

[0290] A processor; and a method for automatically identifying potential pathways of a circuit that, when executed, causes the processor to perform any of the foregoing.

[0291] The beneficial technical effects achieved by the embodiments of the present invention are as follows:

[0292] By converting the collected data of various basic physical components into three discrete resistance values ​​that can be accurately numerically represented, different states of different physical components are mapped to achieve precise characterization of the different states of different physical components in circuit design. These values ​​are then used as input to a neural network for intelligent analysis, thereby enabling accurate automated analysis and efficient identification of potential pathways in large and complex circuit system designs. This eliminates errors from manual identification and improves the accuracy of potential pathway detection. Therefore, this method is simpler and more effective.

[0293] The use of a ternary resistor model solves the problem that the traditional binary model (physical components only have 0 and 1) cannot accurately represent the intermediate state of the component.

[0294] It employs a dedicated neural network architecture based on system scale to ensure an optimal match between model complexity and problem scale; it achieves a fully automated processing flow from data to output, eliminating inconsistencies caused by manual intervention. Furthermore, it can identify unknown potential paths and is adaptable to the simulation and identification of dynamic potential paths in complex circuit systems.

[0295] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process may be rearranged without departing from the scope of this disclosure. The appended method claims provide elements of various steps in an exemplary order and are not intended to limit the scope to the specific order or hierarchy described.

[0296] In the above detailed description, various features are combined together in a single embodiment to simplify this disclosure. This approach to disclosure should not be construed as reflecting an intention that embodiments of the claimed subject matter require more features than are explicitly stated in each claim. Rather, as reflected in the appended claims, the invention is presented with fewer features than all of the features of the single disclosed embodiment. Therefore, the appended claims are hereby explicitly incorporated into the detailed description, wherein each claim stands alone as a preferred embodiment of the invention.

[0297] The disclosed embodiments have been described above to enable any person skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of this disclosure. Therefore, this disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.

[0298] The foregoing description includes examples of one or more embodiments. It is certainly impossible to describe all possible combinations of components or methods in order to describe the above embodiments, but those skilled in the art will recognize that further combinations and arrangements of the various embodiments are possible. Therefore, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. Furthermore, the term "comprising" as used in the specification or claims is interpreted in a manner similar to the term "including," as interpreted when used as a conjunction in the claims. Additionally, the use of any term "or" in the specification of the claims is intended to mean "non-exclusive or."

[0299] Those skilled in the art will also understand that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of both. To clearly demonstrate the interchangeability of hardware and software, the functions of the various illustrative components, units, and steps described above have been generally described. Whether such functionality is implemented through hardware or software depends on the specific application and the overall system design requirements. Those skilled in the art can implement the described functions using various methods for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present invention.

[0300] The various illustrative logic blocks or units described in the embodiments of this invention can be implemented or operate the described functions using a general-purpose processor, digital signal processor, application-specific integrated circuit (ASIC), field-programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof. The general-purpose processor can be a microprocessor; alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented using a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors combined with a digital signal processor core, or any other similar configuration.

[0301] The steps of the methods or algorithms described in the embodiments of this invention can be directly embedded in hardware, a software module executed by a processor, or a combination of both. The software module can be stored in RAM, flash memory, ROM, EPROM, EEPROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from and write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and storage medium can be housed in an ASIC, which can be housed in a user terminal. Optionally, the processor and storage medium can also be housed in different components of the user terminal.

[0302] In one or more exemplary designs, the functions described in the embodiments of the present invention can be implemented in hardware, software, firmware, or any combination of these three. If implemented in software, these functions can be stored on a computer-readable medium or transmitted on a computer-readable medium in the form of one or more instructions or code. Computer-readable media include computer storage media and communication media that facilitate the transfer of computer programs from one place to another. Storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. For example, such computer-readable media can include, but is not limited to, RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code in the form of instructions or data structures and other forms that can be read by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Furthermore, any connection can be suitably defined as a computer-readable medium, for example, if the software is transmitted from a website, server, or other remote resource via a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wirelessly, such as infrared, wireless, and microwave, it is also included in the defined computer-readable medium. The disks and discs mentioned include compressed disks, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs. Disks typically copy data magnetically, while discs typically copy data optically using lasers. Combinations of the above can also be contained in computer-readable media.

[0303] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An automatic identification method for potential circuit paths, characterized in that, include: The state of each physical element in the actual circuit connection diagram of the circuit system is abstracted into a state value of the corresponding three-value resistor state, and the state vector of the circuit system is constructed based on the state value. The state vector is input into the potential circuit recognition neural network model, and the functional output value of the output circuit system is output. Based on the function output value, determine whether each function of the circuit system is normal and whether there are any potential pathways.

2. The automatic identification method for potential circuit paths according to claim 1, characterized in that, The states of each physical component in the actual circuit connection diagram of the circuit system are abstracted into a state value of the corresponding three-value resistor state, and the state vector of the circuit system is constructed, including: Using a three-value resistor model, based on the three-value resistor state mapping rules of each physical element and the connection topology of each physical element in the actual circuit connection diagram, each physical element is abstracted into a state value of the three-value resistor state. A circuit system state vector is constructed based on the state values ​​of all the physical elements, and the dimension of the circuit system state vector is the same as the number of physical elements.

3. The automatic identification method for potential circuit paths according to claim 2, characterized in that, It also includes the step of constructing a three-valued resistor state mapping rule: The parameter information of each physical component is standardized according to the component list of the circuit system to obtain the type and parameters of each physical component; Based on the component type and parameters of each physical element, the three-value resistor model abstracts each physical element into a three-value resistor, thereby obtaining the three-value resistor state mapping rule for each physical element. The three-value resistor state includes the open circuit state, the state of the physical element during the operation of the circuit system, and the open circuit state.

4. The automatic identification method for potential circuit paths according to claim 1, characterized in that, Also includes: Circuit connection design data is extracted from the circuit schematic of the circuit system using image processing and topology analysis. The wiring table of the circuit system is analyzed to obtain the actual wiring data; The circuit connection design data and the actual wiring data are combined to obtain the actual circuit connection diagram of the circuit system; Construct a list of physical components, which includes a unique identifier for each physical component in the actual circuit connection diagram, and a physical component association matrix, which refers to the other physical components or nodes connected to the physical component.

5. The automatic identification method for potential circuit paths according to claim 1, characterized in that, The state vector is input into the latent circuit recognition neural network model, and the output circuit system's functional output values ​​are included: The number of neurons in the input layer of the latent circuit recognition neural network model is set to the number of all physical components of the circuit system, and the number of neurons in the output layer of the latent circuit recognition neural network model is set to the number of functions of all physical components of the circuit system; wherein, each function to be implemented by the circuit system is extracted from the functional specification document of the circuit system; The state vector is input into the potential circuit recognition neural network model, and the output values ​​of each function to be implemented by the circuit system are output.

6. The automatic identification method for potential circuit paths according to claim 1, characterized in that, Based on the functional output values, determine whether each function of the circuit system is normal and whether there are any potential pathways, including: The state of a function is determined based on its function type and output value during normal operation of the circuit system; wherein, the function type of each function is either a normal function or an emergency function. If the function is a normal function, when the function output value is greater than or equal to the first output threshold, it is determined that the function is normal and is at a low risk level. When the function output value is less than the first output threshold and greater than or equal to the second output threshold, it is determined to be a function warning, which is of medium risk level. When the functional output value is less than the second output threshold and greater than or equal to the third output threshold, it is determined to be a functional failure, indicating a potential path risk, which is classified as a high-risk level. When the output value of the function is less than the third output threshold, the function is determined to be completely failed, which is a serious risk level. If the function is an emergency function, and the output value of the function is not greater than the third output threshold, the function is determined to be safe and at a low risk level. When the output value of the function is greater than the third output threshold, the function is determined to be at risk, and is classified as low risk.

7. The automatic identification method for potential circuit paths according to claim 1, characterized in that, Also includes: Based on the functional and physical component association matrix and connection topology, functions with faults and functions with risks are traced back in reverse. Through intersection analysis and sensitivity positioning of physical components, the specific component combinations and potential paths that lead to the functions with faults and functions with risks are identified, and a potential path report is formed. The potential path report includes function output value, judgment result, risk level, potential path list, potential path description, fault cause tracing, and suspect component list. A risk level assessment report is generated based on the stated risk level. Repair recommendations for the circuit system are generated based on the potential pathway report and the risk level assessment report.

8. An automatic identification system for potential circuit paths, characterized in that, include: The ternary resistor construction unit is used to abstract the state of each physical element in the actual circuit connection diagram of the circuit system into a state value of the corresponding ternary resistor state, and construct the state vector of the circuit system. The identification unit is used to input the state vector into the potential circuit identification neural network model and output the functional output value of the circuit system. The intelligent judgment unit is used to determine whether each function of the circuit system is normal and whether there is a potential path based on the function output value.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs that, when executed by a computer device, cause the computer device to perform the automatic identification method for potential paths of the circuit according to any one of claims 1-7.

10. A computer device, characterized in that, include: processor; And a memory arranged to store computer-executable instructions, which, when executed, cause the processor to perform the automatic identification method for potential paths of the circuit according to any one of claims 1-7.

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