A linear equation set solving device and method based on RRAM differential array and analog closed loop feedback

Abstract

This invention discloses a device and method for directly solving linear equations based on an RRAM differential array and a pure analog negative feedback closed loop. The device includes a dynamic polarity reversal control module, an NVM differential cross array, a fully differential transimpedance amplifier, and an error feedback adjustment module. The device utilizes the difference in conductance between the positive and negative arrays to map matrix weights; the dynamic polarity reversal control module monitors the voltage polarity in real time and dynamically reverses the signal flow direction, forcibly maintaining the closed-loop negative feedback steady state to prevent system divergence; the fully differential transimpedance amplifier converts the output current of the positive and negative arrays locally into differential voltages and provides virtual ground clamping; the error adjustment module directly compares and generates errors in the analog domain and continuously feeds them back. This invention overcomes the performance bottlenecks of ADC conversion and digital iterative memory access in traditional mixed-signal architectures, driving system evolution entirely within the continuous-time analog domain using physical laws, achieving extremely low power consumption and extremely fast high-precision solving.

Description

Technical Field

[0003] This invention relates to the field of in-memory computing and analog integrated circuit design technology, and in particular to a device and method for directly solving linear equations based on RRAM differential cross array, dynamic polarity reversal control and pure analog negative feedback closed loop. Background Technology

[0005] Solving linear equations (AX = B) is a fundamental problem in scientific computing, signal processing, and machine learning. Traditional digital computing methods are based on the von Neumann architecture, where computing units and storage units are separated, and data is frequently moved between the two, forming the "von Neumann bottleneck." This results in high system latency and high energy consumption, making it difficult to meet the needs of high-concurrency, low-power edge computing scenarios.

[0006] To overcome the aforementioned bottlenecks, Processing-in-Memory (PIM) technology has emerged. Among them, analog in-memory computing schemes based on novel non-volatile memories (such as resistive random access memory, RRAM) can directly perform matrix multiplication and addition operations in the analog domain using Ohm's law and Kirchhoff's current law, exhibiting extremely high parallelism and energy efficiency advantages.

[0007] To compensate for computational errors caused by the non-ideal characteristics of RRAM devices, current mainstream solution architectures mostly adopt a "hybrid analog-digital" approach: first, a low-precision approximation is performed by an analog array, then sampling is done by an analog-to-digital converter (ADC), and finally, the back-end digital processing unit performs multiple rounds of iterative correction. However, as the dimension of the solution matrix increases, this hybrid architecture exposes serious performance bottlenecks in high-concurrency scenarios: on the one hand, there is the huge power consumption caused by high-frequency ADC conversion; on the other hand, the digital post-processing unit needs to frequently read and write intermediate variables during multiple iterations, resulting in severe memory access latency and bandwidth limitations (i.e., the "memory wall" effect), which significantly weakens the original high energy efficiency and parallel advantages of analog in-memory computing architectures.

[0008] To overcome the limitations of digital conversion and data scheduling, researchers attempted to construct a purely analog negative feedback closed-loop system to directly approximate the solution to the equations. However, in practical physical circuits, the purely analog closed-loop scheme faces two major challenges: First, the high-dimensional coefficient matrix in practical applications usually contains alternating positive and negative weights. When the polarity of the input signal is not properly combined with the polarity of the matrix weights, it is very easy for the local closed-loop feedback branch to flip from "negative feedback" to "positive feedback," thereby causing the system to diverge. Second, at the array readout end, fluctuations in the bit line (column line) voltage will cause changes in the voltage drop across the RRAM device, resulting in severe conductance nonlinear distortion, which in turn damages the accuracy of analog calculations.

[0009] Therefore, existing in-memory computing architectures have always struggled to balance the high energy consumption bottleneck of digital iteration with the stability issues of pure analog closed loops. There is an urgent need for a pure analog closed-loop architecture that can dynamically maintain the stability of the system's negative feedback and has high linearity and low latency analog readout capabilities. Summary of the Invention

[0011] The purpose of this invention is to overcome the problems of existing pure analog solvers, such as easy getting trapped in positive feedback divergence when processing complex matrices, nonlinear distortion in array calculations, and the bottlenecks of ADC conversion overhead and digital iterative memory access in traditional hybrid analog-digital architectures. This invention proposes a novel linear equation solving architecture and method based on RRAM differential arrays, dynamic polarity reversal control, and a pure analog negative feedback closed loop. This architecture performs closed-loop calculations entirely in the continuous-time analog domain, ensuring stable negative feedback convergence characteristics and maximizing the overall energy efficiency of the system.

[0012] To achieve the above objectives, the present invention adopts the following technical solution:

[0013] A linear equation solving device based on RRAM differential array and analog closed-loop feedback, forming a continuous-time analog domain closed-loop solution path, characterized in that it includes: a dynamic polarity reversal control module, an NVM differential cross array, a transimpedance amplifier circuit, and an error feedback adjustment module.

[0014] The dynamic polarity reversal control module is configured in the forward path or feedback loop of the input signal entering the NVM differential cross array. This module includes a polarity detection circuit (a comparator and XOR gate with hysteresis) and a polarity reversal switch circuit (cross-coupled switch array). It is used to detect the voltage sign of a specific node in real time and dynamically reverse the connection polarity of the differential input signal according to XOR logic. This, in conjunction with the subsequent differential array, completes four-quadrant operations, forcibly maintaining the negative feedback stability of the entire analog closed loop and preventing system divergence.

[0015] The NVM differential cross array, specifically an RRAM differential cross array, is used to receive polarity-controlled voltage signals and statically map the coefficient matrix of a linear equation system, directly generating column-accumulated currents in the analog domain using physical laws. The positive and negative weights of the target matrix are accurately mapped using the conductance difference between the positive and negative polarity arrays, and the mapping relationship satisfies: ,in For positive polarity array conductance, The negative polarity array conductance, k is the scaling factor;

[0016] The fully differential transimpedance amplifier circuit is directly connected to the positive and negative column lines of the NVM differential cross array. Utilizing the local closed loop formed by the fully differential amplifier (FDA) and its feedback network, the column line voltages are strictly clamped near the common-mode reference voltage to form a virtual ground, eliminating the conductance nonlinearity distortion caused by the column line parasitic voltage drop, and directly converting the weak positive and negative column accumulated currents output by the array into a pair of differential analog voltage signals with high linearity.

[0017] The error feedback adjustment module has a comparison node that directly receives the paired differential analog voltage signals output by the transimpedance amplifier circuit and compares them with the input signal of the target constant vector by physical summation to calculate the error voltage. The error voltage is then used as a correction quantity and continuously fed back to the system input through a pure analog path to drive the system to spontaneously evolve to an equilibrium state.

[0018] Beneficial effects:

[0019] 1. Constructing a simplified analog-domain high-speed solution closed loop: This architecture focuses on continuous-time pure analog computation, directly approximating the solution vector using a physical feedback mechanism. Since this core solution path does not require the introduction of analog-to-digital conversion overhead or concurrent read / write scheduling of digital storage, this analog closed-loop device achieves a simplified signal processing path, providing extremely high computational speed while maintaining extremely low system power consumption.

[0020] 2. Maintaining stable convergence of high-dimensional systems: The innovative introduction of a dynamic polarity reversal control module (LoopReverse) uses physical XOR logic to monitor and dynamically toggle the signal flow polarity in real time, completely solving the positive feedback divergence problem caused by changes in matrix weight signs in pure analog solutions, and ensuring that the system can stably maintain negative feedback convergence for any high-dimensional complex matrix.

[0021] 3. Provides a high-linearity physical calculation basis: By integrating a fully differential transimpedance amplifier at the array readout end to provide virtual ground clamping, the RRAM conductance distortion caused by parasitic effects is greatly suppressed, ensuring the high linearity of the analog current-to-voltage conversion link and improving the final accuracy of the solution from the physical level. Attached Figure Description

[0023] Figure 1 This is the overall system flowchart of the linear equation solving device based on RRAM differential array and pure analog negative feedback closed loop of the present invention;

[0024] Figure 2 This is the core overall circuit structure diagram of the present invention, which includes a dynamic polarity reversal control module (Loop Reverse), an RRAM differential cross array, and a fully differential transimpedance amplifier readout circuit. Detailed Implementation

[0026] The specific implementation of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0027] Example 1

[0028] This invention relates to a linear equation solving device based on an RRAM differential array and a pure analog negative feedback closed loop. The device employs a differential memory structure combining positive and negative weight arrays, and highly integrates dynamic polarity control and a virtual ground clamping readout mechanism, directly achieving closed-loop solution of linear equations in the analog domain. The device can directly and rapidly solve high-dimensional linear equations in an extremely parallel manner without requiring any digital matrix decomposition, analog-to-digital conversion, or discrete clock iteration.

[0029] This embodiment details the underlying hardware coordination and signal flow relationship of the system under normal operating conditions. The solving device includes a dynamic polarity reversal control module, an NVM differential cross array, a fully differential transimpedance amplifier circuit, and an error feedback adjustment module. These four core modules are seamlessly connected to form a pure analog closed-loop solving path.

[0030] The signal flow originates from an externally input reference voltage signal or a transient voltage signal from the feedback loop. This signal first enters the dynamic polarity reversal control module. Two hysteresis comparators within this module detect the voltage polarity sign of the positive and negative nodes in real time and input them to an XOR gate to generate hardware control logic. Based on this logic state, the bottom cross-coupled switch array instantaneously determines whether to "straight through" or "cross-connect" the differential input voltage to the word line terminals of the subsequent array. This core mechanism ensures that even in extreme cases where positive and negative weights are drastically interleaved within the matrix, the overall loop gain is always forced to be negative, physically preventing oscillations or system divergence.

[0031] Subsequently, a voltage signal with the correct polarity is applied to the NVM differential cross array. Both the positive-weighted RRAM array and the negative-weighted RRAM array are formed by the intersection of several row word lines and several column bit lines; according to Ohm's law and Kirchhoff's current law, positive and negative accumulated currents are instantaneously aggregated in parallel at each bit line terminal.

[0032] Immediately afterwards, the positive and negative accumulated currents flow without delay into the fully differential transimpedance amplifier circuit connected to the end of the bit line. This circuit utilizes a fully differential amplifier (FDA) and a deep feedback network to forcibly clamp the positive and negative bit line voltages to a virtual ground level, thereby perfectly eliminating the bit line voltage drop effect caused by data changes during RRAM array calculations (i.e., eliminating conductance nonlinearity distortion). Simultaneously, the FDA converts the weak positive and negative column currents into a pair of differential analog voltage signals with high linearity.

[0033] The differential analog voltage signals output by the FDA are directly input to the subsequent error feedback adjustment module. This module receives the reference constant voltage corresponding to the constant vector B, and at the comparison node, it directly uses an operational amplifier network to physically sum and compare the differential signals from the FDA, generating a continuous error voltage representing the current approximation deviation. This error voltage is continuously fed back to the system input stage via a hardware path, driving the entire network to spontaneously adjust its output state. When the system evolves to a physical equilibrium state, the voltage maintained by the feedback node is the solution vector of the final equation.

[0034] Example 2

[0035] This embodiment details the continuous-time dynamic evolution process of the aforementioned pure analog closed-loop solver when actually solving the linear equation system (AX=B). This process is completely independent of the clock cycle drive of traditional digital systems, relying purely on the spontaneous convergence of analog physical quantities towards the point of lowest potential energy (solution space):

[0036] Step 1 (corresponding to) Figure 1 (S1 in the middle): System initialization, establish the initial state at the frontmost input vector (X) node, and assign an initial bias voltage (usually set to system common mode or zero level) as the signal starting point for analog closed-loop evolution.

[0037] Step 2 (corresponding) Figure 1 (S2 in the diagram): This voltage signal enters the dynamic polarity reversal control module. This module continuously monitors the voltage polarity of the node. If it detects a positive feedback polarity combination that would cause divergence, it instantly flips the cross switch to reverse the signal flow and outputs a safe polarity routing voltage.

[0038] Step 3 (corresponding) Figure 1 (Note S3): The positive and negative conductance matrices (NVM differential cross array) of the coefficient matrix A are pre-statically mapped to receive the polarity routing voltage. Using physical laws, the column-accumulated differential analog current representing the approximate product (AX) of the current state is instantaneously aggregated in parallel.

[0039] Step 4 (corresponding) Figure 1 (S4 in the diagram): The accumulated current then flows into the fully differential transimpedance amplifier circuit. This network, while maintaining the virtual ground of the bit line, converts the weak analog current in place into a differential approximation state voltage with high linearity.

[0040] Step 5 (corresponding) Figure 1 (S5 in the diagram): This differential voltage is directly transmitted to the subsequent error feedback adjustment module. At this node, the signal combines with the preset target constant vector reference (B) to continuously generate the error voltage E (satisfying E=B-AX). This error signal is fed back to the input terminal at high speed through a closed-loop path, driving the system to adjust automatically.

[0041] Step 6 (corresponding) Figure 1 (S6 in the diagram): Under the strong and continuous physical negative feedback, the system evolves rapidly toward zero error. When the voltages at each node are completely stable and no longer drift (satisfying B-AX≈0), the final high-precision result of the linear equation system is read from the output of the last node, which simulates the steady-state solution (X).

[0042] In summary, this invention completely eliminates the digital compromises inherent in mixed-signal architectures, directly achieving stable solutions to high-dimensional linear equations in the continuous analog domain. It overcomes the divergence barrier of purely analog systems by utilizing a Loop Reverse dynamic inversion mechanism, eliminates readout distortion by employing a fully differential transimpedance amplifier with local virtual ground clamping, and ultimately achieves zero digital delay and extremely low power consumption equation solving through a purely physical negative feedback network. This invention has broad application prospects in next-generation high-efficiency electronic systems with extremely stringent energy efficiency and real-time requirements.

[0043] The specific descriptions or embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A closed-loop simulation solution device for linear equation systems based on a non-volatile memory (NVM) differential array, characterized in that, include: The NVM differential cross array stores the weight information of the coefficient matrix of the linear equation system to be solved, and represents the positive and negative values ​​of the matrix elements through a differential conductance structure. The NVM differential cross array generates column accumulated current in the analog domain according to the input analog voltage signal to realize parallel matrix-vector multiplication. The dynamic polarity reversal control module is configured in the forward path or feedback loop of the input signal entering the NVM differential cross array. It is used to detect the voltage sign of a specific node in real time and dynamically reverse the signal polarity. It works with the NVM differential cross array to complete the four-quadrant operation and forcibly maintain the negative feedback stability of the analog closed loop. The analog readout and error feedback adjustment module receives the positive and negative column accumulated current output by the NVM differential cross array through a fully differential transimpedance amplifier, converts it directly into a differential analog voltage signal, and compares it with the input signal of the target constant vector to calculate the error signal. The error signal is amplified by a hardware-constructed closed-loop feedback loop and continuously fed back to the input of the NVM differential cross array, so that the entire analog system converges and directly outputs the analog solution vector that satisfies the linear equation.

2. The apparatus according to claim 1, characterized in that: The NVM differential cross-connect array is specifically a resistive random access memory (RRAM) differential cross-connect array, including a first conductance array and a second conductance array, wherein the matrix elements satisfy... In the formula The conductance of the first conductance array, Let be the conductance of the second conductance array, and k be the scaling factor, so that the positive and negative representations of the matrix elements are achieved by the difference between the two sets of positive conductances.

3. The apparatus according to claim 1, characterized in that: The dynamic polarity reversal control module includes a polarity detection circuit and a polarity reversal switch circuit. The polarity detection circuit is used to detect the sign of the differential node voltage and output digital control logic instructions. The polarity reversal switch circuit receives the digital control logic instructions and dynamically controls the direct connection or cross-connection of the differential input signals to prevent the feedback branch from turning into positive feedback due to the alternation of positive and negative matrix weights, thereby causing system divergence.

4. The apparatus according to claim 3, characterized in that: The polarity detection circuit includes two comparators with hysteresis characteristics and an XOR gate; the two comparators with hysteresis characteristics detect the voltage of the positive and negative nodes respectively and output to the XOR gate, which outputs the digital control logic instruction; the polarity flip switch circuit includes a cross-coupled switch array, which dynamically connects the differential input signal directly to the subsequent bit line or flips it in reverse according to the output logic state of the XOR gate.

5. The apparatus according to claim 1, characterized in that: The analog readout and error feedback adjustment module includes a fully differential transimpedance amplifier circuit. The fully differential transimpedance amplifier circuit is configured to use a local closed-loop negative feedback mechanism formed by the fully differential amplifier (FDA) and its feedback network to clamp the positive and negative column line voltages of the NVM differential cross array near the common-mode reference voltage to form a virtual ground, thereby eliminating the nonlinear distortion of conductance caused by the parasitic voltage drop of the column lines. The positive and negative column accumulated currents output by the array are directly converted into differential analog voltage signals with high linearity and input to the comparison node of the error feedback adjustment module.

6. A method for solving linear equations based on NVM differential array and analog closed-loop feedback, applied to the device described in any one of claims 1 to 5, characterized in that, The process includes the following sequential steps: statically mapping the coefficient matrix of the linear equation system to be solved and writing it into the NVM differential cross array; inputting the reference voltage signal corresponding to the target constant vector into the system and providing an initial voltage for the output vector; The dynamic polarity reversal control module detects the voltage polarity of the current input or feedback node in real time, and dynamically controls the cross switch through XOR logic to determine whether the signal is passed through or reversed, thereby ensuring that the entire system is always in a stable negative feedback state. The NVM differential cross array receives the processed voltage signal and uses physical laws to directly generate a differential current representing the matrix-vector multiplication and addition result in the analog domain. The analog readout and error feedback adjustment module converts the differential current into a voltage and compares it with the reference voltage signal to generate an error voltage, and continuously feeds this error voltage back to the array input as a correction. As the closed loop adjusts spontaneously, the error voltage gradually decreases. When the system reaches dynamic physical equilibrium, the final analog voltage solution vector is directly read from the node of the feedback loop.

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