Chip system automatic generation method, device and equipment and storage medium

Abstract

This disclosure relates to a method, apparatus, device, and storage medium for automatically generating chip systems, comprising: connecting various signals within the main domain to generate the number of channels and register reset values ​​of the main domain I / O controller; routing the I / O control signals generated by the main domain I / O controller differently according to power supply affiliation; allocating addresses to main domain devices and generating a main domain address mapping table; instantiating the main domain devices and connecting them to the corresponding main domain bus; and integrating main domain interrupt signals, main domain DMA signals, and main domain error signals; connecting various signals within the backup domain to generate the number of channels and register reset values ​​of the backup domain I / O controller; routing the I / O control signals generated by the backup domain I / O controller to a multiplexer to allocate addresses to backup domain peripherals and generate a backup domain address mapping table; instantiating the backup domain peripherals and connecting them to the corresponding backup domain bus; and integrating backup domain interrupt signals, backup domain DMA signals, and backup domain error signals.

Description

Technical Field

[0001] This disclosure relates to the field of chip design technology, and in particular to a method, apparatus, device and storage medium for automatically generating chip systems. Background Technology

[0002] As chips are increasingly used in more and more scenarios, the modules integrated within chips (such as MCUs) are becoming more numerous and complex. Simultaneously, the power consumption and area requirements for chips are also increasing. This necessitates that chip designs balance the number of internal processors, pins, and peripherals to accommodate a wider range of operating scenarios within the smallest possible area. Depending on the application scenario, the same series of chips may be divided into dozens of models based on differences in Flash and SRAM size, the number of peripherals, the number of pins, and the package. This is especially true for automotive-grade chips, which have graded functional safety requirements, resulting in even greater diversity in specifications.

[0003] Currently, the design approach for chip systems involves writing a design specification document and then manually instantiating and wiring peripherals at the RTL level according to that document. However, once the design is complete, any subsequent modifications to the internal design require the creation of a new design specification document and significant refactoring. Furthermore, peripheral instantiation and wiring must be manually redone in the code, extending the development cycle and increasing the risk of logical conflicts in signals. Summary of the Invention

[0004] To solve the above-mentioned technical problems, or at least partially solve them, this disclosure provides a method, apparatus, device, and storage medium for automatically generating chip systems.

[0005] A first aspect of this disclosure provides a method for automatically generating a chip system, the method comprising: The file processing center extracts primary domain configuration information from the primary domain configuration document and backup domain configuration information from the backup domain configuration document. The primary domain configuration information includes primary domain device information, IO default configuration information, and primary domain connection information. The backup domain configuration information includes backup domain device information, IO mapping information, and backup domain connection information. Through the main domain connector of the main domain processing center, the analog signals, digital signals and IO multiplexed signals in the main domain are connected according to the default IO configuration information and the main domain connection information, respectively, to generate the number of channels and register reset value of the main domain IO controller, and to perform differentiated routing of the IO control signals generated by the main domain IO controller according to power supply affiliation; The main domain generator in the main domain processing center allocates addresses to the main domain devices and generates a main domain address mapping table based on the main domain device information. It instantiates the main domain devices and connects them to the corresponding main domain bus, and integrates the main domain interrupt signal, the main domain DMA signal and the main domain error signal. Through the backup domain connector in the backup domain processing center, based on the IO mapping information and the backup domain connection information, the digital signals and IO multiplexing signals in the backup domain are connected respectively to generate the number of channels and register reset value of the backup domain IO controller, and the IO control signals generated by the backup domain IO controller are routed to the multiplexer. The backup domain generator in the backup domain processing center allocates addresses to backup domain peripherals and generates backup domain address mapping tables based on the backup domain device information. It instantiates the backup domain peripherals and connects them to the corresponding backup domain bus, and integrates backup domain interrupt signals, backup domain DMA signals, and backup domain error signals.

[0006] A second aspect of this disclosure provides a chip system automatic generation apparatus, the apparatus comprising: The first extraction module is used to extract primary domain configuration information from the primary domain configuration document and backup domain configuration information from the backup domain configuration document through the file processing center. The primary domain configuration information includes primary domain device information, IO default configuration information and primary domain connection information, and the backup domain configuration information includes backup domain device information, IO mapping information and backup domain connection information. The first connection module is used to connect analog signals, digital signals and IO multiplexed signals in the main domain according to the IO default configuration information and the main domain connection information through the main domain connector of the main domain processing center, generate the number of channels and register reset value of the main domain IO controller, and perform differentiated routing of the IO control signals generated by the main domain IO controller according to power supply affiliation. The first generation module is used to allocate addresses to main domain devices and generate main domain address mapping tables according to the main domain device information through the main domain generator of the main domain processing center, instantiate the main domain devices and connect them to the corresponding main domain bus, and integrate main domain interrupt signals, main domain DMA signals and main domain error signals. The second connection module is used to connect the digital signals and IO multiplexing signals in the backup domain respectively through the backup domain connector of the backup domain processing center, based on the IO mapping information and the backup domain connection information, to generate the number of channels and register reset value of the backup domain IO controller, and to perform differentiated routing of the IO control signals generated by the backup domain IO controller according to power supply affiliation. The second generation module is used to allocate addresses to backup domain peripherals and generate backup domain address mapping tables according to the backup domain device information through the backup domain generator in the backup domain processing center, instantiate the backup domain peripherals and connect them to the corresponding backup domain bus, and integrate backup domain interrupt signals, backup domain DMA signals and backup domain error signals.

[0007] A third aspect of this disclosure provides an electronic device comprising: a processor and a memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the method described in the first aspect.

[0008] A fourth aspect of this disclosure provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the method of the first aspect described above.

[0009] The technical solution provided in this disclosure has the following advantages compared with the prior art: This embodiment of the disclosure can automatically generate a chip system through a primary domain configuration document and a backup domain configuration document. Thus, when the design changes, only the primary domain configuration document and the backup domain configuration need to be updated to automatically reconstruct the chip system. This significantly reduces human error and repetitive work caused by design changes. Under the premise of ensuring system stability and functional safety, it greatly accelerates the development cycle of new chip systems and effectively reduces the workload of document writing, peripheral instantiation and wiring. Attached Figure Description The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a flowchart of an automatic chip system generation method provided in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the working logic of a file processing center provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of the structure of a primary domain processing center and a backup domain processing center provided in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the working logic of a master domain connector provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of a preset master domain bus architecture provided in an embodiment of this disclosure; Figure 6 This is a schematic diagram of the working logic of a main domain generator provided in an embodiment of this disclosure; Figure 7 This is a schematic diagram of the working logic of a backup domain connector provided in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the working logic of a multiplexer provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of a preset backup domain bus architecture provided in an embodiment of this disclosure; Figure 10 This is a schematic diagram of the structure of an automatic chip system generation device provided in an embodiment of this disclosure; Figure 11 This is a schematic diagram of the structure of an electronic device according to an embodiment of this disclosure. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] As chips are increasingly used in more and more scenarios, the modules integrated within chips (such as MCUs) are becoming more numerous and complex. Simultaneously, the power consumption and area requirements for chips are also increasing. This necessitates that chip designs balance the number of internal processors, pins, and peripherals to accommodate a wider range of operating scenarios within the smallest possible area. Depending on the application scenario, the same series of chips may be divided into dozens of models based on differences in Flash and SRAM size, the number of peripherals, the number of pins, and the package. This is especially true for automotive-grade chips, which have graded functional safety requirements, resulting in even greater diversity in specifications.

[0015] Current design solutions typically involve writing a design specification document and then manually instantiating and wiring peripherals at the RTL level according to that document. However, once a system design is complete, any subsequent modifications to the internal design require writing a new design specification document and significant refactoring. Peripheral instantiation, interrupt connections, DMA signal connections, error signal connections, I / O multiplexing connections, internal device wiring, and memory testing interfaces all need to be manually redone in the code, extending the development cycle and increasing the risk of signal logic conflicts. Furthermore, after writing the design specification document, testers need to re-arrange the test base addresses for addresses and registers, which is inefficient.

[0016] In view of this, the present disclosure provides a method, apparatus, device, and storage medium for automatically generating chip systems. The method for automatically generating chip systems will be described in detail below. Figure 1 This is a flowchart illustrating an automatic chip system generation method provided in this disclosure, which can be executed by an electronic device. This electronic device can be exemplarily understood as a device such as a mobile phone, tablet computer, laptop computer, or desktop computer. Figure 1 As shown, the method provided in this embodiment includes the following steps: S110. Through the file processing center, extract the primary domain configuration information from the primary domain configuration document and the backup domain configuration information from the backup domain configuration document. The primary domain configuration information includes primary domain device information, IO default configuration information and primary domain connection information. The backup domain configuration information includes backup domain device information, IO mapping information and backup domain connection information.

[0017] Specifically, a chip (such as an MCU) includes a main domain (i.e., the Main / Off Domain) and a backup domain (i.e., the Backup Domain / AON Domain). The main domain includes main domain devices such as the CPU, peripherals, and main memory, while the backup domain includes backup domain devices such as the RTC, backup registers, and comparators.

[0018] Specifically, the primary domain configuration document records primary domain configuration information such as the primary domain devices, their connection relationships, resource configurations, and operational attributes. The primary domain configuration document can be, for example, an Excel document or a Word document, but is not limited to these formats.

[0019] Specifically, the master domain configuration information includes master domain device information, I / O default configuration information, and master domain connection information. Master domain device information describes the information of each master domain device included in the master domain (such as type and quantity). I / O default configuration information describes the configuration data of the I / O pins in reset or default states, including their functions, electrical characteristics, and multiplexing modes. Master domain connection information describes the signal connections and access paths between master domain devices within the master domain, as well as the signal connections and access paths between each master domain device domain and the master domain bus.

[0020] Specifically, the backup domain configuration document records the primary domain configuration information, such as the devices in the backup domain, their connection relationships, resource configurations, and operational attributes. The backup domain configuration document can be, for example, an Excel document or a Word document, but is not limited to these formats.

[0021] Specifically, the backup domain configuration information includes backup domain device information, I / O mapping information, and backup domain connection information. The backup domain device information describes the information of each backup domain device (such as type and quantity). The I / O mapping information describes the correspondence between the same I / O pin in the primary and backup domains, and typically includes the default configuration information for these I / O pins. The backup domain connection information describes the signal connections and access paths between backup domain devices within the backup domain, as well as the signal connections and access paths between each backup domain device domain and the backup domain bus.

[0022] Optionally, primary domain configuration information can be extracted from the primary domain configuration document and backup domain configuration information can be extracted from the backup domain configuration document, including: The worksheets in the primary domain configuration document are divided into three categories according to their table names: primary domain system requirements table, IO multiplexing table, and primary domain system connection table. Extract primary domain device information from the primary domain system requirements table, extract IO default configuration information from the IO multiplexing table, and extract primary domain connection information from the primary domain system connection table. The worksheets in the backup domain configuration document are divided into three categories according to their table names: backup domain system requirements table, IO mapping table, and backup domain system connection table. Extract backup domain device information from the backup domain system requirements table, extract IO mapping information from the IO mapping table, and extract backup domain connection information from the backup domain system connection table.

[0023] Specifically, the primary domain system requirements table records the types and quantities of primary domain devices. The I / O multiplexing table defines the default configurations for I / O (such as GPIO). The primary domain system connection table describes internal connection information and multiplexed connection information within the primary domain. All these worksheets together constitute the complete signal interconnection topology within the primary domain.

[0024] For example, the primary domain system requirements table is a worksheet in the primary domain configuration document named "Requirements" (such as an Excel spreadsheet). The IO multiplexing table is a worksheet in the primary domain configuration document named "IO Multiplexing Table". The primary domain connection table is all worksheets in the primary domain configuration document whose table names are excluding "Requirements" and "IO Multiplexing Table". Thus, the three types of tables are identified by strictly matching their table names: only when the table name equals "Requirements" or "IO Multiplexing Table" are they classified as either the primary domain system requirements table or the IO multiplexing table, respectively; all other worksheets (such as those named primary domain device names) are considered primary domain connection tables. Then, the primary domain system requirements table and the IO multiplexing table are sent to the initialization information extraction module of the file processing center, and the primary domain system connection table is sent to the connection information extraction module of the file processing center. The initialization information extraction module extracts two types of information: the type and quantity of main domain devices (i.e., main domain device information, extracted from the main domain system requirement table) and GPIO default configuration (i.e., IO default configuration information, extracted from the IO multiplexing table). After statistical analysis, these are packaged and sent to the information integration module in the file processing center. The connection information extraction module summarizes all main domain system connection tables, performs deduplication processing on the connection information in the main domain system connection tables, and classifies the deduplicated connection information into digital pin types, analog pin types, and internal device types based on the connection object type associated with each connection information. The categorized connection information (i.e., main domain connection information) is then packaged and output to the information integration module. The information integration module packages the main domain device information, IO default configuration information, and main domain connection information and sends them to the main domain processing center.

[0025] Specifically, the backup domain system requirements table records the types and quantities of backup domain devices. The IO mapping table records the correspondence between primary and backup domain IO. The backup domain system connection table describes the internal connection information and multiplexing connection information within the backup domain. All these worksheets together constitute the complete signal interconnection topology within the backup domain.

[0026] For example, such as Figure 2As shown, the Backup Domain System Requirements Table is the worksheet (such as an Excel sheet) in the Backup Domain Configuration Document named "Requirements". The IO Mapping Table is the worksheet in the Backup Domain Configuration Document named "IO Mapping Table". The Backup Domain Connection Table is all worksheets in the Backup Domain Configuration Document except those named "Requirements" and "IO Multiplexing Table". Thus, the three types of tables are identified by strictly matching their names: only when the table name equals "Requirements" or "IO Multiplexing Table" are they classified as the Backup Domain System Requirements Table or the IO Multiplexing Table, respectively; all other worksheets (such as those named Backup Domain Device Name) are considered Backup Domain Connection Tables. Then, the Backup Domain System Requirements Table and the IO Mapping Table are sent to the Initialization Information Extraction Module, and the Backup Domain System Connection Table is sent to the Connection Information Extraction Module. The initialization information extraction module extracts two types of information: backup domain device types and quantities (i.e., backup domain device information, extracted from the backup domain system requirement table) and IO mapping information (extracted from the IO mapping table). After statistical analysis, these are packaged and sent to the information integration module. The connection information extraction module summarizes all backup domain system connection tables, performs deduplication on the connection information in the backup domain system connection tables, and classifies the deduplicated connection information into digital pin categories and internal device categories based on the connection object type associated with each connection information. The categorized connection information (i.e., backup domain connection information) is then packaged and output to the information integration module. The information integration module packages the backup domain device information, IO default configuration information, and backup domain connection information and sends them to the backup domain processing center.

[0027] Understandably, by automatically dividing the worksheets in the primary domain configuration document into three categories based on table names, a structured separation of primary domain configuration information is achieved. This allows for the extraction of primary domain device information, default IO configuration information, and primary domain connection information from the three categories of worksheets, effectively avoiding errors from manual integration and providing a reliable and clear data foundation for the automated implementation of the primary domain system. The same principle applies to the backup domain configuration document, and will not be elaborated upon here.

[0028] S120. Through the main domain connector of the main domain processing center, the analog signals, digital signals and IO multiplexed signals in the main domain are connected according to the IO default configuration information and the main domain connection information, generating the number of channels and register reset values ​​of the main domain IO controller, and routing the IO control signals generated by the main domain IO controller differently according to power supply affiliation.

[0029] Specifically, such as Figure 3As shown, the main domain processing center includes a main domain connector and a main domain generator. The main domain connector traverses all connection information involved in the "IO default configuration information and main domain connection information," completing the following three types of interconnections: connecting analog signals to the corresponding analog signal ports, routing digital signals to internal main domain devices, and configuring IO multiplexed signals according to their default pin functions, thereby completing the correct interconnection of various signals within the main domain. Based on the IO default configuration information and main domain connection information, the main domain connector generates the number of channels and register reset values ​​for the main domain IO controller. When performing differentiated routing of IO control signals, the main domain connector integrates the power domain attributes and default functions in the IO default configuration information, as well as the connection information and multiplexing topology in the main domain connection information, to determine whether each IO control signal should be directly driven by the main domain IO controller or forwarded to the backup domain connector for cross-domain processing.

[0030] Optionally, based on the default IO configuration information and the main domain connection information, the analog signals, digital signals, and IO multiplexed signals within the main domain are connected separately to generate the number of channels and register reset values ​​for the main domain IO controller. The IO control signals generated by the main domain IO controller are then routed differently according to power supply affiliation, including: Based on the default IO configuration information and the primary domain connection information, construct mutually independent analog interconnection matrices and digital interconnection matrices; Based on the analog interconnect matrix, connect the analog signals in the main domain to the corresponding analog signal ports; Based on the digital interconnection matrix, establish digital signal connections between devices in each main domain within the main domain; Based on the digital interconnection matrix, establish the configuration connection for the IO multiplexing write signal and the configuration connection for the IO multiplexing read signal of the main domain IO controller; Based on the IO initialization information in the default IO configuration information, generate the number of channels and register reset values ​​for the primary domain IO controller; If the IO control signal generated by the main domain IO controller controls an IO pin that belongs only to the main domain, connect it to the corresponding main power domain PAD. If the IO control signal generated by the primary domain IO controller controls an IO pin belonging to both the primary and backup domains, it is passed to the multiplexer of the backup domain connector.

[0031] Specifically, the digital interconnection matrix is ​​a unified digital signal exchange hub within the main domain. It is responsible for data communication between devices in the main domain and also provides the main domain IO controller with a configuration access path for IO multiplexing functions.

[0032] Specifically, an analog interconnect matrix is ​​a switching network specifically designed for routing analog signals (such as voltage, current, or sensor signals) to connect analog signals within a main domain to corresponding analog signal ports.

[0033] Specifically, such as Figure 4 As shown, the master domain connector loads the connection information involved in the default IO configuration information and master domain connection information into the digital interconnect matrix and the analog interconnect matrix. According to the analog interconnect matrix, analog signals within the master domain are routed and connected to the corresponding analog signal ports (such as IO pads supporting analog functions, and the input / output terminals of analog IP cores). Furthermore, based on the digital interconnect matrix, on the one hand, digital data and control paths are established between various master domain devices within the master domain; on the other hand, the control paths for IO multiplexing functions by the master domain IO controller are configured (such as IO multiplexing write control paths and IO multiplexing read control paths).

[0034] Specifically, the master domain connector also passes IO initialization information to the master domain IO controller instantiation unit to determine the number of channels of the generated IO controller and its register reset value.

[0035] Specifically, the main power domain PAD refers to the input / output pins powered by the chip's main power supply. The backup power domain PAD refers to the dedicated pins powered by an independent backup power supply.

[0036] Specifically, such as Figure 4 As shown, the main power domain PAD is directly driven by the main domain IO controller. More specifically, if the IO pin controlled by the IO control signal belongs only to the main domain, it is connected to the corresponding main power domain PAD. The backup power domain PAD is not directly connected to the main domain IO controller. More specifically, if the IO pin controlled by the IO control signal belongs to both the main domain and the backup domain, it is passed to the multiplexer of the backup domain connector. The multiplexer performs the multiplexing selection with the IO control signals in the backup domain. For details on the operation, please refer to the backup domain connector section, which will not be elaborated here.

[0037] Understandably, by integrating the default IO configuration information with the main domain connection information, the system automatically completes the classification and connection of analog signals, digital signals, and IO multiplexed signals within the main domain. At the same time, it accurately generates the number of channels and register reset values ​​required by the main domain IO controller, and further implements differentiated routing of IO control signals based on the power domain affiliation (main domain or backup domain) of each IO pin, avoiding signal disconnection, function failure, pin conflict, or multiplexing configuration errors caused by manual wiring omissions.

[0038] S130. Through the main domain generator in the main domain processing center, based on the main domain device information, the main domain device is assigned an address and a main domain address mapping table is generated. The main domain device is instantiated and connected to the corresponding main domain bus. The main domain interrupt signal, main domain DMA signal and main domain error signal are integrated.

[0039] Specifically, based on the master domain device information (such as the type and number of master domain devices), a unique base address is assigned to each master domain device, and its occupied address range is calculated to generate a master domain address mapping table. The master domain devices are instantiated according to this master domain address mapping table and connected to the corresponding master domain bus. Interrupt request signals (i.e., master domain interrupt signals), DMA transfer request / acknowledgment signals (i.e., master domain DMA signals), and error reporting signals (i.e., master domain error signals, such as bus errors, checksum exceptions, etc.) from each master domain device are integrated and routed to the interrupt controller, DMA controller, and error management unit, respectively, thereby constructing a master domain system with clear addresses, complete connections, and coordinated control signals.

[0040] Specifically, the main generator automatically generates the top-level interconnect structure based on a preset main domain bus architecture. The specific structure of the preset main domain bus architecture can be set by those skilled in the art according to actual circumstances, and is not limited here. For example, such as... Figure 5 As shown, the CPU exists as an "empty shell" module containing only the top-level bus interface, without any specific microarchitecture implementation, thus supporting flexible adaptation to different manufacturers' or types of processor cores. Various master domain devices (excluding the CPU) strictly follow predefined connection rules, being instantiated and mounted only to their designated target buses (such as IBUS, DBUS, or PBUS), as shown in the figure. Each master domain bus is allocated a fixed address range, and the base addresses of master domain devices are sequentially arranged on their respective master domain buses, ensuring continuous, conflict-free, and statically resolvable address mappings. The master domain bus address allocation list is as follows:

[0041] Furthermore, IBUS, DBUS, and PBUS all support optional implementations between the TileLink and AXI protocols. Regardless of the protocol used, ECC (Error Correcting Code) protection mechanisms are deployed on both the address and data channels for address integrity verification and data transmission fault tolerance, respectively. Simultaneously, each primary domain device interface is configured with an independent bus firewall to monitor and intercept unauthorized access, unauthorized transactions, and abnormal operations in real time, thereby meeting the hardware-level security and reliability requirements of functional safety standards (such as ISO 26262 ASIL-B / D).

[0042] Optionally, based on the master domain device information, an address is allocated to the master domain device and a master domain address mapping table is generated. The master domain device is instantiated and connected to the corresponding master domain bus. Master domain interrupt signals, master domain DMA signals, and master domain error signals are integrated, including: Based on the various types of primary domain devices and their quantities recorded in the primary domain device information, addresses are allocated to the primary domain devices in sequence and mapping relationships are established to obtain the primary domain address mapping table. The primary domain address mapping table is then exported as a worksheet and a header file, respectively. Based on the primary domain address mapping table, generate the primary domain bus code, and instantiate the primary domain devices based on their types and addresses, then connect the instances of the primary domain devices to the bus. The system integrates the main domain interrupt signals, main domain DMA request signals, and main domain error signals output by each main domain device instance. The main domain interrupt signals are aggregated into multi-bit wide interrupt vectors, the main domain DMA signals are distributed to multiple different DMA modules according to a preset allocation strategy, and the error signals are packaged and connected to the error control unit.

[0043] Specifically, such as Figure 6 As shown, the master generator automatically assigns a unique base address to each master domain device based on the master domain device information and calculates the address range it occupies, thereby generating a complete master domain address mapping table. This master domain address mapping table will be output synchronously in two formats: an Excel document (for document archiving) and a C language header file (for software and testing). Understandably, the automatic generation and multi-format output of the master domain address mapping table effectively avoid address conflicts or omissions caused by manual allocation.

[0044] Specifically, such as Figure 6 As shown, the main generator automatically generates the code and instantiation units of the main domain bus based on the main domain address mapping table. Furthermore, according to the base address, address range, and bus type defined in the main domain address mapping table, it instantiates the corresponding main domain device and attaches its interface to the specified main domain bus. This eliminates the tedious work of manually writing code, avoids problems such as incorrect connections, omissions, or address conflicts, and makes chip integration faster, more accurate, and more reliable.

[0045] Specifically, such as Figure 6As shown, three types of key global signals are automatically collected and integrated: For interrupt signals (i.e., master domain interrupt signals), all single-bit interrupt request lines of master domain devices are merged into a multi-bit interrupt vector and output uniformly to the interrupt controller input port; for DMA signals (i.e., master domain DMA signals), according to a preset allocation strategy (such as polling and equal distribution), the DMA signals of master domain devices are evenly distributed to the available channels of multiple DMA controllers; for error signals (i.e., master domain error signals), they are uniformly packaged and connected to the fault control unit for centralized processing. The source-destination connection relationships of the above three types of signals will be output in both Excel spreadsheet and / or Markdown document formats for easy integration verification and design traceability. It can be understood that the automatic integration and structured document output of interrupt, DMA, and error signals significantly enhances the traceability and functional safety of the system control path.

[0046] Optionally, the method further includes: constructing a register model of the primary domain device, and exporting the register model into header file and register abstraction layer description file formats respectively based on the register model; Declare I / O pins not occupied by master domain devices as general purpose input / output ports.

[0047] Specifically, for each primary domain device's register description, register fields, access permissions, and reset values ​​are extracted to generate a standardized register model, which is output as follows: a C header file (periph_regs.h) for embedded software use; and a UVMRALF file (periph.ralf) for verifying register abstraction layer modeling in the environment, supporting automated pre-simulation and post-simulation testing. In essence, the generation of the register model provides a unified and reliable register abstraction foundation for front-end and back-end verification.

[0048] Specifically, all chip pins not used by internal logic (including unassigned general-purpose I / O, reserved debug interfaces, or unconnected analog channels) will be directly brought out as top-level module ports and handed over to the MainConnector module for subsequent processing, including: I / O multiplexing configuration, power domain attribution determination, electrical attribute settings, and physical pin binding. Understandably, this unified top-level outreach mechanism for unbound I / O pins ensures the complete exposure and flexible reuse of chip I / O resources, providing a clear interface for the MainConnector's subsequent power domain allocation, pin multiplexing configuration, and physical implementation.

[0049] S140. Through the backup domain connector of the backup domain processing center, based on the IO mapping information and backup domain connection information, the digital signals and IO multiplexed signals in the backup domain are connected respectively to generate the number of channels and register reset value of the backup domain IO controller, and the IO control signals generated by the backup domain IO controller are routed to the multiplexer. Specifically, the backup domain processing center includes a backup domain connector and a backup domain generator. The backup domain connector traverses all connection information involved in the "IO mapping information and backup domain connection information," completing the following two types of interconnections: routing digital signals to internal backup domain devices, and configuring IO multiplexed signals according to IO mapping relationships and default pin functions, thereby completing the correct interconnection of various signals within the backup domain. Based on the IO mapping information and backup domain connection information, the backup domain connector generates the number of channels and register reset values ​​for the backup domain IO controller. The backup domain connector routes each IO control signal to the corresponding multiplexer.

[0050] Optionally, based on IO mapping information and backup domain connection information, the digital signals and IO multiplexed signals within the backup domain are connected separately to generate the number of channels and register reset values ​​for the backup domain IO controller. The IO control signals generated by the backup domain IO controller are then routed differently according to power supply affiliation, including: Construct a backup domain interconnection matrix based on IO mapping information and backup domain connection information; Based on the backup domain interconnection matrix, establish digital signal connections between peripheral devices in each backup domain; Based on the backup domain interconnection matrix, establish the configuration connection for the IO multiplexing write signal and the configuration connection for the IO multiplexing read signal of the backup domain IO controller; Based on the IO initialization information in the IO mapping information, generate the number of channels and register reset values ​​for the IO controller; If the IO control signal generated by the backup domain IO controller controls an IO pin that belongs only to the backup domain, connect it to the corresponding backup power domain PAD. If the IO control signal generated by the backup domain IO controller controls an IO pin belonging to both the primary and backup domains, it is passed to the multiplexer of the backup domain connector.

[0051] Specifically, the backup domain interconnection matrix is ​​a unified digital signal exchange hub within the backup domain. It is responsible for data communication between backup domain devices and also provides the backup domain IO controller with a configuration access path for IO multiplexing functions.

[0052] Specifically, such as Figure 7As shown, the backup domain connector loads the connection information involved in the IO mapping information and backup domain connection information into the backup domain interconnect matrix. Based on the backup domain digital interconnect matrix, on the one hand, digital data and control paths between backup domain devices are established, and on the other hand, the control paths of the backup domain IO controller for IO multiplexing functions (such as IO multiplexing write control path and IO multiplexing read control path) are also configured.

[0053] Specifically, such as Figure 7 As shown, the backup domain connector also passes IO initialization information to the backup domain IO controller instantiation unit to determine the number of channels and register reset values ​​of the generated IO controller.

[0054] Specifically, such as Figure 7 As shown, the backup domain connector performs a multiplexing (MUX) on the I / O control signals from the primary and backup domains based on the I / O mapping information. The specific selection logic is as follows: Figure 8 As shown: If a backup power domain PAD is not defined in the primary / backup mapping table, it is directly driven by the primary domain IO controller; if a corresponding relationship exists, the MUX selection strategy is as follows: When the primary power domain is powered off, the MUX defaults to selecting the backup domain IO control signal to ensure that critical functions (such as RTC wake-up) can still work; when the primary power domain is powered on, the primary IO controller outputs an IO control selection signal to dynamically determine whether to use the primary or backup domain control signal, enabling flexible switching during operation.

[0055] Understandably, by integrating IO mapping information and backup domain connection information, the system automatically completes the classification and connection of digital signals and IO multiplexed signals within the backup domain. At the same time, it accurately generates the number of channels and register reset values ​​required by the backup domain IO controller and routes each IO control signal to the corresponding multiplexer, avoiding signal disconnection, functional failure, pin conflict, or multiplexing configuration errors caused by omissions in manual wiring.

[0056] S150. Through the backup domain generator in the backup domain processing center, based on the backup domain device information, the backup domain peripherals are assigned addresses and a backup domain address mapping table is generated. The backup domain peripherals are instantiated and connected to the corresponding backup domain bus. The backup domain interrupt signal, backup domain DMA signal and backup domain error signal are integrated.

[0057] Specifically, based on the backup domain device information (such as the type and number of backup domain devices), a unique base address is assigned to each backup domain device, and its occupied address range is calculated to generate a backup domain address mapping table. The backup domain devices are instantiated according to this backup domain address mapping table and connected to the corresponding backup domain bus. Interrupt request signals (i.e., backup domain interrupt signals), DMA transfer request / acknowledgment signals (i.e., backup domain DMA signals), and error reporting signals (i.e., backup domain error signals, such as bus errors and checksum exceptions) from each backup domain device are integrated and routed to the interrupt controller, DMA controller, and error management unit, respectively, thereby constructing a backup domain system with clear addresses, complete connections, and coordinated control signals.

[0058] Specifically, the backup generator automatically generates the top-level interconnect structure based on a preset backup domain bus architecture. The specific structure of the preset backup domain bus architecture can be set by those skilled in the art according to actual conditions, and is not limited here. For example, such as... Figure 9 As shown, all backup domain devices (including SRAM controllers, SCUs, etc.) are mounted on the same shared backup domain bus. This backup domain bus supports the following configuration options: data width: 8 bits or 32 bits; bus protocol: APB or BRAM interface; to adapt to backup CPUs with different performance and area requirements (such as small RISC-V cores, 8051 cores, or state machine controllers). In addition to being accessible within the backup domain, the SRAM controller and system control unit (SCU) can also be configured or monitored by the primary domain system via an external bus (corresponding to the APB2 interface in the primary generator), thereby achieving controlled collaboration between the primary and backup domains. Optionally, based on the backup domain device information, addresses are allocated to backup domain peripherals and a backup domain address mapping table is generated. Backup domain peripherals are instantiated and connected to the corresponding backup domain bus. Backup domain interrupt signals, backup domain DMA signals, and backup domain error signals are integrated, including: Based on the various backup domain peripherals and their quantities recorded in the backup domain device information, addresses are allocated to the backup domain peripherals in sequence and mapping relationships are established to obtain the backup domain address mapping table. The backup domain address mapping table is then exported as a worksheet and a header file, respectively. Based on the backup domain address mapping table, generate the code for the backup domain bus, and instantiate the backup domain peripherals based on their types and addresses, then connect the backup domain peripheral instances to the bus. The backup domain interrupt signal, backup domain DMA request signal and backup domain error signal output by each backup domain peripheral are integrated. The backup domain interrupt signal is aggregated into a multi-bit wide interrupt vector, the backup domain DMA signal is distributed to multiple different DMA modules according to a preset allocation strategy, and the error signal is packaged and connected to the error control unit.

[0059] Specifically, the backup generator automatically assigns a unique base address to each backup domain device based on the backup domain device information and calculates the address range it occupies, thereby generating a complete backup domain address mapping table. This backup domain address mapping table will be output synchronously in two formats: an Excel document (for document archiving) and a C language header file (for software and testing). Understandably, the automatic generation and multi-format output of the backup domain address mapping table effectively avoids address conflicts or omissions caused by manual allocation.

[0060] Specifically, the backup generator automatically generates the code and instantiation units of the backup domain bus based on the backup domain address mapping table. Furthermore, according to the base address, address range, and bus type defined in the backup domain address mapping table, it instantiates the corresponding backup domain devices and attaches their interfaces to the designated backup domain bus. This eliminates the tedious work of manually writing code, avoids problems such as incorrect connections, omissions, or address conflicts, and makes chip integration faster, more accurate, and more reliable.

[0061] Specifically, the system automatically collects and integrates three types of critical global signals: For interrupt signals (i.e., backup domain interrupt signals), all single-bit interrupt request lines from backup domain devices are merged into a multi-bit interrupt vector and output uniformly to the interrupt controller input port; for DMA signals (i.e., backup domain DMA signals), according to a preset allocation strategy (such as polling and equal distribution), the DMA signals from backup domain devices are evenly distributed to the available channels of multiple DMA controllers; for error signals (i.e., backup domain error signals), they are uniformly packaged and connected to the fault control unit for centralized processing. The source-destination connection relationships of the above three types of signals will be output in both Excel spreadsheet and / or Markdown document formats for easy integration verification and design traceability. It is understandable that the automatic integration and structured document output of interrupt, DMA, and error signals significantly enhances the traceability and functional safety of the system control path.

[0062] Optionally, the method further includes: constructing a register model for the backup domain device, and exporting the register model into header file and register abstraction layer description file formats respectively based on the register model; Declare the I / O pins not occupied by backup domain devices as general purpose input / output ports.

[0063] Specifically, for each backup domain device's register description, register fields, access permissions, and reset values ​​are extracted to generate a standardized register model, which is output as follows: a C header file (periph_regs.h) for embedded software use; and a UVM RALF file (periph.ralf) for verifying register abstraction layer modeling in the environment, supporting automated pre-simulation and post-simulation testing. In essence, the generation of the register model provides a unified and reliable register abstraction foundation for front-end and back-end verification.

[0064] Specifically, all chip pins not used by internal logic (including unassigned general-purpose I / O, reserved debug interfaces, or unconnected analog channels) will be directly brought out as top-level module ports and handed over to the Backup Connector module for subsequent processing, including: I / O multiplexing configuration, power domain attribution determination, electrical attribute settings, and physical pin binding. Understandably, this unified top-level outreach mechanism for unbound I / O pins ensures the complete exposure and flexible reuse of chip I / O resources, reserving a clear interface for subsequent power domain partitioning, pin multiplexing configuration, and physical implementation by the Backup Connector.

[0065] In summary, this disclosure presents an automatic chip system generation scheme based on primary domain configuration documents and backup domain configuration documents to complete the chip system design. This disclosure can automatically generate instantiated structures within the SpinalHDL architecture, automatically connect interrupt, DMA, and error signals, connect multiplexed signals and internal special signals according to the connection information, and output the automatically connected documents and test / verification files, significantly improving accuracy and efficiency. Furthermore, this disclosure relies on a specific bus design, integrating multiple functional safety measures such as ECC, bus monitoring, and error diagnosis on the link, meeting ASIL-D requirements at its highest level. The special bus design caters to low-power requirements, allowing for separate design for low-power systems. The flexible bus design is compatible with various CPUs, enabling flexible system design. The automated design can generate address mapping table files, address mapping header files, peripheral header files, and peripheral uvmralf files, facilitating testing and verification.

[0066] Figure 10 This is a schematic diagram of a chip system automatic generation device provided in an embodiment of this disclosure. This chip system automatic generation device can be understood as the aforementioned electronic device or a functional module within the aforementioned electronic device. For example... Figure 10 As shown, the automatic chip system generation device includes: The first extraction module 1010 is used to extract primary domain configuration information from the primary domain configuration document and backup domain configuration information from the backup domain configuration document through the file processing center. The primary domain configuration information includes primary domain device information, IO default configuration information and primary domain connection information, and the backup domain configuration information includes backup domain device information, IO mapping information and backup domain connection information. The first extraction module 1020 is used to connect analog signals, digital signals and IO multiplexed signals in the main domain according to the IO default configuration information and the main domain connection information through the main domain connector of the main domain processing center, generate the number of channels and register reset value of the main domain IO controller, and perform differentiated routing of the IO control signals generated by the main domain IO controller according to power supply affiliation. The first generation module 1030 is used to allocate addresses to main domain devices and generate main domain address mapping tables according to the main domain device information through the main domain generator of the main domain processing center, instantiate the main domain devices and connect them to the corresponding main domain bus, and integrate main domain interrupt signals, main domain DMA signals and main domain error signals. The second connection module 1040 is used to connect the digital signals and IO multiplexing signals in the backup domain respectively through the backup domain connector of the backup domain processing center, based on the IO mapping information and the backup domain connection information, to generate the number of channels and register reset value of the backup domain IO controller, and to perform differentiated routing of the IO control signals generated by the backup domain IO controller according to power supply affiliation. The second generation module 1050 is used to allocate addresses to backup domain peripherals and generate backup domain address mapping tables according to the backup domain device information through the backup domain generator of the backup domain processing center, instantiate the backup domain peripherals and connect them to the corresponding backup domain bus, and integrate backup domain interrupt signals, backup domain DMA signals and backup domain error signals.

[0067] Optionally, the first extraction module 1010 is specifically used to divide the worksheets in the main domain configuration document into three categories according to the table name: main domain system requirements table, IO multiplexing table, and main domain system connection table; Extract the primary domain device information from the primary domain system requirements table, extract the IO default configuration information from the IO multiplexing table, and extract the primary domain connection information from the primary domain system connection table; The worksheets in the backup domain configuration document are divided into three categories according to their table names: backup domain system requirements table, IO mapping table, and backup domain system connection table. The backup domain device information is extracted from the backup domain system requirement table, the IO mapping information is extracted from the IO mapping table, and the backup domain connection information is extracted from the backup domain system connection table.

[0068] Optionally, the first extraction module 1020 is specifically used to construct mutually independent analog interconnection matrices and digital interconnection matrices based on the IO default configuration information and the main domain connection information; Based on the analog interconnection matrix, the analog signals within the main domain are connected to the corresponding analog signal ports; Based on the digital interconnection matrix, establish digital signal connections between each main domain device within the main domain; Based on the digital interconnection matrix, establish the configuration connection for the IO multiplexing write signal and the configuration connection for the IO multiplexing read signal of the main domain IO controller; Based on the IO initialization information in the IO default configuration information, generate the number of channels and register reset values ​​of the primary domain IO controller; If the IO pin controlled by the IO control signal generated by the main domain IO controller belongs only to the main domain, connect it to the corresponding main power domain PAD; If the IO pin controlled by the IO control signal generated by the primary domain IO controller belongs to both the primary domain and the backup domain, it is passed to the multiplexer of the backup domain connector.

[0069] Optionally, the first generation module 1030 is specifically used to allocate addresses to the main domain devices and establish mapping relationships according to the various types of main domain devices and their quantities recorded in the main domain device information, so as to obtain the main domain address mapping table, and export the main domain address mapping table into worksheet and header file formats respectively; Based on the primary domain address mapping table, the code for the primary domain bus is generated, and based on the type and address of the primary domain device, the primary domain device is instantiated, and the instance of the primary domain device is connected to the bus. The main domain interrupt signal, main domain DMA request signal and main domain error signal output by each instance of the main domain device are integrated. The main domain interrupt signal is aggregated into a multi-bit wide interrupt vector. The main domain DMA signal is distributed to multiple different DMA modules according to a preset allocation strategy. The error signal is packaged and connected to the error control unit.

[0070] Optionally, the device further includes: a first construction module for constructing a register model of the primary domain device, and exporting the register model into a header file and a register abstraction layer description file format, respectively; The first declaration module is used to declare IO pins not occupied by the main domain device as general-purpose input / output ports.

[0071] Optionally, the second connection module 1040 is used to construct a backup domain interconnection matrix based on the IO mapping information and the backup domain connection information; Based on the backup domain interconnection matrix, establish digital signal connections between peripheral devices of each backup domain within the backup domain; Based on the backup domain interconnection matrix, establish the configuration connection for the IO multiplexing write signal and the configuration connection for the IO multiplexing read signal of the backup domain IO controller; Based on the IO initialization information in the IO mapping information, the number of channels and register reset values ​​of the IO controller are generated; If the IO pin controlled by the IO control signal generated by the backup domain IO controller belongs only to the backup domain, connect it to the corresponding backup power domain PAD; If the IO pin controlled by the IO control signal generated by the backup domain IO controller belongs to both the main domain and the backup domain, it is passed to the multiplexer of the backup domain connector.

[0072] Optionally, the second generation module 1050 is used to allocate addresses and establish mapping relationships for the backup domain peripherals in sequence according to the various types of backup domain peripherals and their quantities recorded in the backup domain device information, so as to obtain the backup domain address mapping table, and export the backup domain address mapping table into worksheet and header file formats respectively. Based on the backup domain address mapping table, generate the code for the backup domain bus, and instantiate the backup domain peripheral based on its type and address, and connect the instance of the backup domain peripheral to the bus. The backup domain interrupt signal, backup domain DMA request signal, and backup domain error signal output by each instance of the backup domain peripheral are integrated. The backup domain interrupt signal is aggregated into a multi-bit wide interrupt vector, the backup domain DMA signal is distributed to multiple different DMA modules according to a preset allocation strategy, and the error signal is packaged and connected to the error control unit.

[0073] The apparatus provided in this embodiment can execute the methods of any of the above embodiments, and its execution method and beneficial effects are similar, so they will not be described again here.

[0074] This disclosure also provides an electronic device, which includes: a memory storing a computer program; and a processor for executing the computer program, wherein when the computer program is executed by the processor, it can implement the methods of any of the above embodiments.

[0075] Example, Figure 11 This is a schematic diagram of the structure of an electronic device according to an embodiment of this disclosure. See below for details. Figure 11The diagram illustrates a structural schematic suitable for implementing the electronic device 1100 in the embodiments of this disclosure. The electronic device 1100 in the embodiments of this disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 11 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0076] like Figure 11 As shown, electronic device 1100 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 1101, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1102 or a program loaded from storage device 1108 into random access memory (RAM) 1103. The RAM 1103 also stores various programs and data required for the operation of electronic device 1100. The processing device 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0077] Typically, the following devices can be connected to I / O interface 1105: input devices 1106 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1107 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1108 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1109. Communication device 1109 allows electronic device 1100 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 11 An electronic device 1100 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0078] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 1109, or installed from storage device 1108, or installed from ROM 1102. When the computer program is executed by processing device 1101, it performs the functions defined in the methods of embodiments of this disclosure.

[0079] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0080] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0081] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0082] The aforementioned computer-readable medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform any of the aforementioned method embodiments.

[0083] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0084] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0085] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0086] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0087] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0088] This disclosure also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the methods of any of the above embodiments. The execution method and beneficial effects are similar, and will not be described again here.

[0089] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for automatically generating a chip system, characterized in that, include: The file processing center extracts primary domain configuration information from the primary domain configuration document and backup domain configuration information from the backup domain configuration document. The primary domain configuration information includes primary domain device information, IO default configuration information, and primary domain connection information. The backup domain configuration information includes backup domain device information, IO mapping information, and backup domain connection information. Through the main domain connector of the main domain processing center, the analog signals, digital signals and IO multiplexed signals in the main domain are connected according to the default IO configuration information and the main domain connection information, respectively, to generate the number of channels and register reset value of the main domain IO controller, and to perform differentiated routing of the IO control signals generated by the main domain IO controller according to power supply affiliation; The main domain generator in the main domain processing center allocates addresses to the main domain devices and generates a main domain address mapping table based on the main domain device information. It instantiates the main domain devices and connects them to the corresponding main domain bus, and integrates the main domain interrupt signal, the main domain DMA signal and the main domain error signal. Through the backup domain connector in the backup domain processing center, based on the IO mapping information and the backup domain connection information, the digital signals and IO multiplexing signals in the backup domain are connected respectively to generate the number of channels and register reset value of the backup domain IO controller, and the IO control signals generated by the backup domain IO controller are routed to the multiplexer. The backup domain generator in the backup domain processing center allocates addresses to backup domain peripherals and generates backup domain address mapping tables based on the backup domain device information. It instantiates the backup domain peripherals and connects them to the corresponding backup domain bus, and integrates backup domain interrupt signals, backup domain DMA signals, and backup domain error signals.

2. The method according to claim 1, characterized in that, The process of extracting primary domain configuration information from the primary domain configuration document and extracting backup domain configuration information from the backup domain configuration document includes: The worksheets in the primary domain configuration document are divided into three categories according to their table names: primary domain system requirements table, IO multiplexing table, and primary domain system connection table. Extract the primary domain device information from the primary domain system requirements table, extract the IO default configuration information from the IO multiplexing table, and extract the primary domain connection information from the primary domain system connection table; The worksheets in the backup domain configuration document are divided into three categories according to their table names: backup domain system requirements table, IO mapping table, and backup domain system connection table. The backup domain device information is extracted from the backup domain system requirement table, the IO mapping information is extracted from the IO mapping table, and the backup domain connection information is extracted from the backup domain system connection table.

3. The method according to claim 1, characterized in that, The step involves connecting analog signals, digital signals, and IO multiplexed signals within the main domain according to the default IO configuration information and the main domain connection information, generating the number of channels and register reset values ​​for the main domain IO controller, and then routing the IO control signals generated by the main domain IO controller differently based on power supply affiliation, including: Based on the default IO configuration information and the primary domain connection information, construct mutually independent analog interconnection matrices and digital interconnection matrices; Based on the analog interconnection matrix, the analog signals within the main domain are connected to the corresponding analog signal ports; Based on the digital interconnection matrix, establish digital signal connections between each main domain device within the main domain; Based on the digital interconnection matrix, establish the configuration connection for the IO multiplexing write signal and the configuration connection for the IO multiplexing read signal of the main domain IO controller; Based on the IO initialization information in the IO default configuration information, generate the number of channels and register reset values ​​of the primary domain IO controller; If the IO pin controlled by the IO control signal generated by the main domain IO controller belongs only to the main domain, connect it to the corresponding main power domain PAD; If the IO pin controlled by the IO control signal generated by the primary domain IO controller belongs to both the primary domain and the backup domain, it is passed to the multiplexer of the backup domain connector.

4. The method according to claim 1, characterized in that, The process of allocating addresses to the main domain devices and generating a main domain address mapping table based on the main domain device information, instantiating the main domain devices and connecting them to the corresponding main domain bus, and integrating main domain interrupt signals, main domain DMA signals, and main domain error signals includes: Based on the various types of primary domain devices and their quantities recorded in the primary domain device information, addresses are allocated to the primary domain devices in sequence and mapping relationships are established to obtain the primary domain address mapping table. The primary domain address mapping table is then exported as a worksheet and a header file, respectively. Based on the primary domain address mapping table, the code for the primary domain bus is generated, and based on the type and address of the primary domain device, the primary domain device is instantiated, and the instance of the primary domain device is connected to the bus. The main domain interrupt signal, main domain DMA request signal and main domain error signal output by each instance of the main domain device are integrated. The main domain interrupt signal is aggregated into a multi-bit wide interrupt vector. The main domain DMA signal is distributed to multiple different DMA modules according to a preset allocation strategy. The error signal is packaged and connected to the error control unit.

5. The method according to claim 4, characterized in that, Also includes: Construct the register model of the primary domain device, and export the register model as a header file and a register abstraction layer description file format, respectively; Declare the I / O pins not occupied by the primary domain device as general-purpose input / output ports.

6. The method according to claim 1, characterized in that, Based on the IO mapping information and the backup domain connection information, the digital signals and IO multiplexed signals within the backup domain are connected respectively to generate the number of channels and register reset values ​​of the backup domain IO controller. The IO control signals generated by the backup domain IO controller are then routed differently according to power supply affiliation, including: Construct a backup domain interconnection matrix based on the IO mapping information and the backup domain connection information; Based on the backup domain interconnection matrix, establish digital signal connections between peripheral devices of each backup domain within the backup domain; Based on the backup domain interconnection matrix, establish the configuration connection for the IO multiplexing write signal and the configuration connection for the IO multiplexing read signal of the backup domain IO controller; Based on the IO initialization information in the IO mapping information, the number of channels and register reset values ​​of the IO controller are generated; If the IO pin controlled by the IO control signal generated by the backup domain IO controller belongs only to the backup domain, connect it to the corresponding backup power domain PAD; If the IO pin controlled by the IO control signal generated by the backup domain IO controller belongs to both the main domain and the backup domain, it is passed to the multiplexer of the backup domain connector.

7. The method according to claim 1, characterized in that, The process of allocating addresses to backup domain peripherals and generating a backup domain address mapping table based on the backup domain device information, instantiating the backup domain peripherals and connecting them to the corresponding backup domain bus, and integrating backup domain interrupt signals, backup domain DMA signals, and backup domain error signals includes: Based on the various types and quantities of backup domain peripherals recorded in the backup domain device information, addresses are allocated to the backup domain peripherals in sequence and mapping relationships are established to obtain the backup domain address mapping table. The backup domain address mapping table is then exported as a worksheet and a header file, respectively. Based on the backup domain address mapping table, generate the code for the backup domain bus, and instantiate the backup domain peripheral based on its type and address, and connect the instance of the backup domain peripheral to the bus. The backup domain interrupt signal, backup domain DMA request signal, and backup domain error signal output by each instance of the backup domain peripheral are integrated. The backup domain interrupt signal is aggregated into a multi-bit wide interrupt vector, the backup domain DMA signal is distributed to multiple different DMA modules according to a preset allocation strategy, and the error signal is packaged and connected to the error control unit.

8. An automatic chip system generation device, characterized in that, include: The first extraction module is used to extract primary domain configuration information from the primary domain configuration document and backup domain configuration information from the backup domain configuration document through the file processing center. The primary domain configuration information includes primary domain device information, IO default configuration information and primary domain connection information, and the backup domain configuration information includes backup domain device information, IO mapping information and backup domain connection information. The first connection module is used to connect analog signals, digital signals and IO multiplexed signals in the main domain according to the IO default configuration information and the main domain connection information through the main domain connector of the main domain processing center, generate the number of channels and register reset value of the main domain IO controller, and perform differentiated routing of the IO control signals generated by the main domain IO controller according to power supply affiliation. The first generation module is used to allocate addresses to main domain devices and generate main domain address mapping tables according to the main domain device information through the main domain generator of the main domain processing center, instantiate the main domain devices and connect them to the corresponding main domain bus, and integrate main domain interrupt signals, main domain DMA signals and main domain error signals. The second connection module is used to connect the digital signals and IO multiplexing signals in the backup domain respectively through the backup domain connector of the backup domain processing center, based on the IO mapping information and the backup domain connection information, to generate the number of channels and register reset value of the backup domain IO controller, and to perform differentiated routing of the IO control signals generated by the backup domain IO controller according to power supply affiliation. The second generation module is used to allocate addresses to backup domain peripherals and generate backup domain address mapping tables according to the backup domain device information through the backup domain generator in the backup domain processing center, instantiate the backup domain peripherals and connect them to the corresponding backup domain bus, and integrate backup domain interrupt signals, backup domain DMA signals and backup domain error signals.

9. An electronic device, characterized in that, include: A processor and a memory, wherein the memory stores a computer program that, when executed by the processor, performs the method of any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-7.

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