Circuit board layout design prediction method, electronic device, and storage medium

Abstract

This application relates to a circuit board layout continuity prediction method, electronic device, and storage medium. The method involves masking first image data and first image structure data to obtain second image data and second image structure data. A layout continuity prediction model is then trained based on the second image data and second image structure data. Since the model verifies whether the layout is continuous, manual routing verification is unnecessary, thus improving the prediction efficiency. Furthermore, because the model learns and predicts from masked, incomplete data during training, it exhibits stronger robustness to noise and missing information in the input data, thereby improving the model's prediction accuracy and the overall accuracy of layout continuity prediction.

Description

Technical Field

[0001] This invention relates to the field of circuit board layout design technology, and in particular to a circuit board layout prediction method, electronic devices, and storage media. Background Technology

[0002] A printed circuit board (PCB) is the support structure for electronic components and the carrier for the electrical interconnection of electronic components.

[0003] After the current circuit board layout is completed, it is necessary to determine whether the layout result is feasible for routing. The relevant technology is to manually route the wires to verify whether the layout result is feasible for routing.

[0004] However, with the increase in circuit board integration and the size of components, the process of verifying the layout and routing through actual manual wiring is time-consuming, resulting in low efficiency in circuit board layout and routing verification. Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a circuit board layout prediction method, an electronic device, and a storage medium, which have the advantages of improving the efficiency and accuracy of circuit board layout prediction.

[0006] According to a first aspect of the embodiments of this application, a circuit board layout prediction method is provided, comprising the following steps:

[0007] Acquire training sample information and the layout and routing prediction model to be trained; the training sample information includes the first layout data of the sample circuit board and the first layout routing result corresponding to the first layout data;

[0008] First image data and first graph structure data are obtained from the first layout data; the first image data includes the distribution information of the devices, and the first graph structure data includes the connection information between the devices;

[0009] The first image data is masked to obtain the second image data; the first image structure data is masked to obtain the second image structure data.

[0010] The second image data and the second graph structure data are input into the layout and routing prediction model to be trained to obtain the second layout and routing result; the layout and routing prediction model to be trained is trained based on the second layout and routing result, the first layout and routing result and the preset loss function to obtain the trained layout and routing prediction model.

[0011] Obtain the layout data of the circuit board to be laid out;

[0012] The layout data of the circuit board to be laid out is input into the trained layout and routing prediction model to obtain the layout and routing prediction results of the circuit board to be laid out.

[0013] According to a second aspect of the embodiments of this application, an electronic device is provided, comprising: a processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed as described above, a circuit board layout prediction method.

[0014] According to a third aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the circuit board layout prediction method as described in any of the above claims.

[0015] This application embodiment obtains second image data and second image structure data by masking first image data and first image structure data, and trains a layout continuity prediction model based on the second image data and second image structure data. Since the model verifies whether the layout is continuous, manual wiring verification is unnecessary, improving the prediction efficiency of layout continuity. Furthermore, because the model needs to learn and predict from the masked incomplete data during training, this makes the model more robust to noise and missing data in the input data, thereby improving the prediction accuracy of the model and the prediction accuracy of layout continuity.

[0016] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application.

[0017] To better understand and implement this invention, the following detailed description is provided in conjunction with the accompanying drawings. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating a circuit board layout prediction method provided in one embodiment of this application.

[0019] Figure 2 This is a schematic block diagram of the structure of an electronic device provided in one embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0021] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0022] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0023] In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims. In the description of this application, it should be understood that the terms "first," "second," "third," etc., are used only to distinguish similar objects and are not necessarily used to describe a specific order or sequence, nor should they be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] Furthermore, in the description of this application, unless otherwise stated, "multiple" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0025] In the process of realizing this invention, the inventors discovered that in related technologies, the determination of whether the layout result of a circuit board can be routed is mainly verified by actual manual wiring. However, manual wiring verification is time-consuming, resulting in low prediction efficiency of layout routed results.

[0026] To address this, this application employs a trained model for layout and routing prediction, eliminating the need for manual routing verification and thus improving prediction efficiency. Furthermore, during model training, this application masks a portion of the input data, learning and predicting from the masked, incomplete data. This enhances the model's robustness to noise and missing data in the input, thereby improving the accuracy of layout and routing prediction.

[0027] Please see Figure 1 This is a flowchart illustrating a circuit board layout and routing prediction method provided in one embodiment of this application. This application provides a circuit board layout and routing prediction method, including the following steps:

[0028] S10: Obtain training sample information and the layout and routing prediction model to be trained; the training sample information includes the first layout data of the sample circuit board and the first layout routing result corresponding to the first layout data.

[0029] The circuit board layout method of this application is implemented by a circuit board layout prediction device, which includes, but is not limited to, computers, tablets, and mobile phones.

[0030] The training sample information can be the first layout data and corresponding first layout routing results of multiple sample circuit boards, or the first layout data and corresponding first layout routing results of a specific module among multiple sample circuit boards. The first layout data includes, but is not limited to, the layout position, rotation angle, and device attribute information, including device name, device specifications, device pins, and device pad specifications. The first layout routing results are the routing results based on the first layout data, including routing successive ...

[0031] The layout prediction model to be trained can be a deep learning neural network model, including but not limited to convolutional neural networks and graph convolutional neural networks.

[0032] In this embodiment of the application, the layout and routing prediction model to be trained is trained according to the training sample information, wherein the first layout data of the sample circuit board is used as the input data of the model, and the first layout and routing result is used as the true label of the model prediction result.

[0033] S20: Obtain first image data and first diagram structure data from the first layout data; the first image data includes the distribution information of the devices, and the first diagram structure data includes the connection information between the devices.

[0034] The distribution information of the devices includes, but is not limited to, the device's location information, device specifications, device shape, layout area information, and the device's pad shape and pin coordinate information.

[0035] The connection information between devices includes the connection relationships between pins of devices in the same circuit.

[0036] In this embodiment, device distribution information is extracted from each device in the first layout data to obtain first image data. Based on the connection relationships between devices in the first layout data, nodes and edges of the graph structure are constructed to obtain first graph structure data.

[0037] S30: Perform masking processing on the first image data to obtain the second image data; perform masking processing on the first image structure data to obtain the second image structure data.

[0038] Masking image data can eliminate certain regions within the image. Similarly, masking graph data can eliminate certain nodes or edges within the graph.

[0039] In this embodiment, an image data masking method is used to mask the pixel values ​​of a portion of the first image data to obtain the second image data. Similarly, a graph structure data masking method is used to mask a portion of the nodes or edges of the first graph structure data to obtain the second graph structure data.

[0040] S40: Input the second image data and the second graph structure data into the layout and routing prediction model to be trained to obtain the second layout and routing result; train the layout and routing prediction model to be trained based on the second layout and routing result, the first layout and routing result and the preset loss function to obtain the trained layout and routing prediction model.

[0041] The preset loss functions include, but are not limited to, the root mean square error loss function and the cross-entropy loss function.

[0042] In this embodiment, the layout and routing prediction model to be trained captures local detail features in the layout data based on the second image data and captures global structural information in the layout data based on the second image structure data. Based on the global structural information and local detail features in the layout data, a second layout and routing result is output. Using the first layout and routing result as the ground truth label, a loss function value is calculated based on the second layout and routing result, the first layout and routing result, and a preset loss function. Based on the loss function value, the layout and routing prediction model to be trained is then trained to obtain the trained layout and routing prediction model.

[0043] S50: Obtain the layout data of the circuit board to be laid out.

[0044] The layout data of the circuit board to be laid out includes, but is not limited to, the layout positions and rotation angles of each component on the circuit board to be laid out.

[0045] In this embodiment of the application, a PCB layout file input by the user can be received. The PCB layout file includes the layout data of the circuit board to be laid out.

[0046] S60: Input the layout data of the circuit board to be laid out into the trained layout routing prediction model to obtain the layout routing prediction result of the circuit board to be laid out.

[0047] In this embodiment of the application, after obtaining the trained layout and routing prediction model, image data and graph structure data are obtained from the layout data of the circuit board to be laid out, and the image data and graph structure data are input into the trained layout and routing prediction model to obtain the layout and routing prediction result of the circuit board to be laid out.

[0048] By applying the embodiments of this application, second image data and second graph structure data are obtained by masking the first image data and the first graph structure data. A layout continuity prediction model is then trained based on the second image data and the second graph structure data. Since the model verifies whether the layout is continuous, manual wiring verification is unnecessary, thus improving the prediction efficiency of layout continuity. Furthermore, because the model needs to learn and predict from the masked incomplete data during training, this makes the model more robust to noise and missing information in the input data, thereby improving the prediction accuracy of the model and the prediction accuracy of layout continuity.

[0049] In one embodiment, the step of obtaining training sample information in step S10 includes steps S21 to S23, as follows:

[0050] S11: Obtain the first training sample data.

[0051] In the process of predicting the deployability of the layout results, the quality and comprehensiveness of the input data have a significant impact on the prediction accuracy of the model. Considering that the PCB design process involves the connection and positional relationships between components, as well as the spatial information of the non-fixed layout area and the spatial information of the components themselves, training sample data can be constructed in various ways.

[0052] In this embodiment, historical layout data from PCB engineers can be obtained, and first training sample data can be obtained based on this historical layout data. Alternatively, layout data for multiple circuit boards can be generated based on various layout algorithms, and first training sample data can be obtained based on the generated layout data.

[0053] S12: Perform data augmentation on the first training sample data to obtain the second training sample data.

[0054] In this embodiment of the application, the first training sample data can be translated, cropped and rotated to obtain the second training sample data.

[0055] S13: Use the first training sample data and the second training sample data as training sample information.

[0056] In the embodiments of this application, training sample information can be obtained from the first training sample data, or from the second training sample data, or simultaneously from both the first and second training sample data.

[0057] The embodiments of this application enhance the quantity, richness, and diversity of training sample information by performing data augmentation processing on the first training sample data.

[0058] In one embodiment, step S11 includes steps S111 to S115, as follows:

[0059] S111: Obtain historical layout data of the sample circuit board, use the historical layout data as the first layout data, and use the layout routing result of the historical layout data as the first layout routing result; and / or,

[0060] In this embodiment of the application, existing engineers have a large number of layout results in irregular areas. Based on modular decomposition, the edges of the layout results of the modules are extracted as the corresponding irregular area information. The layout results and irregular area information are used as the first layout data, and the first layout routing result is that the layout is routingable.

[0061] S112: Based on the automatic placement algorithm, place the components on the sample circuit board to obtain first placement data; based on the automatic routing algorithm, route the components on the sample circuit board to obtain the first placement routing result; and / or,

[0062] In this embodiment of the application, based on the existing automatic layout algorithm, a layout result that conforms to the design standard is generated in a given irregular area, and the automatic routing algorithm is used to perform routing to obtain the corresponding routing result and whether it can be routed, which is used as the first layout routing result.

[0063] S113: Based on the simultaneous solution layout algorithm, the components of the sample circuit board are laid out and routed to obtain the first layout data and the first layout routing result; and / or,

[0064] In this embodiment of the application, based on the existing simultaneous solution automatic layout algorithm, the corresponding layout result and routing result are obtained in the given irregular area, and the routing compatibility of the routing result is taken as the first layout routing result.

[0065] S114: Based on the simultaneous solution layout algorithm, the components of the sample circuit board are laid out to obtain layout data; the layout area containing the layout data is trimmed to obtain the trimmed layout area; based on the simultaneous solution layout algorithm, the components in the trimmed layout area are rearranged and routed to obtain first layout data and first layout routing results; and / or,

[0066] In this embodiment of the application, based on the existing simultaneous solution automatic layout algorithm, the layout and routing are performed, and the irregular areas are re-trimmed and extracted from the layout edges according to the final layout result. These irregular areas are then input into the algorithm for a second simultaneous solution to obtain the layout result and the routing result. The routing compatibility of the routing result is taken as the first layout routing result.

[0067] S115: Based on the solver, the components of the sample circuit board are laid out and routed to obtain the first layout data and the first layout routing result.

[0068] In this embodiment of the application, the open-source or-tools solver is used for automatic placement. A preset number of valid solutions are obtained from the top of the sorted results of each solution. Each valid result is used as a placement result. Routing is performed on each placement result. Whether the final routing result can be routed is used as the first placement routing result.

[0069] The embodiments of this application can improve the quantity and quality of the first training sample data through the above-described layout and routing method.

[0070] In one embodiment, step S12 includes steps S121 to S124, as follows:

[0071] S121: Adjust the rotation angle of each device in the first training sample data to a preset rotation angle to obtain the first layout data; based on the first layout data, obtain the first layout routing result; or,

[0072] In this embodiment, each device in the first training sample data is rotated by 90 degrees, 180 degrees, and 270 degrees to obtain first layout data. Based on the first layout data, routing is performed on the devices to obtain the first layout routing result. Optionally, since the change in rotation angle does not affect the layout routing result, the layout routing result before the rotation angle adjustment can be used as the first layout routing result.

[0073] S122: Crop the layout region corresponding to the first training sample data to obtain the first layout data and the first layout routing result; or...

[0074] In this embodiment, cropping the layout area where the device is located in the first training sample data does not change the layout data of the device, but the layout routing result will be affected. For example, the layout routing result corresponding to the layout data before cropping is routing-enabled, while the layout routing result after cropping becomes routing-unenabled.

[0075] Specifically, the layout data before clipping is used as the first layout data. If the layout before clipping is passable, then the first layout is not passable.

[0076] S123: Translate the positions of the devices in the first training sample data to obtain the first layout data; based on the first layout data, obtain the first layout routing result; or,

[0077] In this embodiment, the positions of the devices in the first training sample data are translated in various directions, and first layout data is obtained based on the translated device positions. Based on the first layout data, routing is performed on the devices to obtain the first layout routing result.

[0078] S124: Remove the device or device pin of the target device circuit in the first training sample data to obtain the first layout data; obtain the first layout routing result based on the first layout data; wherein, the target device circuit is any device circuit in the first training sample data.

[0079] In this embodiment of the application, the layout results of some device circuits are randomly removed, including randomly deleting devices and randomly deleting device pins. Since only devices or device pins are deleted, the layout and routing results will not be affected. The layout and routing results before removal can be used as the first layout and routing results.

[0080] This application embodiment obtains second training sample data by performing various transformation operations on the first training sample data, thereby generating more diverse training sample information.

[0081] In one embodiment, step S20 includes steps S21 to S23, as follows:

[0082] S21: Obtain the position information, shape information, pad information, and layout area information of each device in the first layout data.

[0083] In this embodiment of the application, specialized electronic design automation software (e.g., EDA software) can be used to extract the position information, shape information, pad information, and layout area information of each device from the first layout data.

[0084] S22: Based on the position information, shape information, pad information and layout area information, fill each device in the first layout data into a blank image, encode the pixel value of each device in the blank image, and obtain the first image data.

[0085] In this embodiment, the size of the blank image is 256*256. In the blank image, the pixels occupied by the pads and pins of the device, the pixels occupied by the device, and the pixels occupied by the outside and edges of the irregular area are filled with different numbers to obtain the first image data. For example, if the pads and pins of device A and device B are in the same network Net1, then the pixels occupied by the pads and pins of device A and device B are filled with the number 1, the pixels occupied by the device are uniformly filled with the number 2, and the pixels occupied by the outside and edges of the irregular area are uniformly represented by the number 255.

[0086] S23: Take the pins of each device in the first layout data as nodes of the first graph structure; take the pin position, pin rotation angle, pin number of the device to which the pin belongs, shape of the pad to which the pin belongs, name of the device to which the pin belongs, rotation angle of the device to which the pin belongs, and shortest distance between the pin and the edge of the layout area as node features of the corresponding nodes; take the connection relationship between pins of the same device loop as the edge of the first graph structure; take the network name of the device loop and the line width of the device loop as the edge features of the first graph structure to obtain the first graph structure data.

[0087] Since the pins of the same network device are interconnected, an undirected graph is used to represent the layout data.

[0088] Among them, the same device loop refers to a loop formed by devices with the same pin network name.

[0089] In this embodiment of the application, the first graph structure data is an undirected graph, and the nodes, node features, edges and edge features of the undirected graph are extracted from the first layout data.

[0090] Through the above operations, the first layout data can be converted into first image data and first graph structure data, thereby facilitating the training of subsequent models.

[0091] In one embodiment, step S30, which involves masking the first image data to obtain the second image data, includes steps S31 to S33, as follows:

[0092] S31: Obtain the first mask matrix; the size of the first mask matrix is ​​the same as the resolution of the first image data.

[0093] In this embodiment of the application, the element values ​​of the first mask matrix can be set. Specifically, the element values ​​of some elements are set to 0, and the element values ​​of some elements are set to 1.

[0094] S32: Multiply the element values ​​of the first mask matrix with the pixel values ​​of each pixel in the first image data to obtain the image data after masking.

[0095] In this embodiment of the application, when an element with a value of 0 in the first mask matrix is ​​multiplied by the pixel value of the corresponding pixel in the first image data, the pixel value becomes 0, and is considered to be masked.

[0096] S33: Based on the pixel value of the first pixel in the masked image data and the positional relationship between the first pixel and the second pixel, the pixel value of the second pixel is reconstructed to obtain the second image data; the first pixel is the pixel whose pixel value is not masked, and the second pixel is the pixel whose pixel value is masked.

[0097] In this embodiment, since the pixel value of the second pixel is masked, the pixel value of the first pixel can be weighted and fused according to the positional relationship between the first pixel and the second pixel to re-obtain the pixel value of the second pixel. Specifically, the closer the first pixel is to the second pixel, the greater its weight is assigned.

[0098] The embodiments of this application reconstruct the pixel value of the second pixel based on the pixel values ​​of multiple first pixel points to obtain second image data. Since each pixel in the second image data has a pixel value, the accuracy of subsequent model training can be improved.

[0099] In one embodiment, step S33 includes step S331, which is as follows:

[0100] S331: Input the masked image data into the self-attention layer to reconstruct the pixel value of the second pixel and obtain the second image data.

[0101] In this embodiment, the self-attention layer performs self-attention score calculation, self-attention score normalization, and weighted fusion operations on the masked image data to obtain second image data. Specifically, the self-attention score represents the degree of proximity between the first pixel and the second pixel; the higher the self-attention score, the greater the weight assigned to the corresponding first pixel. Self-attention score normalization involves normalizing the attention scores using the Softmax activation function, ensuring that the sum of all scores is 1. The weighted fusion operation involves weighting and fusing the pixel values ​​of the first pixel according to their assigned weights to re-obtain the pixel values ​​of the second pixel.

[0102] This application embodiment utilizes the self-attention mechanism of the self-attention layer to reconstruct the pixel value of the second pixel, thereby automatically and quickly obtaining the second image data.

[0103] In one embodiment, step S30, which involves masking the first graph structure data to obtain the second graph structure data, includes steps S34 to S35, as follows:

[0104] S34: Obtain the second mask matrix; the size of the second mask matrix is ​​the same as the size of the adjacency matrix of the first graph structure data.

[0105] In this embodiment of the application, the element values ​​of the second mask matrix can be set. Specifically, the element values ​​of some elements are set to 0, and the element values ​​of some elements are set to 1.

[0106] S35: Multiply the second mask matrix with the adjacency matrix of the first graph structure data to obtain the second graph structure data.

[0107] In graph structures, the adjacency matrix is ​​a matrix used to represent the adjacency relationship between vertices in a graph.

[0108] In this embodiment, each element of the second mask matrix is ​​multiplied by the corresponding element in the adjacency matrix of the first graph structure data, thereby modifying some elements in the adjacency matrix and changing the edge connections between nodes to obtain the second image data. For example, after multiplying the element with a value of 0 in the second mask matrix by the corresponding element in the adjacency matrix, the value of that element becomes 0, which is considered as no edge connection between nodes.

[0109] This application embodiment can automatically mask some edges in the first graph structure data by applying the second mask matrix to the first graph structure data.

[0110] In one embodiment, step S35 includes steps S351 to S352, as follows:

[0111] S351: Multiply the second mask matrix with the adjacency matrix of the first graph structure data to obtain the first graph structure data after masking.

[0112] In this embodiment of the application, step S351 is the same as the aforementioned step S35, and will not be repeated here.

[0113] S352: Reconstruct the masked edges in the first graph structure data after masking to obtain the second graph structure data.

[0114] In this embodiment, a self-attention mechanism can be used to reconstruct the masked edges in the first graph structure data after masking to obtain the second graph structure data. Specifically, the correlation between each node and the node whose edge connection relationship has been modified in the first graph structure data after masking is calculated, and the masked edges are reconstructed based on the edge connection relationship of each node.

[0115] This application embodiment reconstructs the masked edges based on the edge connection relationships of multiple nodes to obtain the second image structure data. Since the edge connection relationships of each node in the second image structure data are determined, the accuracy of subsequent model training can be improved.

[0116] In one embodiment, the layout-to-network prediction model to be trained includes a convolutional layer, a graph convolutional layer, a fully connected layer, a first normalization layer, an activation layer, a regularization layer, and a second normalization layer. Step S40, which involves inputting the second image data and the second graph structure data into the layout-to-network prediction model to obtain the second layout-to-network result, includes steps S41 to S44, as follows:

[0117] S41: Input the second image data into the convolutional layer for feature extraction to obtain the first feature map.

[0118] The first and second normalization layers are both LayerNorm layers, and the regularization layer is a Dropout layer.

[0119] In this embodiment of the application, a first feature map is obtained by performing a convolution operation on the second image data through a convolutional layer to extract the feature information of the second image data.

[0120] S42: Input the second graph structure data into the graph convolutional layer for feature extraction to obtain the second feature map.

[0121] In this embodiment, a graph convolution operation is performed on the second graph structure data through a graph convolution layer to extract the feature information of the second graph structure data and obtain a second feature map.

[0122] S43: Concatenate the first feature map with the second feature map to obtain the third feature map.

[0123] In this embodiment of the application, the first feature map and the second feature map are connected in the channel dimension to obtain the third feature map.

[0124] S44: Input the third feature map sequentially into the fully connected layer, the first normalization layer, the activation layer, the regularization layer, and the second normalization layer to obtain the second layout routing result.

[0125] In this embodiment, the third feature map is input into the Dense fully connected layer to extract the effective information from the third feature map and obtain the hidden layer variables. Then, through the normalization operation of the first normalization layer, the activation function of the activation layer, the regularization strategy of the regularization layer, and the normalization operation of the second normalization layer, the effective information in the hidden layer variables is further extracted to obtain the second layout routing result.

[0126] The embodiments of this application utilize the cooperation of convolutional layers, graph convolutional layers, fully connected layers, first normalization layers, activation layers, regularization layers, and second normalization layers to enable the model to effectively extract feature information and output the second layout routing result.

[0127] In one embodiment, the preset loss function includes a first loss function, a second loss function, and a third loss function. Step S40, which involves training the layout prediction model to be trained based on the second layout result, the first layout result, and the preset loss function to obtain the trained layout prediction model, includes steps S45 to S47, as follows:

[0128] S45: Based on the second layout routing result, the first layout routing result, and the first loss function, obtain the first loss function value; based on the second layout routing result, the first layout routing result, and the second loss function, obtain the second loss function value; based on the second layout routing result, the first layout routing result, and the third loss function, obtain the third loss function value.

[0129] In this embodiment, both the first and third loss functions are root mean square error functions, and the second loss function is a cross-entropy loss function. Specifically, the expression for the first loss function is as follows:

[0130]

[0131] The expression for the second loss function is as follows:

[0132]

[0133] The expression for the third loss function is as follows:

[0134]

[0135] Where S represents all the constructed training samples, and y represents the first layout layout result. This indicates the second layout routing result, where i represents the i-th category, i.e., layout routing or layout not routing.

[0136] S46: Sum the first loss function value, the second loss function value, and the third loss function value to obtain the total loss function value.

[0137] In this embodiment, the expression for the total loss function is as follows:

[0138] Loss=image_loss+graph_loss+classification_loss

[0139] S47: Based on the total loss function value, train the layout and routing prediction model to be trained to obtain the trained layout and routing prediction model.

[0140] In this embodiment, based on the total loss function value, gradient descent and backpropagation algorithms are used to iteratively update the network weight parameters of the layout and routing prediction model to be trained, thereby obtaining the trained layout and routing prediction model.

[0141] This application embodiment constructs a total loss function by setting a first loss function, a second loss function, and a third loss function. The model is trained based on the total loss function value, which can improve the robustness and stability of the model.

[0142] The following are embodiments of the device described in this application, which can be used to execute the methods described in the embodiments of this application. For details not disclosed in the embodiments of the device described in this application, please refer to the methods described in the embodiments of this application.

[0143] Please see Figure 2 This application also provides an electronic device 300, which may specifically be a computer, mobile phone, tablet computer, circuit board layout and routing prediction device, etc. In an exemplary embodiment of this application, the electronic device 300 is a circuit board layout and routing prediction device, which may include: at least one processor 301, at least one memory 302, at least one display, at least one network interface 303, user interface 304, and at least one communication bus 305.

[0144] The user interface 304 is primarily used to provide an input interface for the user and to acquire user input data. Optionally, the user interface may also include a standard wired interface or a wireless interface.

[0145] The network interface 303 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface).

[0146] The communication bus 305 is used to enable communication between these components.

[0147] The processor 301 may include one or more processing cores. The processor connects to various parts of the electronic device using various interfaces and lines, and performs various functions and processes data by running or executing instructions, programs, code sets, or instruction sets stored in memory, and by calling data stored in memory. Optionally, the processor may be implemented using at least one hardware form of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), or Programmable Logic Array (PLA). The processor may integrate one or a combination of several of the following: Central Processing Unit (CPU), Graphics Processing Unit (GPU), and modem. The CPU primarily handles the operating system, user interface, and applications; the GPU is responsible for rendering and drawing the content required for display; and the modem handles wireless communication. It is understood that the modem may also be implemented as a separate chip without being integrated into the processor.

[0148] The memory 302 may include random access memory (RAM) or read-only memory. Optionally, the memory may include a non-transitory computer-readable storage medium. The memory can be used to store instructions, programs, code, code sets, or instruction sets. The memory may include a program storage area and a data storage area, wherein the program storage area may store instructions for implementing an operating system, instructions for at least one function (such as touch functionality, sound playback functionality, image playback functionality, etc.), instructions for implementing the various method embodiments described above, etc.; the data storage area may store data involved in the various method embodiments described above, etc. The memory may also optionally be at least one storage device located remotely from the aforementioned processor. Figure 2 As shown, a memory, as a computer storage medium, may include an operating system, a network communication module, a user interface module, and operating applications.

[0149] The processor can be used to call the application program of the circuit board layout prediction method stored in the memory, and specifically execute the method steps of the above embodiment. For the specific execution process, please refer to the specific description shown in the embodiment, which will not be repeated here.

[0150] This application also provides a computer-readable storage medium storing a computer program thereon, the instructions of which are adapted to be loaded by a processor and executed by the method steps of the embodiments shown above. For details of the execution process, please refer to the specific descriptions shown in the embodiments, which will not be repeated here. The device containing the storage medium can be an electronic device such as a personal computer, laptop computer, smartphone, or tablet computer.

[0151] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative, wherein the components described as separate parts may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this application according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0152] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0153] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function selected in one or more boxes.

[0154] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function selected in one or more boxes.

[0155] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0156] Memory may include non-persistent memory in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0157] Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape storage, disk storage, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transient computer-readable media, such as modulated data signals and carrier waves.

[0158] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0159] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A method for predicting circuit board layout, characterized in that, The method includes the following steps: Acquire training sample information and a layout and routing prediction model to be trained; the training sample information includes first layout data of the sample circuit board and the first layout and routing result corresponding to the first layout data; First image data and first graph structure data are obtained from the first layout data; the first image data includes the distribution information of the devices, and the first graph structure data includes the connection information between the devices. The first image data is masked to obtain the second image data; the first image structure data is masked to obtain the second image structure data. The second image data and the second graph structure data are input into the layout and routing prediction model to be trained to obtain the second layout and routing result; the layout and routing prediction model to be trained is trained according to the second layout and routing result, the first layout and routing result and the preset loss function to obtain the trained layout and routing prediction model. Obtain the layout data of the circuit board to be laid out; The layout data of the circuit board to be laid out is input into the trained layout routing prediction model to obtain the layout routing prediction result of the circuit board to be laid out.

2. The circuit board layout prediction method according to claim 1, characterized in that: The step of obtaining the first image data and the first graph structure data from the first layout data includes: Obtain the position information, shape information, pad information, and layout area information of each device in the first layout data; Based on the location information, shape information, pad information, and layout area information, each device in the first layout data is filled into a blank image, and the pixel value of each device in the blank image is encoded to obtain the first image data. The pins of each device in the first layout data are used as nodes of the first graph structure; the position of the pin, the rotation angle of the pin, the pin number of the device to which the pin belongs, the shape of the pad to which the pin belongs, the name of the device to which the pin belongs, the rotation angle of the device to which the pin belongs, and the shortest distance between the pin and the edge of the layout area are used as node features of the corresponding nodes; the connection relationship between pins of the same device loop is used as the edge of the first graph structure; the network name of the device loop and the line width of the device loop are used as the edge features of the first graph structure to obtain the first graph structure data.

3. The circuit board layout prediction method according to claim 1, characterized in that: The step of masking the first image data to obtain the second image data includes: Obtain the first mask matrix; the size of the first mask matrix is ​​the same as the resolution of the first image data; Multiply the element values ​​of the first mask matrix with the pixel values ​​of each pixel in the first image data to obtain the image data after masking. Based on the pixel value of the first pixel in the masked image data and the positional relationship between the first pixel and the second pixel, the pixel value of the second pixel is reconstructed to obtain the second image data; the first pixel is the pixel whose pixel value is not masked, and the second pixel is the pixel whose pixel value is masked.

4. The circuit board layout prediction method according to claim 3, characterized in that: The step of reconstructing the pixel value of the second pixel based on the pixel value of the first pixel in the masked image data and the positional relationship between the first pixel and the second pixel to obtain the second image data includes: The image data after masking is input into the self-attention layer to reconstruct the pixel value of the second pixel and obtain the second image data.

5. The circuit board layout prediction method according to claim 1, characterized in that: The step of masking the first graph structure data to obtain the second graph structure data includes: Obtain the second mask matrix; the size of the second mask matrix is ​​the same as the size of the adjacency matrix of the first graph structure data; The second mask matrix is ​​multiplied by the adjacency matrix of the first graph structure data to obtain the second graph structure data.

6. The circuit board layout prediction method according to claim 5, characterized in that: The step of multiplying the second mask matrix with the adjacency matrix of the graph structure data to obtain the second graph structure data includes: Multiply the second mask matrix with the adjacency matrix of the first graph structure data to obtain the first graph structure data after masking. The masked edges in the first graph structure data after the masking process are reconstructed to obtain the second graph structure data.

7. The circuit board layout prediction method according to any one of claims 1 to 6, characterized in that: The layout and routing prediction model to be trained includes a convolutional layer, a graph convolutional layer, a fully connected layer, a first normalization layer, an activation layer, a regularization layer, and a second normalization layer. The step of inputting the second image data and the second graph structure data into the layout and routing prediction model to be trained to obtain the second layout and routing result includes: The second image data is input into the convolutional layer for feature extraction to obtain the first feature map; The second graph structure data is input into the graph convolutional layer for feature extraction to obtain the second feature map; The first feature map is concatenated with the second feature map to obtain the third feature map; The third feature map is sequentially input into the fully connected layer, the first normalized layer, the activation layer, the regularization layer, and the second normalized layer to obtain the second layout routing result.

8. The circuit board layout prediction method according to any one of claims 1 to 6, characterized in that: The preset loss function includes a first loss function, a second loss function, and a third loss function; The step of training the layout prediction model to be trained based on the second layout result, the first layout result, and a preset loss function to obtain a trained layout prediction model includes: Based on the second layout routing result, the first layout routing result, and the first loss function, a first loss function value is obtained; based on the second layout routing result, the first layout routing result, and the second loss function, a second loss function value is obtained; based on the second layout routing result, the first layout routing result, and the third loss function, a third loss function value is obtained. The first loss function value, the second loss function value, and the third loss function value are summed to obtain the total loss function value; Based on the total loss function value, the layout and routing prediction model to be trained is trained to obtain the trained layout and routing prediction model.

9. An electronic device, characterized in that, include: A processor and a memory; wherein the memory stores a computer program adapted to be loaded by the processor and executed as the circuit board layout prediction method as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the circuit board layout prediction method as described in any one of claims 1 to 7.

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