Integrated circuit device and method of manufacturing the same

Abstract

Embodiments of this application relate to integrated circuit (IC) devices and methods of manufacturing the same. The integrated circuit device includes an array of sub-circuit unit cells (SUCs) having the same SUC configuration. The SUC configuration includes a first number of P-type active regions and a different number of second number of N-type active regions. The array of SUCs includes: a first SUC configuring a first sub-circuit of analog circuitry, and a second SUC configuring a second sub-circuit of analog circuitry, the second sub-circuit being different from the first sub-circuit.

Description

Technical Field

[0001] Embodiments of this application relate to integrated circuit devices and methods for manufacturing the same. Background Technology

[0002] Integrated circuit (“IC”) devices comprise one or more semiconductor devices represented in an IC layout diagram (also known as a “layout diagram,” “layout,” or “IC layout”). IC layouts are hierarchical, comprising modules that perform higher-level functions according to the design specifications of the semiconductor devices. These modules are typically constructed from combinations of cells, each cell representing one or more semiconductor devices configured to perform a specific function. Cells with pre-designed layout diagrams are stored in cell libraries (sometimes referred to as “libraries” for simplicity) and are accessible through various tools, such as electronic design automation (EDA) tools, to generate, optimize, and verify IC designs. Summary of the Invention

[0003] According to one aspect of the embodiments of this application, an integrated circuit (IC) device is provided, comprising: an array of sub-circuit unit cells (SUCs), the SUCs having the same SUC configuration, wherein the SUC configuration includes a first number of P-type active regions and a second number of N-type active regions, the first number being different from the second number, and the array of SUCs including a first SUC and a second SUC, the first SUC configuring a first sub-circuit of an analog circuit, and the second SUC configuring a second sub-circuit of an analog circuit, the second sub-circuit being different from the first sub-circuit.

[0004] According to another aspect of the embodiments of this application, an integrated circuit (IC) device is provided, comprising: a circuit region including different sub-circuits of an analog circuit; and a pseudo-region surrounding the circuit region, the pseudo-region including pseudo-transistors, wherein the circuit region does not have pseudo-transistors that separate sub-circuits in the sub-circuits of the analog circuit from other sub-circuits in the sub-circuits of the analog circuit.

[0005] According to another aspect of the present application, a method for manufacturing an integrated circuit device is provided, comprising: forming a plurality of transistors in a circuit region above a substrate; and forming a plurality of conductive components above the plurality of transistors, wherein the plurality of conductive components electrically couple the plurality of transistors into an analog circuit, the analog circuit including multiple rows of decoupling capacitors and at least one sub-circuit in multiple rows other than the decoupling capacitors, and the multiple rows of decoupling capacitors and the at least one sub-circuit in multiple rows are physically interleaved. Attached Figure Description

[0006] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a functional flowchart of the IC design process according to some embodiments.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D These are circuit diagrams of various analog circuits in IC devices according to some embodiments.

[0009] Figure 3A , Figure 3B , Figure 3C This is a layout diagram of various sub-circuit unit cells (SUCs) according to some embodiments.

[0010] Figure 3D This includes schematic diagrams of various SUC configurations according to some embodiments.

[0011] Figure 4A , Figure 4B , Figure 4C This is a schematic diagram of one or more layouts of various IC devices according to some embodiments.

[0012] Figure 5 This includes schematic diagrams of the layout of the SUC and the corresponding back-end process (BEOL) unit according to some embodiments.

[0013] Figure 6 This is a schematic cross-sectional view of an IC device according to some embodiments.

[0014] Figure 7 This is a flowchart of a portion of an IC design flow according to some embodiments.

[0015] Figure 8A , Figure 8B These are flowcharts of various methods according to some embodiments.

[0016] Figure 9 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0017] Figure 10 This is a block diagram of an IC device manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0018] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific embodiments or examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., may be considered. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Source / drain may be referred to individually or collectively as source or drain, depending on the context.

[0019] Furthermore, for ease of description, this document may use spacing terms such as “below,” “under,” “lower,” “above,” “upper,” etc., to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spacing descriptors used herein may be interpreted accordingly.

[0020] IC devices include analog and digital circuits configured to provide various functions and / or solve various problems. In some embodiments, the analog circuitry includes different sub-circuits, all of which are implemented on the same sub-circuit unit cell (SUC) in the same SUC configuration. This configuration differs from other methods, where each sub-circuit wiring is implemented in a separate cell within a separate circuit region. For example, in other methods, decoupling capacitor (decap or dcap) cells configuring decoupling capacitors are arranged in a circuit region surrounded by non-circuit regions, current mirror cells configuring current mirrors are arranged in another separate circuit region surrounded by other non-circuit regions, and so on. In other methods, the non-circuit regions occupy a larger area. In contrast, in some embodiments, various sub-circuits, such as decoupling capacitors, inverters, current mirrors, etc., are implemented on the same SUC within the same circuit region. In at least one embodiment, a single pseudo-region surrounds the circuit region in which various sub-circuits are located. As a result, in one or more embodiments of the IC device, the area of ​​pseudo-regions or non-circuit regions that are not electrically coupled or not configured to perform IC device functions can be reduced. In addition to the chip area improvements described above, some embodiments achieve further improvements, including but not limited to improved design uniformity, custom-designed process flows, reduced density gradient effects (DGE), reduced parasitic resistance and / or capacitance (RC), and shorter interconnects with improved performance (speed). Further advantages and / or effects can be achieved in one or more embodiments described herein.

[0021] Figure 1 This is a functional flowchart of an IC design flow 100 according to some embodiments.

[0022] In at least one embodiment, the IC design flow 100 utilizes one or more electronic design automation (EDA) tools (or systems) to test the design of an IC device (sometimes simply referred to as "IC") prior to manufacturing. In some embodiments, the EDA tool includes one or more sets of executable instructions for execution by at least one processor or controller or programming computer to perform the indicated functions. In at least one embodiment, the IC design flow 100 is executed by the design room of the IC manufacturing system discussed herein. Figure 1 In the example configuration, IC design flow 100 includes operations 110-170.

[0023] At operation 110, the design of the IC is provided or generated, for example, by a circuit designer. In some embodiments, the IC design includes an IC schematic, i.e., a circuit diagram. In some embodiments, the IC schematic is generated or provided in the form of a schematic netlist, such as a simulation program and integrated circuit focus (SPICE) netlist. Other data formats for describing the design are available in some embodiments.

[0024] At operation 120, for example, a pre-layout simulation is performed on the design using an EDA tool to determine if the design conforms to predetermined specifications. If the design does not conform to predetermined specifications, the IC is redesigned. In some embodiments, SPICE simulation is performed on the SPICE netlist. In other embodiments, other simulation tools may be used instead of SPICE simulation or as a supplement to SPICE simulation.

[0025] At operation 130, a layout (or IC layout) of the IC is generated based on the design. The IC layout includes the physical locations of the various circuit elements (or devices) of the IC, as well as the physical locations of various networks and vias interconnecting the circuit elements. In some embodiments, the IC layout is generated by an EDA tool in the form of a Graphical Design System (GDS) file or a GDSII file. Other data formats used to describe the IC layout are within the scope of various embodiments. For example, in one or more embodiments, the IC layout is generated and / or output in the form of an Open Artworks System Exchange Standard (OASIS) file or a Design Framework II (DFII) file. For simplicity, this document provides a non-limiting example of an IC layout contained in a GDS file.

[0026] In some embodiments, the IC layout is generated in operation 130 by an EDA tool or EDA system (such as an Automated Place and Route (APR) tool). The APR tool receives the IC design in netlist form as described herein and performs a placement operation (or placement). For example, cells configured to provide predefined functionality and having a pre-designed layout are stored in at least one library on at least one non-transitory computer-readable medium. The APR tool accesses various cells from the at least one library and places these cells in an adjacency manner to generate an IC layout corresponding to the IC schematic. Example cells include, but are not limited to, inverters, adders, multipliers, logic gates, phase-locked loops (PLLs), flip-flops, multiplexers, memory cells, combinations thereof, etc. Example logic gates include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-Inverted (AOI), OR-AND-Inverted (OAI), MUX, flip-flops, BUFF, latches, delays, clock cells, etc. In some embodiments, the unit includes one or more active or passive circuit elements. Examples of active circuit elements (sometimes referred to as "semiconductor devices") include, but are not limited to, transistors and diodes. Examples of transistors include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, p-channel and / or n-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, complementary field-effect transistors (CFETs), etc. Examples of diodes include, but are not limited to, varactor diodes, etc. Examples of passive circuit elements include, but are not limited to, capacitors, inductors, fuses, and resistors.

[0027] The APR tool then performs a routing operation (or routing) to route various networks and vias that interconnect the placed circuit elements. Examples of networks include, but are not limited to, conductive pads, conductive patterns, and conductive redistribution layers. The routing operation ensures that the interconnections of the routing satisfy a set of constraints. After the routing operation, the APR tool outputs an IC layout in a GDS file, including the placed circuit elements and the networks and vias of the routing, as described herein. Networks and vias are generally referred to herein as routing features. The APR operation described is exemplary. Other arrangements are within the scope of various embodiments. For example, in one or more embodiments, one or more of the described operations are omitted.

[0028] At operation 140, a layout and schematic (LVS) check is performed. The LVS check ensures that the generated IC layout corresponds to the design. Specifically, the LVS check tool, i.e., an EDA tool or EDA system, identifies or extracts electrical components and their connections from the pattern of the generated IC layout. The LVS check tool then generates a layout netlist representing the identified electrical components and connections. The LVS check tool compares the generated layout netlist of the IC layout with the schematic netlist of the design (sometimes called the “source netlist”). If the two netlists match, for example, within the matching tolerance, the LVS check passes. Otherwise, at least one of the IC layout or design is corrected by returning the process to operations 110 and / or 130. In some embodiments, additional verification processes are available.

[0029] At operation 150, a design rule check (DRC) is performed on the GDS file including the IC layout, for example using an EDA tool, to ensure that the IC layout meets specific manufacturing design rules, i.e., to ensure the manufacturability of the IC. If one or more design rules are violated, at least one of the IC layout or design is corrected by returning the process to operation 110 and / or operation 130. Examples of design rules include, but are not limited to, width rules specifying the minimum width of patterns in the IC layout, pitch rules specifying the minimum pitch between adjacent patterns in the IC layout, area rules specifying the minimum area of ​​patterns in the integrated circuit layout, metal-to-via spacing rules specifying the minimum spacing between metal patterns and adjacent vias, metal-to-metal spacing rules, etc. In some embodiments, other verification processes are available.

[0030] At operation 160, resistance and capacitance (RC) extraction is performed, for example, using EDA tools, to determine parasitic parameters of interconnects in the IC layout, such as parasitic resistance and capacitance, for timing simulation in subsequent operations. In some embodiments, other verification procedures are available.

[0031] At operation 170, a post-layout simulation is performed using a simulation tool (i.e., an EDA tool) to determine whether the IC layout conforms to predetermined specifications, taking into account extracted parasitic parameters. If the simulation indicates that the IC layout does not conform to predetermined specifications, for example, if parasitic parameters cause undesirable delays, at least one of the IC layout or design is corrected by returning the process to operations 110 and / or 130. Otherwise, the IC layout is passed to manufacturing or additional verification processes. In some embodiments, the unmodified IC layout and / or the modified IC layout and / or the final IC layout for manufacturing are stored on a non-transitory computer-readable medium.

[0032] In some embodiments, one or more of the operations are omitted. For example, in one or more embodiments, one or more of the pre-layout simulation in operation 120, RC extraction in operation 160, and post-layout simulation in operation 170 are omitted. Other arrangements are within the scope of various embodiments. For simplicity, various operations and / or determinations are described herein as being performed by an APR tool. However, in at least one embodiment, one or more of the operations and / or determinations are performed outside of the APR tool, for example by one or more other automation systems, one or more processors, and / or one or more computer systems.

[0033] In some embodiments, the IC schematic at operation 110 includes digital and analog circuits, and the APR tool at operation 130 is configured to generate a layout that includes circuit regions containing digital circuits and other circuit regions containing analog circuits.

[0034] In at least one embodiment, the transistors in the digital circuit are controllably switched to be off or on in a binary manner. For example, the voltage on the transistor gate is controllably switched between a first reference voltage (e.g., a first supply voltage, such as VDD) and a second reference voltage (e.g., a second supply voltage, such as VSS) to turn the transistor on / off. When the transistor is on, a given portion of the substrate corresponding to the transistor channel substantially completely depletes the majority carriers of the substrate and becomes a depletion region. When a channel is formed / induced, the depletion region also temporarily increases the minority carriers of the substrate, i.e., the minority carrier density in the depletion region temporarily increases, which temporarily forms or induces a conductive channel in the substrate. The corresponding operating modes of the transistor are depletion mode or saturation mode.

[0035] In at least one embodiment, transistors in the analog circuit are configured and / or controlled such that the amount of current flowing through the transistor, i.e., the degree to which the transistor is turned on, varies continuously. This continuous / analog approach to controlling the current in the analog circuit transistor contrasts with the binary approach to controlling the current flowing through the transistor in the digital circuit. For example, the transient current flowing through the transistor in the analog circuit varies continuously in proportion to the gate voltage on the transistor gate, such that the corresponding operating mode of the transistor is ohmic mode. More specifically, the degree of depletion in the depletion region varies proportionally to the magnitude of the gate voltage, ranging from substantially incomplete depletion to substantially complete depletion. In ohmic mode, the transistor gain is sensitive to the potential difference between the gate voltage and the substrate voltage, and changes in the substrate voltage affect the degree of depletion in the depletion region, thereby affecting the amount of current conducted through the channel.

[0036] Reference Figures 2A-2D Examples of analog circuits according to some embodiments are described. (Refer to...) Figures 3A-3DExamples of SUCs and SUC configurations for implementing analog circuits are described according to some embodiments. (Refer to...) Figures 4A-4C Examples of one or more IC layouts, including one or more analog circuits implemented on one or more SUCs, are described according to some embodiments. (Refer to...) Figure 7 Examples of one or more APR operations are described, according to some embodiments, using one or more SUCs to generate one or more circuit regions containing analog circuitry.

[0037] Figure 2A These are circuit diagrams of example analog circuits in IC devices according to some embodiments. Figure 2A The example analog circuit in the example is a current-controlled oscillator (ICO) 200A.

[0038] The ICO 200A includes a current mirror 210, decoupling capacitors 221 and 222, and a differential ring oscillator (DRO) 230. The current mirror 210, decoupling capacitors 221 and 222, and DRO 230 are electrically coupled to form the ICO 200A and are examples of sub-circuits of an analog circuit.

[0039] The current mirror 210 includes P-type transistors MP1 and MP2. In the analog circuits described herein with respect to some example embodiments, the P-type transistors are P-channel metal-oxide-semiconductor (PMOS) transistors, and the N-type transistors are N-channel metal-oxide-semiconductor (NMOS) transistors. Other transistors are configured within the range of various embodiments. Each of transistors MP1 and MP2 has a first source / drain coupled to VDD and a second source / drain 211 and 212 coupled to corresponding decoupling capacitors 221 and 222. The second source / drain 211 of transistor MP1 is also coupled to the gate of transistors MP1 and MP2 and a current source CS. In some embodiments, the current source CS is not part of ICO 200A and is configured to provide a substantially constant current Ictr1, which, in one or more embodiments, is dynamically controllable to compensate for voltage, temperature, and / or process variations. The current mirror 210 is configured to generate a mirror current Imiror of the current Ictrl and output the current Imiror from the second source / drain 212 of the transistor MP2 to the DRO 230.

[0040] Each decoupling capacitor 221, 222 has a first end (or terminal) and a second end coupled to the second source / drain of the respective transistor MP1, MP2. In some embodiments, the second end of each decoupling capacitor 221, 222 is coupled to a conductor carrying a reference voltage, such as a power rail configured to carry VDD or VSS. In at least one embodiment, at least one of the decoupling capacitors 221, 222 is configured by a transistor having source / drain electrodes electrically coupled together. A decoupling capacitor configured by a P-type transistor is called a P-type decoupling capacitor (or pmoscap), and a decoupling capacitor configured by an N-type transistor is called an N-type decoupling capacitor (or nmoscap). An example N-type decoupling capacitor is decoupling capacitor 225 configured by transistor MN3. The gate of transistor MN3 corresponds to one end of decoupling capacitor 225. The source / drain of transistor MN3 is coupled to each other, corresponding to the other end of decoupling capacitor 225, and is coupled to VSS in one or more embodiments. An exemplary P-type decoupling capacitor is decoupling capacitor 226 configured by transistor MP3. The gate of transistor MP3 corresponds to one end of decoupling capacitor 226. The source / drain of transistor MP3 is coupled to each other, corresponding to the other end of decoupling capacitor 226, and is coupled to VDD in one or more embodiments.

[0041] The DRO 230 includes multiple inverter stages 231, 232, ... 233 coupled in a ring. Figure 2A In the example configuration shown, three inverter stages are illustrated. Other numbers of inverter stages are within the range of various embodiments. In DRO 230, the input of one inverter stage is coupled to the output of another inverter stage. For example, the input of inverter stage 232 is coupled to the output of inverter stage 231, the input of inverter stage 231 is connected to the output of inverter stage 233, and so on. A current Imirror is provided to DRO 230 to power inverter stages 231, 232, ... 233, which are configured to generate an output current Iout at the output of inverter stage 233.

[0042] exist Figure 2AIn the example configuration, at least one of inverter stages 231, 232, ... 233 has an inverter stage 240 comprising inverters INV_A, INV_B, INV_C, and INV_D. The inputs of inverters INV_A and INV_B are differential inputs corresponding to the inputs of one of the inverter stages 231, 232, ... 233. The outputs of inverters INV_C and INV_D are differential outputs corresponding to the outputs of one of the inverter stages 231, 232, ... 233. The output of inverter INV_A is coupled to the input of inverter INV_C and the output of inverter INV_D. The output of inverter INV_B is connected to the input of inverter INV_D and the output of inverter INV_C. At least one of the inverters INV_A, INV_B, INV_C, and INV_D has an inverter 245 configuration comprising a P-type transistor MP4 and an N-type transistor MN4. The gate of the P-type transistor MP4 is coupled to the gate of the N-type transistor MN4, and the source / drain of the P-type transistor MP4 is coupled to the source / drain of the N-type transistor MN4. Inverters INV_A and INV_B are configured with delay units, and inverters INV_C and INV_D are configured with latches. The configuration of DRO 230 and / or inverter stage 240 is an example. Other ring oscillator configurations are within the scope of various embodiments. For example, in one or more embodiments, each inverter stage 231, 232, ... 233 includes an inverter, thereby forming a single-ended ring oscillator. The various inverter stages and inverters described herein are further examples of sub-circuits of analog circuits.

[0043] In some embodiments, the ICO 200A is implemented by a SUC with a PPN (or NPP) configuration, such as Figure 3A , Figure 3D , Figure 4A , Figure 4B One or more of the above.

[0044] Figure 2B These are circuit diagrams of example analog circuits in IC devices according to some embodiments. Figure 2B The example analog circuit in the example is the operational transconductance amplifier (OTA) 200B.

[0045] The OTA 200B includes P-type transistors M10, MP0-MP5 and N-type transistors N10, MN0-MN5. The gates of transistors MP0 and MP1 are correspondingly coupled to receive input signals Vin+ and Vin-. The first source / drain terminals of transistors MP0, MP1, and M10 are coupled together. The second source / drain terminal of transistor M10 is coupled to VDD. The gates of transistors MN0 and MN1 are correspondingly coupled to receive input signals Vin+ and Vin-. The first source / drain terminals of transistors MN0, MN1, and M20 are coupled together. The second source / drain terminal of transistor M20 is coupled to VSS. Transistors MP3, MP5, MN5, and MN3 are series coupled between VDD and VSS. Transistors MP2, MP4, MN4, and MN2 are series coupled between VDD and VSS. The second source / drain terminal of transistor MN0 is connected to the source / drain terminals of transistors MP3 and MP5. The second source / drain of transistor MN1 is connected to the source / drain of transistors MP2 and MP4. The second source / drain of transistor MP0 is connected to the source / drain of transistors MN3 and MN5. The second source / drain of transistor MP1 is connected to the source / drain of transistors MN2 and MN4. The gates of transistors MP3, MP2, MN3, and MN2 are coupled to the source / drain of transistors MP5 and MN5. The gates of transistors MP5 and MP4 are coupled together. The gates of transistors MN5 and MN4 are coupled together.

[0046] In some embodiments, the OTA 200B is implemented by a SUC with a PPNN (or NNPP) configuration, having P-type active regions P1, P2 and N-type active regions N1, N2, as shown below. Figure 3C , Figure 3D One or more of the above are described. For example, transistor M10 is implemented by one of the P-type active regions P1 and P2, one or more of transistors MP0-MP5 are implemented by the other of the P-type active regions P1, P1, and P2, transistor M20 is implemented by one of the N-type active regions N1 and N2, and one or more of transistors MN0-MN5 are implemented by the other of the N-type active regions N1 and N2. Other arrangements are within the scope of various embodiments.

[0047] Figure 2C These are circuit diagrams of example analog circuits in IC devices according to some embodiments. Figure 2C The example analog circuit in the example is a sense amplifier (SA) comparator 200C.

[0048] The SA comparator 200C includes P-type transistors MP10-MP18 and N-type transistors MN10-MN14 and MN17-MN18. Transistors MP10 and MN10 are coupled to form an inverter with input and output op coupled to node oni. Transistors MP17 and MN17 are coupled to form an inverter with input and output on coupled to node opi. The first source / drain of transistors MP11-MP16 is coupled to VDD. The gates of transistors MP11, MP12, MP15, MP16, MP18, and MN18 are coupled to receive a clock signal clk. The gate of transistor MP13, the second source / drain of transistors MP14 and MP15, the first source / drain of transistor MP18, and the gate of transistor MN13 are coupled to node opi. The gate of transistor MP14, the second source / drain of transistors MP12 and MP13, the second source / drain of transistor MP18, and the gate of transistor MN14 are coupled to node oni. The first source / drain of transistors MN13 and MN14 are coupled to nodes oni and opi, respectively. The second source / drain of transistors MP11, MN13, and MN11 are coupled together. The second source / drain of transistors MP16, MN14, and MN12 are coupled together. The gates of transistors MN11 and MN12 are coupled to receive input signals inp and inn, respectively. The first source / drain of transistors MN11 and MN12 is coupled to the first source / drain of transistor MN18. The source / drain of transistor MN18 is coupled to VSS.

[0049] In some embodiments, the SA comparator 200C is implemented by a SUC with a PNN (or NNP) configuration, having a P-type active region P and N-type active regions N1, N2, as shown below. Figure 3B , Figure 3D One or more of the above are described. For example, transistors MP10-MP18 are implemented by a P-type active region P, while one or more of transistors MN10, MN13, MN14, MN17 are implemented by one of N-type active regions N1, N2, and one or more of transistors MN11, MN12, MN18 are implemented by another of N-type active regions N1, N2. Other arrangements are within the scope of various embodiments.

[0050] Figure 2D This includes circuit diagrams of example analog circuits in IC devices according to some embodiments. Figure 2D The example analog circuit in the example is part of a DDR (Double Data Rate) receiver (Rx) circuit 200D and includes a transadmittance amplifier (TAS) 261 and a transimpedance amplifier (TIA) 262.

[0051] TAS 261 includes P-type transistors MP20-MP23, N-type transistors MN20 and MN21, resistor R21, and capacitor C21. Transistors MP20, MP22, and MN20 are coupled in series to VSS. Transistors MP21, MP23, and MN21 are also coupled in series to VSS. The first terminal of resistor R21 and capacitor C21 is coupled to the source / drain of transistor MP20 and the source / drain of transistor MP22. The second terminal of resistor R21 and capacitor C21 is coupled to the source / drain of transistor MP21 and the source / drain of transistor MP23.

[0052] The TIA 262 includes P-type transistors MP24-MP27, N-type transistors MN26 and MN27, and resistors R26 and R27. Transistors MP24, MP26, and MN26 are coupled in series to VSS. Transistors MP25, MP27, and MN27 are also coupled in series to VSS. The first terminal of resistor R26 is coupled to the gate of transistors MP26 and MN26, and the second terminal is coupled to the source / drain of transistors MP26 and MN26. The first terminal of resistor R27 is coupled to the gate of transistors MP27 and MN27, and the second terminal is coupled to the source / drain of transistors MP27 and MN27.

[0053] In some embodiments, at least one of TAS 261 or TIA 262 is implemented by a SUC having a PPN (or NPP) configuration having P-type active regions P1, P2 and N-type active region N, such as Figure 3A , Figure 3D One or more of the following are described. For example, one or more of transistors MP20 and MP21 are implemented by one of the P-type active regions P1 and P2, and one or more of transistors MP22 and MP23 are implemented by the other of the P-type active regions P1 and P2. Transistors MN20 and MN21 are implemented by the N-type active region N. As another example, one or more of transistors MP24 and MP25 are implemented by one of the P-type active regions P1 and P2, and one or more of transistors MP26 and MP27 are implemented by the other of the P-type active regions P1 and P2. Transistors MN26 and MN27 are implemented by the N-type active region N. Other arrangements are within the scope of various embodiments. Regarding Figures 2A-2D The analog circuit described is an example. Other analog circuits, such as voltage-controlled oscillators, digital-to-analog converters (DACs), bandgap reference circuits, etc., are also within the scope of various embodiments.

[0054] Figure 3AThis is a schematic diagram of the layout of SUC 300A according to some embodiments. SUC 300A has a PPN (or NPP) configuration with P-type active regions P1, P2 and N-type active region N. In some embodiments, the same instance of SUC 300B is placed in the layout of the IC device to implement different sub-circuits of one or more analog circuits, as shown in the reference... Figure 4A As described above. In at least one embodiment, the SUC 300A is stored as a unit in a unit library on a non-transitory computer-readable medium.

[0055] The SUC 300A includes a boundary 310 (i.e., a cell boundary) through which multiple instances of the SUC 300A are placed adjacent to each other. Boundary 310 includes edges 311, 312, 313, and 314. Edges 311 and 312 extend along the X-axis, and edges 313 and 314 extend along the Y-axis. In some embodiments, the X-axis is an example of one of a first direction and a second direction, and the Y-axis is an example of the other of the first direction and the second direction. Edges 311, 312, 313, and 314 are joined together to form a closed boundary 310. In the placement and routing operation described herein (also known as “Automatic Placement and Routing (APR)”), multiple instances of the SUC 300A are adjacent to each other at their respective boundaries in the layout of the IC device. A rectangular or square shape of boundary 310 is an example.

[0056] The SUC 300A also includes active regions P1, P2, and N arranged continuously along the Y-axis. Active regions P1, P2, and N are spaced apart from each other along the Y-axis and extend continuously along the X-axis. Figure 3A In the example configurations, each active region P1, P2, N includes two portions spaced apart from each other along the Y-axis. For example, active region P1 includes active region portions 321, 322, active region P2 includes active region portions 323, 324, and active region N includes active region portions 325, 326. In at least one embodiment, each of the active region portions 321-326 corresponds to a nanosheet or a stack of nanosheets, and the transistor configured by active regions P1, P2, N is a nanosheet transistor, such as a nanosheet FET. In some embodiments, the active regions described herein are active regions of a CFET, wherein a transistor or active region is stacked on top of another transistor or active region in the thickness direction of the IC device. Other active region configurations are within the range of various embodiments. Active regions are sometimes referred to as oxide-defined (OD) regions and are schematically shown in the figures with the label “OD”. Active regions P1, P2 are P-type active regions configured to form P-type transistors, such as PMOS transistors. The active region N is an N-type active region and is configured to form an N-type transistor, such as an NMOS transistor.

[0057] The SUC 300A also includes gates on each active region P1, P2, N. The gates are within boundary 310. For simplicity, the gates on active region P1 are designated as gates 330-341, while most gates on active regions P2 and N are unnumbered. The gates on active region P1 are aligned along the Y-axis with their corresponding gates on active region P2 and active region N. For example, gate 341 above active region P1 is aligned along the Y-axis with its corresponding gate 342 above active region P2 and its corresponding gate 343 above active region N. Adjacent gates are spaced apart by a gate pitch (CPP) along the X-axis, where CPP is the distance along the X-axis between the center lines of adjacent gates. Two gates are considered adjacent (or directly adjacent) if there are no other gates between them. Each gate is a conductive gate, comprising a conductive material such as polysilicon, and is schematically shown in the figures with the label “PO”. Other conductive materials for the gates, such as metals, are within the scope of various embodiments. The gate is configured with a corresponding PMOS or NMOS transistor along with each active region P1, P2, N. The gate is sometimes referred to as a finger, gate stack, or stack.

[0058] Transistors electrically coupled to a circuit or sub-circuit configured to perform the functions of an IC device are referred to herein as functional transistors. Transistors not electrically coupled to a circuit or sub-circuit configured to perform the functions of an IC device are referred to herein as dummy transistors. In at least one embodiment, a dummy transistor is identical to a functional transistor except that it is not electrically coupled to another transistor, device, or circuit. For example, a dummy transistor has a gate and a source / drain that are electrically floating or electrically coupled together. In at least one embodiment, a dummy transistor has a dummy gate made of a non-conductive material. Other dummy transistor configurations are available across a variety of embodiments. In at least one embodiment, the SUC 300A does not include dummy transistors. In some embodiments, the SUC 300A also includes a guard ring (not shown). In some embodiments, one or more guard rings disclosed herein include one or more dummy transistors.

[0059] In some embodiments, all gates in the SUC 300A have the same width (e.g., gate width) along the X-axis and the same length (e.g., gate length) along the Y-axis. The SUC 300A has a cell height H along the Y-axis and a cell width W along the X-axis. The cell height H is the distance along the Y-axis between edges 311 and 312. The cell width W is the distance along the X-axis between edges 313 and 314. The cell height H depends on the gate length and the number of active regions in the SUC 300A (i.e., 3 active regions). The cell width W depends on the gate width and the total number of gates (or fingers) on the active regions. Figure 3AIn the example configuration, the SUC 300A includes 12 gates or 12 fingers on each active region P1, P2, N. The number of other gates on each active region ranges from one embodiment to another. In some embodiments, the gate width and gate length are predetermined, for example, through one or more manufacturing processes to produce a predetermined cell height H. In at least one embodiment, the cell width W is customizable, for example, automatically customized by a programming processor and / or by a human designer specifying the total number of gates on each active region.

[0060] According to some embodiments, the SUC is configured to implement different sub-circuits of one or more analog circuits. Figure 3A In the example configuration, the SUC 300A is configured to implement different sub-circuits, including at least one individual PMOS transistor and at least one inverter.

[0061] Specifically, the active region P1 is configured to form a PMOS transistor 351 together with the corresponding gates 330-341. This PMOS transistor 351 will be electrically coupled to another identical PMOS transistor (not shown) of the same SUC as SUC 300A to form a reference PMOS transistor. Figure 2A The current mirror 210 described corresponds to the current mirror. Transistor 351 includes 12 gates (or fingers) electrically coupled together through various conductive components described herein to provide a drive strength of 12. In some embodiments, the gates or fingers of transistors in a plurality of SUCs are coupled together to form a transistor with a drive strength greater than that provided by a transistor in a single SUC. The number of fingers or drive strength of transistor 351 described is an example and may be automatically customized by a programming processor and / or a human designer in one or more embodiments.

[0062] Active regions P2 and N are configured together with their respective gates to form corresponding PMOS and NMOS transistors, which are then electrically coupled through conductive components to form a PMOS transistor and an NMOS transistor. Figure 2A The inverter 245 described in the text corresponds to the inverter. Figure 3AIn the example configuration, the 12 fingers on active region P2 are divided into four groups or sets, each group or set having three fingers. This results in four PMOS transistors, each with a drive strength of 3. Two of the four PMOS transistors are designated as transistors 352 and 354. Similarly, the 12 fingers on active region N are divided into four groups or sets, each group or set having three fingers. This results in four NMOS transistors, each with a drive strength of 3. Two of the four NMOS transistors are designated as transistors 355 and 357. In at least one embodiment, the number of groups and / or the number of fingers in each group is customizable, for example, automatically customized by a programming processor and / or a human designer. Each PMOS transistor configured by active region P2 is electrically coupled to a corresponding NMOS transistor configured by active region N via conductive components to form an inverter. For example, transistor 352 is coupled to transistor 355 to form an inverter, transistor 354 is coupled to transistor 357 to form another inverter, and so on.

[0063] exist Figure 3A In the example configuration, the SUC 300A can be configured to fully or partially implement different sub-circuits, such as a current mirror and an inverter. The SUC 300A can be configured in different ways to implement other sub-circuits, such as a current mirror and one or more decoupling capacitors. In one example, the active region P2 and the corresponding gate can be configured as a single PMOS transistor with a drive strength of 12, similar to transistor 351, to form a complete current mirror with transistor 351. The active region N and the corresponding gate can be configured with reference to... Figure 2A The described decoupling capacitor 225 corresponds to one or more decoupling capacitors. In another example, the SUC 300A is configured to implement different sub-circuits, such as those described above. Figure 2D Other configurations are within the scope of various embodiments. The flexibility of the SUC 300A to implement various subcircuits in a single unit is an improvement over other methods, in which each subcircuit is implemented by a separate unit, or each unit is configured to implement only one subcircuit.

[0064] Figure 3B This is a schematic diagram of the layout of the SUC 300B according to some embodiments. The SUC 300B has an NNP (or PNN) configuration with N-type active regions N1, N2 and P-type active regions P. In some embodiments, identical instances of the SUC 300B are placed in the layout of the IC device to implement different sub-circuits of one or more analog circuits. In at least one embodiment, the SUC 300B is stored as a cell in a cell library on a non-transitory computer-readable medium.

[0065] The SUC 300B includes a boundary 360 through which multiple instances of the SUC 300B are placed adjacent to each other. In some embodiments, boundary 360 corresponds to boundary 310. The SUC 300B also includes active regions N1, N2, P and corresponding gates arranged continuously along the Y-axis, configured similarly to a reference designation. Figure 3A The active regions and gates are described. For example, active region N1 includes active region portions 361 and 362, active region N2 includes active region portions 363 and 364, and active region P includes active region portions 365 and 366. Active regions N1 and N2 are N-type active regions and are configured to form an N-type transistor, such as an NMOS transistor, together with their respective gates. Active region P is a P-type active region and is configured to form a P-type transistor, such as a PMOS transistor, together with its respective gate. In at least one embodiment, SUC 300B does not have a dummy transistor. In some embodiments, SUC 300B also includes a guard ring (not shown).

[0066] In some embodiments, similar to reference Figure 3A The manner in which the number of gates on each active region and / or how the gates above each active region in the SUC 300B are grouped into one or more groups is customizable, for example, by a programming processor and / or automatically by a human designer. In at least one embodiment, the SUC 300B is configured to implement different sub-circuits, for example, as referenced Figure 2C According to some embodiments, SUC 300B may achieve one or more advantages relative to SUC 300A.

[0067] Figure 3C This is a schematic diagram of the layout of the SUC 300C according to some embodiments. The SUC 300C has an NNPP (or PPNN) configuration, having N-type active regions N1, N2 and P-type active regions P1, P2. In some embodiments, identical instances of the SUC 300C are placed in the layout of the IC device to implement different sub-circuits of one or more analog circuits. In at least one embodiment, the SUC 300C is stored as a cell in a cell library on a non-transitory computer-readable medium.

[0068] The SUC 300C includes a boundary 370 through which multiple instances of the SUC 300C are placed adjacent to each other. In some embodiments, boundary 370 corresponds to boundary 310. The SUC 300C also includes active regions N1, N2, P1, P2 and corresponding gates arranged continuously along the Y-axis, configured similarly to a reference designation. Figure 3AThe active regions and gates are described. For example, active region N1 includes active region portions 371 and 372, active region N2 includes active region portions 373 and 374, active region P1 includes active region portions 375 and 376, and active region P2 includes active region portions 377 and 378. Active regions N1 and N2 are N-type active regions and are configured to form N-type transistors, such as NMOS transistors, together with their respective gates. Active regions P1 and P2 are P-type active regions and are configured to form P-type transistors, such as PMOS transistors, together with their respective gates. In at least one embodiment, the SUC 300C does not have a dummy transistor. In some embodiments, the SUC 300C also includes a guard ring (not shown).

[0069] In some embodiments, similar to reference Figure 3A The manner in which the number of gates on each active region and / or how the gates above each active region are grouped into one or more groups in the SUC 300C is customizable, for example, by a programming processor and / or automatically by a human designer. In at least one embodiment, the SUC 300C is configured to implement different sub-circuits, for example, as referenced Figure 2B According to some embodiments, the SUC 300C may implement one or more advantages described with reference to the SUC 300A.

[0070] Figure 3D This includes schematic diagrams of various SUC configurations 381-388 according to some embodiments. Figure 3D This is not an exhaustive list of possible SUC configurations according to various embodiments.

[0071] SUC configuration 381 (PPN) and SUC configuration 382 (NPP) are equivalent and are considered the same SUC configuration in one or more embodiments. See also... Figure 3A Examples of SUC configurations 381 and 382 are described. SUC configuration 383 (NNP) and SUC configuration 384 (PNN) are equivalent and are considered the same SUC configuration in one or more embodiments. See also... Figure 3B Examples of SUC configurations 383 and 384 are described. SUC configuration 385 (NNPP) and SUC configuration 386 (PPNN) are equivalent and are considered the same SUC configuration in one or more embodiments. See also... Figure 3CExamples of SUC configurations 385 and 386 are described. In one or more embodiments, SUC configuration 387 (PPPN) and its equivalent SUC configuration (NPPP) (not shown), as well as equivalent SUC configurations NNNP and PNNN (not shown), are used as examples of other SUC configurations. According to some embodiments, SUC configuration 388 (NNNNP) and its equivalent SUC configuration (PNNNN) (not shown), as well as equivalent SUC configurations PPPPN and NPPPP (not shown), are used as examples of other SUC configurations.

[0072] In some embodiments, the programming processor and / or human designer automatically determine which SUC configuration to select for implementing various sub-circuits of one or more analog circuits. In at least one embodiment, such a decision is made based on the number of PMOS and / or NMOS transistors in the analog circuit to be implemented and / or the required drive strength.

[0073] For example, to implement analog circuits that require a greater number of PMOS transistors than NMOS transistors and / or need to provide a greater drive strength than NMOS transistors, a SUC configuration including more P-type active regions than N-type active regions is selected, such as one of SUC configurations 381 and 387. SUC configuration 381 is selected when the imbalance in the number and / or drive strength of PMOS and NMOS transistors in the analog circuit is low. SUC configuration 387, with more P-type active regions, is selected when the imbalance in the number and / or drive strength of PMOS and NMOS transistors in the analog circuit is high.

[0074] Conversely, for analog circuits requiring a greater number of NMOS transistors and / or needing to provide a greater drive strength than PMOS transistors, a SUC configuration including more N-type active regions than P-type active regions is selected, such as one of SUC configurations 383 and 388. SUC configuration 383 is selected when the imbalance in the number and / or drive strength of NMOS and PMOS transistors in the analog circuit is low. SUC configuration 388, with more N-type active regions, is selected when the imbalance in the number and / or drive strength of NMOS and PMOS transistors in the analog circuit is high.

[0075] To implement analog circuits with the same or substantially the same number of PMOS transistors and drive strength as NMOS transistors, a SUC configuration, such as SUC configuration 385, is selected, comprising an equal number of N-type and P-type active regions. In some embodiments, SUC configurations 381, 383, and 385 are sufficient to implement all analog circuitry in the IC device.

[0076] In some embodiments, the same SUC with the selected SUC configuration, or multiple instances of the same SUC with the selected SUC configuration, are placed in the circuit area of ​​the IC device layout to implement one or more analog circuits. Non-limiting specific examples are described herein using SUC configuration 381 (PPN) and equivalent SUC configuration 382. Other SUC configurations may also be used in a similar manner.

[0077] Figure 4A This is a schematic diagram of a layout 400A of an IC device according to some embodiments. In at least one embodiment, the layout 400A is generated by an APR tool and / or stored on a non-transitory computer-readable medium.

[0078] Layout 400A includes an array of SUC 410s having the same SUC configuration 381 or 382. In some embodiments, the array is obtained by placing multiple instances of SUC 410s in multiple rows and columns of the array. Rows extend along the X-axis. Columns extend along the Y-axis. In some embodiments, SUC 410 corresponds to SUC 300A and has 12 fingers on each active region. In at least one embodiment, the number of fingers on each active region of SUC 410 is not 12.

[0079] The 400A SUC 410 array is configured to implement different sub-circuits of one or more analog circuits. Figure 4A In the example configuration, the SUC array 410 is configured to implement various sub-circuits of one or more instances of the ICO 200A. Specifically, the array of SUC 410 includes regions 401-403 arranged along the Y-axis. Region 401 is configured to implement transistor MP1 of the current mirror 210 and the corresponding decoupling capacitor 221. Region 402 is configured to implement transistor MP2 of the current mirror 210 and the corresponding decoupling capacitor 222. Region 403 is configured to implement DRO 230.

[0080] Region 401 includes sub-regions 404 and 405. In some embodiments, sub-region 405 is configured similarly to sub-region 404. Sub-region 404 includes two adjacent rows of SUCs 410. The two rows of SUCs 410 in sub-region 404 include four rows of P-type active regions corresponding to four rows of PMOS transistors 411, 412, 415, and 416, and two rows of N-type active regions corresponding to two rows of NMOS transistors 413 and 414. The PMOS transistors in rows 411, 412, 415, and 416 are configured as transistor MP1 of the current mirror 210. The NMOS transistors in rows 413 and 414 are configured as decoupling capacitors 221, which are N-type decoupling capacitors (nmoscap), and are coupled to transistor MP1 configured by the PMOS transistors in rows 411, 412, 415, and 416.

[0081] Region 402 includes sub-regions 406 and 407. In some embodiments, sub-region 407 is configured similarly to sub-region 406. Sub-region 406 includes two adjacent rows of SUCs 410. The two rows of SUCs 410 in sub-region 406 include four rows of P-type active regions corresponding to four rows 421, 422, 425, and 426 of PMOS transistors, and two rows of N-type active regions corresponding to two rows 423 and 424 of NMOS transistors. The PMOS transistors in rows 421, 422, 425, and 426 are configured as transistor MP2 of current mirror 210. The NMOS transistors in rows 423 and 424 are configured as decoupling capacitors 222, which are N-type decoupling capacitors (nmoscap), and are coupled to transistor MP2 configured by the PMOS transistors in rows 421, 422, 425, and 426.

[0082] Area 403 includes information about Figure 4B At least one instance of sub-region 435 is described in detail. In at least one embodiment, region 403 includes multiple instances of sub-region 435. In some embodiments, all instances of sub-region 435 do not occupy the entire region 403, and portions of region 403 opposite to instances of sub-region 435 are configured similarly to regions 401, 402.

[0083] exist Figure 4BIn this embodiment, sub-region 435 includes a repeating pattern of block 440, which includes a plurality of SUCs 410. Block 440 is composed of sub-blocks A, B, C, and D. Sub-blocks A and D belong to a row of SUCs 410, and sub-blocks B and C belong to an adjacent row of SUCs 410. Each of sub-blocks A and B includes five SUCs 410, and each of sub-blocks C and D includes two SUCs 410. Other numbers of SUCs 410 and / or rows of SUCs 410 in each sub-block are within the range of various embodiments. Block 440 includes four rows of P-type active regions corresponding to four rows 441, 442, 445, and 446 of PMOS transistors, and two rows of N-type active regions corresponding to two rows 443 and 444 of NMOS transistors. The PMOS transistors in rows 441 and 446 are configured as transistors for current mirrors. For example, the PMOS transistor in row 441 is configured as transistor MP1 of current mirror 210, while the PMOS transistor in row 446 is used as transistor MP2 of current mirror 210.

[0084] The NMOS transistors in rows 443 and 444 and the corresponding PMOS transistors in rows 442 and 445 are configured to be in relation to a reference. Figure 2A The inverter described corresponds to inverter 245. The inverter is coupled to a reference inverter. Figure 2A The described DRO 230 corresponds to the DRO. Therefore, block 440 and similar blocks are also referred to as DRO blocks. In some embodiments, inverters in sub-block A are coupled to configure an inverter corresponding to inverter INV_A, inverters in sub-block B are coupled to configure an inverter corresponding to inverter INV_B, inverters in sub-block C are coupled to configure an inverter corresponding to inverter INV_C, and inverters in sub-block D are coupled to configure an inverter corresponding to inverter INV_D, as referenced. Figure 2A In a non-limiting example, inverters INV_A and INV_B include more fingers and have greater drive strength than inverters INV_C and INV_D.

[0085] In some embodiments, within the DRO block, a P-type active region (e.g., in) is used to implement a current mirror in each SUC. Figure 4B The configuration in lines 441 and 446 is similar to that in the section about Figure 3A The active region P1 is described as all 12 fingers in a set or group. P-type and N-type active regions are used to implement inverters in each SUC (e.g., in...). Figure 4BIn lines 442-445, sub-blocks A, B, C, and D are configured differently. For example, in lines 442-444, the 12 fingers on each P-type or N-type active region of each SUC are divided into four groups for sub-blocks A and B, with three fingers in each group, and into six groups for sub-blocks C and D, with two fingers in each group. Other configurations are also within the scope of various embodiments.

[0086] In some embodiments, outside the DRO block, a P-type active region (e.g., in) is used to implement a current mirror in each SUC. Figure 4A The configuration in lines 411, 412, 415, 416, 421, 422, 425, and 426 is similar to that in the section about Figure 3A The active region P1 is described as having all 12 fingers in a set or group. The N-type active region (e.g., in) is used to implement the decoupling capacitor in each SUC. Figure 4A The configuration in lines 413, 414, 423, and 424 is similar to that in the section about Figure 3A The described active region N has four groups, each with three fingers. Other configurations are within the scope of various embodiments.

[0087] exist Figure 4A , Figure 4B In the example configuration, the SUC 410 array includes various SUC 410s, which are identical but electrically coupled to configure different sub-circuits of analog circuits (such as ICO). For example, in Figure 4A SUC 410, with its active region, located in rows 411-413, is an example of a SUC configured with a current mirror and a decoupling capacitor. Figure 4B SUC 420, with its active region in rows 441-443, is another example of a SUC configured with a current mirror and an inverter. Therefore, various sub-circuits, such as decoupling capacitors, current mirrors, inverters, and DROs, are implemented in the array of SUC 410.

[0088] In at least one embodiment, the SUC 410 array does not have dummy transistors that separate sub-circuits of the analog circuit from other sub-circuits of the analog circuit. For example, the SUC 410 array does not have dummy transistors that separate the current mirrors and / or decoupling capacitors in regions 401 and / or 402 from the DRO in region 403. In some embodiments, the SUC 410 array does not have dummy transistors surrounding sub-circuits of the analog circuit. For example, the SUC 410 array does not have dummy transistors surrounding the DRO and separating the DRO from the current mirror and decoupling capacitor.

[0089] Figure 4CThis is a schematic diagram of a layout 400C of an IC device according to some embodiments. In at least one embodiment, the layout 400C is generated by an APR tool and / or stored on a non-transitory computer-readable medium.

[0090] Layout 400C includes a circuit region 460 and a pseudo-region 470 surrounding the circuit region 460. In some embodiments, the circuit region 460 corresponds to a reference. Figure 4A The array of SUC 410 is described. For example, circuit region 460 includes... Figure 4A Regions 401, 402, and 403 correspond to regions 461, 462, and 463. Regions 461 and 462 are configured to implement a current mirror (CM) and a decoupling capacitor (Decap), while region 463 is configured to implement a DRO. Circuit regions 460 constitute an array of SUCs 465. In some embodiments, SUCs 465 correspond to SUCs 410. In at least one embodiment, circuit regions 460 are filled with SUCs 465 until circuit regions 460 contact at least one, some, or all of the four edges of dummy region 470.

[0091] In some embodiments, not all transistors in SUC 465 and / or one or more SUC 465 are coupled to a particular subcircuit. For example, given the required drive strength and / or number of transistors in a particular DRO configuration, not all SUC 465s in the row containing region 463 are used to configure the required DRO. Such "unused" SUC 465s and / or "unused" transistors in one or more partially used SUC 465s are configured as additional decoupling capacitors. In some embodiments, in the array of SUC 410, transistors in any subcircuit not configured with analog circuitry (e.g., ICO) are configured as additional decoupling capacitors. In at least one embodiment, SUC 410 includes one or more first transistors configuring at least one subcircuit (e.g., current mirror, inverter, DRO) of analog circuitry (e.g., ICO), and one or more second transistors configuring any subcircuit not configured with analog circuitry. Such one or more second transistors are configured as additional decoupling capacitors.

[0092] exist Figure 4C In the example configuration, additional decoupling capacitors are arranged in regions 466 and 467, opposite region 463. Figure 4CIn the example configuration, circuit region 460 also includes an additional region 468 containing additional decoupling capacitors. The specific arrangement of regions 466-468 including additional decoupling capacitors is shown as an example, and other arrangements are also within the range of various embodiments depending on the actual design of the IC device. In at least one embodiment, the configuration of regions 466, 467 is similar to that of regions 461, 462, and includes not only decoupling capacitors but also current mirrors. In some embodiments, the additional decoupling capacitors are not only arranged in separate regions such as regions 466-468, but also distributed at various locations in the sub-circuits of circuit region 460 other than the decoupling capacitors. Therefore, in one or more embodiments, the number of decoupling capacitors available in the IC device can be increased without requiring or increasing the dedicated chip area for decoupling capacitors.

[0093] In at least one embodiment, circuit region 460 does not have a dummy transistor that separates a sub-circuit of the analog circuit from other sub-circuits of the analog circuit. For example, circuit region 460 does not have a dummy transistor that separates the current mirror and / or decoupling capacitor in regions 461 and / or 462 from the DRO in region 463. In some embodiments, circuit region 460 does not have a dummy transistor surrounding a sub-circuit of the analog circuit. For example, circuit region 460 does not have a dummy transistor surrounding the DRO in region 463 and separating the DRO from the current mirror and decoupling capacitor.

[0094] The pseudo-region 470 surrounds the circuit region 460 on all four sides. The pseudo-region 470 includes pseudo-transistors as described herein. Figure 4C In the example configuration, pseudo-region 470 is filled with multiple instances of SUC 475; the transistors of SUC 475 are not electrically coupled to any particular circuit. In some embodiments, SUC 475 has the same SUC configuration as SUC 465. In at least one embodiment, SUC 475 is identical to SUC 465. Pseudo-region 470 has widths d1-d4 at the corresponding edges of circuit region 460. In some embodiments, widths d1-d4 have predetermined values ​​to avoid or mitigate density gradient effects (DGE). In at least one embodiment, widths d1-d4 are 5 μm or greater.

[0095] Currently, with the continuous shrinking of semiconductor technology, stringent process design rules limit the gate length and / or width that can be used in analog circuits. Because analog circuits are limited to very small usable gate lengths, according to some embodiments, designs and layouts using a uniform and single-patterned digital center are employed to achieve better area reduction. In at least one embodiment, a CFET is used to configure analog circuits in a design similar to that of digital circuits. By using a CFET, in one or more embodiments, analog circuits with similar reduction capabilities to digital circuit layouts can be implemented.

[0096] In some cases, foundry process development kits (PDKs) provide templates for individual PMOS transistors, individual NMOS transistors, and pairs of NMOS transistors. To meet various analog circuit key performance indicators (KPIs), such as matching, speed, noise, and high decoupling capacitors, other methods use different cells in different circuit blocks, resulting in uneven layout. Compared to other methods that use different cells for different circuit blocks, analog circuits according to some embodiments use multiple instances of a single cell configured to implement a uniform integration layout approach.

[0097] Furthermore, other methods utilize a significant amount of chip area to create pseudo-surround structures around each circuit block. For example, in other methods, decoupling capacitor cells, which configure decoupling capacitors, are arranged within a circuit region surrounded by a non-circuit region; current mirror cells, which, unlike the decoupling capacitors, are arranged within a separate circuit region surrounded by another non-circuit region, and so on. In other methods, the area occupied by the non-circuit region is disadvantageously large, potentially leading to undesirable high IR drops (voltage drops). Compared to other methods that require separate pseudo-surround structures for each circuit block or circuit region, various sub-circuits of the analog circuit according to some embodiments are implemented on the same SUC within the same circuit region, and separate pseudo-regions surround the circuit region containing the various sub-circuits to avoid or at least mitigate density gradient effects (DGE). Therefore, in one or more embodiments, the area of ​​pseudo-regions or non-circuit regions in the IC device can be reduced while addressing DGE issues and / or achieving improved process control. In one or more embodiments, the area improvement is from about 20% to about 40%. In a non-limiting example, such as Figure 2A , Figure 3A , Figure 4A , Figure 4B One or more of the ICO designs described above provide approximately 30% area improvement compared to other methods.

[0098] According to some embodiments, examples of sub-circuits constituting one or more analog circuits include, but are not limited to, a single P-type transistor, a single N-type transistor, an array of P-type transistors, an array of N-type transistors, a P-type decoupling capacitor, an N-type decoupling capacitor, an inverter such as a CMOS inverter, a buffer, a current mirror, a differential pair, a cascode structure, a switch such as a CMOS switch, a ring oscillator such as a differential ring oscillator, etc.

[0099] In some embodiments, different sub-circuits of the analog circuit are implemented by the same SUC configured with different numbers of P-type active regions and N-type active regions. Regarding Figure 3A , Figure 3B , Figure 3D One or more examples of such a SUC configuration are described herein, wherein the number of rows of P-type active regions (or rows of P-type transistors) in the SUC differs from the number of rows of N-type active regions (or rows of N-type transistors). In at least one embodiment, such a SUC configuration is advantageously suited for implementing analog circuits with unbalanced designs, such as analog circuits including a large number of current mirrors (i.e., a large number of PMOS transistors) or a large number of decoupling capacitors (i.e., a large number of NMOS transistors for nmoscap).

[0100] In some embodiments, a single gate length design is employed, wherein the layout of analog circuitry is implemented using a single SUC. In some embodiments, the SUC has a fixed cell height and / or cell width. Example SUC configurations include, but are not limited to, PPN, NPP, PPNN, NNPP, etc. In at least one embodiment, the SUC is scalable relative to the number of stacks (e.g., the number of fingers in each group as described herein) and / or the number of fingers (e.g., the total number of fingers on each active region). Therefore, in one or more embodiments, a simplified, uniform layout, reduced pseudo-region area, and improved autonomous process flow can be achieved through a single SUC configuration.

[0101] In at least one embodiment, area scaling is achieved by using a single SUC configured for different sub-circuits. Therefore, in one or more embodiments, different sub-circuits of an analog circuit can be packaged together in an easily mating manner without requiring separate pseudo-encirclement structures for individual sub-circuits, and with a unified pseudo-region surrounding the entire analog circuit.

[0102] In at least one embodiment, a performance advantage is achieved because the SUC-based layout is uniform and shorter, resulting in shorter interconnections between transistors and / or sub-circuits. Therefore, in one or more embodiments, parasitic RC can be mitigated without inducing high gradients in the active region and / or gate.

[0103] In at least one embodiment, the specification definition and / or DRC check of the autonomous layout process based on SUC, according to some embodiments, becomes easier compared to analog circuit layout according to other methods.

[0104] In some embodiments, based on a fixed layout construction, the SUC and / or SUC configuration described herein are included as part of the PDK. In at least one embodiment, the PDK includes one or more fixed features and one or more customizable features. Example fixed features include the gate length and width defining the cell height H. Another example fixed feature also includes the number and / or order of P-type and N-type active regions in the SUC, i.e., the SUC configuration of the SUC. Examples of customizable features in the PDK include, but are not limited to, the number of stacks, the number of fingers, the threshold voltage Vth, etc. Example threshold voltages include, but are not limited to, standard threshold voltage (SVT), low threshold voltage (LVT), ultra-low threshold voltage (ULVT), extremely low threshold voltage (ELVT), etc.

[0105] In some embodiments, a limited number of SUC configurations can be provided in the PDK by implementing different sub-circuits using SUCs with the same SUC configuration, but all analog circuits can use such SUC configurations. In at least one embodiment, an efficient analog / mixed-signal design approach using a single type of SUC is feasible.

[0106] In some cases, approximately 30% of the analog circuit area in an IC device is occupied by decoupling capacitors; therefore, saving area on decoupling capacitors is a design consideration. According to some embodiments, the layout of the analog circuit includes decoupling capacitors distributed throughout the layout, rather than arranging all decoupling capacitors in a block surrounded by non-circuit areas as described in other methods. For example, as per [reference to...] Figure 4A The aforementioned multi-row decoupling capacitors (e.g., Figure 4A Rows 413, 414, 423, 424 in the circuit and multiple rows of at least another sub-circuit (e.g., Figure 4A The rows 411, 412, 415, 416, 421, 422, 425, and 426 are physically interleaved. For example... Figure 4A As shown, unused transistors in the SUC active circuitry or sub-circuits are configured as decoupling capacitors. Therefore, in one or more embodiments, a high number of decoupling capacitors can be achieved while reducing the area occupied by decoupling capacitors in the analog circuitry. In one non-limiting example, the decoupling capacitor area is improved by approximately 11% compared to other methods.

[0107] Figure 5This includes schematic diagrams showing the layout of the SUC 300A and the corresponding back-end process online (BEOL) cell 500 according to some embodiments. BEOL cells are sometimes referred to as metal unit cells. In at least one embodiment, the BEOL cells 500 are stored as cells in a cell library on a non-transitory computer-readable medium.

[0108] BEOL unit 500 includes boundary 510, which corresponds to the boundary of the SUC configured in BEOL unit 500. Figure 5 In the example configuration, BEOL cell 500 is configured for SUC 300A, and boundary 510 corresponds to boundary 310 of SUC 300A. For example, boundary 510 is identical to boundary 310, and during placement, BEOL cell 500 is placed on top of SUC 300A such that boundary 510 coincides with boundary 310. In another non-limiting example, the BEOL cell configured for another SUC (e.g., SUC 300C (NNPP)) has a boundary that is identical to boundary 370 of SUC 300C.

[0109] The BEOL cell 500 also includes conductive patterns of one or more metal layers in its boundary 510, forming a redistribution structure. This redistribution structure is formed during BEOL fabrication above a transistor configured with an active region and a gate, which are formed during front-end processing (FEOL) fabrication. The redistribution structure includes multiple metal layers and multiple via layers arranged alternately in the thickness direction of the IC device. The bottommost metal layer immediately above the transistor is the metal zero (M0) layer. In other words, the M0 layer is the bottommost metal layer above the active region and gate, or the metal layer closest to the active region and gate. The next metal layer immediately above the M0 layer is the metal one (M1) layer, the next metal layer immediately above the M1 layer is the metal two (M2) layer, and so on. Conductors or conductive patterns in the M0 layer are referred to herein as M0 conductors or M0 conductive patterns, and wires or conductive patterns in the M1 layer are referred to herein as M1 conductors or M1 conductive patterns, etc. A via layer Vn is disposed between layers Mn and Mn+1, electrically coupling the two layers, where n is an integer greater than or equal to zero. For example, the zero via (V0) layer is the bottommost via layer disposed between layers M0 and M1, electrically coupling the two layers. Other via layers are V1, V2, etc. (See reference...) Figure 6 A non-restricted example of a redistribution structure is described.

[0110] exist Figure 5In the example configuration, BEOL cell 500 includes conductive patterns of M0, M1, and M2 layers. Other configurations including conductive patterns of more or fewer metal layers in the BEOL cell are within the scope of various embodiments. In at least one embodiment, BEOL cell 500 also includes vias of one or more via layers, such as V0 and / or V1 layers. In some embodiments, vias are not included in BEOL cell 500 but are generated during wiring operations.

[0111] The conductive pattern of the metal layer in the BEOL cell 500 is configured according to the sub-circuit implemented by the corresponding SUC (e.g., SUC 300A). Figure 5 In the example configuration, the SUC 300A will be used to implement a PMOS transistor for a current mirror at the active region P1 and an inverter at the active regions P2 and N, as per the example configuration. Figure 3A As described above, because the PMOS transistor in the current mirror is configured to handle a larger current than the PMOS and NMOS transistors in the inverter, the conductive pattern corresponding to the active region P1 (i.e., corresponding to the current mirror) is configured differently from the conductive patterns corresponding to the active regions P2 and N (e.g., wider than the conductive patterns corresponding to the active regions P2 and N (i.e., corresponding to the inverter)). Furthermore, since the PMOS and NMOS transistors in the inverter are configured to handle approximately the same current, the conductive patterns corresponding to the active regions P2 and N are configured in the same manner.

[0112] Specifically, in the BEOL unit 500, the M0 layer includes three sets of M0 conductive patterns 511, 512, and 513, which are located above the active regions P1, P2, and N respectively, and extend along the X-axis. Figure 5 In the example configuration, the three sets of M0 conductive patterns 511, 512, and 513 have the same configuration; for example, the M0 conductive patterns 511, 512, and 513 have the same metal width on the Y-axis and are spaced apart from each other along the Y-axis with the same metal pitch. Other configurations are within the scope of various embodiments. For example, in one or more embodiments, at least one of the metal width or metal pitch of the M0 conductive pattern 511 above the active region P1 is greater than that of the corresponding M0 conductive patterns 512 and 513 above the active regions P2 and N.

[0113] The M1 layer comprises three sets of M1 conductive patterns 521, 522, and 523, respectively located above the active regions P1, P2, and N, and extending along the Y-axis. At least one of the metal width or metal pitch of the M1 conductive pattern 521 above the active region P1 is greater than that of the corresponding M1 conductive patterns 522 and 523 above the active regions P2 and N, while the M1 conductive patterns 522 and 523 have the same metal width and metal pitch. For example, each of the M1 conductive patterns 521 has a metal width w1 along the X-axis, and each of the M1 conductive patterns 522 and 523 has a metal width w2 along the X-axis, where w1 > w2. Alternatively, M1 conductive pattern 521 may have a metal pitch p1, which is the distance along the X-axis between the center lines of adjacent M1 conductive patterns 521, and M1 conductive patterns 522 and 523 may have a metal pitch p2, which is the distance along the X-axis between the center lines of adjacent M1 conductive patterns 522 and 523, and p1 > p2. The larger metal width and / or larger metal pitch of M1 conductive pattern 521 results in fewer M1 conductive patterns 520 (e.g., 4) compared to the number of M1 conductive patterns 522 or M1 conductive patterns 523 (e.g., 8).

[0114] The M2 layer comprises three sets of M2 conductive patterns 531, 532, and 533, respectively located above the active regions P1, P2, and N, and extending along the X-axis. At least one of the metal width or metal pitch of the M2 conductive pattern 531 above the active region P1 is greater than that of the M2 conductive patterns 532 and 533 above the active regions P2 and N, while the M2 conductive patterns 532 and 533 have the same metal width and metal pitch. For example, each of the M2 conductive patterns 531 has a metal width w3 along the Y-axis, and each of the M2 conductive patterns 532 and 533 has a metal width w4 along the Y-axis, where w3 > w4. Alternatively, the M2 conductive pattern 531 may have a metal pitch p3, which is the distance along the Y-axis between the center lines of adjacent M2 conductive patterns 531, and the M2 conductive patterns 532 and 533 may have a metal pitch p4, which is the distance along the Y-axis between the center lines of adjacent M1 conductive patterns 532 and 533, and p3 > p4. The larger metal width and / or larger metal pitch of the M2 conductive pattern 531 results in a smaller number of M2 conductive patterns 531 (e.g., 2) compared to the number of M2 conductive patterns 532 or M2 conductive patterns 533 (e.g., 4).

[0115] The configuration of the conductive patterns in BEOL cell 500 is an example corresponding to a non-limiting, specific manner in which SUC 300A is used to implement a particular set of sub-circuits (i.e., current mirrors and inverters). In some embodiments, when SUC 300A is used to implement another set of sub-circuits, for example, as... Figure 4AThe current mirror and decoupling capacitor described in lines 411-413, BEOL unit 500 are configured differently or different BEOL units are provided. For example, when SUC 300A is used to implement, as per the description... Figure 4A When using the current mirror and decoupling capacitor described in lines 411-413, the M1 conductive pattern 522 above the active region P2 has the same metal width w1 and the same metal pitch p1 as the M1 conductive pattern 521 above the active region P1, and the M2 conductive pattern 532 above the active region P2 has the same metal thickness w3 and the same metal pitch p3 as the M2 conductive pattern 531 above the active region P1.

[0116] In some embodiments, the IC device includes a BEOL cell array, and each BEOL cell is located on a corresponding SUC in the SUC array, as referenced. Figure 4A As described herein. In at least one embodiment, different BEOL cells are configured for the same SUC and correspond to different ways in which the SUC is used to implement different sub-circuits. These different BEOL cells are included in the BEOL cell array to configure conductive components that electrically couple the transistors of the underlying SUC to the intended sub-circuit. Because analog metrics are sensitive to metal interconnects, providing the same metal interconnects and / or repeating metal interconnect cells in the BEOL cells, as described herein, can achieve better accuracy and speed matching. In some embodiments, the uniformity of analog circuit layout in the underlying SUC array and the upper BEOL cell array improves the autonomous flow of the design process.

[0117] Figure 6 This is a schematic cross-sectional view of an IC device 600 according to some embodiments. In at least one embodiment, the IC device 600 includes components for reference to... Figures 2A-2D , Figures 3A-3D , Figures 4A-4C , Figure 5 One or more analog circuits configured in one or more ways as described.

[0118] like Figure 6 As shown, the IC device 600 includes a substrate 650 on which circuit elements and structures corresponding to one or more circuit regions and / or layouts described herein are formed. The substrate 650 has a thickness direction along the Z-axis ( Figure 6 (Not shown in the diagram), the Z-axis is perpendicular to the X and Y axes. In at least one embodiment, the substrate 650 comprises silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor or dielectric material. In some embodiments, the substrate 650 is a p-doped substrate. In some embodiments, the substrate 650 is an n-doped substrate. In some embodiments, the substrate 650 is a rigid crystalline material other than a semiconductor material, such as diamond, sapphire, aluminum oxide (Al2O3), etc.

[0119] IC device 600 also includes N-type and P-type dopants added to substrate 650 to form NMOS active region 651 and PMOS active region 652 respectively. In some embodiments, an isolation structure is formed between adjacent active regions. For simplicity, Figure 6 The isolation structure is omitted. In at least one embodiment, active regions 651 and 652 correspond to one or more active regions as described herein.

[0120] IC device 600 also includes various gate structures above the active region. For example, the gate structure includes a gate 654 and a corresponding gate dielectric 653 on the active region of the substrate 650. Example materials comprising one or more layers of gate dielectric 653 include HfO2, ZrO2, etc. Example materials for gate 654 include polysilicon, metal, etc. In some embodiments, the various gate structures of IC device 600 correspond to one or more gates described herein. In at least one embodiment, the gate structure corresponding to a dummy gate includes a dielectric material.

[0121] IC device 600 also includes a metal-to-device (MD) contact structure 655 for electrically coupling the bottom source / drain of various transistors in the active region to other circuit elements. In some embodiments, the MD contact structure is included in the layout of the SUC.

[0122] IC device 600 also includes a gate-to-gate (VG) via located above and electrically in contact with the gate, and a device-to-device (VD) via located above and electrically in contact with the MD contact structure. For example, Figure 6 The diagram shows a representative VG via 656 and a representative VD via 657.

[0123] IC device 600 also includes a redistribution structure 660 located above vias VD and VG, comprising multiple metal layers M0, M1, ... and multiple via layers V0, V1, V2, ..., alternately arranged in the thickness direction of substrate 650 (i.e., along the Z-axis). The redistribution structure 660 also includes various interlayer dielectric (ILD) layers (not shown or numbered) in which the metal layers and via layers are embedded. The metal layers and via layers of interconnect structure 660 are configured to electrically couple various components or circuits of IC device 600 to each other and / or to external circuitry. For simplicity, Figure 6 The metal layer and via layer above layer M1 are omitted. Figure 6In the example configuration, the M0 layer includes M0 conductive patterns 663 and 664 that are correspondingly located above and electrically contacting the VG via 656 and VD via 657. The V0 layer includes V0 vias 665 and 666 that are correspondingly located above and electrically contacting the M0 conductive patterns 663 and 664. The M1 layer includes M1 conductive patterns 667 and 668 that are correspondingly located above and electrically contacting the V0 vias 665 and 666.

[0124] MD contact structures, VG vias, VD vias, conductive patterns in one or more metal layers, and corresponding vias in one or more via layers are examples of conductive components that, as described herein, electrically couple underlying transistors into sub-circuits and further electrically couple sub-circuits into one or more analog circuits.

[0125] Figure 7 This is a flowchart of a portion of an IC design flow 700 according to some embodiments. In some embodiments, IC design flow 700 corresponds to one or more operations of IC design flow 100, such as APR at operation 130. In some embodiments, IC design flow 700 is executed entirely automatically by a programming processor. In at least one embodiment, IC design flow 700 is executed automatically by a programming processor using input provided by a human designer. In some embodiments, IC design flow 700 is executed to generate a layout including one or more analog circuits, as shown in reference... Figures 4A-4C The above describes the use of a reference. Figures 3A-3D The same SUC configuration. In at least one embodiment, one or more operations of the IC design flow 700 as described herein are omitted.

[0126] At operation 710, identify the block or sub-circuit of the analog circuit. For example, when the analog circuit is as follows: Figure 2A When using the ICO 200A, three blocks or sub-circuits are identified, including a current mirror, a DRO, and a decoupling capacitor. In some embodiments, the identification of sub-circuits of the analog circuit is, for example, input provided by a human designer to the APR tool.

[0127] At operation 712, layout planning is performed, focusing on at least one critical block of the analog circuit. In some embodiments, among the blocks or sub-circuits identified at operation 710, the critical block is the one whose speed has a greater impact on the overall speed of the analog circuit than other sub-circuits. For example, the critical block of the ICO is the DRO. With the DRO as the focus, a plan view of the ICO sub-circuit layout is developed. For example, as... Figure 4A , Figure 4C The image shown and about Figure 4A , Figure 4CAs described, the placement location for the DRO is arranged in the middle of the circuit area where the ICO is to be configured, while the placement locations for the current mirror and decoupling capacitor are arranged on the opposite side or around the placement location for the DRO.

[0128] At operation 714, a SUC configuration for implementing the ICO is selected. In one example, the current mirror is determined to include PMOS transistors with high drive strength, the DRO includes a balanced arrangement of PMOS and NMOS transistors in terms of quantity and drive strength, and the decoupling capacitor includes an NMOS transistor. Considering the requirement for high drive strength PMOS transistors in the current mirror, a SUC configuration with more P-type active regions is selected. For example, SUC configuration 381 or PPN is selected. In some embodiments, the selection of the SUC configuration for implementing the analog circuit is, for example, input provided by a human designer to the APR tool.

[0129] At operation 716, the maximum number of stacks in the analog circuit design is determined. For example, considering the drive strength requirements of the current mirror, DRO, and decoupling capacitor, the PMOS transistor of the current mirror requires a stack of 12 fingers, while the transistors of the DRO and decoupling capacitor require a stack of two or three fingers in each group. Therefore, the maximum number of stacks is 12.

[0130] At operation 718, the cell width W of each SUC is determined based on the maximum number of stacks (e.g., 12 fingers) determined in operation 716. In some embodiments, when the exact number of sub-circuits to be implemented (e.g., 1000 transistors MP1 in a current mirror) cannot be obtained with a single cell width, an additional SUC with the same SUC configuration (e.g., PPN) but a different cell width is used to match the exact number of sub-circuits to be implemented.

[0131] In some embodiments, based on the plan view generated in operation 712, multiple instances of a SUC having a SUC configuration selected in operation 714, the number of fingers and cell width of each active region determined accordingly in operations 716 and 718, and a predetermined cell height are placed.

[0132] At operation 720, the P-type and N-type active regions of each SUC are assigned to specific blocks in the circuit. For example, as... Figure 4A , Figure 4BAs shown, the P-type and N-type active regions of each SUC are allocated differently depending on whether the SUC is inside or outside the DRO block (e.g., block 440). Specifically, for each SUC inside the DRO block, one P-type active region is allocated to implement a current mirror, while another P-type active region and an adjacent N-type active region are allocated to implement the DRO inverter. For each SUC outside the DRO block, both P-type active regions are allocated to implement a current mirror, while the N-type active region is allocated to implement a decoupling capacitor.

[0133] At operation 722, the SUC is configured to complete the critical block first, i.e., before other less critical or non-critical blocks or sub-circuits of the analog circuit. For example, if the DRO is a critical block, the SUC for the DRO implementation is configured to complete the DRO first before the current mirror and decoupling capacitor. In at least one embodiment, wiring operations are performed to create transistors in the SUC within the DRO block that are electrically coupled to conductive components of the DRO. In at least one embodiment, a balanced common-center layout is obtained, as per [reference to...]. Figure 4B The sub-regions 435 and / or blocks 440 are described in the diagram. Therefore, in one or more embodiments, process variations that may affect one side of the layout can be balanced, and matching between transistors in at least the DRO block can be improved.

[0134] At operation 724, the remaining SUCs are configured to complete other blocks of the analog circuit. For example, wiring operations are performed to create conductive components that electrically couple the transistors of the SUCs outside the DRO block to current mirrors and decoupling capacitors. In some embodiments, a symmetrical layout pattern is used to perform operation 724.

[0135] At operation 726, devices or transistors not used in the active block of the analog circuit are configured as decoupling capacitors. In at least one embodiment, the active block of the analog circuit is a sub-circuit configured to perform signal processing. For example, the DRO and current mirror are active blocks of the ICO. In some embodiments, the decoupling capacitor is not considered an active block or sub-circuit. Transistors not used in the active block are electrically coupled as decoupling capacitors via conductive components, for example, generated during wiring operations. As a result of operation 726, transistors not specified for implementing the active block (e.g., current mirror and DRO) are configured as decoupling capacitors that are scattered with the transistors in the active block. This differs from other methods that place the decoupling capacitor in an empty area.

[0136] At operation 728, routing operations are completed to fulfill the required interconnections in the redistribution structure and obtain a layout containing analog circuitry. One or more of the advantages described herein can be achieved using IC devices corresponding to the layout obtained from IC design flow 700.

[0137] Figure 8AThis is a flowchart of method 800A according to some embodiments. In some embodiments, method 800A is executed at least in part by at least one processor, and / or includes information about Figure 1 , Figure 7 Describes at least a portion of one or more IC design flows.

[0138] At operation 820, multiple identical sub-circuit unit cells (SUCs) are placed within the analog circuit layout of the IC device. For example, as shown in reference... Figure 4A The SUC array 410 is generated by placing multiple instances of the same SUC adjacent to each other.

[0139] At operation 822, multiple metal unit cells are placed on top of corresponding SUCs among multiple SUCs. The multiple metal unit cells include a first metal unit cell and a second metal unit cell. The first metal unit cell includes a first set of conductive patterns corresponding to a first sub-circuit of the analog circuit, and the second metal unit cell includes a second set of conductive patterns different from the first set of conductive patterns and corresponding to a second sub-circuit of the analog circuit. (Reference) Figure 4B , Figure 5 An example of a first metallic unit cell, or BEOL cell, is described, where the BEOL cell 500 includes a first set of conductive patterns located above the lower SUC 300A, corresponding to the PMOS transistors of the current mirror and inverter. Reference Figure 4A , Figure 5 An example of a second metal unit cell is described, wherein the BEOL cell includes a second set of conductive patterns located above the lower SUC 300A, corresponding to the PMOS transistors of the current mirror and decoupling capacitor. In one or more embodiments, providing different BEOL cells for the same SUC makes it possible to implement different subcircuits using the same SUC, which improves the autonomous flow in the design process.

[0140] At operation 824, the obtained layout is stored on a non-transitory computer-readable recording medium. According to some embodiments, one or more of the advantages described herein can be achieved through the layout generated by method 800A and / or IC devices manufactured using such layout.

[0141] Figure 8B This is a flowchart of method 800B according to some embodiments. In some embodiments, method 800B is a manufacturing process performed using a manufacturing system discussed below, wherein at least one of the following is performed: (A) performing one or more photolithographic exposures, (B) fabricating one or more semiconductor masks, or (C) fabricating one or more components in an IC device layer. In some embodiments, IC devices are fabricated by method 800B based on one or more IC layouts generated by IC design flows 100, 700, method 800A, or as described herein.

[0142] At operation 840, for example, as referenced... Figure 6 The circuit region above the substrate is formed with a plurality of transistors. For example, active regions 651, 652 including source / drain electrodes and a channel therebetween are formed on substrate 650. In some embodiments, the active regions comprise one or more of a semiconductor material (e.g., silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), etc.), a dopant material (e.g., boron (B), phosphorus (P), arsenic (As), gallium (Ga), or another suitable material). In some embodiments, the active regions comprise nanosheet structures, such as one or more layers of one or more semiconductor materials in a continuous volume. In various embodiments, a single nanosheet layer comprises a single layer or multiple layers of a given semiconductor material. In at least one embodiment, the active regions are formed as part of a CFET structure.

[0143] Next, multiple gates are formed over and across the multiple active regions to configure multiple transistors. For example, gate 654 is formed to extend over and across the active regions 651, 652 to configure various transistors. In some embodiments, the gate is part of a gate structure and includes one or more conductive materials, such as polysilicon, copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), ruthenium (Ru), or one or more other metals or other suitable materials. The gate structure also includes a gate dielectric layer comprising one or more insulating materials, such as silicon dioxide, silicon nitride (Si3N4), and / or one or more other suitable materials, such as low-k materials with a k value less than 3.8, or high-k materials with a k value greater than 3.8, such as aluminum oxide (Al2O3), hafnium oxide (HfO2), tantalum pentoxide (Ta2O5), or titanium oxide (TiO2).

[0144] At operation 842, multiple conductive components are formed above multiple transistors to electrically couple the multiple transistors into an analog circuit. (Reference) Figure 6 Examples of conductive components are described, including various MD contact structures, VG vias, VD vias, conductive patterns in one or more metal layers M0, M1, etc., and vias in one or more via layers V0, V1, etc. The conductive components electrically couple underlying transistors into an analog circuit comprising multiple rows of decoupling capacitors and multiple rows of at least one sub-circuit excluding the decoupling capacitors, wherein the multiple rows of decoupling capacitors are physically interleaved with the multiple rows of at least one sub-circuit. For example, as shown in the reference... Figure 4AThe analog circuit (e.g., ICO) includes multiple rows 413, 414, 423, 424 of decoupling capacitors and multiple rows 411, 412, 415, 416, 421, 422, 425, 426 of different sub-circuits (e.g., current mirrors). The rows 413, 414, 423, 424 of the decoupling capacitors and the rows 411, 412, 415, 416, 421, 422, 425, 426 of the current mirrors are physically interleaved at least along the Y-axis, as shown below. Figure 4A The example configuration is shown. In some embodiments, on opposite sides of sub-region 435 (DRO block) on the X-axis, the N-type active region is configured with rows of additional decoupling capacitors, and the P-type active region is configured with rows of additional current mirrors, which are physically interleaved with the rows of additional decoupling capacitors along the Y-axis. In some embodiments, one or more of the advantages described herein can be achieved by an IC device manufactured according to method 800B.

[0145] In at least one embodiment, operation 840 includes forming additional transistors in a dummy region above the substrate, wherein the dummy region surrounds a circuit region containing analog circuitry. For example, as shown in reference... Figure 4C The pseudo-region 470 is formed around the circuit region 460, which includes analog circuitry. In some embodiments, operation 842 is performed such that the transistors in the circuit region 460 are electrically coupled into a sub-circuit, and then into an analog circuit, but the other transistors in the pseudo-region 470 are not electrically coupled into a circuit. In other words, the other transistors in the pseudo-region 470 are configured as pseudo-transistors.

[0146] The method includes example operations, but they do not necessarily need to be performed in the order shown. Operations may be appropriately added, substituted, rearranged, and / or eliminated according to the spirit and scope of embodiments of this disclosure. Embodiments combining different features and / or different embodiments are within the scope of this disclosure and will be apparent to those skilled in the art upon reading this disclosure.

[0147] Figure 9 This is a block diagram of an electronic design automation (EDA) system 900 according to some embodiments.

[0148] In some embodiments, EDA system 900 includes an APR system. According to one or more embodiments, the design layout method described herein represents wiring arrangements, which, for example, can be implemented using EDA system 900 according to some embodiments.

[0149] In some embodiments, the EDA system 900 is a general-purpose computing device including a hardware processor 902 and a non-transitory computer-readable recording medium 904. Among other things, the recording medium 904 is encoded with (i.e., stored) computer program code 906 (i.e., a set of executable instructions). Execution of the instructions 906 by the hardware processor 902 represents (at least partially) an EDA tool that implements some or all of the methods described herein (hereinafter referred to as the processes and / or methods) according to one or more embodiments.

[0150] Processor 902 is electrically coupled to computer-readable recording medium 904 via bus 908. Processor 902 is also electrically coupled to I / O interface 910 via bus 908. Network interface 912 is also electrically connected to processor 902 via bus 908. Network interface 912 is connected to network 914, enabling processor 902 and computer-readable recording medium 904 to be connected to external components via network 914. Processor 902 is configured to execute computer program code 906 encoded in computer-readable recording medium 904 to make system 900 available for performing part or all of the process and / or method. In one or more embodiments, processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0151] In one or more embodiments, the computer-readable recording medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable recording medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable recording medium 904 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video optical disc (DVD).

[0152] In one or more embodiments, recording medium 904 stores computer program code 906 configured to enable system 900 (where such execution representation (at least partially) EDA tools) to perform some or all of the said processes and / or methods. In one or more embodiments, recording medium 904 also stores information that facilitates the execution of some or all of the said processes and / or methods. In one or more embodiments, recording medium 904 stores a unit library 907 comprising the units disclosed herein.

[0153] EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuitry. In one or more embodiments, the I / O interface 910 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processor 902.

[0154] EDA system 900 also includes a network interface 912 coupled to processor 902. Network interface 912 allows system 900 to communicate with a network 914 to which one or more other computer systems are connected. Network interface 912 includes a wireless network interface, such as Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 900.

[0155] System 900 is configured to receive information via I / O interface 910. The information received via I / O interface 910 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 902. This information is transmitted to processor 902 via bus 908. EDA system 900 is configured to receive UI-related information via I / O interface 910. This information is stored as a user interface (UI) 942 in computer-readable recording medium 904.

[0156] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 900. In some embodiments, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout generation tool.

[0157] In some embodiments, these processes are implemented as the functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0158] Figure 10 This is a block diagram of an integrated circuit (IC) manufacturing system 1000 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1000 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a semiconductor integrated circuit layer.

[0159] exist Figure 10 In this IC manufacturing system 1000, entities such as design room 1020, mask room 1030, and IC manufacturing plant / manufacturer (“Fab”) 1050 interact with each other in the design, development, and manufacturing cycle and / or services related to the manufacture of IC device 1060. The entities in system 1000 are connected via a communication network. In some embodiments, the communication network is a single network. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1020, mask room 1030, and IC manufacturing plant 1050 are owned by a single, larger company. In some embodiments, two or more of the design room 1020, mask room 1030, and IC manufacturing plant 1050 coexist in a shared facility and use shared resources.

[0160] Design studio (or design team) 1020 generates IC design layout 1022. IC design layout 1022 includes various geometric patterns designed for IC device 1060. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of the IC device 1060 to be manufactured. These layers combine to form various IC features. For example, a portion of IC design layout 1022 includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads, which will be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1020 implements appropriate design procedures to form IC design layout 1022. The design process includes one or more of logic design, physical design, or placement and routing operations. IC design layout 1022 is presented in the form of one or more data files containing geometric pattern information. For example, IC design layout 1022 can be represented in GDSII or DFII file format.

[0161] Mask chamber 1030 includes data preparation 1032 and mask fabrication 1044. Mask chamber 1030 uses an IC design layout 1022 to fabricate one or more masks 1045 for fabricating various layers of an IC device 1060 according to the IC design layout 1022. Mask chamber 1030 performs mask data preparation 1032, in which the IC design layout 1022 is converted into a representative data file (“RDF”). Mask data preparation 1032 provides the RDF to mask fabrication 1044. Mask fabrication 1044 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (marker) 1045 or a semiconductor wafer 1053. The design layout 1022 is manipulated by mask data preparation 1032 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fabrication plant 1050. Figure 10 In this embodiment, mask data preparation 1032 and mask manufacturing 1044 are shown as separate elements. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0162] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other process effects. OPC adjusts the IC design layout (Figure 1022). In some embodiments, mask data preparation 1032 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, treating OPC as an inverse imaging problem.

[0163] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1022, which has already been processed in the OPC. This set of mask generation rules includes certain geometric and / or connectivity constraints to ensure sufficient margin to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1022 to compensate for constraints during mask fabrication 1044, which may undo some modifications performed by the OPC to satisfy the mask creation rules.

[0164] In some embodiments, mask data preparation 1032 includes a lithography process check (LPC), which simulates a process performed by an IC fabrication plant 1050 to manufacture an IC device 1060. The LPC simulates this process based on an IC design layout 1022 to create a simulated manufactured device, such as IC device 1060. Process parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the LPC has created a simulated manufactured device, if the shape of the simulated device is not close enough to meet design rules, the OPC and / or MRC are repeated to further refine the IC design layout 1022.

[0165] It should be understood that, for clarity, the above description of mask data preparation 1032 has been simplified. In some embodiments, data preparation 1032 includes additional features, such as modifying the logic operations (LOPs) of the IC design layout 1022 according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1022 during data preparation 1032 can be performed in various different sequences.

[0166] After mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or a set of masks 1045 is fabricated based on a modified IC design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more photolithographic exposures based on the IC design layout 1022. In some embodiments, a pattern is formed on the mask (photomask or mask plate) 1045 using a mechanism of electron beam (e-beam) or multiple electron beams based on the modified IC design layout 1022. The mask 1045 can be formed using various techniques. In some embodiments, a binary technique is used to form the mask 1045. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of the mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, a phase-shifting technique is used to form mask 1045. In the phase-shifting mask (PSM) version of mask 1045, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1044 is used in various processes. For example, this mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1053, in etching processes to form various etched regions in semiconductor wafer 1053, and / or in other suitable processes.

[0167] IC manufacturing plant 1050 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC manufacturing plant 1050 is a semiconductor foundry. For example, there may be one manufacturing facility for front-end manufacturing (front-end process (FEOL) manufacturing) of multiple IC products, a second manufacturing facility for providing back-end manufacturing (back-end process (BEOL) manufacturing) for the interconnection and packaging of IC products, and a third manufacturing facility for providing other services for foundry operations.

[0168] IC manufacturing plant 1050 includes manufacturing tools 1052 configured to perform various manufacturing operations on semiconductor wafers 1053 to manufacture IC devices 1060 according to a mask (e.g., mask 1045). In various embodiments, manufacturing tools 1052 include one or more of the following: wafer stepper, ion implanter, photoresist coater, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes described herein.

[0169] IC fabrication plant 1050 uses a mask 1045, fabricated by mask chamber 1030, to fabricate IC device 1060. Therefore, IC fabrication plant 1050 uses IC design layout 1022 at least indirectly to fabricate IC device 1060. In some embodiments, semiconductor wafer 1053 is fabricated by IC fabrication plant 1050 using mask 1045 to form IC device 1060. In some embodiments, IC fabrication includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1022. Semiconductor wafer 1053 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1053 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0170] In some embodiments, the integrated circuit (IC) device includes an array of sub-circuit unit cells (SUCs) having identical SUC configurations. The SUC configuration includes a first number of P-type active regions and a second number of N-type active regions, the first number differing from the second number. The array of SUCs includes a first SUC and a second SUC, the first SUC configuring a first sub-circuit of an analog circuit, and the second SUC configuring a second sub-circuit of an analog circuit, the second sub-circuit differing from the first sub-circuit.

[0171] In some embodiments, the array of SUCs further includes a third SUC, which configures a third sub-circuit of the analog circuit, the third sub-circuit being different from the second and first sub-circuits.

[0172] In some embodiments, at least one of the first sub-circuit, the second sub-circuit, or the third sub-circuit is selected from the group consisting of: P-type transistors, N-type transistors, P-type decoupling capacitors, N-type decoupling capacitors, inverters, current mirrors, buffers, differential pairs, cascode structures, switches, and ring oscillators.

[0173] In some embodiments, the analog circuit is selected from the group consisting of: current-controlled oscillators, voltage-controlled oscillators, operational transconductance amplifiers, sense amplifier comparators, transconductance amplifiers, transimpedance amplifiers, digital-to-analog converters (DACs), and bandgap reference circuits.

[0174] In some embodiments, in a SUC configuration, a first number of P-type active regions and a second number of N-type active regions are arranged consecutively.

[0175] In some embodiments, the SUC is configured as follows: a first SUC configuration including a first P-type active region, a second P-type active region, and an N-type active region arranged in succession; or a second SUC configuration including a first N-type active region, a second N-type active region, and a P-type active region arranged in succession.

[0176] In some embodiments, the IC device further includes a pseudo-region surrounding the array of the SUC, the pseudo-region including pseudo-transistors.

[0177] In some embodiments, the IC device further includes: a pseudo-region surrounding an array of SUCs, wherein the SUCs included in the pseudo-region have the same SUC configuration as the SUCs in the array of SUCs, and the SUCs in the pseudo-region include pseudo transistors.

[0178] In some embodiments, the IC device further includes a metal layer located on the array of the SUC, wherein the metal layer includes: a first conductive pattern group corresponding to a first sub-circuit, a second conductive pattern group corresponding to a second sub-circuit, and satisfies at least one of the following: the width of each first conductive pattern in the first conductive pattern group is different from the width of each second conductive pattern in the second conductive pattern group; the number of first conductive patterns in the first conductive pattern group is different from the number of second conductive patterns in the second conductive pattern group; or the pitch between adjacent first conductive patterns in the first conductive pattern group is different from the pitch between adjacent second conductive patterns in the second conductive pattern group.

[0179] In some embodiments, the IC device further includes: an array of metal unit cells, each metal unit cell including a first conductive pattern group and a second conductive pattern group, wherein each metal unit cell in the array of metal unit cells is located above a corresponding SUC in the array of SUCs.

[0180] In some embodiments, the integrated circuit (IC) device includes: a circuit region comprising different sub-circuits of an analog circuit; and a pseudo-region surrounding the circuit region, the pseudo-region comprising pseudo-transistors. The circuit region does not have pseudo-transistors that separate a sub-circuit of the analog circuit from other sub-circuits of the analog circuit.

[0181] In some embodiments, the circuit region does not have pseudo transistors of sub-circuits within sub-circuits surrounding the analog circuit.

[0182] In some embodiments, at least one sub-circuit is selected from the group consisting of: P-type transistors, N-type transistors, P-type decoupling capacitors, N-type decoupling capacitors, inverters, current mirrors, buffers, differential pairs, cascode structures, switches, and differential ring oscillators (DROs).

[0183] In some embodiments, the analog circuit is selected from the group consisting of: current-controlled oscillators, voltage-controlled oscillators, operational transconductance amplifiers, sense amplifier comparators, transconductance amplifiers, transimpedance amplifiers, digital-to-analog converters (DACs), and bandgap reference circuits.

[0184] In some embodiments, in the circuit region, transistors in any sub-circuit of a sub-circuit not configured as analog circuits are configured as decoupling capacitors.

[0185] In some embodiments, the circuit region includes an array of SUCs having the same SUC configuration, and different sub-circuits of the analog circuit are configured by the SUCs having the same SUC configuration.

[0186] In some embodiments, the SUC in the array of SUCs includes: one or more first transistors, at least one sub-circuit of the sub-circuit configured with analog circuitry, and one or more second transistors, any sub-circuit of the sub-circuit not configured with analog circuitry, wherein the one or more second transistors are configured as one or more decoupling capacitors.

[0187] In some embodiments, a method of manufacturing an integrated circuit device includes: forming a plurality of transistors in a circuit region above a substrate; and forming a plurality of conductive components above the plurality of transistors. The plurality of conductive components electrically couple the plurality of transistors into an analog circuit, the analog circuit including multiple rows of decoupling capacitors and multiple rows of at least one sub-circuit excluding the decoupling capacitors, and the multiple rows of decoupling capacitors and the multiple rows of at least one sub-circuit are physically interleaved.

[0188] In some embodiments, the method further includes: forming a plurality of additional transistors in a pseudo-region above a substrate, wherein the pseudo-region surrounds a circuit region, and performing the step of forming a plurality of conductive components to configure the plurality of additional transistors as pseudo-transistors without electrically coupling the plurality of additional transistors in the pseudo-region into a circuit.

[0189] In some embodiments, in the circuit region, the plurality of transistors includes: a first number of rows of P-type transistors and a second number of rows of N-type transistors, the second number being different from the first number.

[0190] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to them within this disclosure without departing from its spirit and scope.

Claims

1. An integrated circuit device, comprising: An array of sub-circuit unit cells (SUCs), wherein the SUCs have identical SUC configurations, The SUC configuration includes a first number of P-type active regions and a second number of N-type active regions, wherein the first number differs from the second number. The array of SUCs includes a first SUC and a second SUC. The first SUC is configured with a first sub-circuit of the analog circuit, and the second SUC is configured with a second sub-circuit of the analog circuit, which is different from the first sub-circuit.

2. The integrated circuit device according to claim 1, wherein, The array of SUCs also includes a third SUC, which configures a third sub-circuit of the analog circuit, and the third sub-circuit is different from the second sub-circuit and the first sub-circuit.

3. The integrated circuit device according to claim 1, wherein, In the SUC configuration, the first number of P-type active regions and the second number of N-type active regions are arranged consecutively.

4. The integrated circuit device according to claim 1, wherein, The SUC is configured as follows: The first SUC configuration includes a continuously arranged first P-type active region, a second P-type active region, and an N-type active region, or The second SUC configuration includes a first N-type active region, a second N-type active region, and a P-type active region arranged in succession.

5. The integrated circuit device according to claim 1, further comprising: A pseudo-region surrounding the array of the SUC, the pseudo-region comprising pseudo-transistors.

6. The integrated circuit device according to claim 1, further comprising: The pseudo-region surrounding the array of the SUC, wherein The pseudo-region includes SUCs with the same SUC configuration as the SUCs in the array of SUCs, and The SUC in the pseudo-region includes a pseudo transistor.

7. The integrated circuit device of claim 1, further comprising a metal layer located above the array of the SUC, wherein, The metal layer includes: The first conductive pattern group corresponds to the first sub-circuit. The second conductive pattern group corresponds to the second sub-circuit, and Satisfy at least one of the following: The width of each first conductive pattern in the first conductive pattern group is different from the width of each second conductive pattern in the second conductive pattern group. The number of first conductive patterns in the first conductive pattern group is different from the number of second conductive patterns in the second conductive pattern group, or The pitch between adjacent first conductive patterns in the first conductive pattern group is different from the pitch between adjacent second conductive patterns in the second conductive pattern group.

8. The integrated circuit device according to claim 7, further comprising: An array of metal unit cells, each metal unit cell comprising the first conductive pattern group and the second conductive pattern group, wherein... Each metal unit in the array of metal unit cells is located above the corresponding SUC in the array of SUCs.

9. An integrated circuit device, comprising: The circuit region includes different sub-circuits of the analog circuit; as well as A pseudo-region, surrounding the circuit region, the pseudo-region including pseudo-transistors, wherein, The circuit region does not have a pseudo transistor that separates a sub-circuit of the analog circuit from other sub-circuits of the analog circuit.

10. A method for manufacturing an integrated circuit device, comprising: Multiple transistors are formed in the circuit region above the substrate; as well as A plurality of conductive components are formed above the plurality of transistors, wherein, The plurality of conductive components electrically couple the plurality of transistors into an analog circuit. The analog circuit includes multiple rows of decoupling capacitors and multiple rows of at least one sub-circuit other than the decoupling capacitors, and the multiple rows of decoupling capacitors are physically interleaved with the multiple rows of at least one sub-circuit.

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