A design evolution graph construction method and device for back-oriented layout optimization

Abstract

This invention discloses a method and apparatus for constructing a design evolution graph for back-layout optimization. The method collects netlist and layout data from multiple physical design stages, including placement, placement optimization, clock tree synthesis, and routing. It establishes pin correspondences between different stages and writes evolution information such as timing status, spatial coordinates, power consumption changes, and optimization operation records for each pin. Based on this, it extracts the circuit timing diagram, retains the timing dependencies between pins, and adds physical proximity edges between spatially adjacent cells. Subsequently, it divides the graph structure into blocks according to logic cones, generating a design evolution graph while preserving local physical adjacency information. This method can uniformly represent the evolution information, timing relationships, and physical relationships of the circuit across multiple physical design stages, solving the problem of difficulty in characterizing cross-stage correlations in back-layout optimization, and providing a circuit representation foundation for improving the prediction accuracy and model transferability of optimization results.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design automation technology, specifically relating to a method and device for constructing a design evolution diagram for back-layout optimization. Background Technology

[0002] In the physical design phase of integrated circuits, designers need to implement Engineering Change Orders (ECOs) on chips that have completed Place and Route (P&R) to correct timing violations and meet design approval requirements. As parasitic effects, routing congestion, and coupling effects gradually increase with advanced process nodes, pins with sufficient timing margins during the placement phase may be affected by buffer insertions and density changes during Clock Tree Synthesis (CTS), leading to timing violations during the routing phase. Commercial EDA tools typically employ a Physically Aware ECO process, repeatedly calling placement and routing tools to perform optimizations, resulting in significant overhead.

[0003] In recent years, research on ECO optimization has increasingly incorporated machine learning (ML) methods. Existing methods typically use different types of encoders to convert circuit netlists, timing diagrams, or layout information into learnable vector representations, which are then used for performance prediction, reinforcement learning (RL), or gradient optimization. These methods can reduce some optimization iterations and model nonlinear physical effects. However, existing methods often use data from a single design stage as input, making it difficult to track continuous changes between placement, place optimization, CTS, and routing stages, and also difficult to describe the impact of operations such as gate size adjustments and threshold voltage replacements on subsequent stages.

[0004] Large Language Models (LLMs) possess strong text-based reasoning capabilities, but circuit implementations have explicit topological dependencies and spatial constraints, making it difficult to obtain physically meaningful circuit representations directly using language models. Existing circuit representation learning methods also lack a graph structure that can uniformly record cross-stage evolutionary information, temporal relationships, physical proximity relationships, and layout features, limiting the model's prediction accuracy and transfer performance on unseen circuits. Summary of the Invention

[0005] Purpose of the invention: In order to overcome the problems of difficulty in depicting cross-design stage relationships and difficulty in uniformly recording circuit structure and physical information in the prior art, the present invention provides a method and device for constructing a Design Evolution Graph (DEG) for backward layout optimization.

[0006] Technical solution: The present invention provides a method for constructing a design evolution diagram for backward layout optimization, comprising the following steps:

[0007] S1 extracts the circuit netlist, timing analysis results and layout information from the layout, layout optimization, clock tree synthesis and routing stages, and constructs a cross-stage pin node set according to the design stage.

[0008] S2, establish cross-stage pin correspondence based on pin names, associated units, and local connection relationships in different stages, and generate a set of text attributes to describe the design evolution history;

[0009] S3. Extract the timing diagram with pins as nodes from the post-routing design, delete constraint-related edges and duplicate edges, retain the effective timing dependencies between pins, and obtain the timing edge set.

[0010] S4. Determine the spatial proximity relationship based on the cell position and pin position in the layout, establish physical proximity edges between the output pins of spatially adjacent cells, and obtain a set of physical proximity edges.

[0011] S5, based on the set of temporal edges and the set of physical proximity edges, divides large-scale circuits into blocks according to logic cones, and retains one-hop physical proximity edges connected to subgraph nodes during the block division process;

[0012] S6, using the divided logical cone diagram as the unit, uniformly number and combine the pin node set, text attribute set, timing edge set, and physical proximity edge set, and output the design evolution diagram; the design evolution diagram is used to characterize the timing relationship, physical proximity relationship, and cross-stage evolution relationship in the post-layout optimization.

[0013] Furthermore, the circuit netlist in step S1 is used to provide pin names, the cell to which the pin belongs, and network connection relationships; the timing analysis results are used to provide the setup time margin, hold time margin, and their changes in adjacent stages for each pin; the layout information in step S1 is used to provide cell type, cell power consumption, physical coordinates of pins or cells, and their changes in adjacent stages.

[0014] Furthermore, the specific implementation process of step S2 is as follows;

[0015] S21: For pins whose names and associated units remain consistent in adjacent stages, establish a direct correspondence;

[0016] S22: For pins that cannot be directly matched, first use Weisfeiler-Lehman graph hashing to describe the local connection structure of the pin, then use the MinHash method to calculate the local subgraph similarity between the current stage pin and the candidate pin in the previous stage, and determine the parent pin and matching confidence based on the similarity.

[0017] S23: For a pin added in the current stage that cannot be found in the previous stage, set its parent pin field to empty;

[0018] S24: Generate text attributes for each pin, ultimately generating a set of text attributes to describe the design evolution history.

[0019] Furthermore, the implementation process of S22 is as follows:

[0020] The pin name, its cell type, and pin direction are used as the initial labels for the pins. Through multiple iterations, the label information of the node itself and its neighbors is aggregated to generate labels reflecting the local connectivity structure. The formula is as follows:

[0021]

[0022] in, Pin node In the The labels obtained after rounds of iteration, For pins In the timing diagram, the set of fan-in and fan-out neighboring pins. For all neighboring pins in the first Multiple sets of labels formed after rounds of iteration. A hash function that maps its own label to neighboring labels as new fixed-length labels;

[0023] After completing the above iterations, all tags generated by each pin during the iterations are merged into a tag set. For the tag sets of the pin to be matched in the current stage and the candidate pins in the previous stage, the same set of hash functions is used to calculate the hash value of each tag element in their respective tag sets. For each hash function, the minimum value is selected from all the hash values ​​of the tags in the respective tag set and retained. The minimum hash values ​​retained by all hash functions are combined in order to form the MinHash signature of each tag set. The proportion of corresponding positions with the same hash value in the two MinHash signatures is counted, and this proportion is used as the similarity of the local subgraph structure of the two pins. The pin with the highest similarity to the current pin in the previous stage is selected as the parent pin, and this similarity is used as the matching confidence.

[0024] Furthermore, the text attributes include stage identifier, pin name, setup time margin, hold time margin, power consumption, cell type, physical coordinates, parent pin, parent cell type, optimization action, and matching confidence.

[0025] Furthermore, the specific implementation process of step S3 is as follows:

[0026] Read the static timing analysis results and netlist connection relationships after routing, and convert the cell timing arcs, network timing arcs and propagation arcs into directed edges between pins; delete the constraint edges marked as pseudo paths or non-data propagation paths in the static timing analysis results; merge the edges that appear repeatedly between the same source pin and the same destination pin into one edge to obtain the timing edge set.

[0027] Furthermore, step S4 is implemented as follows:

[0028] Based on the cell coordinates, pin coordinates, and cell bounding boxes in the layout after routing, all cells with mutually contacting bounding boxes are selected. For each group of such cells, the corresponding output pin is selected as a representative node, and physical proximity edges are established between the output pins. The physical proximity edges are used to characterize the potential physical coupling effects caused by spatial proximity in the layout, including local congestion, density changes, crosstalk, and wire-wound coupling effects.

[0029] Furthermore, the implementation process of step S5 is as follows:

[0030] Using the endpoint to be predicted and the endpoint of the violation path as the root node, the system expands along the temporal edges in the fan-in and fan-out directions to form a logical cone graph that includes the local temporal context. The temporal edges inside the subgraph are preserved. For the case where a node inside the subgraph is connected to a one-hop adjacent node outside the subgraph through a physical proximity edge, the one-hop adjacent node and the corresponding physical proximity edge are preserved, thus controlling the size of the subgraph while preserving the local physical coupling relationship.

[0031] Further, the design evolution diagram described in step S6 is represented as follows: ,in For a set of pin nodes, This is a set of text attributes corresponding to each pin. For a time-series edge set, It is the set of physically nearest edges.

[0032] An electronic device according to the present invention includes a memory and a processor, wherein:

[0033] Memory is used to store computer programs that can run on a processor;

[0034] A processor, used to perform the steps of the back-layout optimization design evolution graph construction method as described above when running the computer program.

[0035] Beneficial Effects: Compared with the prior art, the beneficial effects of this invention are as follows: 1. This invention writes the evolution information of the placement, placement optimization, clock tree synthesis, and routing stages into pin-level text attributes, which can track changes in timing margin, power consumption, location, cell type, and optimization operations, and improve the ability to express cross-stage correlations; 2. This invention introduces physical proximity edges in the timing diagram, so that the graph structure simultaneously retains circuit topology and layout space relationships, adapting to physical constraints in post-placement optimization; 3. This invention uses logic cone partitioning and retains one-hop physical proximity connections, which facilitates the construction of design evolution graphs in large-scale circuits; the resulting DEG can be used as input for circuit representation learning models such as DiffDEG, and supports multiple types of post-placement optimization tasks. Attached Figure Description

[0036] Figure 1 This is a flowchart of the design evolution diagram construction method for back-layout optimization proposed in this invention. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings.

[0038] like Figure 1 As shown, this invention provides a method for constructing a design evolution graph (DEG) for back-to-back layout optimization. This method addresses the problem in back-to-back layout optimization where timing violations accumulate gradually over multiple physical design stages. It expands the traditional timing graph, which only describes the timing propagation relationships between pins, into a DEG. The DEG uses pins as nodes and simultaneously records the cross-stage state changes, timing dependencies, and spatial proximity relationships of pins, thus providing a unified input for subsequent timing change prediction, optimization strategy prediction, and back-to-back layout optimization. The specific implementation process is as follows:

[0039] Step S1: Extract the circuit netlist, timing analysis results and layout information from the layout, layout optimization, clock tree synthesis and routing stages, and construct a cross-stage pin node set.

[0040] Using pins as the recording objects, the circuit netlist is used to obtain pin names, their associated cells, and network connections; timing analysis results are used to obtain the setup time margin, hold time margin, and changes in adjacent stages during placement, placement optimization, clock tree synthesis, and routing for each pin; layout information is used to obtain cell type, cell power consumption, physical coordinates of pins or cells, and coordinate changes in adjacent stages. The circuit netlist, timing analysis results, and layout information are organized in the order of placement stage, placement optimization stage, clock tree synthesis stage, and routing stage to obtain a set of pin nodes, which is used to subsequently establish the correspondence between pins in different stages and generate a set of text attributes.

[0041] Step S2: Establish cross-stage pin correspondence based on pin names, associated units, and local connection relationships in different stages, and generate a set of text attributes to describe the design evolution history.

[0042] For pins whose names and associated units remain consistent across adjacent stages, a direct correspondence is established.

[0043] For pins whose names or local adjacency relationships change between adjacent stages, a graph structure similarity method is used to determine the cross-stage correspondence: First, the Weisfeiler-Lehman graph hash is used to describe the pin's local connectivity structure. The pin name, its cell type, and its orientation are used as the initial labels for the pin. Through multiple iterations, the label information of the node itself and its neighbors is aggregated to generate labels reflecting the local connectivity structure. The formula is as follows:

[0044]

[0045] in, Pin node In the The labels obtained after rounds of iteration, For pins In the timing diagram, the set of fan-in and fan-out neighboring pins. For all neighboring pins in the first Multiple sets of labels formed after rounds of iteration. A hash function is used to map the pin's own label to its neighboring labels as new fixed-length labels. After the above iterations, all labels generated by each pin during the iterations are merged into a label set, which comprehensively reflects the local connectivity structure information of the pin within its neighborhood. For the label sets of the pin to be matched in the current stage and the candidate pins in the previous stage, the same set of hash functions is used to calculate the hash value of each label element in each set. For each hash function, the minimum hash value is selected from all the hash values ​​of the labels in the set and retained. The minimum hash values ​​retained by all hash functions are combined in order to form the MinHash signature of the set. Subsequently, the proportion of corresponding positions with the same hash value in the two MinHash signatures is counted, and this proportion is used as the similarity of the local subgraph structures of the two pins. Finally, the pin with the highest similarity to the current pin in the previous stage is selected as its parent pin, and this similarity value is used as the matching confidence.

[0046] For pins added in the current stage that cannot be found in the previous stage, set their parent pin field to empty.

[0047] Generate text attributes for each pin, including stage identifier, pin name, setup time margin, hold time margin, power consumption, cell type, physical coordinates, parent pin, parent cell type, optimization action, and matching confidence.

[0048] Step S3: Extract timing diagrams with pins as nodes from the post-routing design to obtain a timing edge set.

[0049] Read the static timing analysis results and netlist connections after routing, and convert the cell timing arcs, network timing arcs, and propagation arcs into directed edges between pins, with the edge direction consistent with the signal propagation direction. For constraint edges marked as pseudo-paths or non-data propagation paths in the static timing analysis results, delete them; for edges that appear repeatedly between the same source pin and the same destination pin, merge them into one edge, thus obtaining the timing edge set.

[0050] Step S4: Based on the temporal topology obtained in step S3, inject physical neighbor edges according to the spatial proximity relationship of the layout to obtain a set of physical neighbor edges.

[0051] Based on the cell coordinates, pin coordinates, and cell bounding boxes in the layout after routing, cells with a minimum physical distance of zero between their bounding box edges are selected. For each group of such cells, all their output pins are selected as representative nodes of physical influence, and physical proximity edges are established between the corresponding output pins. These physical proximity edges are used to characterize the potential physical coupling effects caused by spatial proximity in the layout, including local congestion, density variations, crosstalk, and wire-wound coupling effects.

[0052] Step S5: Based on the time-series edge set obtained in step S3 and the physical proximity edge set obtained in step S4, the large-scale circuit is divided into blocks according to the logic cone.

[0053] Using the endpoint to be predicted and the endpoint of the violation path as the root node, the system expands along the temporal edges obtained in step S3 in both the fan-in and fan-out directions to form a logical cone graph containing local temporal contexts. For cases where a node within the subgraph is connected to a one-hop adjacent node outside the subgraph via the physical proximity edge obtained in step S4, the one-hop adjacent node and its corresponding physical proximity edge are retained, thereby preserving local physical coupling relationships while controlling the size of the subgraph.

[0054] Step S6: Using the logic cone diagram divided in step S5 as the unit, the pin node set obtained in step S1, the text attribute set obtained in step S2, the timing edge set obtained in step S3, and the physical proximity edge set obtained in step S4 are uniformly numbered and combined to output the design evolution diagram DEG.

[0055] The design evolution diagram can be represented as follows: ,in For a set of pin nodes, This is a set of text attributes corresponding to each pin. For a time-series edge set, This represents the set of physically adjacent edges. Through this representation, the design evolution graph retains the signal propagation relationships found in traditional timing diagrams while also supplementing pin evolution information across stages and spatial proximity information within the layout.

[0056] To verify the effectiveness of the Design Evolution Graph (DEG) constructed in this invention, after the DEG is constructed, a subsequent representation learning verification framework, DiffDEG, can be built based on the DEG. DiffDEG takes the constructed DEG as input and is used to verify the DEG's support effect on the post-layout optimization task in subsequent experiments.

[0057] In the DiffDEG verification framework, a text encoding model can be used to verify the text attribute t of each pin in the DEG. i Encode the text to obtain the text representation Z. LLM =ReasonLLM(t i Then, the graph structure augmentation network is used to enhance the node representation based on the temporal edges and physical proximity edges in the DEG, resulting in the structure augmentation representation Z. Diff The text is then represented as Z. LLM Structural enhancement representation Z Diff Circuit-level features, timing edges, and physical proximity edges are input into the fusion model DEGFormer to obtain a unified representation Z. DEG The unified representation of Z DEG It can be connected to different output modules for time series change prediction, optimization policy prediction, reinforcement learning optimization, or gradient optimization.

[0058] This embodiment presents simulation experiments on the DiffDEG framework based on the DEG designed in this invention. The experiments utilize publicly available circuit designs from IWLS, OpenCores, and Chipyard, comprising a total of 19 designs. All RTL designs were synthesized and placed / routed using commercial 12nm process libraries, and design quality was evaluated using static timing analysis tools. ReasonLLM was initialized based on LLM2Vec and Llama-3.1-8B, with an output dimension of 768; DiffGUNet was trained for 64 epochs with a diffusion step count of 520; and DEGFormer was pre-trained for 50 epochs.

[0059] Experimental results show that the present invention achieves an average coefficient of determination (R²) of 0.94 and a mean absolute error (MAE) of 7.22 ps on eight unseen designs, demonstrating its ability to accurately predict time-series changes after layout optimization. In the optimization strategy prediction task, the average F1 score of the present invention reaches 0.904. Five unseen designs were selected for comparison with methods proposed by ICCAD22, TODAES23, and ISPD25; the results are shown in Table 1.

[0060] Table 1 Comparison of prediction results for optimization strategies (F1 score)

[0061]

[0062] In reinforcement learning optimization tasks, this invention achieved convergence speed improvements of 1.75x and 2.78x in two test designs, respectively. By combining the prediction strategy with gradient optimization, compared to commercial physical-aware ECO tools, the average total negative time margin was improved by 12.5%, and the overall running speed was improved by approximately 4x.

[0063] The experimental results above show that DiffDEG, which uses the evolution diagram of this invention as input, can utilize cross-stage textual attributes, directional diffusion enhancement, and physical knowledge fusion to form a unified circuit representation with high accuracy and transferability, and provide representation support for post-layout optimization tasks.

[0064] The present invention also proposes an electronic device, including a memory and a processor, wherein: the memory is used to store a computer program that can run on the processor; the processor is used to execute, when running the computer program, the steps of the design evolution graph construction method for back-layout optimization as described above.

[0065] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A method for constructing a design evolution diagram for backward layout optimization, characterized in that, Includes the following steps: S1 extracts the circuit netlist, timing analysis results and layout information from the layout, layout optimization, clock tree synthesis and routing stages, and constructs a cross-stage pin node set according to the design stage. S2, establish cross-stage pin correspondence based on pin names, associated units, and local connection relationships in different stages, and generate a set of text attributes to describe the design evolution history; S3. Extract the timing diagram with pins as nodes from the post-routing design, delete constraint-related edges and duplicate edges, retain the effective timing dependencies between pins, and obtain the timing edge set. S4. Determine the spatial proximity relationship based on the cell position and pin position in the layout, establish physical proximity edges between the output pins of spatially adjacent cells, and obtain a set of physical proximity edges. S5, based on the set of temporal edges and the set of physical proximity edges, divides large-scale circuits into blocks according to logic cones, and retains one-hop physical proximity edges connected to subgraph nodes during the block division process; S6, using the divided logical cone diagram as the unit, uniformly number and combine the pin node set, text attribute set, timing edge set, and physical proximity edge set, and output the design evolution diagram; the design evolution diagram is used to characterize the timing relationship, physical proximity relationship, and cross-stage evolution relationship in the post-layout optimization.

2. The method for constructing a design evolution diagram for backward layout optimization according to claim 1, characterized in that, The circuit netlist in step S1 is used to provide pin names, the cell to which the pin belongs, and network connection relationships; the timing analysis results are used to provide the setup time margin, hold time margin, and their changes in adjacent stages for each pin; the layout information in step S1 is used to provide cell type, cell power consumption, physical coordinates of pins or cells, and their changes in adjacent stages.

3. The method for constructing a design evolution diagram for backward layout optimization according to claim 1, characterized in that, The specific implementation process of step S2 is as follows; S21: For pins whose names and associated units remain consistent in adjacent stages, establish a direct correspondence; S22: For pins that cannot be directly matched, first use Weisfeiler-Lehman graph hashing to describe the local connection structure of the pin, then use the MinHash method to calculate the local subgraph similarity between the current stage pin and the candidate pin in the previous stage, and determine the parent pin and matching confidence based on the similarity. S23: For a pin added in the current stage that cannot be found in the previous stage, set its parent pin field to empty; S24: Generate text attributes for each pin, ultimately generating a set of text attributes to describe the design evolution history.

4. The method for constructing a design evolution diagram for backward layout optimization according to claim 3, characterized in that, The implementation process of S22 is as follows: The pin name, its cell type, and pin direction are used as the initial labels for the pins. Through multiple iterations, the label information of the node itself and its neighbors is aggregated to generate labels reflecting the local connectivity structure. The formula is as follows: in, Pin node In the The labels obtained after rounds of iteration, For pins In the timing diagram, the set of fan-in and fan-out neighboring pins. For all neighboring pins in the first Multiple sets of labels formed after rounds of iteration. A hash function that maps its own label to neighboring labels as new fixed-length labels; After completing the above iterations, all tags generated by each pin during the iterations are merged into a tag set. For the tag sets of the pin to be matched in the current stage and the candidate pins in the previous stage, the same set of hash functions is used to calculate the hash value of each tag element in their respective tag sets. For each hash function, the minimum value is selected from all the hash values ​​of the tags in the respective tag set and retained. The minimum hash values ​​retained by all hash functions are combined in order to form the MinHash signature of each tag set. The proportion of corresponding positions with the same hash value in the two MinHash signatures is counted, and this proportion is used as the similarity of the local subgraph structure of the two pins. The pin with the highest similarity to the current pin in the previous stage is selected as the parent pin, and this similarity is used as the matching confidence.

5. The method for constructing a design evolution diagram for backward layout optimization according to claim 3, characterized in that, The text attributes include stage identifier, pin name, setup time margin, hold time margin, power consumption, cell type, physical coordinates, parent pin, parent cell type, optimization action, and matching confidence.

6. The method for constructing a design evolution diagram for backward layout optimization according to claim 1, characterized in that, The specific implementation process of step S3 is as follows: Read the static timing analysis results and netlist connection relationships after routing, and convert the cell timing arcs, network timing arcs and propagation arcs into directed edges between pins; delete the constraint edges marked as pseudo paths or non-data propagation paths in the static timing analysis results; merge the edges that appear repeatedly between the same source pin and the same destination pin into one edge to obtain the timing edge set.

7. The method for constructing a design evolution diagram for backward layout optimization according to claim 1, characterized in that, The implementation process of step S4 is as follows: Based on the cell coordinates, pin coordinates, and cell bounding boxes in the layout after routing, all cells with mutually contacting bounding boxes are selected. For each group of such cells, the corresponding output pin is selected as a representative node, and physical proximity edges are established between the output pins. The physical proximity edges are used to characterize the potential physical coupling effects caused by spatial proximity in the layout, including local congestion, density changes, crosstalk, and wire-wound coupling effects.

8. The method for constructing a design evolution diagram for backward layout optimization according to claim 1, characterized in that, The implementation process of step S5 is as follows: Using the endpoint to be predicted and the endpoint of the violation path as the root node, the system expands along the temporal edges in the fan-in and fan-out directions to form a logical cone graph that includes the local temporal context. The temporal edges inside the subgraph are preserved. For the case where a node inside the subgraph is connected to a one-hop adjacent node outside the subgraph through a physical proximity edge, the one-hop adjacent node and the corresponding physical proximity edge are preserved, thus controlling the size of the subgraph while preserving the local physical coupling relationship.

9. The method for constructing a design evolution diagram for backward layout optimization according to claim 1, characterized in that, The design evolution diagram described in step S6 is represented as follows: ,in For a set of pin nodes, This is a set of text attributes corresponding to each pin. For a time-series edge set, It is the set of physically nearest edges.

10. An electronic device, characterized in that, Includes memory and processor, wherein: Memory is used to store computer programs that can run on a processor; A processor, configured to, while running the computer program, perform the steps of the design evolution graph construction method for back-layout optimization as described in any one of claims 1 to 9.

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