A signal processing method for dynamic protocol self-learning of an RFID reader-writer

Abstract

This invention relates to the field of radio frequency identification (RFID) technology, and more particularly to a signal processing method for dynamic protocol self-learning in RFID readers. The method includes: acquiring the RF demodulated bit stream, detecting the duration of continuous idle levels to segment frame boundaries, and determining the current frame length; extracting candidate preambles based on the frame length, traversing a verification rule base for verification, and confirming that the preamble, verification rules, and frame length together constitute valid protocol feature information; retrieving the feature base using this information, and retrieving existing parsing strategies or generating new strategies for storage based on the search results; extracting the current frame payload using the parsing strategy; for subsequent frames, constructing a unique identifier from the preamble, verification rules, and frame length, and directly mapping to the corresponding parsing strategy using this identifier as an index for parsing, replacing the time-division polling switching of protocol logic. This invention achieves automatic identification of unknown protocols and adaptive matching of parsing strategies.

Description

Technical Field

[0001] This invention relates to the field of radio frequency identification (RFID) technology, and in particular to a signal processing method for self-learning dynamic protocols of RFID readers. Background Technology

[0002] Radio Frequency Identification (RFID) technology, as a non-contact automatic identification technology, enables data exchange between tags and readers through radio frequency signals. It has been widely used in many fields such as logistics tracking, asset management, personnel positioning, vehicle management, and warehouse management. With the rapid development of IoT technology and the continuous growth in demand for real-time asset tracking across industries, the active RFID market continues to expand, placing higher demands on the compatibility of readers in scenarios where multiple types of tags coexist.

[0003] Existing active dual-frequency RFID readers generally employ a pre-defined protocol stack, sequentially attempting to match and parse different protocol formats upon receiving data. In multi-protocol tag deployment scenarios, this approach faces significant limitations: the protocol parsing logic is deeply tied to specific vendor tags, requiring multiple reader sets to be deployed when multiple tag types coexist, increasing procurement costs by over 30% and significantly increasing deployment complexity; the fixed protocol stack architecture necessitates firmware upgrades or even hardware replacements for adapting to new or proprietary non-standard protocols, severely limiting scalability; under the time-sharing polling mechanism, single-frame processing latency reaches 10 to 20 ms, with a missed read rate exceeding 15%, failing to meet the identification requirements of high-concurrency and high-speed mobile scenarios; furthermore, the fixed frame length preset cannot adapt to protocol frames varying from 8 to 128 bytes, and redundant hardware module solutions further increase cost and power consumption. These shortcomings restrict the reader's versatility, real-time performance, and scalability in multi-brand tag deployment scenarios. Summary of the Invention

[0004] To overcome the above shortcomings, this invention provides a signal processing method for dynamic protocol self-learning of RFID readers, aiming to improve the compatibility, real-time and scalability problems caused by the limited protocol adaptation capability, static fixed parsing strategy and frame processing dependence on polling switching in the prior art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: A signal processing method for self-learning dynamic protocol of RFID reader / writer includes: The bitstream data output from the demodulated radio frequency signal is acquired, and the frame length of the current protocol frame is determined by detecting the duration of continuous idle levels in the bitstream data and segmenting the frame boundaries. Based on the frame length, candidate preamble features are extracted, and the current protocol frame is verified by traversing the preset verification rule base until the verification is passed. After verification, the candidate preamble features, the corresponding verification rules, and the frame length are confirmed to constitute valid protocol feature information. The preset feature library is retrieved using the effective protocol feature information, and existing parsing strategies are retrieved or new strategies are generated and stored in the feature library based on the retrieval results. The data payload of the current protocol frame is extracted using the parsing strategy that is retrieved or generated. For each subsequently received protocol frame, a unique protocol identifier is constructed from the preamble features, verification rule features, and frame length. This identifier is then used as an index to directly map to the corresponding parsing strategy for parsing, replacing the time-division polling switching of the protocol logic.

[0006] Furthermore, the acquisition of the bitstream data output from the demodulated radio frequency signal specifically includes: The bitstream data demodulated by the RF unit is transmitted to the receive buffer of the main control processing unit through the DMA controller; An interrupt is triggered when the data reaches a preset length to notify the main control processing unit to perform parsing.

[0007] Furthermore, the step of segmenting frame boundaries to determine the frame length of the current protocol frame specifically includes: The duration of continuous constant level is detected by traversing the bit stream data using a sliding window. If the duration reaches a preset idle threshold, the current moment is determined to be an inter-frame idle interval; The dynamic frame length of the current protocol frame is determined based on the number of bits between two adjacent idle intervals.

[0008] Furthermore, the step of extracting candidate preamble features based on the frame length includes: In the beginning part of the current protocol frame, the starting bit sequence of the frame is traversed to retrieve a bit pattern that conforms to a preset rule; The identified matching patterns are recorded as candidate preambles.

[0009] Furthermore, the step of traversing the preset verification rule base to verify the current protocol frame includes: The current protocol frame is verified by sequentially calling various verification algorithms from the preset verification rule base; If the verification result of any verification algorithm is consistent with the verification information carried in the current protocol frame, the verification is deemed to have passed, and the verification algorithm is recorded as the corresponding verification rule feature.

[0010] Furthermore, the step of generating the new strategy includes: Generate parsing logic based on the valid protocol feature information; The parsing logic is used to extract the data payload of the current protocol frame; The valid protocol feature information is associated with the parsing logic and stored in the feature library.

[0011] Furthermore, the construction of the unique protocol identifier specifically includes: The preamble feature, the verification rule feature, and the frame length are combined into a key value, which is used as the unique protocol identifier.

[0012] Furthermore, the step of directly mapping the identifier to the corresponding parsing strategy for parsing includes: The feature database is queried using the unique protocol identifier as an index; If a match is successful, the parsing strategy corresponding to the unique protocol identifier in the feature library is directly invoked.

[0013] Furthermore, the parsing strategy includes the following steps: Each protocol frame is independently identified, its features are extracted, and its payload is parsed. The parsing process for each frame is independent of each other to eliminate the time dependence when parsing different protocol frames.

[0014] The present invention has the following beneficial effects: 1. In this invention, the inter-frame idle interval is determined by detecting the duration of continuous idle levels in the bit stream, and the frame length is calculated based on the number of bits between adjacent idle intervals, realizing dynamic frame length adaptive recognition without relying on a preset template, and supporting automatic adaptation of variable-length protocol frames from 8 to 128 bytes; at the same time, candidate preambles are extracted by pattern matching of the start bit sequence, and multiple verification algorithms are sequentially called to compare with the intra-frame check code to confirm the verification rules. Combined with the preamble features, verification rules and frame length, a triplet of valid protocol feature information is constructed to realize automated detection and reverse recognition of unknown protocol structure logic.

[0015] 2. In this invention, the feature library is retrieved using valid protocol feature information as the key. When a match is successful, the existing parsing strategy is directly retrieved. When a match fails, parsing logic is generated and associated with the non-volatile memory, thus completing the automatic solidification of the new protocol features. This allows subsequent protocol frames with the same features to directly reuse the existing strategy without repeated feature extraction and verification operations, achieving automatic compatibility with new protocol types without replacing hardware or upgrading firmware.

[0016] 3. In this invention, a unique protocol identifier is generated by fusing preamble features, verification rule features, and frame length encoding. This identifier is then used as an index to directly address the corresponding parsing strategy entry point, replacing the time-division polling method that attempts each protocol template sequentially, thus eliminating the waiting delay caused by protocol switching. Boundary identification, feature extraction, and payload parsing of each frame are all completed independently based on their own bitstream, eliminating inter-frame timing dependencies. The single-frame processing delay is reduced to less than 1ms, and the missed read rate is reduced to less than 0.5% in high-density concurrent scenarios. Attached Figure Description

[0017] Figure 1 This is a flowchart of a signal processing method for self-learning dynamic protocol of RFID reader proposed in this invention; Figure 2 This is a flowchart of the verification rule traversal and feature confirmation process proposed in this invention; Figure 3 This is a flowchart of the feature library retrieval and strategy adaptation proposed in this invention; Figure 4 This is a block diagram of the hardware circuit of the reader / writer proposed in this invention; Figure 5 This is a flowchart of the dynamic protocol processing method proposed in this invention. Detailed Implementation

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Example 1 This invention provides a signal processing method for self-learning dynamic protocols in RFID readers, such as... Figure 1 As shown, it includes the following steps: S100: Acquire the bitstream data output by demodulating the radio frequency signal, and determine the frame length of the current protocol frame by detecting the duration of continuous idle levels in the bitstream data and segmenting the frame boundaries; Furthermore, the acquisition of the bitstream data output from the demodulated radio frequency signal specifically includes: The bitstream data demodulated by the RF unit is transmitted to the receive buffer of the main control processing unit through the DMA controller; An interrupt is triggered when the data reaches a preset length to notify the main control processing unit to perform parsing.

[0020] Specifically, in this embodiment, the main control processing unit employs an ARM Cortex-M7 core processor with high-performance instruction processing capabilities, operating at a clock frequency of 400MHz to ensure real-time response to high-speed bitstreams. The radio frequency (RF) unit receives the 2.45GHz RF signal from the tag, performs GFSK demodulation, and outputs the raw baseband bitstream. To reduce the burden on the processor core and avoid high-speed data loss, bitstream data transmission is implemented using a DMA controller. The RF unit is specifically connected to the external bus of the main control processing unit via an SPI interface, configured with a communication rate of 1Mbps.

[0021] When the RF unit detects valid RF energy and begins outputting a bit stream, the DMA controller directly transfers data from the interface peripheral register to the receive buffer allocated within the main control processing unit. This receive buffer is set to 512 bytes, capable of holding any protocol frame in the range of 8 to 128 bytes. When the length of the received data reaches a preset monitoring threshold or the RF unit's IRQ pin triggers an interrupt signal, the main control processing unit is awakened and enters the data parsing state.

[0022] Furthermore, the step of segmenting frame boundaries to determine the frame length of the current protocol frame specifically includes: The duration of continuous constant level is detected by traversing the bit stream data using a sliding window. If the duration reaches a preset idle threshold, the current moment is determined to be an inter-frame idle interval; The dynamic frame length of the current protocol frame is determined based on the number of bits between two adjacent idle intervals.

[0023] Specifically, after acquiring the bitstream, the processor determines the physical boundaries of the protocol frames by executing a dynamic frame length detection algorithm. This process does not rely on a preset protocol template, but is based on the energy distribution patterns of the physical layer signals. In this embodiment, the processor uses a sliding window with a step size of 1 bit and a window size of 1 bit to traverse the entire receive buffer area. The core logic of the detection is to identify the continuous constant level representing the inter-frame idle state in the bitstream.

[0024] At a communication rate of 1 Mbps, set an idle threshold. for According to the physical layer definition, if a continuous low level appears in the bitstream and lasts for a certain duration... If the signal segment is not found to be a gap between frames, then the bit length of the current protocol frame is calculated by recording the boundary positions of two adjacent gaps. The frame length calculation formula is as follows: ; in, The dynamic frame length of the current protocol frame, in bits; This is the address of the first non-idle bit after the initial idle interval ends, representing the start boundary of the frame; This is the address of the last non-idle bit before the start of the next idle interval, representing the end boundary of the frame.

[0025] If detected Located in the 0th position of the cache. If it is located at position 511, then the frame length can be calculated. It is 512 bits, or 64 bytes. If another frame of signal is detected subsequently... If the 63rd bit is selected, the frame length is automatically identified as 8 bytes. This mechanism allows the device to automatically adapt to variable-length protocol frames defined by different manufacturers without manual intervention.

[0026] By detecting the duration of continuous idle levels in the bitstream to determine the inter-frame idle interval, and calculating the frame length based on the number of bits between adjacent idle intervals, dynamic frame length adaptive recognition without relying on any preset protocol template is achieved, supporting automatic adaptation of protocol frames of any length in the range of 8 to 128 bytes. At the same time, the direct transmission of bitstream data from the radio frequency unit to the processor cache is realized through the DMA controller. Combined with the mechanism of triggering interrupts by a preset length threshold, the low-latency acquisition of high-speed bitstream is completed in the data acquisition stage, reducing the processor intervention frequency.

[0027] S200: Extract candidate preamble features based on the frame length, traverse the preset verification rule base to verify the current protocol frame, and confirm that the candidate preamble features, the corresponding verification rules and the frame length together constitute valid protocol feature information after the verification is passed. Furthermore, the step of extracting candidate preamble features based on the frame length includes: In the beginning part of the current protocol frame, the starting bit sequence of the frame is traversed to retrieve a bit pattern that conforms to a preset rule; The identified matching patterns are recorded as candidate preambles.

[0028] Specifically, the logical structure of an unknown protocol is determined by reverse-engineering the mathematical characteristics of the bitstream's internal structure. The processor identifies the frame start boundary. Then, the start bit sequence of the current protocol frame is traversed to retrieve the characteristic bit pattern used for the synchronization signal. In this embodiment, the processor starts from... Initially, the length of the cut is... The bit sequence is used as the feature analysis interval. Set... The length is 32 bits, which is sufficient to cover the preamble length of most active RFID protocols. The processor uses a pattern matching algorithm to retrieve bit combinations with high repetition or specific patterns.

[0029] If the start bit sequence presents alternating levels of 10101010, the processor recognizes it as an 8-bit synchronization preamble. If the bit sequence presents consecutive 0000000011111111, it is recorded as a 16-bit preamble feature. The identified specific bit patterns and their bit lengths are temporarily stored as candidate preamble features.

[0030] Furthermore, such as Figure 2 As shown, the step of traversing the preset verification rule base to verify the current protocol frame includes: The current protocol frame is verified by sequentially calling various verification algorithms from the preset verification rule base; If the verification result of any verification algorithm is consistent with the verification information carried in the current protocol frame, the verification is deemed to have passed, and the verification algorithm is recorded as the corresponding verification rule feature.

[0031] Specifically, after obtaining the candidate preamble and frame length, the processor needs to verify the legality of the protocol structure using a mathematical verification algorithm and determine its verification rule characteristics. The processor calls a pre-stored verification rule library, which covers commonly used cyclic redundancy check algorithms, including CRC-8, CRC-16, and CRC-32. The verification logic follows the mathematical model below: ; in, A verification function for performing specific polynomial operations; This refers to the data payload portion of the current protocol frame excluding the checksum bit. The parameters of the generator polynomial used for the verification algorithm; This is the checksum calculated by the processor based on the current data load.

[0032] The processor sequentially extracts the bits at the end of the protocol frame as the original checksum carried in that frame. and compared with the results calculated by different algorithms Perform a comparison. If the conditions are met... If the current verification algorithm is determined to be the statutory verification rule for the protocol frame, then the processor stops traversing and associates the verification rule features with the previously extracted candidate preamble features and frame length.

[0033] Once the verification passes, the processor confirms that the structural logic of the current protocol frame has been identified. The vector consisting of the preamble value, the verification algorithm index number, and the frame length value constitutes the valid protocol feature information. This information serves as the sole basis for generating the subsequent parsing strategy, ensuring accurate modeling of non-standard or proprietary protocols.

[0034] By setting a fixed feature analysis interval during the preamble recognition stage and performing pattern matching on the start bit sequence within this interval to extract candidate preamble features, the dependence on preset synchronization code templates for different protocols is eliminated. Simultaneously, during the verification stage, a verification algorithm containing multiple generator polynomial parameters is sequentially called to perform calculations on the frame data payload, and the calculation results are compared one by one with the original check codes within the frame until they match. When they match, the verification rule is confirmed. Combined with the preamble features, verification rules, and frame length, a triplet of valid protocol feature information is constructed, thereby achieving automated detection and reverse identification of unknown protocol structure logic.

[0035] S300: Retrieve a preset feature library using the effective protocol feature information, and retrieve an existing parsing strategy or generate a new strategy based on the retrieval results and store it in the feature library; Furthermore, such as Figure 3 As shown, the steps for generating the new strategy include: Generate parsing logic based on the valid protocol feature information; The parsing logic is used to extract the data payload of the current protocol frame; The valid protocol feature information is associated with the parsing logic and stored in the feature library.

[0036] Specifically, by reusing known features or solidifying new features, the reader / writer achieves adaptive processing for multiple tag protocols. The processor constructs retrieval keys using effective protocol feature information. In this embodiment, the feature library is stored in the W25Q128JV QSPI Flash, and to improve retrieval efficiency, the index table is loaded into the random access memory (RAM) of the main control processing unit during system initialization.

[0037] The processor abstracts the effective protocol feature information into composite key-value pairs. Its mathematical expression is: ; in, These are the bit pattern feature values ​​of the preamble; For the type index of the verification algorithm; This represents the total bit length of the protocol frame.

[0038] The processor performs a matching operation in the RAM index table. If the search results show a perfect match... If the processor directly retrieves the corresponding parsing strategy from the feature library, the response time for this retrieval process is less than 0.1ms, ensuring real-time performance in high-speed label recognition scenarios.

[0039] If the search result shows a match failure, the processor determines that the current protocol is an unknown protocol being identified for the first time, and then initiates a self-learning process to generate a new parsing strategy. Based on the frame structure of the current protocol frame, the processor determines the physical offset of the data payload in the bitstream, that is, it locates the start and end bits of the payload based on the preamble length and checksum length; the processor generates parsing logic based on this location information.

[0040] The processor generates parsing logic based on the bit start and end interval mapping relationship of the data payload in the current protocol frame, and immediately uses this logic to extract data from the protocol frame in the current receive buffer to obtain payload information such as tag ID and RSSI.

[0041] After generating the parsing logic, the processor will The feature is associated with and encapsulated with the corresponding parsing logic to form a new feature entry. This entry is written to external non-volatile memory via the QUADSPI interface. In this embodiment, the feature library reserves 128 protocol storage bits. Each time a new protocol feature is stored, the feature library counter increments. For subsequent protocol frames with the same features, the processor will directly jump to the process of retrieving the existing strategy, thereby avoiding redundant verification operations and logic generation. This self-learning mechanism enables the reader to achieve automatic compatibility with newly added third-party tags without replacing hardware or upgrading firmware.

[0042] By combining the preamble bit pattern feature value, the verification algorithm type index, and the frame length into a composite key, and using this key as an index to perform a matching search in a pre-set feature library, a millisecond-level fast mapping from protocol features to parsing strategies is achieved when a match is found. When a match is not found, parsing logic is generated based on the physical offset of the data payload located in the current frame structure and associated with it, stored in non-volatile memory, completing a self-learning closed loop from recognition to solidification of new protocol features. This mechanism allows the reader to directly reuse existing strategies when encountering protocol frames with the same features in subsequent calls, avoiding repetitive feature extraction and verification operations. This enables automatic compatibility with new protocol types without replacing hardware or upgrading firmware, improving system throughput and adaptability in multi-protocol hybrid deployment scenarios.

[0043] S400: Extract the data payload of the current protocol frame using the parsing strategy that is retrieved or generated; Specifically, based on the bit offset interval defined in the parsing strategy, the bitstream residing in the receive buffer is directly sliced. Since the RF demodulation output is a baseband bitstream, the processor needs to perform data alignment and extraction through shift and mask operations; among which, the field offset... The bitmask represents the number of bits shifted to the right relative to the word boundary of this field. Used to shield against interference from non-target bits, its width is determined by the field length. When processing a 64-byte vehicle tag protocol frame, if the parsing strategy defines its tag ID as being located in bits 16 to 47, the processor will extract these 32 bits of data and convert them into a hexadecimal string.

[0044] The extracted raw payload needs to be repackaged using signal quality indicators. The processor obtains the Signal Strength Indicator (RSSI) of the current frame by reading the registers of the radio frequency unit and binds it to the extracted data payload. The standardized data packet... The physical structure is defined as follows: ; in, A globally unique identifier representing a label; This indicates the status bits or sensor information carried in the protocol frame; This indicates the received signal strength, usually expressed in dBm. This indicates a protocol type feature code identified through self-learning, used by the backend to distinguish different brands or uses.

[0045] This embodiment preferably employs a single-frame independent processing mechanism. Thanks to the 400MHz main control processing unit's clock frequency and the efficient retrieval of the parsing strategy, the total time from acquiring the raw bitstream to completing data payload extraction is controlled within 1ms. This polling-free parsing mode eliminates the latency caused by protocol switching in traditional solutions. In high-density scenarios with 200 tags concurrently arriving per second, the processor can respond to each frame of data in real time, ensuring that the receive buffer does not overflow due to insufficient processing speed. The parsed standard-format data is transmitted to the Ethernet controller via the RMII interface and then sent to the backend management system.

[0046] By directly slicing the bitstream in the resident buffer according to the bit offset interval defined in the parsing strategy, and completing data alignment and extraction with field offset and bitmask, efficient conversion from raw protocol frame payload to structured fields is achieved. By binding and encapsulating the extracted data payload with signal strength indication and protocol type feature code according to a preset format, standardized and unified expression of payload data of different protocol frames is achieved. At the same time, with the high main frequency computing power and single frame independent processing mechanism of the main control processing unit, the total time from acquiring the bitstream to extracting the payload of a single frame is controlled within 1ms, achieving real-time response in a scenario with 200 tags per second of concurrency, eliminating the waiting delay caused by protocol switching in the traditional time-division polling mechanism, and completing the final conversion from private non-standard bitstream to standard industry data.

[0047] S500: For each subsequently received protocol frame, a unique protocol identifier is constructed from the preamble features, verification rule features, and frame length. This identifier is then used as an index to directly map to the corresponding parsing strategy for parsing, replacing the time-division polling switching of the protocol logic.

[0048] Furthermore, the construction of the unique protocol identifier specifically includes: The preamble feature, the verification rule feature, and the frame length are combined into a key value, which is used as the unique protocol identifier.

[0049] Specifically, a unique protocol identifier is constructed to enable rapid indexing and parallel parsing of subsequent massive amounts of tag data, logically eliminating the polling waiting mechanism present in traditional multi-protocol readers. Bitstream features are dimensionality-reduced, extracting multi-dimensional protocol attributes into fixed-length unique protocol identifiers, which serve as the global index key for the retrieval and parsing strategy. The preamble features, checksum features, and dynamic frame length of the current frame are extracted and combined to form a unique protocol identifier. Specifically, the preamble features, checksum features, and frame length are encoded and fused to generate a fixed-length integer value, which serves as the global index key for the retrieval and parsing strategy.

[0050] The input consists of the preamble 0xAA, CRC-16 check algorithm, and a frame length of 64 bytes. After encoding and fusion, a 32-bit integer value is generated to uniquely identify the protocol type, which serves as the global index key for the protocol in the feature library.

[0051] Furthermore, the step of directly mapping the identifier to the corresponding parsing strategy for parsing includes: The feature database is queried using the unique protocol identifier as an index; If a match is successful, the parsing strategy corresponding to the unique protocol identifier in the feature library is directly invoked.

[0052] Specifically, after obtaining the unique protocol identifier, instead of attempting to match each protocol template individually, the processor retrieves the parsing logic via hash mapping or direct addressing. The processor uses the unique protocol identifier as an index to query the feature mapping table located in RAM. If the query matches, the processor directly jumps to the parsing strategy entry address associated with that unique protocol identifier.

[0053] In traditional technologies, devices need to try protocols A, B, and C sequentially, with single-frame recognition latency typically between 10ms and 20ms. By adopting the direct mapping mechanism of this embodiment, the addressing time of the parsing strategy is reduced to less than 10μs. This mapping mechanism enables the reader to respond quickly when faced with mixed tags from different manufacturers, as if processing a single protocol, reducing the overall single-frame processing latency to less than 1ms.

[0054] Furthermore, the parsing strategy includes the following steps: Each protocol frame is independently identified, its features are extracted, and its payload is parsed. The parsing process for each frame is independent of each other to eliminate the time dependence when parsing different protocol frames.

[0055] Specifically, to cope with scenarios involving a high density of tags, the processor implements independent parsing processes for each protocol frame. The main control processing unit utilizes multiple independent receive buffers in conjunction with DMA multi-channel technology. While the payload extraction of the first frame of data is underway, the bitstream of the second frame of data has already been written to an adjacent buffer via another DMA channel.

[0056] The parsing process for each frame includes frame boundary identification, feature extraction, and payload parsing, with each step based on the local bitstream data of the current frame. Physically, the parsing logic for each frame is entirely determined by its own unique protocol identifier, independent of the protocol type or processing state of the previous frame.

[0057] In the test scenario of this embodiment, the tag concurrency frequency was set to 200 frames per second. Since the parsing process for each frame is independent and there is no polling switching time, the system's missed read rate remained below 0.5%. In contrast, traditional polling schemes with time-dependent characteristics typically have a missed read rate exceeding 15% at the same density. This independent parsing mechanism ensures the system's robustness under high load conditions, stably supporting high-speed mobile tag recognition up to 120 km / h.

[0058] By fusing preamble features, check rule features, and frame length encoding to generate a unique protocol identifier, and using this identifier as an index to directly address the corresponding parsing strategy entry in the RAM feature mapping table, the strategy addressing time is significantly shortened to the microsecond level. Compared to the millisecond-level delay caused by trying each protocol template sequentially in the traditional time-division polling mechanism, this represents an order-of-magnitude improvement. At the same time, with the independent receive buffer of multiple DMA channels, the boundary identification, feature extraction, and payload parsing of each frame are all completed independently based on their own bitstream data, eliminating inter-frame timing dependencies. This significantly reduces the missed read rate in high-density concurrent scenarios and stably supports the identification of high-speed mobile tags, thus logically eliminating the polling waiting bottleneck present in traditional multi-protocol readers.

[0059] Example 2 This embodiment provides a signal processing scheme for dynamic protocol self-learning of RFID readers based on an ARM Cortex-M7 embedded hardware platform. This scheme is designed for small- to medium-scale applications such as mixed personnel / asset positioning in warehouses and small to medium-sized parking lots. It features low cost and simple deployment, and those skilled in the art can directly implement products based on this embodiment. This invention also provides a signal processing method for dynamic protocol self-learning of RFID readers, including: The bitstream data output from the demodulated radio frequency signal is acquired, and the frame length of the current protocol frame is determined by detecting the duration of continuous idle levels in the bitstream data and segmenting the frame boundaries. Based on the frame length, candidate preamble features are extracted, and the current protocol frame is verified by traversing the preset verification rule base until the verification is passed. After verification, the candidate preamble features, the corresponding verification rules, and the frame length are confirmed to constitute valid protocol feature information. The preset feature library is retrieved using the effective protocol feature information, and existing parsing strategies are retrieved or new strategies are generated and stored in the feature library based on the retrieval results. The data payload of the current protocol frame is extracted using the parsing strategy that is retrieved or generated. For each subsequently received protocol frame, a unique protocol identifier is constructed from the preamble features, verification rule features, and frame length. This identifier is then used as an index to directly map to the corresponding parsing strategy for parsing, replacing the time-division polling switching of the protocol logic.

[0060] Specifically, the reader / writer involved in this embodiment adopts a single hardware architecture and achieves multi-protocol compatibility through software algorithms, eliminating the need for multiple independent hardware modules. The specific components and selections are shown in Table 1.

[0061] Table 1 Hardware Composition and Component Selection of the Equipment Each component is connected to the main controller via a standard interface, and the signal flow is clear.

[0062] The SPI interface of the low-frequency wake-up unit ATA5276, including the SCK, MOSI, MISO, and NSS pins, is connected to the host controller's SPI1 peripheral. Its interrupt pin INT is connected to the host controller's PA0 pin. The host controller configures the wake-up unit's transmit period and transmit power via SPI. The default transmit period is 10ms, and the default transmit power is 10dBm. The wake-up unit's status is fed back to the host controller via interrupts.

[0063] The SPI interface of the 2.4G RF unit nRF24L01P is connected to the main controller's SPI2 peripheral, and its interrupt pin IRQ is connected to the main controller's PA1 pin. After receiving the 2.4G signal from the tag and completing GFSK demodulation, the RF unit directly transmits the raw baseband bitstream to the main controller's RAM receive buffer via DMA. This receive buffer is 512 bytes in size, which is sufficient to hold protocol frames of up to 128 bytes. At the same time, an interrupt is triggered to notify the main controller to process the data.

[0064] The QSPI interface of the W25Q128JV storage unit is connected to the host QUADSPI peripheral, enabling high-speed read and write at up to 80MHz, and is used for storing protocol feature libraries.

[0065] The RMII interface of the LAN8720 interface unit is connected to the main controller ETH peripheral to enable high-speed uploading of parsed tag data.

[0066] The MP2307 power supply unit converts the input 12V DC to 5V, and then the AMS1117-3.3 converts it to 3.3V, supplying power to the main control unit, RF unit, memory unit, and interface unit. A 0.1μF filter capacitor is connected in parallel to the power supply pins of each component to ensure power stability.

[0067] like Figure 4 As shown, each component is connected to the main controller via a standard interface, and the signal flow is clear.

[0068] The workflow of this device is divided into the initialization stage, the tag wake-up stage, the dynamic protocol processing stage, and the data upload stage.

[0069] The initialization phase is executed once after power-on. The main controller initializes all peripherals, including SPI1, SPI2, QSPI, ETH, and the DMA controller; it reads the stored protocol features from the W25Q128JV and loads them into the RAM cache to accelerate subsequent matching; it configures the low-frequency wake-up unit to transmit with a period of 10ms and a transmit power of 10dBm, enabling it to periodically transmit a 125KHz wake-up signal; and it configures the 2.4G RF unit to receive with a sensitivity of -94dBm and a communication rate of 1Mbps, entering a receive standby state.

[0070] When a semi-active tag enters the coverage area of ​​the low-frequency wake-up unit, which is 0 to 5 meters, its low-frequency receiving circuit wakes up from the dormant state after receiving the wake-up signal and starts its own 2.4G communication module. The tag packages the data into protocol frames according to its own private protocol and sends them to the reader via the 2.4G frequency band. The protocol frame length and structure of different tags are completely different, so there is no need to inform the reader in advance.

[0071] When the 2.4G radio frequency unit receives the tag signal and transmits the raw data to the main control receiver buffer, the main control starts the dynamic protocol analysis algorithm, such as... Figure 5 As shown, the dynamic protocol analysis algorithm includes four core steps: dynamic frame length detection, automatic protocol feature extraction, feature library matching and self-learning, and parallel polling-free parsing. The specific steps are as follows: During dynamic frame length detection, a sliding window with a window size of 1 bit and a step size of 1 bit is used to traverse the entire buffer of the bit stream in the receive buffer to detect the idle interval of the signal. The idle interval between tag frames is greater than or equal to 10 μs, which corresponds to a continuous low level in the bit stream. The frame length is automatically calculated by the idle interval between the start and end of the frame. It supports any length from 8 to 128 bytes without the need for preset.

[0072] During the automatic extraction of protocol features, for the identified frame, the first N bits of the frame are traversed to identify the continuous synchronization code, such as 8 bits 10101010 or 16 bits 0000000011111111, and the length and value of the preamble are automatically determined. The frame data is then checked sequentially using CRC8, CRC16, and CRC32 check algorithms until the check passes, and the CRC rule of the protocol is automatically identified.

[0073] During the feature library matching and self-learning process, the extracted protocol features, including the preamble, CRC type, and frame length, are used as keys to match the feature library in RAM. If the match is successful, the stored parsing logic is directly called, with a single frame processing time of only 0.1ms. If the match fails, temporary parsing logic is generated based on the extracted features to complete the parsing of the current frame data. At the same time, the protocol features are written into the Flash feature library, so that subsequent tags of the same protocol can be directly matched, achieving one-time learning and permanent adaptation.

[0074] During the parallel polling-free parsing process, this algorithm processes each frame of data independently in parallel, eliminating the mode switching waiting time. The overall processing time for a single frame is less than or equal to 1ms, which is far lower than the 10 to 20ms of traditional polling. In a concurrent scenario of 200 tags per second, the missed read rate is less than or equal to 0.5%, effectively solving the missed read problem of traditional solutions.

[0075] After parsing, the main controller packages the tag data from different protocols into a standard format, including tag ID, RSSI signal strength, and protocol type identifier, and uploads it to the backend system via Ethernet. The backend can directly use all tag data without any protocol adaptation.

[0076] Through the above process, this embodiment achieves a complete closed-loop processing from physical signal acquisition, frame boundary identification, protocol feature extraction, adaptive matching of parsing strategies, to standardized data output. The dynamic frame length detection mechanism enables the device to automatically adapt to protocol frames of any length within the range of 8 to 128 bytes without the need for a preset fixed frame length; the automatic protocol feature extraction and self-learning mechanism enables the device to automatically identify unknown protocols and solidify parsing strategies without manual intervention; the parallel polling-free parsing mechanism eliminates the waiting delay of traditional time-sharing polling, shortening the single-frame processing time to less than 1ms, and controlling the missed read rate to below 0.5% in a concurrent scenario of 200 tags per second.

[0077] The entire processing flow enables the reader to automatically identify, adaptively parse, and standardize the output of multiple tag protocols, solving problems such as static protocol stack fixation, limited frame length adaptation, high polling latency, and high missed read rate.

[0078] This embodiment retains the dual-band architecture (125kHz low-frequency wake-up + 2.4G reception) and achieves automatic compatibility of multiple protocol tags through improvements to the dynamic protocol processing hardware architecture and adaptive algorithm engine. Core performance comparisons are shown in Table 2.

[0079] Table 2 Comparison of Core Performance Indicators Multi-protocol compatibility is achieved through software algorithms, automatically identifying and adapting to new protocols without manual intervention; a parallel processing mechanism replaces traditional time-division polling, eliminating latency and missed reads caused by protocol switching; at the same time, the RF module adopts a universal interface design, which can flexibly replace RF chips from different manufacturers without modifying the main control software; while achieving the above full functions, the overall cost and power consumption are comparable to single-protocol products, giving it a high cost-performance advantage.

[0080] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A signal processing method for self-learning dynamic protocol of RFID reader / writer, characterized in that, include: The bitstream data output from the demodulated radio frequency signal is acquired, and the frame length of the current protocol frame is determined by detecting the duration of continuous idle levels in the bitstream data and segmenting the frame boundaries. Based on the frame length, candidate preamble features are extracted, and the current protocol frame is verified by traversing the preset verification rule base until the verification is passed. After verification, the candidate preamble features, the corresponding verification rules, and the frame length are confirmed to constitute valid protocol feature information. The preset feature library is retrieved using the effective protocol feature information, and existing parsing strategies are retrieved or new strategies are generated and stored in the feature library based on the retrieval results. The data payload of the current protocol frame is extracted using the parsing strategy that is retrieved or generated. For each subsequently received protocol frame, a unique protocol identifier is constructed from the preamble features, verification rule features, and frame length. This identifier is then used as an index to directly map to the corresponding parsing strategy for parsing, replacing the time-division polling switching of the protocol logic.

2. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The acquisition of the bitstream data output from the demodulated radio frequency signal specifically includes: The bitstream data demodulated by the RF unit is transmitted to the receive buffer of the main control processing unit through the DMA controller; An interrupt is triggered when the data reaches a preset length to notify the main control processing unit to perform parsing.

3. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The process of segmenting frame boundaries to determine the frame length of the current protocol frame specifically includes: The duration of continuous constant level is detected by traversing the bit stream data using a sliding window. If the duration reaches a preset idle threshold, the current moment is determined to be an inter-frame idle interval; The dynamic frame length of the current protocol frame is determined based on the number of bits between two adjacent idle intervals.

4. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The step of extracting candidate preamble features based on the frame length includes: In the beginning part of the current protocol frame, the starting bit sequence of the frame is traversed to retrieve a bit pattern that conforms to a preset rule; The identified matching patterns are recorded as candidate preambles.

5. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The step of traversing the preset verification rule base to verify the current protocol frame includes: The current protocol frame is verified by sequentially calling various verification algorithms from the preset verification rule base; If the verification result of any verification algorithm is consistent with the verification information carried in the current protocol frame, the verification is deemed to have passed, and the verification algorithm is recorded as the corresponding verification rule feature.

6. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The steps for generating the new strategy include: Generate parsing logic based on the valid protocol feature information; The parsing logic is used to extract the data payload of the current protocol frame; The valid protocol feature information is associated with the parsing logic and stored in the feature library.

7. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The unique protocol identifier specifically includes: The preamble feature, the verification rule feature, and the frame length are combined into a key value, which is used as the unique protocol identifier.

8. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The step of directly mapping the identifier to the corresponding parsing strategy for parsing includes: The feature database is queried using the unique protocol identifier as an index; If a match is successful, the parsing strategy corresponding to the unique protocol identifier in the feature library is directly invoked.

9. The signal processing method for self-learning dynamic protocol of RFID reader / writer according to claim 1, characterized in that, The parsing strategy includes the following steps: Each protocol frame is independently identified, its features are extracted, and its payload is parsed. The parsing process for each frame is independent of each other to eliminate the time dependence when parsing different protocol frames.

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