A neuromorphic computing unit and a method of fabricating the same, a reservoir computing system

Abstract

This disclosure provides a neuromorphic computing unit and its fabrication method, as well as a reservoir computing system. The neuromorphic computing unit includes: a first substrate; multiple nanowires and multiple electrodes formed on the first substrate; the multiple nanowires forming a nano-neural network layer, and the multiple electrodes distributed within the nano-neural network layer; wherein the nanowires possess the characteristic of electrically driven solid-state amorphization; the multiple electrodes include an input electrode, a ground electrode, and at least one output electrode; wherein the input electrode is used to receive an input voltage, and the output electrode is used to output a target voltage, the target voltage serving as feature information for achieving the target task. The neuromorphic computing unit provided by this disclosure features low power consumption and large-scale integration capability.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a neuromorphic computing unit and its fabrication method, and a reservoir computing system. Background Technology

[0002] Traditional computers are based on the von Neumann architecture, which, due to the separation of memory and computing chips, requires frequent data transfer between them for data access and processing, making it difficult to achieve breakthroughs in speed and power consumption during computation. To further improve data processing speed, new computing hardware needs to be developed to help break through the traditional von Neumann computing bottleneck.

[0003] Given that the human brain can store and process various neural information on a large scale, in parallel and in a distributed manner, if a brain-like electronic device can be developed that can integrate information storage and computation (referred to as storage-computing integration) like the human brain, the von Neumann computing bottleneck can be fundamentally solved.

[0004] Neuromorphic computing, also known as brain-inspired computing, is based on the principle of simulating the information processing methods of biological nervous systems. It achieves efficient information processing based on biomimetic pulse elements. The problem that needs to be solved is how to realize low-power, large-scale neuromorphic computing units. Summary of the Invention

[0005] This disclosure provides a neuromorphic computing unit and its preparation method, as well as a reservoir computing system.

[0006] In a first aspect, embodiments of this disclosure provide a neuromorphic computing unit, including:

[0007] First substrate;

[0008] Multiple nanowires and multiple electrodes are formed on the first substrate; the multiple nanowires form a nano-neural network layer, and the multiple electrodes are distributed within the nano-neural network layer; wherein, the nanowires have the characteristic of electrically driven solid-state amorphization;

[0009] The plurality of electrodes includes an input electrode, a ground electrode, and at least one output electrode; wherein the input electrode is used to receive an input voltage, the output electrode is used to output a target voltage, and the target voltage serves as characteristic information for achieving the target task.

[0010] In some embodiments, the nanowire body is indium selenide nanowire, and the catalyst nanoparticles are gold palladium nanoparticles.

[0011] In some embodiments, the target task is a classification task and / or a sequence recall task.

[0012] Secondly, embodiments of this disclosure provide a method for preparing a neuromorphic computing unit, comprising:

[0013] A first substrate is provided on which a plurality of electrodes are formed; and a second substrate is provided on which a plurality of nanowires are formed; wherein the nanowires have the property of electrically driven solid-state amorphization.

[0014] The plurality of nanowires are transferred to the surface of the first substrate on which the plurality of electrodes are formed, and the second substrate is removed to obtain the neuromorphic computing unit; wherein the plurality of nanowires form a nano-neural network layer, and the plurality of electrodes are distributed within the nano-neural network layer.

[0015] In some embodiments, forming a plurality of electrodes on the first substrate includes:

[0016] An electrode layer is formed above the first substrate;

[0017] The electrode layer is patterned to obtain the plurality of electrodes.

[0018] In some embodiments, forming a plurality of nanowires on the second substrate includes:

[0019] Multiple catalyst nanoparticles are formed on the second substrate;

[0020] Using the catalyst nanoparticles as seeds, materials with the characteristics of electrically driven solid-state amorphization are grown to obtain multiple nanowire bodies; one end of each nanowire body is connected to the second substrate, and the other end is connected to the catalyst nanoparticles, and the nanowire bodies and the catalyst nanoparticles constitute the nanowires.

[0021] In some embodiments, the nanowire body is indium selenide nanowire, and the catalyst nanoparticles are gold palladium nanoparticles.

[0022] In some embodiments, when a plurality of electrodes are formed on the first substrate, the method further includes:

[0023] An isolation structure is formed on the first substrate, and the plurality of electrodes are divided into multiple groups of electrodes by the isolation structure;

[0024] Correspondingly, after removing the second substrate, the method further includes:

[0025] By removing the isolation structure, multiple neuromorphic computing units are obtained.

[0026] Thirdly, embodiments of this disclosure provide a reserve pool computing system, including:

[0027] A signal converter is used to receive the object to be detected and convert the object to be detected into a voltage pulse signal;

[0028] The neuromorphic computing unit as described in any of the first aspects is configured to receive the voltage pulse signal through the input electrode and output at least one target voltage through the at least one output electrode;

[0029] An output layer is used to receive the at least one target voltage and output the detection result corresponding to the target task based on the at least one target voltage.

[0030] In some embodiments, the target task is a classification task, and the object to be detected includes an image to be detected.

[0031] In some embodiments, the target task is a sequence recall task, and the object to be detected includes multiple sub-objects;

[0032] The neuromorphic computing unit is also used to output a target current through the grounding electrode;

[0033] The output layer is further configured to receive the target current and output a detection result corresponding to the sequence recall task based on the at least one target voltage and the target current; or, the output layer is further configured to determine at least one first parameter based on the at least one target voltage and the at least one target current, and output a detection result corresponding to the sequence recall task based on the at least one first parameter, wherein the first parameter is resistance or conductance.

[0034] In some embodiments, the reservoir calculation system further includes an ammeter and at least one voltmeter;

[0035] The ammeter is connected between the grounding electrode and the grounding terminal and is used to measure the current value of the target current.

[0036] The voltmeter is connected to the corresponding output electrode and is used to measure the voltage value of the corresponding target voltage.

[0037] In some embodiments, the target task includes at least one subtask; each subtask corresponds to its own input electrode and at least one output electrode;

[0038] The output layer includes at least one sub-output layer corresponding to the at least one sub-task, and each sub-output layer outputs the detection result of the corresponding sub-task.

[0039] This disclosure provides a neuromorphic computing unit and its fabrication method, as well as a reservoir computing system. Utilizing the electrically driven solid-state amorphization properties of nanowires in a nano-neural network layer, an input voltage is applied to the input electrode to drive the nanowires to undergo solid-state amorphization. A target voltage is output in real-time at the output electrode. Simultaneously, due to the reaction time during the solid-state amorphization process, the resistance / conductance of the nano-neural network layer exhibits hysteresis relative to the target voltage. Based on the real-time changing target voltage and the hysteretic resistance / conductance as characteristic information for different types of target tasks, tasks such as classification and sequence recall can be achieved with low power consumption. Furthermore, this neuromorphic computing unit can be fabricated on a large scale. Attached Figure Description

[0040] Figure 1 A top view schematic diagram of a neuromorphic computing unit provided in an embodiment of this disclosure;

[0041] Figure 2 This is a schematic front view of a neuromorphic computing unit provided in an embodiment of the present disclosure;

[0042] Figure 3 This is a schematic diagram of the composition structure of a reservoir computing system provided in an embodiment of the present disclosure;

[0043] Figure 4 This is a schematic diagram illustrating the conversion of an image to be detected into a voltage pulse signal, as provided in an embodiment of this disclosure.

[0044] Figure 5 A schematic diagram of the working process of a reservoir calculation system provided in this embodiment of the disclosure. Figure 1 ;

[0045] Figure 6 A schematic diagram of the working process of a reservoir calculation system provided in this embodiment of the disclosure. Figure 2 ;

[0046] Figure 7 A schematic diagram illustrating the correspondence between a reservoir computing unit and a neuromorphic computing unit provided in an embodiment of this disclosure;

[0047] Figure 8 A schematic diagram illustrating a method for fabricating a neuromorphic computing unit according to an embodiment of this disclosure;

[0048] Figure 9 A schematic diagram of the fabrication process of a neuromorphic computing unit provided in this embodiment of the present disclosure. Figure 1 ;

[0049] Figure 10 A schematic diagram of the fabrication process of a neuromorphic computing unit provided in this embodiment of the present disclosure. Figure 2 ;

[0050] Figure 11 This is a schematic diagram of a large-scale integrated neuromorphic computing unit provided in an embodiment of the present disclosure. Detailed Implementation

[0051] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0053] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0054] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0055] The microscopic mechanisms driving the formation of amorphous and other disordered phases from ordered phases in materials have long puzzled scientists. Typically, amorphization involves rapid cooling of a molten liquid, bypassing the thermodynamically favorable crystallization process. Electrically induced amorphization is uncommon; to date, only a handful of material systems have achieved amorphization via pulsed current using melt-quenching processes. If electrically driven solid-state amorphization could be achieved without the melting step, it would open up possibilities for low-power device applications.

[0056] Based on this, embodiments of the present disclosure provide a neuromorphic computing unit, including: a first substrate; a plurality of nanowires and a plurality of electrodes formed on the first substrate; the plurality of nanowires forming a nano-neural network layer, and the plurality of electrodes distributed within the nano-neural network layer; wherein the nanowires have the characteristic of electrically driven solid-state amorphization; the plurality of electrodes include an input electrode, a ground electrode, and at least one output electrode; wherein the input electrode is used to receive an input voltage, the output electrode is used to output a target voltage, and the target voltage serves as feature information for achieving a target task.

[0057] In this way, by utilizing the electrically driven solid-state amorphization property of nanowires in the nano-neural network layer, an input voltage is applied to the input electrode to drive the nanowires to undergo solid-state amorphization, and the target voltage is output in real time at the output electrode. At the same time, due to the reaction time during the solid-state amorphization process, the resistance / conductance of the nano-neural network layer has hysteresis relative to the target voltage. Based on the real-time changing target voltage and the hysteresis resistance / conductance as feature information for different types of target tasks, tasks such as classification and sequence recall can be realized with low power consumption.

[0058] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0059] In one embodiment of this disclosure, see [link to embodiment]. Figure 1 and Figure 2 This illustration shows a schematic diagram of a neuromorphic computing unit provided in an embodiment of this disclosure. Figure 1 and Figure 2 As shown, the neuromorphic computing unit 10 includes:

[0060] First substrate 101;

[0061] Multiple nanowires 102 and multiple electrodes 103 are formed on a first substrate 101; the multiple nanowires 102 form a nano-neural network layer 102A, and the multiple electrodes 103 are distributed within the nano-neural network layer 102A; wherein, the nanowires 102 have the characteristic of electrically driven solid-state amorphization.

[0062] The plurality of electrodes 103 include an input electrode, a ground electrode and at least one output electrode; wherein the input electrode is used to receive an input voltage, the output electrode is used to output a target voltage, and the target voltage serves as characteristic information for achieving the target task.

[0063] It should be noted that in practical applications, the total number of electrodes 103, the total number of output electrodes, the width and length of nanowires 102, the density of nanowires 102 in the nano-neural network layer 102A, the total number of input electrodes, etc., can all be adjusted and set according to actual needs, and this disclosure embodiment does not make specific limitations in this regard.

[0064] by Figure 1As shown in the example, the neuromorphic computing unit 10 includes 16 electrodes 103: one input electrode (electrode 0), five output electrodes (electrodes 1, 2, 12, 13, and 14), one ground electrode (electrode 3), and the remaining nine electrodes (electrodes 4, 5, 6, 7, 8, 9, 10, 11, and 15) are spare electrodes, which can be used as input or output electrodes when there is a need for more input or output. The input electrode can also be called the source electrode, serving as the starting point of the current; the ground electrode can also be called the drain electrode, serving as the ending point of the current; and the output electrodes serve as the signal output terminals, also known as readout electrodes.

[0065] like Figure 2 As shown, (b) is a partial schematic diagram of the nano-neural network layer 102A, and (c) is a schematic diagram of the nanowire 102. In this embodiment, catalyst nanoparticles 1022 can be used as seeds to induce the growth of nanowires 102, that is, the nanowires 102 are obtained based on the growth of catalyst nanoparticles 1022. Therefore, as Figure 2 As shown in (c), the nanowire 102 may include a nanowire body 1021 and catalyst nanoparticles 1022, wherein the width of the nanowire body 1021 is equal to the diameter of the catalyst nanoparticles 1022. Here, the width of the nanowire body 1021 refers to the width perpendicular to the extension direction of the nanowire 102.

[0066] In other examples, if the nanowires 102 are prepared in other ways, they may contain only the nanowire body 1021, or they may contain the nanowire body 1021 and other particles.

[0067] It should also be noted that, in this embodiment, the nanowire 102 exhibits electrically driven solid-state amorphization characteristics, specifically referring to the nanowire body 1021 possessing these characteristics, which are reversible. The nanowire body 1021 with solid-state amorphization characteristics can be indium selenide (In2Se3) nanowires 1021, and the catalyst nanoparticles 1022 can be gold-palladium nanoparticles. In the following description, indium selenide nanowires will be used as an example.

[0068] like Figure 1 and Figure 2As shown, multiple indium selenide nanowires 1021 are distributed on the surface of the first substrate 101 to form a nano-neural network layer 102A, and electrodes 103 are distributed within the nano-neural network layer 102A. When the input electrode 0 receives an input voltage, an electric field and current are generated under the action of the voltage, causing a phase transition inside the indium selenide nanowires 1021, forming a force and generating a pressure effect. At the same time, the indium selenide nanowires 1021 are ferroelectric materials, and under the action of the electric field, ferroelectric polarization occurs, exhibiting the characteristics of both ferroelectric and nanomaterials. Under the coupling effect of electric field, current, pressure effect, and ferroelectric polarization, the ferroelectric indium selenide nanowires 1021 can achieve energy saving and unconventional solid-state amorphization, that is, without going through a molten state, directly converting from a crystalline state to an amorphous state, thus greatly reducing the energy required for the conversion process, and can be used as a low-power device.

[0069] When a certain input voltage is applied to the input electrodes, based on the characteristics of the indium selenide nanowire 1021, unconventional solid-state amorphization is achieved, and the target voltage is output in real time at each output electrode. Simultaneously, during the unconventional solid-state amorphization process, the phase transition within the ferroelectric indium selenide nanowire 1021 requires a certain amount of time. Therefore, when the input voltage is continuously applied, the change in resistance (or conductance) relative to the real-time output voltage exhibits a certain lag as the amorphization process continues. In other words, there is a lag effect in resistance / conductance, thus enabling the neuromorphic computing unit 10 to possess a "memory" function.

[0070] Based on the characteristics of the neuromorphic computing unit 10, the target voltage and / or resistance / conductance can be used as the feature information (or dynamic descriptor) required to achieve the target task, thereby obtaining the corresponding target task detection result.

[0071] Therefore, see Figure 3 It shows a schematic diagram of the composition structure of a reservoir computing system 30 for achieving a target task provided in an embodiment of this disclosure, such as... Figure 3 As shown, the reservoir calculation system 30 includes:

[0072] Signal converter 301 is used to receive the object to be detected and convert the object to be detected into a voltage pulse signal;

[0073] The neuromorphic computing unit 10 is used to receive voltage pulse signals through input electrodes and output at least one target voltage through at least one output electrode.

[0074] The output layer 302 is used to receive at least one target voltage and output the detection result of the corresponding target task based on the at least one target voltage.

[0075] It should be noted that the object to be detected can be an image or a sequence of objects. For an image to be detected, the target task can be a classification task (or recognition task), and for a sequence of objects, the target task can be a sequence recall task (or temporal recall task, sequence memory task, memory task, etc.). Alternatively, embodiments of this disclosure can also implement other neural network-related tasks, which are not specifically limited thereto.

[0076] The image to be detected can be in the form of a digital image, or it can be converted from other forms of image to digital image first. The signal converter 301 has the function of converting digital image into voltage pulse signal, for example: based on grayscale, pixel value, etc., it converts a column, a row, a single pixel, or several pixels into a voltage pulse. An image to be detected can be converted into a continuous voltage pulse signal. For example Figure 4 As shown, (a) illustrates the image to be detected, containing the digit "5". After processing by signal converter 301, a voltage pulse signal is obtained. A schematic diagram of the voltage pulse signal is shown below. Figure 4 As shown in (b) in the figure, the horizontal axis represents time (in seconds (s) and the vertical axis represents voltage (in volts (V)), which is represented as a time-voltage pulse current.

[0077] In this way, the digital image is converted into a voltage pulse signal, which is then input as the input voltage to the input electrodes of the neuromorphic computing unit 10. Assuming there are n output electrodes, where n is a positive integer, then the n output electrodes of the neuromorphic computing unit 10 each output n target voltages, such as... Figure 3 As shown, they are denoted as target voltage 1, target voltage 2, ..., target voltage n, respectively.

[0078] n target voltages are input as n feature information into the output layer 302, and the output layer 302 performs inference to obtain the final detection result.

[0079] It's also worth noting that Reservoir Computing is a neural network-based computational method. Its core lies in a fixed, randomly generated, large neural network—the so-called "reservoir." Unlike traditional neural networks, this network doesn't require comprehensive training; instead, it maintains its initial, randomized connection state. The reservoir's role is to transform the input data into a higher-dimensional, dynamic representation, a process that enhances the data's non-linearity and complexity. The only part that needs training is the network's output, which greatly simplifies the training process and reduces computational resource requirements.

[0080] In this embodiment, the neuromorphic computing unit 10 based on indium selenide nanowires can output dynamic, real-time changing output voltage, resistance / conductance, etc. as feature information according to the input voltage. Therefore, the output feature information can also be called dynamic descriptor, which makes the reservoir computing system 30 based on indium selenide nanowires have the characteristics of real-time online and dynamic learning, which is different from the traditional scheme of using fixed static descriptors for training and prediction.

[0081] For example, the reservoir computing system 30 can consist of the following three main components:

[0082] The system comprises an input layer, an intermediate layer (or reservoir layer), and an output layer. The main function of the input layer is to receive external input signals and pass them to the intermediate layer. In this embodiment, the signal converter 301 is equivalent to the input layer, used to convert the input digital image into a voltage pulse signal. The intermediate layer consists of multiple nodes connected sparsely to form a network, capable of generating a nonlinear response after receiving a signal. The number of nodes is typically large and the connections are sparse, making it timely in processing complex time-series data. In this embodiment, the neuromorphic computing unit 10 is equivalent to the intermediate layer, and the nanowire 102 is equivalent to a node, which can also be considered a "synapse" in a neural network. The output layer can be a weighted adder used to linearly combine the outputs of the intermediate layers to obtain the final detection result. In the reservoir computing system 30, the weights of the intermediate layer are randomly generated and remain unchanged after generation; only the weights of the output layer need to be trained.

[0083] In this embodiment, the output layer can be implemented in software or as a program embedded in hardware circuitry, etc., and is not specifically limited thereto. For different specific implementations, the target voltage output by the neuromorphic computing unit 10 can be converted according to actual conditions to generate data or signals that meet the requirements of the output layer.

[0084] In one specific implementation, the target task is a classification task, and the objects to be detected include the images to be detected.

[0085] like Figure 5 As shown in (a), assuming there are N samples, i.e., N images to be detected, the signal converter converts each image from a digital image into a voltage pulse signal, i.e. Figure 5 The 1D time-voltage pulse stream shown in (a) is a voltage signal that varies along a single time axis. There is a certain time interval between adjacent images to be detected to distinguish different images. For example, in... Figure 5In this process, several columns of pixels are used as the smallest unit for conversion. The voltage pulse signal output by the signal converter is used as the input to the neuromorphic computing unit 10.

[0086] like Figure 5 As shown in (b), in the reservoir computing system 30, the neuromorphic computing unit 10, also known as a ferroelectric nanowire neural network device, includes 16 electrodes 103, labeled 0, 1, 2, ..., 15. Electrode 0 serves as the input electrode, electrodes 1, 2, 12, 13, and 14 serve as output electrodes, outputting five target voltages; electrode 3 serves as the ground electrode, connected to the ground terminal GND; and the remaining electrodes 4, 5, 6, 7, 8, 9, 10, 11, and 15 serve as backup electrodes.

[0087] Based on the intrinsic properties of ferroelectric indium selenide nanowires 1021, under the action of input voltage (i.e., voltage pulse signal), indium selenide nanowires 1021 will output the target voltage in real time as a dynamic feature (i.e., dynamic descriptor) for real-time classification tasks under the coupling effects of electric field, current, pressure effect, and ferroelectric polarization.

[0088] like Figure 5 As shown in (c), the target task is a classification task, and the output layer can be a classifier. The five target voltages output by the neuromorphic computing unit 10 are used as five feature information inputs to the classifier. During the training phase, the classifier is dynamically trained based on all the target voltages, enabling it to identify the target in the image to be detected based on the target voltage. For example, for image 1 to be detected, the classifier can identify the target as the number "5", and for image 2 to be detected, the classifier can identify the target as the number "0". As an example, such as Figure 5 As shown in (c), for this scenario where the target of recognition is a number, the recognition result may be the number "0", "1", "2", ..., "9".

[0089] In another specific implementation, the target task is a sequence recall task, and the object to be detected includes multiple sub-objects;

[0090] The neuromorphic computing unit 10 is also used to output a target current through a ground electrode;

[0091] The output layer 302 is also used to receive the target current and output the detection result of the corresponding sequence recall task based on at least one target voltage and target current; or, the output layer is also used to determine at least one first parameter based on at least one target voltage and at least one target current and output the detection result of the corresponding sequence recall task based on at least one first parameter, wherein the first parameter is resistance or conductance.

[0092] It should be noted that resistance or conductance indicates the ability of the path between the input electrode and the output electrode to carry current. Since the unconventional solid-state amorphization process of indium selenide nanowires requires a certain amount of time, this delay is reflected in the hysteresis of the resistance / conductance of the path. That is, there is a delay in the real-time output of resistance / conductance relative to the target voltage. Based on the hysteresis of resistance / conductance, the nano-neural network layer 102A can have the ability to "memorize" multiple consecutive sub-objects, enabling the reservoir computing system 30 to realize the sequence recall task.

[0093] Resistance or conductance can be calculated from voltage and current, where resistance is the ratio of voltage to current and conductance is the reciprocal of resistance. Using resistance or conductance values ​​as input features for the output layer allows for inference of the detection results for the sequence recall task. The following example... Figure 6 Let's take an example to illustrate.

[0094] like Figure 6 As shown, for the following number sequence: 1, 4, 7, 5, 1, 4, 7, 9, each number is a sub-object. Assume the object to be detected is the sequence to be detected, and the sequence length L = 4, meaning the sequence to be detected includes 4 sub-objects: 7, 5, 1, 4.

[0095] During training, the following inputs are continuously fed into the reservoir computing system 30: 7, 5, 1, 4, 7, 5, 1, 4, ..., 7, 5, 1, 4. Here, it is assumed that each number is as follows: Figure 4 In the image to be detected, each sub-object is a separate image to be detected (digital image). The signal converter first transforms each sub-object, generating an image like... Figure 6 The time-voltage pulse stream (i.e., voltage pulse signal) shown in (a) also has a certain time interval between adjacent sub-objects to distinguish different sub-objects.

[0096] like Figure 6 As shown in (b), the neuromorphic computing unit 10 (or ferroelectric nanowire neural network device) includes 16 electrodes 103, labeled 0, 1, 2, ..., 15. Electrode 0 serves as the input electrode, electrodes 11 and 13 serve as output electrodes, outputting two target voltages; electrode 3 serves as the ground electrode, connected to the ground terminal GND, and is also used to output the target current; the remaining electrodes 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, and 15 serve as spare electrodes.

[0097] Based on the intrinsic properties of ferroelectric indium selenide nanowires, and based on the input target voltage, the indium selenide nanowires, under the coupling effects of electric field, current, pressure, and ferroelectric polarization, will output the target voltage in real time as a dynamic descriptor, while simultaneously detecting the current as another dynamic descriptor. Due to the hysteresis effect of resistance / conductance, the influence of the voltage pulse signal corresponding to the digit "7" on the path resistance / conductance is reflected in the input time of the voltage pulse signals corresponding to the digits "5", "1", and "4", with the influence weakening sequentially over time. Similarly, the influence of the voltage pulse signal corresponding to the digit "5" on the path resistance / conductance is reflected in the input time of the voltage pulse signals corresponding to the digits "1" and "4". Thus, under continuous training with inputs of 7, 5, 1, and 4, when 5, 1, and 4 are known, the output layer can "recall" the previous digit as "7" based on 5, 1, and 4, thereby achieving the sequence recall task.

[0098] In this embodiment, the curve relationship between the current, target voltage, and current can be measured to characterize resistance / conductance. For sequence recall tasks, the output layer can be a trainer. Thus, the target voltage and current can be directly input to the trainer, which uses the change relationship between the target voltage and current as a feature for detection and outputs the detection result. Alternatively, the conductance or resistance can be calculated first based on the target voltage and current, and then the conductance or resistance can be used as a feature for detection, outputting the detection result. Here, there are multiple target voltages, and multiple target voltages correspond to the same current.

[0099] It should also be noted that, for example, with the sequence 7, 5, 1, 4, the trainer, knowing the subsequent digits, uses hysteresis resistance or conductance to "recall" the preceding digits. Assuming "7" is the digit to be "recalled," then 5, 1, and 4 can be known targets, or the trainer can simultaneously function as a classifier, identifying 5, 1, and 4 based on target voltages, and then using hysteresis resistance or conductance to "recall" 7. Here, using three known digits to "recall" a preceding digit is merely an example and does not constitute a limitation on actual "recall" scenarios. For example, with higher accuracy, the trainer can, knowing 4, infer to "recall" 1, then 5, and then 7.

[0100] To obtain the values ​​of voltage and current, such as Figure 6 As shown, the reservoir calculation system 30 also includes a current meter 304 and at least one voltmeter 305;

[0101] Ammeter 304 is connected between the grounding electrode and the grounding terminal to measure the current value of the target current and send it to the output layer 302;

[0102] Voltmeter 305 is connected to the corresponding output electrode and is used to measure the voltage value of the corresponding target voltage and send it to the output layer 302.

[0103] Furthermore, embodiments of this disclosure can also utilize a reservoir computing system 30 to implement multiple tasks. In this case, the target task includes at least one subtask; each subtask corresponds to its own input electrode and at least one output electrode.

[0104] The output layer 302 includes at least one sub-output layer corresponding to at least one sub-task, and each sub-output layer outputs the detection result of the corresponding sub-task.

[0105] It should be noted that in this case, multiple subtasks can share a single neural network computing unit, but they still need to allocate their own signal converters and sub-output layers.

[0106] For example, the two sub-tasks are Task 1 and Task 2, corresponding to Signal Converter 1 and Signal Converter 2, and Sub-output Layer 1 and Sub-output Layer 2, respectively. Assume that the neuromorphic computing unit includes 16 electrodes 103, including: two input electrodes, where input electrode 1 corresponds to Task 1 and receives the input voltage converted by Signal Converter 1, and input electrode 2 corresponds to Task 2 and receives the input voltage converted by Signal Converter 2; eight output electrodes, where input electrodes 1 to 4 correspond to Task 1 and output four target voltages to Sub-output Layer 1, and input electrodes 5 to 8 correspond to Task 2 and output four target voltages to Sub-output Layer 2; one ground electrode is also included, and the remaining electrodes 103 are used as spare electrodes.

[0107] Thus, embodiments of this disclosure can also utilize a single neuromorphic computing unit 10 to perform multiple tasks.

[0108] In short, such as Figure 7 As shown, the neuromorphic computing unit 10 in this embodiment can serve as the reservoir layer in the reservoir computing system 30, or the reservoir computing unit (RCU), to implement reservoir computing.

[0109] In summary, this disclosure presents a voltage-controlled online learning neuromorphic computing unit based on the energy-saving and unconventional solid-state amorphization characteristics of ferroelectric In2Se3 nanowires under the influence of electric field, current, pressure, and ferroelectric polarization coupling. This online learning neuromorphic computing unit features low power consumption and large-scale integration. Specifically, firstly, based on the intrinsic properties of the nanowires, the real-time output voltage, as a dynamic feature, enables online learning of image classification tasks. Furthermore, by voltage-controlled phase transitions between crystalline and amorphous states in the In2Se3 nanowires, various continuous resistance states can be achieved. Based on the correlation between resistances caused by the hysteresis effect of resistance changes, a sequence memory task can be implemented.

[0110] This disclosure also provides a method for preparing the aforementioned neuromorphic computing unit 10, such as... Figure 8 As shown, the preparation method includes the following steps:

[0111] S801: A first substrate 101 is provided, on which a plurality of electrodes 103 are formed; and a second substrate 201 is provided, on which a plurality of nanowires 102 are formed; wherein the nanowires 102 have the characteristic of electrically driven solid-state amorphization.

[0112] It should be noted that the first substrate 101 can be provided first and multiple electrodes 103 can be formed, or the second substrate 201 can be provided first and nanowires 102 can be formed, or both can be performed simultaneously. The embodiments disclosed herein do not specify the order of these actions.

[0113] A plurality of electrodes 103 are formed on the first substrate 101, including:

[0114] An electrode layer 103A is formed above the first substrate 101;

[0115] The electrode layer 103A is patterned to obtain multiple electrodes 103.

[0116] It should be noted that both the first substrate 101 and the second substrate 201 can be silicon substrates or substrates containing other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof. This disclosure does not specifically limit the specific types of substrates.

[0117] like Figure 9 As shown in (a1), an electrode layer 103A is first formed by depositing a conductive material on top of the first substrate 101. The conductive material can be a conductive metal (such as tungsten, copper), titanium nitride, etc.

[0118] The electrode layer 103A is patterned into a plurality of electrodes 103. For example, the specific steps of the patterning process may be: forming a mask layer or photoresist layer with electrode patterns over the electrode layer 103A, wherein the mask layer or photoresist layer covers the area of ​​the electrode layer 103A that needs to be retained to form the electrodes 103, and exposes the area of ​​the electrode layer 103A that needs to be removed.

[0119] The electrode layer 103A exposed by the mask layer is removed, for example by etching, to transfer the electrode pattern to the electrode layer 103A. The mask layer is then removed by etching to obtain multiple electrodes 103. Specifically, as shown... Figure 9 As shown in (b1), there are 10 electrodes 103, and the shape of the electrodes 103 resembles a matchstick. It should be noted that... Figure 9 The number, shape, and arrangement of the electrodes 103 shown are only examples. The specific shape and number of electrodes 103 can be designed according to actual needs and are not specifically limited. However, it is usually necessary to ensure that there are at least three electrodes 103, which serve as input electrodes, output electrodes, and ground electrodes respectively.

[0120] In some embodiments, a plurality of nanowires 102 are formed on the second substrate 201, including:

[0121] Multiple catalyst nanoparticles 1022 are formed above the second substrate 201;

[0122] Using catalyst nanoparticles 1022 as seeds, materials with electrically driven solid-state amorphization characteristics are grown to obtain multiple nanowire bodies 1021; one end of the nanowire body 1021 is connected to the second substrate 201, and the other end is connected to the catalyst nanoparticles 1022. The nanowire bodies 1021 and the catalyst nanoparticles 1022 constitute nanowires 102.

[0123] It should be noted that in the embodiments disclosed herein, the nanowire body 1021 can be indium selenide nanowires, and the catalyst nanoparticles 1022 can be gold-palladium (Au-Pd) nanoparticles.

[0124] Catalyst nanoparticles 1022 can act as seeds to induce the growth of indium selenide into nanowires. The width of the indium selenide nanowires (i.e., the dimension in the direction perpendicular to the nanowire extension direction) depends on the diameter of the catalyst nanoparticles 1022; that is, the width of the indium selenide nanowires 1021 equals the diameter of the catalyst nanoparticles 1022. Therefore, by controlling the process parameters for forming the catalyst nanoparticles 1022, catalyst nanoparticles 1022 of the desired size can be prepared, thereby obtaining indium selenide nanowires 1021 of the desired size.

[0125] The catalyst nanoparticles 1022 can be prepared using methods such as chemical reduction, sputtering evaporation, electrochemical deposition, laser ablation, and various heat treatments. Figure 9 In this study, the overall process for preparing nanowires 102 is the vapor-liquid-solid (VLS) method.

[0126] For example, such as Figure 9 As shown in (a2), a catalyst material (such as gold-palladium) is first deposited on top of the second substrate 201 to form a catalyst layer 202 (such as a gold-palladium layer, i.e., an Au-Pd layer). Then, the gold-palladium layer is processed into nanoparticles. For example, the gold-palladium layer is first heated to a molten state, forming liquid particles, and then cooled to solidify the liquid particles to obtain catalyst nanoparticles 1022, specifically as follows... Figure 9 As shown in (b2) above. Here, the heating temperature, heating rate, cooling rate, etc., can all be adjusted and controlled to obtain catalyst nanoparticles 1022 of the desired size.

[0127] Next, the prepared catalyst nanoparticles 1022 were used as seeds to induce the growth of indium selenide nanowires 1021. For example, as shown... Figure 9As shown in (c2), an inert gas (e.g., argon) is introduced, and the gas flow simultaneously carries indium selenide powder to be uniformly distributed on the second substrate 201. The temperature is then raised to a level sufficient for nucleation growth (e.g., around 700°C), and maintained for a certain growth time (e.g., 3–6 hours, the specific time depending on the desired length of the indium selenide nanowire 1021). The indium selenide grows towards the second substrate 201, and the resulting indium selenide nanowire 1021 is shown in Figure 1. Figure 9 As shown in (d2), one end of the indium selenide nanowire 1021 is located on the second substrate 201, and the other end is connected to the catalyst nanoparticle 1022. It can be understood that the growth of the indium selenide nanowire 1021 is affected by various factors such as process conditions and growth mechanism, and its extension direction is often random and arbitrary, such as... Figure 9 As shown in (d2), it may be perpendicular to the second substrate 201, or it may intersect the second substrate 201 at a certain angle, or it may be parallel to or almost parallel to the second substrate 201. In this case, the side of the indium selenide nanowire 1021 is almost completely in contact with the second substrate 201.

[0128] In this scheme, the preparation of In2Se3 nanowires by the VLS method requires the assistance of a specific catalyst (i.e., Au-Pd metal particles). For example... Figure 9 As shown, In2Se3 powder is blown onto the second substrate 201 by argon gas, where it adheres to the catalyst nanoparticles 1022 and nucleates. The nanowires then grow in the reverse direction along the catalyst nanoparticles 1022, with the size (width) of the nanowires uniquely determined by the diameter of the catalyst nanoparticles 1022. Finally, the nanowires 102 with the catalyst nanoparticles 1022 are arbitrarily arranged on the first substrate 101.

[0129] S802: Transfer multiple nanowires 102 to the surface of the first substrate 101 on which multiple electrodes 103 are formed, and remove the second substrate 201 to obtain a neuromorphic computing unit; wherein, the multiple nanowires 102 form a nano-neural network layer 102A, and the multiple electrodes 103 are distributed in the nano-neural network layer 102A.

[0130] It should be noted that after step S801, both the electrode 103 and the nanowire 102 have been prepared. Next, the nanowire 102 needs to be transferred to the first substrate 101 where the electrode 103 is located.

[0131] For example, such as Figure 9 As shown in (c1), the nanowires 102 can be transferred via contact printing. The process is briefly described below:

[0132] First, a template with nanopatterns is prepared, which is equivalent to the second substrate 201 with nanowires 102 prepared in this scheme; and a thermoplastic polymer photoresist is coated on the substrate (equivalent to the first substrate 101 with electrodes 103 prepared in this scheme).

[0133] Then, the side of the second substrate 201 with nanowires 102 formed is pressed into the high-temperature softened photoresist and maintained at a certain high temperature and high pressure for a period of time.

[0134] Irradiation with ultraviolet light causes the photoresist to harden and solidify.

[0135] After final cooling and solidification, the second substrate 201 is removed by demolding, and residual photoresist is etched away. The demolding process can be a lift-off process. The final result is as follows: Figure 9 The neuromorphic computing unit is shown in (d1). Under pressure, the morphology of the nanowire 102 no longer resembles... Figure 9 The (d2) shown is perpendicular or approximately perpendicular to the surface of the first substrate 101 / second substrate 201 or intersects at a certain angle, but is pressed to be parallel or almost parallel to the surface of the first substrate 101, forming a nanowire neural network 102A, and multiple electrodes 103 are distributed in the nanowire neural network 102A.

[0136] In other words, the nanowires 102 that were originally grown vertically or nearly vertically are transferred to the first substrate 101 with electrodes 103 by "contact printing". The catalyst nanoparticles 1022 are in direct contact with the first substrate 101. In this case, specific metal particles (i.e., catalyst nanoparticles 1022) can be directly observed on the first substrate 101.

[0137] The preparation of In₂Se₃ nanowires using the VLS method requires a specific catalyst (Au-Pd metal particles). Therefore, catalyst particles are observable on the sample, and the preparation process can be determined by characterizing the particle composition (Au-Pd), particle size (diameter), and component abundance. This method can estimate the density of nanowires 10₂ based on the density of the catalyst nanoparticles 10₂.

[0138] Furthermore, based on the foregoing steps, embodiments of this disclosure can also integrate and fabricate multiple neuromorphic computing units on a large scale. Therefore, when forming multiple electrodes 103 on the first substrate 101, the method may further include:

[0139] An isolation structure is formed on the first substrate 101, and the multiple electrodes 103 are divided into multiple groups of electrodes 103 by the isolation structure.

[0140] Correspondingly, after removing the second substrate 201, the method further includes:

[0141] By removing the isolation structure, multiple neuromorphic computing units are obtained.

[0142] It should be noted that, as Figure 10 As shown, taking the simultaneous fabrication of four neuromorphic computing units as an example, before forming the electrode layer 103A, a cross-shaped isolation structure 104 is first formed above the first substrate 101. The isolation structure 104 divides the surface of the first substrate 101 into four regions, and conductive material is deposited in each region to form the electrode layer 103A. Due to the isolation effect of the isolation structure 104, the electrode layers 103A in the four regions are isolated from each other and will not connect to each other. Then, patterning is performed to obtain the following... Figure 10 The structure shown in (a) is as follows. The material of the isolation structure 104 can be photoresist, and the isolation structure 104 can be formed by deposition. Alternatively, a complete conductive layer can be first formed on the first substrate 101, then the conductive layer is patterned to form a cross-shaped groove, photoresist is deposited in the groove to obtain the isolation structure 104, and then the patterning process for forming the electrode 103 is performed to obtain the structure shown in (a). Figure 10 The structure shown in (a) is shown in the image.

[0143] The area of ​​the second substrate 201 corresponds to that of the first substrate 101. After forming indium selenide nanowires 1021 on the surface of the second substrate 201, as follows... Figure 10 As shown in (b), indium selenide nanowires 1021 are transferred to the surface of a first substrate 101. Then, the second substrate 201 is removed by demolding, resulting in the structure shown in Figure 1021. Figure 10 As shown in (c) above. Finally, the isolation structure 104 is removed, resulting in the following: Figure 10 The four independent neuromorphic computational units are shown in (d) in the figure.

[0144] It should be noted that, Figure 10 The four neuromorphic computational units shown are for illustrative purposes only. Figure 11 A schematic diagram of the structure after obtaining electrode 103 when forming 16 neuromorphic computing units is also shown. The process is similar for fabricating more or fewer neuromorphic computing units, and will not be described in detail here.

[0145] In summary, the fabrication process of this neural network computing unit is as follows: First, based on the VSL mechanism, ferroelectric In2Se3 nanowires are grown on a Si substrate using an Au-Pd catalyst; second, a metal electrode layer is deposited on the Si substrate and patterned to form multiple electrodes, wherein electron beam etching can be used for patterning; third, the In2Se3 nanowires are transferred to the first substrate containing the electrodes using a contact printing method; fourth, the second substrate is removed. This fabrication scheme can be used for the large-scale integration of online learning neuromorphic computing units.

[0146] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0147] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0148] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0149] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0151] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0152] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A neuromorphic computing unit, characterized in that, include: First substrate; Multiple nanowires and multiple electrodes formed on the first substrate; The plurality of nanowires form a nano-neural network layer, and the plurality of electrodes are distributed within the nano-neural network layer; wherein, the nanowires have the characteristic of electrically driven solid-state amorphization; The plurality of electrodes includes an input electrode, a ground electrode, and at least one output electrode; wherein the input electrode is used to receive an input voltage, the output electrode is used to output a target voltage, and the target voltage serves as characteristic information for achieving the target task.

2. The neuromorphic computing unit according to claim 1, characterized in that, The nanowires are grown from catalyst nanoparticles and include a nanowire body and the catalyst nanoparticles. The width of the nanowire body is equal to the diameter of the catalyst nanoparticles.

3. The neuromorphic computing unit according to claim 2, characterized in that, The nanowire body is indium selenide nanowire, and the catalyst nanoparticles are gold palladium nanoparticles.

4. The neuromorphic computing unit according to claim 1, characterized in that, The target task is a classification task and / or a sequence recall task.

5. A method for preparing a neuromorphic computing unit, characterized in that, The method includes: A first substrate is provided on which a plurality of electrodes are formed; and a second substrate is provided on which a plurality of nanowires are formed; wherein the nanowires have the property of electrically driven solid-state amorphization. The plurality of nanowires are transferred to the surface of the first substrate on which the plurality of electrodes are formed, and the second substrate is removed to obtain the neuromorphic computing unit; wherein the plurality of nanowires form a nano-neural network layer, and the plurality of electrodes are distributed within the nano-neural network layer.

6. The method according to claim 5, characterized in that, The formation of multiple electrodes on the first substrate includes: An electrode layer is formed above the first substrate; The electrode layer is patterned to obtain the plurality of electrodes.

7. The method according to claim 5, characterized in that, The formation of multiple nanowires on the second substrate includes: Multiple catalyst nanoparticles are formed on the second substrate; Using the catalyst nanoparticles as seeds, materials with the characteristics of electrically driven solid-state amorphization are grown to obtain multiple nanowire bodies; one end of each nanowire body is connected to the second substrate, and the other end is connected to the catalyst nanoparticles, and the nanowire bodies and the catalyst nanoparticles constitute the nanowires.

8. The method according to claim 7, characterized in that, The nanowire body is indium selenide nanowire, and the catalyst nanoparticles are gold palladium nanoparticles.

9. The method according to claim 5, characterized in that, When multiple electrodes are formed on the first substrate, the method further includes: An isolation structure is formed on the first substrate, and the plurality of electrodes are divided into multiple groups of electrodes by the isolation structure; Correspondingly, after removing the second substrate, the method further includes: By removing the isolation structure, multiple neuromorphic computing units are obtained.

10. A reservoir calculation system, characterized in that, include: A signal converter is used to receive the object to be detected and convert the object to be detected into a voltage pulse signal; The neuromorphic computing unit as described in any one of claims 1 to 4 is configured to receive the voltage pulse signal through the input electrode and output at least one target voltage through the at least one output electrode; An output layer is used to receive the at least one target voltage and output the detection result corresponding to the target task based on the at least one target voltage.

11. The reservoir calculation system according to claim 10, characterized in that, The target task is a classification task, and the objects to be detected include the images to be detected.

12. The reservoir calculation system according to claim 10, characterized in that, The target task is a sequence recall task, and the object to be detected includes multiple sub-objects; The neuromorphic computing unit is also used to output a target current through the grounding electrode; The output layer is further configured to receive the target current and output a detection result corresponding to the sequence recall task based on the at least one target voltage and the target current; or, the output layer is further configured to determine at least one first parameter based on the at least one target voltage and the at least one target current, and output a detection result corresponding to the sequence recall task based on the at least one first parameter, wherein the first parameter is resistance or conductance.

13. The reservoir calculation system according to claim 12, characterized in that, The reservoir calculation system also includes an ammeter and at least one voltmeter; The ammeter is connected between the grounding electrode and the grounding terminal and is used to measure the current value of the target current. The voltmeter is connected to the corresponding output electrode and is used to measure the voltage value of the corresponding target voltage.

14. The reservoir calculation system according to claim 10, characterized in that, The target task includes at least one sub-task; each sub-task corresponds to its own input electrode and at least one output electrode. The output layer includes at least one sub-output layer corresponding to the at least one sub-task, and each sub-output layer outputs the detection result of the corresponding sub-task.

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