Monitoring method and system for sram boundary failure model

Abstract

This invention provides a monitoring method and system for SRAM boundary failure models. The method includes: acquiring the physical layout of the SRAM chip; dividing the SRAM memory array into its smallest analysis unit based on the physical layout; dividing the SRAM chip into multiple physical modules according to analysis requirements, and calculating the boundary coordinates of each physical module using the smallest analysis unit as the unit of measurement; acquiring failure test data of the SRAM chip and statistically analyzing the failure status at each boundary location; generating a corresponding canvas based on the size of the multiple physical modules into which the SRAM chip is divided, and displaying the smallest analysis unit of failure on the canvas. This invention has the significant advantages of quantifiable data, visualized location, and timely feedback, and is suitable for failure monitoring and process health monitoring of various SRAM products.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing and integrated circuit testing and analysis technology, and in particular to a monitoring method and system for SRAM boundary failure models. Background Technology

[0002] In the semiconductor manufacturing industry, failure analysis has always been a crucial step in ensuring chip yield and driving process development iterations. Identifying and resolving the causes of chip failures through various analytical methods is of great significance for improving R&D progress, enhancing process health, and achieving customer yield expectations.

[0003] SRAM (Static Random Access Memory) chips are widely used in the industry as one of the most common tools for monitoring the health of mature process platforms and developing new process platforms due to their compact and regular structure, manufacturing process that is closer to that of logic products, and extreme sensitivity to process variations. Consequently, failure analysis methods for SRAM chips have always been a key research focus in the field of semiconductor engineering.

[0004] Currently, the mainstream analytical methods for SRAM failures in the industry are mainly divided into two categories:

[0005] (1) Electrical Failure Analysis (EFA): Through probe testing, voltage contrast imaging and other techniques, electrical diagnosis is performed on the failed chip to initially locate the failure area or failure unit.

[0006] (2) Physical Failure Analysis (PFA): Based on EFA localization, the failure point is directly observed and its mechanism is confirmed at the physical level through destructive means such as delamination, focused ion beam (FIB) cutting, and transmission electron microscopy (TEM).

[0007] Long-term industry practice has shown that the traditional analytical process relying on EFA and PFA has the following significant shortcomings:

[0008] First, the timeliness is poor. When a failure first occurs, it is necessary to first use EFA and PFA methods to summarize the problem, which cannot be fed back to the production line for self-inspection of the cause in a timely manner, often missing the best window of opportunity for process debugging.

[0009] Second, the conclusions are difficult to quantify and reproduce. PFA analysis relies on destructive sectioning and observation of a limited number of samples (usually a few to dozens of chips). The conclusions obtained are greatly affected by individual differences in the samples and are difficult to replicate. A lot of manpower and resources are needed for reproducible sectioning verification.

[0010] Third, a long-term monitoring mechanism cannot be established. Because the PFA conclusions for each failed chip are relatively isolated, it is impossible to form effective data to monitor the process fluctuations of the failure, making it difficult to achieve continuous and dynamic tracking and early warning of process fluctuations.

[0011] Especially in advanced process nodes, the HKMG (high dielectric metal gate) process, due to the complexity of process steps and the narrow process window, certain systematic failure modes, such as metal gate filling defects at array boundaries caused by pattern loading, will recur. However, such failures usually manifest as "soft failures" or sporadic yield losses in the early stages. Traditional PFA processes struggle to distinguish them from random defects, making it difficult for process teams to identify the systemic root cause of the failure in a timely manner, let alone establish targeted prevention and monitoring systems. Summary of the Invention

[0012] The purpose of this invention is to provide a monitoring method and system for SRAM boundary failure models, which has the outstanding advantages of quantifiable data, visualized location, and timely feedback, and is applicable to failure monitoring and process health monitoring of various SRAM products.

[0013] To achieve the above objectives, the present invention provides a monitoring method for SRAM boundary failure models, comprising:

[0014] Obtain the physical layout of the SRAM chip, and based on the physical layout, divide the smallest analysis unit of the SRAM memory array;

[0015] According to the analysis requirements, the SRAM chip is divided into multiple physical modules, and the boundary coordinates of each physical module are calculated using the smallest analysis unit as the unit of measurement.

[0016] Acquire the failure test data of the SRAM chip and statistically analyze the failure status at each boundary location;

[0017] A corresponding canvas is generated based on the size of the multiple physical modules into which the SRAM chip is divided, and the smallest analysis unit that fails is displayed in the canvas.

[0018] Optionally, the minimum analysis unit is the minimum logical unit region defined according to the analysis requirements.

[0019] Optionally, the minimum analysis unit is obtained based on the minimum physical region division of the SRAM chip.

[0020] Optionally, the smallest physical region is a bit cell of the SRAM storage array.

[0021] Optionally, the failed minimum analysis units can be displayed on the canvas in the form of a density distribution.

[0022] Optionally, the method for statistically analyzing failures at each boundary location includes: marking the boundary coordinates as boundary types, matching the failure locations with the boundary coordinates, and statistically analyzing failures at each boundary location.

[0023] Optionally, the failure status at each boundary location includes at least the number of failed minimum analysis units and the proportion of the number of failed minimum analysis units at each boundary location to the total number of failed minimum analysis units on the SRAM chip.

[0024] Optionally, in the canvas, border lines and frames are overlaid on the boundaries of the physical modules to indicate the boundary positions of each physical module.

[0025] Based on another aspect of the present invention, the present invention also provides a monitoring system for an SRAM boundary failure model, comprising:

[0026] The partitioning module is used to obtain the physical layout of the SRAM chip and, based on the physical layout, partition the smallest analysis unit of the SRAM memory array.

[0027] The coordinate calculation module divides the SRAM chip into multiple physical modules according to the analysis requirements, and calculates the boundary coordinates of each physical module using the smallest analysis unit as the unit of measurement.

[0028] The failure statistics module acquires the failure test data of the SRAM chip and counts the failure status at each boundary position.

[0029] A visualization module is used to generate a corresponding canvas based on the size of the multiple physical modules into which the SRAM chip is divided, and to display the smallest analysis unit of failure in the canvas.

[0030] In another aspect, the present invention also provides a storage medium having a program stored thereon, which, when executed, implements the monitoring method for the SRAM boundary failure model as described above.

[0031] As described above, traditional SRAM failure analysis relies on EFA and PFA methods, which suffer from drawbacks such as poor timeliness, difficulty in quantifying and reproducing conclusions, and the inability to establish a long-term monitoring mechanism. This invention divides the SRAM chip into multiple physical modules and calculates boundary coordinates using the smallest analysis unit as the unit of measurement. By matching and statistically analyzing failure test data with boundary coordinates, it can quantify and output the number of smallest analysis units at each boundary location and their proportion of all failures, thus obtaining quantifiable and statistically significant data indicators. Furthermore, it can distinguish the problem of insufficient front-end process windows caused by pattern loading changes from other random defect failures, achieving long-term quantitative monitoring of specific boundary failure types. Further, this invention generates a corresponding canvas based on the size of each physical module, displaying the smallest analysis units of failure in the form of a density distribution on the canvas. Edge lines and frames are overlaid on the boundaries of the physical modules to indicate their locations. Engineers can intuitively determine the concentrated failure areas by observing the density distribution on the canvas, and quickly identify whether the failure occurs at the edge of the physical module by using the edge lines and frames. This invention can output monitoring results through data statistics and visualization at the initial stage of failure, eliminating the need for time-consuming EFA and PFA methods to summarize problems and providing feedback to the R&D department on anomalies. By observing the fluctuation trends of quantitative indicators such as the failure rate at the boundary, it can promptly identify deficiencies in the process window, providing the R&D department with a clear direction for quickly finding the causes of process failures, thereby effectively improving process development efficiency and yield improvement speed. In summary, this invention has outstanding advantages such as quantifiable data, visualized location, and timely feedback, and is suitable for failure monitoring and process health monitoring of various SRAM products. Attached Figure Description

[0032] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0033] Figure 1 This is a flowchart of a monitoring method for an SRAM boundary failure model according to an embodiment of the present invention;

[0034] Figure 2 This is a distribution diagram of bitwise failures according to an embodiment of the present invention;

[0035] Figure 3 This is a statistical demonstration diagram of boundary failure and other failure types according to an embodiment of the present invention;

[0036] Figure 4 This is a failure density distribution image according to an embodiment of the present invention;

[0037] Figure 5 This is a visualization of the boundary failure distribution according to an embodiment of the present invention. Detailed Implementation

[0038] In this document, unless otherwise stated, the terms “upper,” “lower,” “left,” “right,” “inner,” “outer,” “front,” “back,” “top,” “bottom,” etc., are used to indicate orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a characteristic orientation and operation, and therefore should not be construed as a limitation of the invention.

[0039] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] Please refer to Figures 1 to 5 This invention provides a monitoring method for SRAM boundary failure models, which includes steps S1, S2, S3 and S4. Steps S1, S2, S3 and S4 are described in detail below.

[0041] Step S1: Obtain the physical layout of the SRAM chip, and based on the physical layout, divide the smallest analysis unit of the SRAM memory array.

[0042] It is understood that the minimum analysis unit can be the minimum logical unit region defined according to the analysis requirements. The minimum analysis unit can also be obtained based on the minimum physical region of the SRAM chip. For example, the minimum physical region is a bit cell of the SRAM memory array, that is, the minimum physical region is a bit cell of the SRAM memory array (i.e., a single storage bit on the physical layout, corresponding to a data storage structure of one bit).

[0043] Step S2: Divide the SRAM chip into multiple physical modules according to the analysis requirements (the multiple physical modules can be the same size or different sizes, and are divided as needed), and calculate the boundary coordinates of each physical module using the smallest analysis unit as the unit of measurement.

[0044] Step S3: Obtain the failure test data of the SRAM chip and statistically analyze the failure status at each boundary location.

[0045] Specifically, the method for statistically analyzing failures at each boundary location includes: marking the boundary coordinates as boundary types to identify the edge positions of the physical module; matching the failure locations with the boundary coordinates; and statistically analyzing failures at each boundary location. Furthermore, the failure statistics at each boundary location include at least the number of failed minimum analysis units (MINUs) and the proportion of the number of failed MINUs at each boundary location to the total number of failed MINUs on the SRAM chip, i.e., the failure ratio. For example, an algorithm can be used to generate data such as the number of failed MINUs at the corresponding boundary coordinate locations and the failure ratio. It is understood that not only should failures at boundary locations be statistically analyzed, but failures within the physical module should also be analyzed; this is simply an emphasis on specifically marking and statistically analyzing failures at boundary locations. Please refer to [reference needed]. Figure 2 , Figure 2 The graph shows the distribution of failures by bit. The horizontal axis represents the memory bit number, arranged sequentially from the 1st to the 252nd memory bit in the SRAM chip. The vertical axis represents the number of the smallest analysis unit where a failure occurs at each memory bit location.

[0046] Please refer to Figure 3 , Figure 3 This is a statistical demonstration chart showing boundary failures and other failure types obtained from statistical analysis of test samples using this monitoring method. The chart shows the product code, lot number, wafer number (wafer column), test time, total number of chips on the wafer, and test conditions. Column SB represents the single-memory bit failure rate, column DBC represents the failure rate of adjacent dual-memory bits in the same column, column DBR represents the failure rate of adjacent dual-memory bits in the same row, column Array E represents the array edge failure rate, and column Instance E represents the submodule edge failure rate. Array and Instance represent partitioning by two different sizes of physical modules, respectively. Figure 3 The data shows that under low-voltage (LV) testing conditions, the failure rate at the array edge (Array E) is significantly higher than other types of failures. For example, the total failure rate of wafer 3 under low-voltage testing conditions is 97.6%, with array edge failures accounting for 51.8%; the total failure rate of wafer 9 under low-voltage testing conditions is 80.5%, with array edge failures accounting for 58.5%. This indicates that failures in the array edge region are not randomly distributed but exhibit obvious systematic patterns, necessitating the development of specialized monitoring methods for this specific failure model.

[0047] Step S4: Generate a corresponding canvas based on the size of the multiple physical modules into which the SRAM chip is divided, and display the smallest analysis unit that failed in the canvas.

[0048] Furthermore, the failed minimum analysis units are displayed on the canvas in the form of a density distribution, for example, the failed bits are displayed on the canvas in the form of a density distribution. Preferably, in the canvas, border lines and frames are superimposed on the boundaries of the physical modules to indicate the boundary positions of each physical module, which can more intuitively show the failure situation at the boundary positions. Please refer to... Figure 4 , Figure 4 This is a failure density distribution image. Figure 4 In this context, INS stands for Instance (submodule). Figure 4 The densely packed white areas indicate a high failure density. Please refer to [the relevant documentation]. Figure 5 In the figure, the horizontal axis SCOL represents the column position number in units of the smallest analysis unit (bit in this embodiment), and the vertical axis SROW represents the row position number in units of the smallest analysis unit (bit in this embodiment). Each colored dot represents a smallest analysis unit that has failed. The figure also shows the boundary lines of the physical modules, used to indicate the boundary positions of each physical module. Figure 5 As shown, some failure points are concentrated near or above the boundary lines, indicating that this type of failure has obvious boundary clustering characteristics.

[0049] Based on another aspect of the present invention, the present invention also provides a monitoring system for an SRAM boundary failure model, comprising:

[0050] The partitioning module is used to obtain the physical layout of the SRAM chip and, based on the physical layout, partition the smallest analysis unit of the SRAM memory array.

[0051] The coordinate calculation module divides the SRAM chip into multiple physical modules according to the analysis requirements, and calculates the boundary coordinates of each physical module using the smallest analysis unit as the unit of measurement.

[0052] The failure statistics module acquires the failure test data of the SRAM chip and counts the failure status at each boundary position.

[0053] A visualization module is used to generate a corresponding canvas based on the size of the multiple physical modules into which the SRAM chip is divided, and to display the smallest analysis unit of failure in the canvas.

[0054] In another aspect, the present invention also provides a storage medium having a program stored thereon, which, when executed, implements the monitoring method for the SRAM boundary failure model as described above.

[0055] As described above, traditional SRAM failure analysis relies on EFA and PFA methods, which suffer from drawbacks such as poor timeliness, difficulty in quantifying and reproducing conclusions, and the inability to establish a long-term monitoring mechanism. This invention divides the SRAM chip into multiple physical modules and calculates boundary coordinates using the smallest analysis unit as the unit of measurement. By matching and statistically analyzing failure test data with boundary coordinates, it can quantify and output the number of smallest analysis units at each boundary location and their proportion of all failures, thus obtaining quantifiable and statistically significant data indicators. Furthermore, it can distinguish the problem of insufficient front-end process windows caused by pattern loading changes from other random defect failures, achieving long-term quantitative monitoring of specific boundary failure types. Further, this invention generates a corresponding canvas based on the size of each physical module, displaying the smallest analysis units of failure in the form of a density distribution on the canvas. Edge lines and frames are overlaid on the boundaries of the physical modules to indicate their locations. Engineers can intuitively determine the concentrated failure areas by observing the density distribution on the canvas, and quickly identify whether the failure occurs at the edge of the physical module by using the edge lines and frames. This invention can output monitoring results through data statistics and visualization at the initial stage of failure, eliminating the need for time-consuming EFA and PFA methods to summarize problems and providing feedback to the R&D department on anomalies. By observing the fluctuation trends of quantitative indicators such as the failure rate at the boundary, it can promptly identify deficiencies in the process window, providing the R&D department with a clear direction for quickly finding the causes of process failures, thereby effectively improving process development efficiency and yield improvement speed. In summary, this invention has outstanding advantages such as quantifiable data, visualized location, and timely feedback, and is suitable for failure monitoring and process health monitoring of various SRAM products.

[0056] It should be noted that references to "an embodiment," "an embodiment," "a specific embodiment," "some embodiments," etc., in the specification only indicate that the described embodiment may include a specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other embodiments is within the knowledge of those skilled in the art.

[0057] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0058] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0059] It should also be understood that, unless otherwise specified or indicated, the terms “first,” “second,” “third,” etc., in the specification are used only to distinguish the various components, elements, and steps in the specification, and not to indicate the logical or sequential relationships between the various components, elements, and steps.

[0060] Furthermore, it should be recognized that the terminology described herein is used only to describe particular embodiments and is not intended to limit the scope of the invention. It must be noted that the singular forms “a” and “an” as used herein include plural bases unless the context clearly indicates otherwise. For example, a reference to “a step” or “an apparatus” means a reference to one or more steps or apparatuses, and may include secondary steps and secondary apparatuses. All conjunctions used should be understood in the broadest sense. Also, the word “or” should be understood to have the definition of logical “or” rather than logical “exclusive OR”, unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or devices in embodiments of the invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A monitoring method for SRAM boundary failure models, characterized in that, include: Obtain the physical layout of the SRAM chip, and based on the physical layout, divide the smallest analysis unit of the SRAM memory array; According to the analysis requirements, the SRAM chip is divided into multiple physical modules, and the boundary coordinates of each physical module are calculated using the smallest analysis unit as the unit of measurement. Acquire the failure test data of the SRAM chip and statistically analyze the failure status at each boundary location; A corresponding canvas is generated based on the size of the multiple physical modules into which the SRAM chip is divided, and the smallest analysis unit that fails is displayed in the canvas.

2. The monitoring method for SRAM boundary failure models as described in claim 1, characterized in that, The minimum analysis unit is the smallest logical unit region defined according to the analysis requirements.

3. The monitoring method for SRAM boundary failure models as described in claim 1, characterized in that, The minimum analysis unit is obtained based on the minimum physical region division of the SRAM chip.

4. The monitoring method for SRAM boundary failure models as described in claim 3, characterized in that, The smallest physical region is the bit cell of the SRAM storage array.

5. The monitoring method for SRAM boundary failure models as described in claim 1, characterized in that, The failed minimum analysis unit is displayed on the canvas in the form of a density distribution.

6. The monitoring method for SRAM boundary failure models as described in claim 1, characterized in that, The method for statistically analyzing failures at each boundary location includes: marking the boundary coordinates as boundary types, matching the failure locations with the boundary coordinates, and statistically analyzing failures at each boundary location.

7. The monitoring method for SRAM boundary failure models as described in claim 1, characterized in that, The failure status at each boundary location includes at least the number of failed minimum analysis units and the proportion of the number of failed minimum analysis units at each boundary location to the total number of failed minimum analysis units on the SRAM chip.

8. The monitoring method for SRAM boundary failure models as described in claim 1, characterized in that, In the canvas, border lines and frames are overlaid on the boundaries of the physical modules to indicate the boundary positions of each physical module.

9. A monitoring system for SRAM boundary failure models, characterized in that, include: The partitioning module is used to obtain the physical layout of the SRAM chip and, based on the physical layout, partition the smallest analysis unit of the SRAM memory array. The coordinate calculation module divides the SRAM chip into multiple physical modules according to the analysis requirements, and calculates the boundary coordinates of each physical module using the smallest analysis unit as the unit of measurement. The failure statistics module acquires the failure test data of the SRAM chip and counts the failure status at each boundary position. A visualization module is used to generate a corresponding canvas based on the size of the multiple physical modules into which the SRAM chip is divided, and to display the smallest analysis unit of failure in the canvas.

10. A storage medium having a program stored thereon, characterized in that, When the program is executed, it implements the monitoring method for the SRAM boundary failure model as described in any one of claims 1-8.

Images