An aircraft data recording device and method

Abstract

This invention discloses an aircraft data recording device and method, belonging to the field of data acquisition and recording technology. The device includes a data acquisition board, a storage control board, and an inter-board connection component. The data acquisition board includes a main control chip and multiple data source interfaces arranged around the main control chip, used to receive data from each data source interface, merge multiple data streams into a single data stream in a time-division multiplexing manner, and then output it. The storage control board is separately configured from the data acquisition board, used to receive the data stream output by the data acquisition board, and without parsing the data stream, directly writes the data stream into the storage chip. The inter-board connection component realizes the data transmission and power supply connection between the two. This invention, by separating the data acquisition and storage control functions, reduces software complexity and chip power consumption, simplifies the storage control logic, improves interface expansion flexibility, data security and maintainability, improves heat dissipation, enhances system reliability, and simultaneously ensures the hardware stability of the high-frequency storage circuit.

Description

Technical Field

[0001] This invention belongs to the field of data acquisition and recording technology, specifically relating to an aircraft data recording device and method. Background Technology

[0002] The aircraft data recording device is used to collect data from multiple data source interfaces, frame and store it in a storage chip, and can read the data back to the host computer according to instructions. Currently, its data acquisition solution generally adopts an integrated board design, that is, data acquisition and storage control are integrated on the same printed circuit board, and processed by a single high-performance SOC chip. The advantage of this solution is that the hardware structure is compact and all functions can be implemented with a single software.

[0003] However, this plan has the following problems: First, the software is large in scale and highly coupled. A single chip needs to handle multiple protocol data reception, framing, cache management, storage writing, and readback responses simultaneously. Interface changes often involve multiple code modifications, increasing development difficulty and reducing system reliability.

[0004] Second, chip power consumption and heat dissipation are prominent issues. The concurrent reception and real-time storage of multiple data streams place high demands on chip performance. High-power chips are prone to heat accumulation in the confined space of an aircraft, increasing the difficulty of heat dissipation design.

[0005] Third, the contradiction between hardware scalability and miniaturization is difficult to reconcile. To adapt to the interface requirements of different projects, either the hardware must be redesigned for each project, resulting in longer cycle times and low reusability; or all commonly used interfaces must be pre-integrated on the board, resulting in an increased cross-sectional area of ​​a single printed circuit board, which is unsuitable for space-constrained aircraft.

[0006] To address the aforementioned issues, a new data acquisition scheme for aircraft data recording devices needs to be proposed to reduce software size and chip performance requirements, while flexibly adapting to multiple data source interfaces within a limited space and minimizing hardware design changes. Summary of the Invention

[0007] In view of one or more of the above-mentioned defects or improvement needs of the prior art, the present invention provides an aircraft data recording device and method, which separates the data acquisition and data storage of the aircraft data recording device in hardware. The data acquisition board receives data from various data source interfaces, adds a specific frame header to the data from each data interface, and then transmits the data to the storage control board responsible for storage control board for data storage via a detachable board-mounted flexible cable.

[0008] To achieve the above objectives, according to one aspect of the present invention, an aircraft data recording device is provided, comprising: The data acquisition board includes a main control chip and multiple data source interfaces arranged around the main control chip, which are used to receive data from each data source interface, merge multiple data streams into a single data stream in a time-division manner, and then output the data. The storage control board is set separately from the data acquisition board. It is used to receive the data stream output by the data acquisition board, but does not parse the data stream and directly writes the data stream into the storage chip. An inter-board connection component is disposed between the data acquisition board and the storage control board to realize data transmission and power supply connection between the data acquisition board and the storage control board.

[0009] As a further improvement of the present invention, the main control chip is a heterogeneous system-on-a-chip that integrates a processor core and a programmable logic core, and the chip also integrates a storage unit.

[0010] As a further improvement of the present invention, the plurality of data source interfaces include a first type of interface connected to the programmable logic core and a second type of interface connected to the processor core, wherein the first type of interface is used to receive high-speed parallel data and the second type of interface is used to receive protocol-type data. The first type of interface includes RS422 interface, LVDS interface and wired telemetry PCM interface, and the second type of interface includes CAN bus interface and Ethernet interface.

[0011] As a further improvement of the present invention, the processor core and the programmable logic core inside the chip interact and synchronize their states through an on-chip bus, the on-chip bus including a first type of bus for handshake signals and a second type of bus for data transmission; The first type of bus includes the AXI GPIO bus or the AXI Lite bus, and the second type of bus includes the AXI BRAM bus or the AXI DMA bus.

[0012] Preferably, the processor core is programmed in embedded C language to receive CAN bus data and Ethernet UDP multicast data; the programmable logic core is programmed in Verilog hardware logic to receive data from RS422 interface, LVDS interface and telemetry wired PCM interface.

[0013] As a further improvement of the present invention, the programmable logic core runs a time-division forwarding state machine configured by hardware logic programming. The time-division forwarding state machine is used to sequentially detect the data status of each buffer, and after tagging the data that meets the forwarding conditions with the corresponding frame header tag, merge them into a single data stream for output.

[0014] As a further improvement of the present invention, the data acquisition board also integrates a power management module, which is used to convert the external input voltage into various voltage levels to power the data acquisition board, and output the power supply voltage to the storage control board through the inter-board connection component; The board-to-board connection assembly includes a detachable high-frequency connector, a flexible flat cable, and a board-to-board connector. The flexible flat cable simultaneously transmits parallel interface data signals and DC power supply voltage.

[0015] According to a second aspect of the present invention, an aircraft data recording method is provided, implemented using the aforementioned aircraft data recording device, comprising the following steps: S1: Data Classification and Reception: The processor core of the data acquisition board receives protocol-type interface data, and the programmable logic core receives parallel interface data; S2: Data hierarchical caching: The processor core stores the received data into a designated partition of memory, and the programmable logic core caches the data received by each interface in its own independent cache queue; S3: The processor core and the programmable logic core perform a handshake synchronization to achieve data transmission state synchronization; S4: The processor core transmits the data in the memory partition to the programmable logic core via the on-chip bus; S5: The time-sharing forwarding state machine sequentially checks the data status of each buffer, adds the unique frame header tag of each data source to the data that meets the forwarding conditions, and splices the data segments with the frame header into a single data stream. S6: The programmable logic core sends the merged data stream to the storage control board through a parallel interface protocol; S7: After receiving the data stream, the storage control board does not parse the data stream, but directly writes the data stream into the storage chip.

[0016] As a further improvement of the present invention, in step S1, the protocol-type interface data includes CAN bus data and Ethernet UDP multicast data; the parallel interface data includes RS422 interface data, LVDS interface data and telemetry wired PCM interface data.

[0017] As a further improvement of the present invention, in step S2, the designated partition of the memory is managed using a circular queue data structure; the cache queue is a FIFO queue and is set with a programmable full flag as a trigger for forwarding. In step S5, the time-division forwarding state machine allocates the data transmission time slices to each data source interface according to the rate of each data source interface, and sequentially detects the data cache status in each cache queue and memory partition. When the programmable full flag of the cache queue is set or the number of unsent bytes in the circular queue of the memory partition reaches a set value, the data forwarding of that cache area is triggered.

[0018] As a further improvement of the present invention, step S8 is also included: data readback and restoration, wherein the host computer reads the complete original data stream from the storage chip, splits and merges the data stream according to the frame header format, and restores the complete original data of each data source interface.

[0019] In summary, the technical solutions conceived by this invention have the following beneficial effects compared with the prior art: (1) This invention separates the data acquisition and storage control functions into two independent boards, each handled by a mid-range performance chip. This avoids the problems of large software size and high functional coupling caused by concentrating all tasks on a single high-performance SOC chip, reduces the power consumption and heat generation of a single chip, improves the heat dissipation conditions in the confined space of the aircraft, and effectively solves the problem of chip heat accumulation. At the same time, the interference between software functions is reduced, which facilitates software maintenance and development.

[0020] (2) The storage control board of the present invention has a fixed function and does not require changes to the hardware design due to changes in the data source interface; the data acquisition board can be flexibly configured or the interface can be changed according to project requirements, which reduces the frequency of changes in the overall hardware design.

[0021] (3) This invention combines multiple heterogeneous data streams into a single data stream by setting a time-division forwarding state machine at the data acquisition end and attaching a frame header tag. The storage control board does not need to perform any parsing or recognition of the data content, but only performs the write operation. The software logic is extremely simplified, which effectively improves the reliability and stability of the storage link. During data readback, the host computer splits and merges the data stream according to the frame header format, which can restore the complete original data of each data source interface. This process is completed entirely on the host computer, without increasing the software burden of the data recording device itself, and further ensuring the operational stability of the recording device.

[0022] (4) The present invention places the power management module on the data acquisition board and supplies power to the storage control board through the inter-board connection component, thereby achieving power supply fault isolation. When the power supply is abnormal, the scope of damage is limited to the data acquisition board, and the storage control board and the data stored inside it are effectively protected.

[0023] (5) The present invention uses two independent small-area printed circuit boards to replace a single large board, which significantly reduces the cross-sectional area of ​​the single board and can be arranged in layers to meet the needs of the narrow installation space of the aircraft, while providing greater flexibility for the structural heat dissipation design.

[0024] (6) The present invention uses a detachable inter-board flexible flat cable in conjunction with a high-frequency connector and a high-speed board-to-board connector to realize the physical connection between the data acquisition board and the storage control board. The high-frequency connector and the flexible flat cable work together to form a continuous electromagnetic shielding path at both ends of the signal transmission path, effectively ensuring the signal integrity of high-frequency data during inter-board transmission. At the same time, the flexible flat cable has good flexibility and can be flexibly routed according to the internal space of the aircraft, which facilitates assembly. While ensuring the quality of high-speed data transmission, it provides good operational flexibility for aircraft assembly. When the connection component is damaged during assembly or use, it can be replaced individually without replacing the entire board, which reduces maintenance costs and improves the maintainability of the product. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the aircraft data recording device according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0027] like Figure 1 As shown, this embodiment of the invention provides an aircraft data recording device, including a data acquisition board, a storage control board, and an inter-board connection component. The data acquisition board includes a main control chip and multiple data source interfaces arranged around the main control chip, used to receive data from each data source interface, merge multiple data streams into a single data stream in a time-division multiplexing manner, and then output it. The storage control board is separately disposed from the data acquisition board, used to receive the data stream output by the data acquisition board, and without parsing the data stream, directly writes the data stream into the storage chip. The inter-board connection component is disposed between the data acquisition board and the storage control board, used to realize data transmission and power supply connection between the two.

[0028] Preferably, the main control chip of the data acquisition board is a heterogeneous system-on-a-chip (SoC) that integrates a processor core and a programmable logic core. The data acquisition board has multiple data source interfaces, including a first type of interface connected to the programmable logic core and a second type of interface connected to the processor core. The first type of interface includes an RS422 interface, an LVDS interface, and a wired telemetry PCM interface, used to receive high-speed parallel data output from various sensors and data transmission devices on the aircraft. The second type of interface includes a CAN bus interface and an Ethernet interface, used to receive CAN interface data, UDP multicast data commands, and network multicast data from the aircraft control bus. More preferably, the main control chip also integrates a storage unit required for its own operation.

[0029] In one specific implementation, the main control chip uses the Fudan Micro JFMSP20S484 chip. This chip adopts a heterogeneous system-in-package (SiP) architecture, integrating two heterogeneous computing units: a processor core (PS, i.e., ARM core) and a programmable logic core (PL, i.e., FPGA core). Simultaneously, the chip also integrates Flash memory and DDR memory through SiP packaging technology, used for storing firmware programs and serving as data cache space during program execution, respectively.

[0030] Based on the above chip architecture, the processor and programmable logic sides respectively undertake the data reception tasks of different types of interfaces.

[0031] Preferably, the processor core is programmed in embedded C language, using a C language function library to implement the CAN bus protocol and Ethernet UDP multicast protocol. Utilizing the chip's built-in CAN interface and Gigabit Ethernet interface, it receives and acquires CAN interface data and UDP multicast data, caching them respectively in designated partitions of internal DDR memory. Each partition is managed using a circular queue data structure. More preferably, the processor core is a dual-core processor. To improve the response speed of CAN interface data and UDP multicast data and avoid frame errors or missing frames due to reception delays, the two cores independently handle the reception response and buffer transfer of CAN interface data and UDP multicast data. One core is responsible for the reception and transfer of CAN interface data, and the other core is responsible for the reception and transfer of UDP multicast data.

[0032] Preferably, the programmable logic terminal is implemented using Verilog hardware logic programming and is equipped with data interfaces such as RS422 interface, LVDS interface, and wired telemetry PCM interface. Due to the excellent interface adaptability of the programmable logic array, the peripheral circuitry on the PL side can be flexibly modified, and interface hardware can be added or replaced according to project requirements. The programmable logic terminal buffers the data received from each interface into its own independent FIFO buffer queue, and sets a programmable full flag for each FIFO as the trigger condition for subsequent readings, for identification by the time-division forwarding state machine.

[0033] It should be noted that the chip model (Fudan Micro JFMSP20S484) listed in the above specific embodiments is only an exemplary implementation and is not intended to limit the present invention. Those skilled in the art will understand that other chips that also adopt a heterogeneous system-in-package architecture and integrate a processor core, programmable logic core, and memory unit can all implement the technical solution of the present invention, and can be selected and substituted according to actual application requirements.

[0034] Furthermore, since the processor core and the programmable logic core are two independently operating units within the main control chip, they require handshake signals for state synchronization when interacting with each other. In this embodiment, the processor core and the programmable logic core interact and synchronize their states via an on-chip bus, which includes a first type of bus for handshake signals and a second type of bus for data transmission.

[0035] Preferably, the first type of bus is an AXI GPIO bus or an AXI Lite bus, used to implement handshake communication between the processor core and the programmable logic core. The AXI GPIO bus consumes fewer resources and is suitable for scenarios where the processor core load is light and sufficient GPIO resources are available for status queries. The AXI Lite bus is a lightweight register bus with a faster response speed, suitable for scenarios where the processor core load is heavy and requires rapid response to reduce interference with the main task. Through the handshake signal, the processor core notifies the programmable logic core that new data is available to be read in its memory partition, and the programmable logic core, in turn, informs the processor core through the handshake signal that the data in its cache queue has been retrieved and can be updated with the next batch of data, thereby achieving bidirectional state synchronization of data transmission.

[0036] Preferably, the second type of bus is an AXI BRAM bus or an AXI DMA bus, used to transfer data received by the processor core to the programmable logic core for subsequent forwarding processing. The AXI BRAM bus achieves data exchange through shared Block RAM, with simple control logic and low implementation overhead, and is suitable for interface data forwarding scenarios with low data rates; the AXI DMA bus supports high-speed batch data transmission without the processor core's full involvement, and is suitable for interface data forwarding scenarios with high data rates.

[0037] Specifically, when using the AXI BRAM bus, the processor core updates data in the Block RAM, and the programmable logic core reads it from the Block RAM using a handshake signal. When using the AXI DMA bus, the processor core can directly transfer data via DMA after configuring the DMA controller. Through these on-chip bus interaction methods, efficient and stable data transfer between the processor core and the programmable logic core is ensured.

[0038] Furthermore, the programmable logic core sequentially queries the data cache status of each interface through time-sharing operations, adds its own frame header to the data, and then sends it to the storage control board for storage through the inter-board connection component using a parallel interface protocol.

[0039] Specifically, the programmable logic core internally operates a time-sharing forwarding state machine configured through hardware logic programming. The time-sharing forwarding state machine first allocates data transmission time slices according to the rate of each data source interface, and then sequentially checks the data buffer status in each FIFO buffer queue and memory partition. When a buffer reaches the trigger condition for forwarding (e.g., the FIFO's programmable full flag is triggered, or the number of unsent bytes in the memory partition's circular queue reaches a set value), the processor core and the programmable logic core perform a handshake synchronization via the bus to confirm that the data is ready. Subsequently, the time-sharing forwarding state machine processes each trigger signal in a preset order, retrieves data from the trigger buffer, adds a unique frame header tag for that data source to the front of the data stream, concatenates the header-tagged data segments into a single data stream, and finally forwards the data to the storage control board via a parallel interface protocol.

[0040] This invention achieves real-time merging and unified output of multiple heterogeneous data streams through a time-division forwarding state machine. This state machine sequentially polls the cache states of each interface using hardware logic, merging data streams from different protocols and rates into a single data stream, and tagging each data stream with a frame header for distinguishing different data sources during readback. Compared to traditional software solutions, the hardware state machine has deterministic timing behavior and parallel processing capabilities, eliminating the risk of data loss due to task preemption or interruption delays. Simultaneously, the storage control board can directly write data without parsing it, further simplifying the storage control software and improving the overall stability and maintainability of the system.

[0041] Preferably, the data acquisition board also integrates a power management module, which is used to convert the external input voltage into various voltage levels to power the data acquisition board, and output the power supply voltage to the storage control board through the inter-board connection components.

[0042] In one specific implementation, the external input voltage is a 28V DC power supply, with an input range allowed between 16V and 40V. The power management module first converts the input voltage to a stable 12V intermediate voltage via a DC-DC converter. Then, through power management chips such as LTM4644 and LTM4630, it distributes the voltage to various levels (5V, 3.3V, 2.5V, 1.8V, and 1.0V) according to the power-up sequence requirements of the main control chip, supplying power to the processor core, programmable logic core, and other chips of the main control chip. Simultaneously, the power management module outputs one 5V voltage to the storage control board via an inter-board connection component, supplying power to the storage control board.

[0043] With the above power supply architecture, when the data acquisition board is damaged due to power supply abnormalities (such as reverse voltage connection, overshoot, etc.), the storage control board and the data stored inside can be effectively protected, which not only ensures data security but also improves the maintainability of the product.

[0044] Furthermore, the data acquisition board and the storage control board are physically connected using a detachable inter-board connection assembly. In one specific implementation, the inter-board connection assembly includes a flexible flat cable and a first high-frequency connector and a second high-frequency connector respectively located at both ends of the flexible flat cable. The first high-frequency connector connects to the data acquisition board, and the second high-frequency connector connects to the storage control board. Compared to using independent wires for inter-board connections, the flexible flat cable connects to both boards via high-frequency connectors at both ends, forming a continuous electromagnetic shielding path at both ends of the flexible flat cable. This effectively suppresses electromagnetic interference during high-frequency data signal transmission between boards, ensuring signal integrity. The inter-board connection assembly consists of a detachable inter-board flexible flat cable and a high-speed board-to-board connector. This flexible flat cable simultaneously transmits three types of signals: parallel interface data signals (including a synchronization clock, data bus, and chip select enable signal), the power supply voltage from the data acquisition board to the storage control board, and a ground wire.

[0045] In one specific implementation, the parallel interface protocol is the parallel SPI protocol. The synchronization clock frequency of the parallel interface data signal is 100MHz, and the data bus width can be flexibly selected between 8 bits, 16 bits, or 32 bits, with a one-bit chip select enable signal for transmission synchronization. The data bus width and synchronization clock frequency can be flexibly configured according to the total data rate of the data acquisition board to adapt to different data transmission requirements.

[0046] Furthermore, the storage control board is a separate printed circuit board used to receive the parallel interface data stream from the data acquisition board and write it directly to the storage chip. Since all data has already undergone frame header marking and merging processing at the acquisition end, the storage control board does not need to parse or split the data content; it only performs write operations. The storage control board simultaneously obtains data signals and power supply voltage through inter-board connection components.

[0047] This invention separates data acquisition and storage control in hardware, employing two independent printed circuit boards—a data acquisition board and a storage control board—each handling their respective functions. The data acquisition board is centered on a heterogeneous system-on-a-chip (SoC), containing a processor core and a programmable logic core, along with integrated storage units for the chip's own operation. The processor core uses embedded software programming to receive protocol-based interface data, while the programmable logic core uses hardware logic programming to receive parallel interface data, caching each interface's data into its corresponding buffer. The two cores interact and synchronize their states via an on-chip bus. The programmable logic core uses a time-division multiplexing state machine to sequentially check the data status of each buffer, tagging data that meets the forwarding conditions with frame headers and merging them into a single data stream. This stream is then transmitted to the storage control board via a detachable inter-board connection component through a parallel interface protocol. The storage control board does not need to parse the data content; it only performs data writing operations, thus achieving physical decoupling between acquisition and storage.

[0048] Furthermore, embodiments of the present invention provide a method for recording aircraft data using the above-described device, comprising the following steps: (1) Data classification and reception The processor core receives protocol-based interface data, including CAN bus data and Ethernet UDP multicast data; the programmable logic core receives parallel interface data, including RS422 interface data, LVDS interface data, and wired telemetry PCM interface data. The two types of cores operate independently and in parallel without interfering with each other.

[0049] (2) Data hierarchical caching The processor core stores the received CAN and UDP data into designated partitions in memory, and each partition is managed using a circular queue data structure. The programmable logic core caches the data received from each interface in its own independent FIFO cache queue, and sets a programmable full flag for each FIFO as a condition for triggering subsequent forwarding.

[0050] (3) Handshake synchronization The processor core and the programmable logic core communicate via a handshake using the AXI GPIO bus or AXI Lite bus. The processor core notifies the programmable logic core that there is new data to be read in its memory partition, and the programmable logic core informs the processor core via a handshake signal that the data in its cache queue has been retrieved and can be updated with the next batch of data, thereby achieving bidirectional state synchronization of data transmission.

[0051] (4) Transfer of processor core data to programmable logic core The processor core transmits CAN and UDP data from the memory partition to the programmable logic core via the AXI BRAM bus or AXI DMA bus. After this step, all data to be forwarded is converged on the programmable logic core side.

[0052] (5) Time-division forwarding and unified frame header The time-sharing forwarding state machine allocates data transmission time slices to each data source interface based on its speed, and sequentially checks the data buffer status in each FIFO buffer queue and memory partition. When a buffer reaches the trigger condition for forwarding, the state machine triggers data forwarding for that buffer, retrieves data from the buffer, adds a unique frame header tag for that data source to the front of the data stream, processes each trigger signal in the order of the time slices, and concatenates the data segments with the pre-attached frame headers into a single data stream.

[0053] (6) Parallel data output The programmable logic core sends the merged data stream to the storage control board via a parallel interface protocol. The data stream passes through connectors on the data acquisition board, inter-board connection components, and connectors on the storage control board before reaching the storage control board.

[0054] (7) Direct writing to the storage control board After receiving the parallel data stream, the storage control board does not parse any frame header information or split the data; it directly writes the entire data stream sequentially to the storage chip. Since the data has already been formatted at the acquisition end, the storage control board's write logic is extremely simplified, effectively improving the reliability and stability of the storage process.

[0055] (8) Data readback and restoration When data needs to be read back, the host computer reads the complete raw data stream from the storage chip of the storage control board, splits the data stream according to the pre-agreed frame header format, and splices together data segments belonging to the same data source by identifying different frame header tags, ultimately restoring the complete raw data of each data source interface. This restoration process is completed entirely on the host computer, without adding any extra burden to the data recording device itself.

[0056] This invention separates data acquisition and storage control in hardware, and completes the classification, reception, time-division forwarding and unified frame header marking of multi-source data at the acquisition end. This effectively reduces software complexity, improves heat dissipation, and enhances interface expansion flexibility. At the same time, the detachable connection components and power isolation design improve the product's maintainability and data security.

[0057] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An aircraft data recording device, characterized in that, include: The data acquisition board includes a main control chip and multiple data source interfaces arranged around the main control chip, which are used to receive data from each data source interface, merge multiple data streams into a single data stream in a time-division manner, and then output the data. The storage control board is set separately from the data acquisition board. It is used to receive the data stream output by the data acquisition board, but does not parse the data stream and directly writes the data stream into the storage chip. An inter-board connection component is disposed between the data acquisition board and the storage control board to realize data transmission and power supply connection between the data acquisition board and the storage control board.

2. The aircraft data recording device according to claim 1, characterized in that, The main control chip is a heterogeneous system-on-a-chip that integrates a processor core and a programmable logic core, and the chip also integrates a storage unit.

3. The aircraft data recording device according to claim 1, characterized in that, The plurality of data source interfaces include a first type of interface connected to the programmable logic core and a second type of interface connected to the processor core. The first type of interface is used to receive high-speed parallel data, and the second type of interface is used to receive protocol-type data. The first type of interface includes RS422 interface, LVDS interface and wired telemetry PCM interface, and the second type of interface includes CAN bus interface and Ethernet interface.

4. The aircraft data recording device according to claim 1, characterized in that, The processor core and programmable logic core inside the chip interact and synchronize their states through an on-chip bus. The on-chip bus includes a first type of bus for handshake signals and a second type of bus for data transmission. The first type of bus includes the AXI GPIO bus or the AXI Lite bus, and the second type of bus includes the AXI BRAM bus or the AXI DMA bus.

5. The aircraft data recording device according to claim 1, characterized in that, The programmable logic core runs a time-division forwarding state machine configured through hardware logic programming. The time-division forwarding state machine is used to sequentially detect the data status of each buffer, and after tagging the data that meets the forwarding conditions with the corresponding frame header tag, merge them into a single data stream for output.

6. The aircraft data recording device according to claim 1, characterized in that, The data acquisition board also integrates a power management module, which is used to convert the external input voltage into various voltage levels to power the data acquisition board, and to output the power supply voltage to the storage control board through the inter-board connection component. The board-to-board connection assembly includes a detachable high-frequency connector, a flexible flat cable, and a board-to-board connector. The flexible flat cable simultaneously transmits parallel interface data signals, DC power supply voltage, and ground.

7. A method for recording aircraft data, characterized in that, The data recording device described in any one of claims 1-6 is used to achieve this, comprising the following steps: S1: Data Classification and Reception: The processor core of the data acquisition board receives protocol-type interface data, and the programmable logic core receives parallel interface data; S2: Data hierarchical caching: The processor core stores the received data into a designated partition of memory, and the programmable logic core caches the data received by each interface in its own independent cache queue; S3: The processor core and the programmable logic core perform a handshake synchronization to achieve data transmission state synchronization; S4: The processor core transmits the data in the memory partition to the programmable logic core via the on-chip bus; S5: The time-sharing forwarding state machine sequentially checks the data status of each buffer, adds the unique frame header tag of each data source to the data that meets the forwarding conditions, and splices the data segments with the frame header into a single data stream. S6: The programmable logic core sends the merged data stream to the storage control board through a parallel interface protocol; S7: After receiving the data stream, the storage control board does not parse the data stream, but directly writes the data stream into the storage chip.

8. The aircraft data recording method according to claim 7, characterized in that, In step S1, the protocol-type interface data includes CAN bus data and Ethernet UDP multicast data; the parallel interface data includes RS422 interface data, LVDS interface data and wired telemetry PCM interface data.

9. The aircraft data recording method according to claim 7, characterized in that, In step S2, the designated partition of the memory uses a circular queue data structure for data management; the cache queue is a FIFO queue and is set with a programmable full flag as a trigger for forwarding. In step S5, the time-division forwarding state machine allocates the data transmission time slices to each data source interface according to the rate of each data source interface, and sequentially detects the data cache status in each cache queue and memory partition. When the programmable full flag of the cache queue is set or the number of unsent bytes in the circular queue of the memory partition reaches a set value, the data forwarding of that cache area is triggered.

10. The aircraft data recording method according to claim 7, characterized in that, It also includes step S8: data readback and restoration, where the host computer reads the complete original data stream from the storage chip, splits and merges the data stream according to the frame header format, and restores the complete original data of each data source interface.

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