A display chip link processing method capable of saving power consumption

Abstract

This application discloses a power-saving display chip link processing method. The method includes: detecting the image data input status of the application processor during each frame synchronization signal cycle, and determining the current frame as a refresh frame or a skip frame; during a refresh frame, image data is directly sent to the panel along a bypass path, and written to the frame buffer after compression encoding along a storage path, while the decompression decoding module is turned off; during a skip frame, none of the modules perform data processing; when the number of consecutive skipped frames reaches a threshold determined based on the panel's minimum available refresh rate, a self-refresh is triggered, compressed data is read from the frame buffer, decompressed, and then sent to the panel. This application can reduce unnecessary data processing in the display chip link and lower the power consumption of the display driver integrated circuit.

Description

Technical Field

[0001] This application relates to the field of display processing technology, and in particular to a display chip link processing method that can save power consumption. Background Technology

[0002] With the development of high refresh rate displays and variable refresh rate technologies in mobile terminals, application processors can dynamically adjust the image output frame rate according to different scenarios such as games, videos, static images, and standby. Display driver integrated circuits need to balance high refresh rate display, low frame rate maintenance, and system power consumption control. Existing display driver chips typically include a compression encoding module, a frame buffer, and a decompression / decoding module in the data link. Image data is compressed and written to the frame buffer, then decompressed and output to the display panel to reduce internal data bandwidth and solve the problem of mismatch between the application processor and the panel refresh timing.

[0003] However, traditional fixed links typically require continuous compression, frame buffer read / write, and decompression of each frame. Even if the application processor reduces the output frame rate or there is no new image data in some frame periods, related modules may still maintain unnecessary operating states, increasing the power consumption of the digital circuitry in the display driver chip. Furthermore, LTPO panels and LTPS panels differ in their low refresh rate capabilities and pixel charge retention characteristics. LTPS panels, in particular, are limited by pixel storage capacitors and thin-film transistor leakage current; excessively low refresh rates can also cause display flicker. Therefore, how to rationally control the operating states of the data links and related functional modules within the display chip by combining the input frame rate and panel characteristics has become a technical problem that needs to be solved to reduce the power consumption of the display system. Summary of the Invention

[0004] This application provides a display chip link processing method and system that can save power consumption, so as to at least solve some of the technical problems existing in the related technologies described above.

[0005] According to a first aspect of the embodiments of this application, a power-saving display chip link processing method is provided, applied to a display driver integrated circuit, wherein the display driver integrated circuit is provided with a compression encoding module, a frame buffer, and a decompression decoding module, characterized in that it includes: In each cycle of the frame synchronization signal, it detects whether the application processor has input image data and determines whether the current frame is a refresh frame or a skip frame. When a refresh frame is detected, the image data is transmitted simultaneously along the bypass path and the storage path. In the bypass path, the image data bypasses the compression encoding module, the frame buffer, and the decompression decoding module before being sent to the panel. In the storage path, the image data is compressed by the compression encoding module and written to the frame buffer, while the decompression decoding module is turned off. When a frame is determined to be skipped, the compression encoding module, the frame buffer, and the decompression decoding module do not perform data processing. When the number of consecutive skipped frames since the last refresh frame reaches a threshold determined based on the minimum available refresh rate of the panel, a self-refresh is triggered. Compressed data written through the storage path is read from the frame buffer, decoded by the decompression and decoding module, and then sent to the panel.

[0006] As an optional solution, during the self-refresh process, if the application processor sends in new image data while the decompression decoding module is reading compressed data from the frame buffer, the display driver integrated circuit will discard the new image data, not send it to the compression encoding module or the frame buffer, and not send it to the panel through the bypass path.

[0007] As an optional solution, after the self-refresh is completed, the display driver integrated circuit re-detects whether the application processor has input image data when the next frame synchronization signal arrives, and selects the corresponding link working mode according to the detection result.

[0008] As an alternative, the threshold is obtained by dividing the frequency of the frame synchronization signal by the minimum available refresh rate of the panel, and the threshold represents the number of frame synchronization signal cycles allowed to pass from the last refresh frame to the triggering of the self-refresh.

[0009] As an optional approach, the display driver integrated circuit counts the number of cycles of the frame synchronization signal between two adjacent refresh frames, and divides the frequency of the frame synchronization signal by the number of cycles of the frame synchronization signal to obtain the current input frame rate of the application processor.

[0010] As an optional solution, the display driver integrated circuit maintains a continuous skip frame counter, increments the continuous skip frame counter when a skip frame is determined, and resets the continuous skip frame counter to zero when a refresh frame is determined; when the value of the continuous skip frame counter reaches the threshold, the self-refresh is triggered.

[0011] As an alternative, when the image data being transmitted by the application processor is in the middle or later part of a frame when the frame synchronization signal arrives, the display driver integrated circuit filters and discards the image data, and re-detects the data input status of the application processor when the next frame synchronization signal arrives.

[0012] As an optional solution, the display driver integrated circuit selects the operating mode of the data link according to the type of the connected panel; when the type of the panel is a low-temperature polycrystalline oxide panel, the image data is bypassed by the compression encoding module, the frame buffer and the decompression decoding module and sent to the panel, and the compression encoding module, the frame buffer and the decompression decoding module are all turned off.

[0013] As an alternative, when the panel is a low-temperature polycrystalline silicon panel, the minimum available refresh rate of the panel is determined based on the pixel storage capacitor capacity and thin-film transistor leakage current level of the panel.

[0014] As an optional solution, the display driver integrated circuit is configured with multiple frame rate thresholds, with different frame rate thresholds corresponding to different panel output refresh rates; the multiple frame rate thresholds are set according to the standard refresh rate levels supported by the connected panel.

[0015] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Furthermore, no embodiment in this disclosure is required to achieve all the effects described above. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0017] Figure 1 This is a schematic diagram of a conventional processing link provided according to embodiments of this disclosure.

[0018] Figure 2 This is a schematic diagram of an internal data link provided according to an embodiment of the present disclosure.

[0019] Figure 3 This is a schematic diagram of the full bypass mode provided according to an embodiment of the present disclosure.

[0020] Figure 4 This is a flowchart of a power-saving display chip link processing method provided according to embodiments of the present disclosure.

[0021] Figure 5 This is another schematic diagram provided according to an embodiment of the present disclosure.

[0022] Figure 6 This is another schematic diagram provided according to an embodiment of the present disclosure.

[0023] Figure 7 This is a schematic diagram of link selection according to an embodiment of the present disclosure.

[0024] Figure 8This is a flowchart of a read / write conflict scenario provided according to an embodiment of this disclosure. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0026] This disclosure provides a power-saving display chip link processing method applicable to display systems supporting variable frame rate input. The display system includes an application processor (AP) and a display driver integrated circuit (DDIC). The AP sends image data to the DDIC at a variable frame rate, for example, from 1Hz to 120Hz, depending on the current application scenario. In high refresh rate scenarios such as games, the AP typically outputs at 120Hz, while in static scenes or standby scenarios, it reduces to 10Hz or even lower, switching between high and low frame rates for a period of time. The DDIC internally includes an encoding module (Encode), a frame buffer, and a decoding module (Decode), arranged sequentially along the data link. The encoding module compresses and encodes the input raw pixel data to reduce data bandwidth; the frame buffer stores the compressed and encoded image data; and the decoding module restores the compressed data read from the frame buffer into pixel data that the panel can directly recognize. This method is applicable to both LTPO (Low Temperature Polycrystalline Oxide) panels and LTPS (Low Temperature Polycrystalline Silicon) panels.

[0027] The implementation process of the method described in this application will be described in detail below with reference to specific embodiments. It should be noted that this embodiment is only used to explain this application and is not intended to limit the scope of protection of this application. Conventional adjustments or substitutions of each step by those skilled in the art without departing from the concept of this application should be included in the scope of protection of this application.

[0028] Figure 1 This is a schematic diagram of a conventional processing link provided according to embodiments of this disclosure, such as... Figure 1As shown, in the traditional link scheme, the front-end image data received by DDIC passes through the compression encoding module, frame buffer, and decompression / decoding module sequentially, forming a fixed processing link. The frame buffer is introduced to solve the screen tearing and timing asynchrony problems caused by the mismatch between the AP and the panel refresh rate. Since directly storing the raw image data into the frame buffer would cause excessive pressure on the chip's internal bus bandwidth, a compression encoding module is set at the front end of the frame buffer to reduce the amount of data, and a decompression / decoding module is set at the back end to restore the pixel data. Figure 1 The gray modules represent other functional modules on the link and are not directly related to this solution.

[0029] Taking 55nm process as an example, the power consumption breakdown of each module in a conventional DDIC design is shown in the table below: In traditional solutions, each frame of data needs to be processed by a compression encoding module and a decompression decoding module, as well as read and write operations of the frame buffer. Compared with the DDIC of the LTPO panel, this increases the current consumption by at least 80mA, resulting in faster battery consumption and affecting the internal working stability of the digital circuit.

[0030] This embodiment addresses the aforementioned power consumption issue by dynamically selecting the data link path within the DDIC based on the AP input frame rate and panel type, selectively enabling or bypassing the compression encoding module, frame buffer, and decompression decoding module, thereby reducing power consumption while maintaining normal panel display. Figure 2 This is a schematic diagram of an internal data link provided according to an embodiment of this disclosure, such as... Figure 2 As shown, the DDIC internal data link is configured with multiple switchable paths.

[0031] In this disclosure, the following non-general terms are defined and explained. Bypass refers to image data being transmitted directly to the next-level module in the link without being processed by a designated functional module. A refresh frame refers to a frame in which new image data input to the AP is detected when the Vertical Sync (VS) signal arrives within the DDIC. A skip frame refers to a frame in which no new image data input to the AP is detected when the VS signal arrives. Self-refresh refers to the operation where, after the AP has stopped sending new data for a certain period, the DDIC reads the compressed data previously written through the storage path from the frame buffer, restores it through the decompression and decoding module, and then sends it to the panel. Its function is to maintain the panel refresh rate at no less than the minimum available refresh rate and prevent screen flickering in the LTPS panel due to leakage of the pixel storage capacitor. A bypass path refers to the transmission channel through which image data is sent directly to the panel, bypassing the compression encoding module, frame buffer, and decompression and decoding module; a storage path refers to the transmission channel through which image data is written to the frame buffer after being compressed by the compression encoding module.

[0032] During initialization, the DDIC determines the type of connected panel through register configuration and selects the operating mode of the data link accordingly. LTPO panels are manufactured using a composite integration process of LTPS and IGZO (indium gallium zinc oxide), combining high electron mobility and low leakage current characteristics, supporting refresh rates as low as 1Hz without display abnormalities. LTPS panels are manufactured using a low-temperature polysilicon process, and due to limitations in the charging and discharging characteristics of pixel storage capacitors and the leakage current level of thin-film transistors, they typically only support a minimum refresh rate of approximately 48Hz. In engineering practice, the minimum usable refresh rate of a panel is determined based on the pixel storage capacitor capacity and the leakage current level of the thin-film transistors. This means that when the panel operates above this refresh rate, the pixel charge can maintain sufficient voltage before the next refresh. Panel manufacturers specify this value in their panel specifications, and the DDIC reads it into its internal registers during initialization, typically set to, for example, 60Hz.

[0033] Figure 3 This is a schematic diagram of the full bypass mode provided in the embodiments of this disclosure. When the panel type is LTPO, DDIC enters the full bypass mode: Since the LTPO panel itself supports full-range variable frame rate display, the image data bypasses the compression encoding module, frame buffer, and decompression decoding module and is sent to the panel. All three modules are turned off. Figure 3 As shown, the power consumption of the DDIC digital circuit is at its lowest level in this mode.

[0034] When the panel type is LTPS, DDIC enters frame rate adaptive mode, dynamically switching between different links based on real-time changes in the AP input frame rate. The following describes each step in this mode.

[0035] Figure 4 This is a flowchart of a power-saving display chip link processing method provided according to embodiments of this disclosure, such as... Figure 4 As shown, the method includes steps S1-S5: Step S1: In each cycle of the frame synchronization signal, detect whether the application processor inputs image data and determine the current frame as a refresh frame or a skip frame.

[0036] In some embodiments, the DDIC internally generates a frame synchronization signal at a fixed frequency, the frequency of which is equal to the DDIC's internal reference refresh rate, for example, configured as 120Hz. At the arrival of each frame synchronization signal cycle, the DDIC samples the AP data input port to detect whether the AP is transmitting new image data. Specifically, the frame detection logic within the DDIC checks whether a valid image data transmission flag exists at the valid edge of the frame synchronization signal: if a valid transmission flag is detected, the current frame is determined to be a refresh frame; if not, the current frame is determined to be a skipped frame.

[0037] The DDIC internally maintains a consecutive skipped frame counter, which is a non-negative integer register starting from zero. The counter is incremented when a skipped frame is detected and reset to zero when a refresh frame is detected. The value of the consecutive skipped frame counter reflects the cumulative number of consecutive skipped frames since the last refresh frame, and is compared with a threshold in subsequent steps to determine whether to trigger a self-refresh.

[0038] In some embodiments, DDIC also obtains the current input frame rate of the AP by counting the number of frame synchronization signal cycles that occur between two adjacent refresh frames. Let the frame synchronization signal frequency be... (Unit: Hz), the number of frame synchronization signal cycles between two adjacent refresh frames is... (Dimensionless positive integer) Divide the frequency of the frame synchronization signal by the number of cycles of the frame synchronization signal to obtain the current input frame rate of the AP. (Unit: Hz): in Input frame rate for AP. For frame synchronization signal frequency, This represents the number of frame synchronization signal cycles that occur between two adjacent refresh frames. For example, when... =120Hz and When =1, =120Hz; when When =2, =60Hz; when When =3, =40Hz. DDIC can use this frame rate value to help determine the current operating status of the AP and the selection of subsequent link modes.

[0039] Step S2: It is determined that when refreshing the frame, the image data is transmitted simultaneously along the bypass path and the storage path.

[0040] Figure 5 This is another schematic diagram based on an embodiment of the present disclosure, such as... Figure 5 As shown, when DDIC determines that the current frame is a refresh frame during a certain frame synchronization signal cycle, the image data is transmitted simultaneously along both the bypass path and the storage path.

[0041] Specifically, the transmission process in the bypass path involves bypassing the image data compression and encoding module, frame buffer, and decompression / decoding module, and directly sending it to the DDIC's internal post-processing module. After processing, the data is sent to the panel for display of the current frame image. In the bypass path, no compression or decompression operations are performed; data travels directly from the AP input port through the DDIC's internal logic to the panel interface, where the panel instantly displays the latest image content sent by the AP.

[0042] The transmission process in the storage path proceeds synchronously with the bypass path. Image data is sent to the compression encoding module, which performs compression encoding operations on the original pixel data, reducing the data volume to a certain proportion of the original data volume before writing it into the frame buffer. The storage path pre-stores the compressed data of the current frame into the frame buffer; this compressed data serves as the data source for subsequent self-refresh stages. Within the storage path, the decompression / decoding module is disabled and does not participate in data processing.

[0043] In this dual-path scheme, two paths operate in parallel. The bypass path handles the real-time display of the panel without passing through the decompression / decoding module, while the storage path writes the compressed data of the latest frame into the frame buffer to support subsequent possible self-refresh operations. In the traditional link scheme, each frame of data undergoes three stages of serial processing: compression / encoding, frame buffer, and decompression / decoding. The decompression / decoding module is active in every frame. In this dual-path scheme, the panel data during the refresh frame stage comes from the bypass path, and the decompression / decoding module is turned off, thus eliminating its power consumption in each refresh frame cycle. Referring to the power consumption breakdown table above, the decompression / decoding module consumes approximately 20mA in the traditional link, accounting for about a quarter of the overall digital circuit power consumption; the dual-path mode reduces the corresponding current consumption during refresh frame operation.

[0044] In step S3, if it is determined that a frame is skipped, the compression encoding module, frame buffer, and decompression / decoding module will not perform data processing.

[0045] In one embodiment, when the DDIC does not detect new image data input from the AP at the time the frame synchronization signal arrives, and determines it as a skipped frame, the compression encoding module, frame buffer, and decompression / decoding module do not perform data processing, and all three are in a low-power or off state. The panel maintains the display content of the previous refresh frame during the skipped frame period. During this stage, the continuous skipped frame counter increments as described in the preceding steps to record the currently accumulated number of continuous skipped frames.

[0046] Step S4: When the number of consecutive skipped frames reaches a threshold determined based on the minimum available refresh rate of the panel, a self-refresh is triggered.

[0047] In some embodiments, the number of consecutive skipped frames continues to accumulate when the AP input frame rate decreases or the AP pauses sending image data. The DDIC compares the value of the consecutive skipped frame counter with a preset threshold in each frame synchronization signal cycle. When the number of consecutive skipped frames reaches a threshold determined based on the panel's minimum available refresh rate, the DDIC triggers a self-refresh if the frame corresponding to the current frame synchronization signal is still a skipped frame.

[0048] The threshold is determined as follows: the frequency of the frame synchronization signal is divided by the minimum available refresh rate of the panel to obtain the threshold. This threshold represents the number of frame synchronization signal cycles allowed to pass from the last refresh frame to the triggering of self-refresh. Let the minimum available refresh rate of the panel be... (Unit: Hz), Threshold (Positive integer) is: in For frame synchronization signal frequency, This is the lowest available refresh rate for the panel. When the calculation result is not an integer, the largest integer not greater than that result is taken. For example, when =120Hz At 60Hz, =120 / 60=2; that is, two frame synchronization signal cycles are allowed after the last frame refresh without refreshing the panel. If no new AP data is detected when the third frame synchronization signal cycle arrives, the value of the continuous skip frame counter has reached the threshold. During the synchronization signal cycle of this frame, DDIC performs a self-refresh operation. The threshold is calculated once during the DDIC initialization phase based on the minimum available refresh rate specified in the panel specification document and stored in the internal register. It is not updated during operation.

[0049] The self-refresh process involves DDIC reading compressed data written to the storage path from the frame buffer. This data represents the data from the most recent refresh frame that was compressed by the compression encoding module and written to the frame buffer in the previous steps. The data is then sent to the decompression and decoding module for decoding and restoration. The restored pixel data is then sent to the panel via a subsequent data processing module. During the self-refresh phase, the compression encoding module is not involved; only the frame buffer read operation and the decompression and decoding module are active. The image content displayed during self-refresh is consistent with the most recent frame image stored in the frame buffer.

[0050] Figure 6 This is another schematic diagram based on an embodiment of the present disclosure, such as... Figure 6 As shown, the pixel storage capacitors in an LTPS panel gradually lose charge between refreshes due to leakage current from the thin-film transistors. When the refresh interval exceeds the charge retention time of the pixel capacitors, a noticeable change in pixel brightness occurs, resulting in screen flicker. The self-refresh mechanism enables the DDIC to continue outputting image data to the panel at a frequency no lower than the panel's minimum available refresh rate even when the AP has not sent new data for an extended period, replenishing the pixel charge before it drops to a critical value.

[0051] Step S5: Frame discarding processing when the decompression / decoding module reads compressed data from the frame buffer during the self-refresh process.

[0052] In some embodiments, during the self-refresh process, the decompression / decoding module is reading compressed data from the frame buffer and performing decoding operations. If the AP restarts sending image data at this time, the frame buffer faces a conflict between read and write concurrency: the storage path needs to write the compressed data of the new frame to the frame buffer, while the decompression / decoding module is simultaneously reading the compressed data of the previous frame from the frame buffer. The access to the frame buffer by both modules overlaps in timing, which may cause data corruption.

[0053] DDIC employs a frame-dropping strategy to handle the aforementioned conflicts. During the self-refresh process, if the AP sends in new image data while the decompression / decoding module is reading compressed data from the frame buffer, DDIC will discard the new image data, not sending it to the compression / decoding module or the frame buffer, and not sending it to the panel via a bypass path. DDIC will continue to complete the current self-refresh operation, and the panel will still display the image content of the previous frame stored in the frame buffer.

[0054] After the self-refresh is completed, DDIC will re-detect whether the AP has input image data when the next frame synchronization signal arrives, and select the corresponding link working mode according to the detection result: if it is determined to be a refresh frame, the image data will be processed in the way that the bypass path and the storage path are transmitted simultaneously in S2; if it is determined to be a skipped frame, it will continue to be executed in the processing method in S3, and the continuous skipped frame counter will determine whether to trigger the self-refresh again according to the rules in S4.

[0055] Frame dropping only occurs during self-refresh operations when the frame buffer read operation of the decompression decoding module overlaps with the arrival time of new AP data. Because the AP frame rate changes continuously, this type of read-write overlap occurs infrequently and usually involves only the dropping of one frame of data, so it does not cause obvious changes in the visual perception of the image.

[0056] In some embodiments, the AP frame rate and the frequency of the DDIC internal frame synchronization signal are not strictly synchronized, and there may be cases where the start time of the AP image data falls in the middle of the frame synchronization signal period. When the frame synchronization signal arrives, if the image data being transmitted by the AP is in the middle or later part of a frame, the DDIC filters and discards the image data. When the next frame synchronization signal arrives, the AP's data input status is re-detected. This frame filtering operation is similar to the frame discarding strategy in the aforementioned steps, both of which abandon the current frame to maintain data integrity when complete frame data cannot be obtained.

[0057] Taking LTPS panels as an example, combined with Figure 7 The link selection and module operating status within each frame synchronization signal period are explained in detail. Assuming the internal frame synchronization signal frequency of the DDIC is 120Hz, and the minimum usable refresh rate of the LTPS panel is 60Hz, the threshold is calculated according to the method in S4.1. =120 / 60=2. Figure 7This is a link selection diagram provided according to an embodiment of the present disclosure, such as... Figure 7 As shown, specifically: (1) When the first frame synchronization signal VS1 arrives, the AP image data input is Frame A. The DDIC detects the new data and determines it to be a refresh frame, and continuously skips the frame counter to zero. As described in S2, Frame A is directly sent to the subsequent module through the bypass path and then enters the panel display. At the same time, it is compressed by the compression encoding module in the storage path and written to the frame buffer. The compression encoding module and the frame buffer are in the writing state, and the decompression decoding module is turned off. The interval between adjacent refresh frames is one frame synchronization signal cycle, and the DDIC outputs data to the panel at 120Hz.

[0058] (2) When VS2 arrives, AP inputs Frame B. DDIC determines it to be a refresh frame, and the continuous skip frame counter is cleared. The processing method is the same as in step (1): Frame B is sent to the panel via a bypass path and written to the frame buffer via a storage path. When VS3 arrives, DDIC does not detect new data from AP and determines it to be a skip frame. As described in S3, the compression encoding module, frame buffer, and decompression decoding module do not work, and the continuous skip frame counter increments to 1. When VS4 arrives, Frame C is detected, and the continuous skip frame counter is cleared. There are two frame synchronization signal cycles between VS2 and VS4, and VS3 in the middle is a skip frame. During the skip frame phase, the three modules do not consume power, and DDIC outputs data to the panel at a frequency of about 80Hz.

[0059] (3) When VS4 arrives, AP inputs FrameC, which DDIC determines to be a refresh frame. FrameC is sent to the panel display via a bypass path and compressed by the compression encoding module in the storage path before being written to the frame buffer. When VS5 arrives, it is determined to be a skipped frame, and the continuous skipped frame counter increments to 1; when VS6 arrives, it is still a skipped frame, and the continuous skipped frame counter increments to 2. The display cycle of FrameC covers two frame synchronization signal cycles from VS4 to VS6. During VS5 and VS6, the three modules are in a low-power state, and DDIC outputs data to the panel at 60Hz.

[0060] (4) When VS7 arrives, DDIC still has not detected new AP data. At this time, the continuous skip frame counter value is 2, which has reached the threshold. =2, according to the rules of S4, DDIC triggers self-refresh. DDIC reads the compressed data written by FrameC in step (3) through the storage path from the frame buffer, sends it to the decompression and decoding module for restoration, and then sends it to the panel through the subsequent module. The displayed content is FrameC. When VS8 arrives, there is still no new AP data, and DDIC continues to maintain the skip frame state. During the self-refresh phase, the frame buffer performs read operations, the decompression and decoding module works, and the compression encoding module is turned off. From VS7 to VS8, DDIC performs self-refresh at about 80Hz, and the refreshed image content is all FrameC.

[0061] (5) When VS9 arrives, AP inputs FrameD, DDIC determines it to be a refresh frame, exits self-refresh mode, and the continuous skip frame counter is cleared. As described in S2, FrameD is sent to the panel via the bypass path and written to the frame buffer via the storage path, restoring the dual-path working mode of simultaneous transmission of the bypass path and the storage path, and DDIC outputs data to the panel at 120Hz.

[0062] Figure 8 This is a flowchart of a read / write conflict scenario provided in an embodiment of this disclosure, and... Figure 7 The difference lies in the fact that during VS7, DDIC is in self-refresh mode, and the decompression / decoding module is reading compressed data from the frame buffer and decoding it. When VS7 ends and VS8 arrives, DDIC detects that new frame data has been sent to AP, but the frame buffer read operation of the decompression / decoding module has not yet finished. According to the aforementioned frame discarding strategy, DDIC discards the frame data, not sending it to the compression / encoding module, the frame buffer, or to the panel via a bypass path. After the self-refresh is completed, when VS9 arrives, DDIC re-detects the AP data status as described above. If there is new refreshed data, it resumes the dual-path working mode; if it is still skipping frames, it continues to execute according to the rules of S3 and S4.

[0063] Optionally, the DDIC can be configured with multi-level frame rate thresholds, each corresponding to a different panel output refresh rate. These thresholds are set based on the standard refresh rate levels supported by the connected panel and stored in the DDIC's registers as a configuration table. The main control chip writes these thresholds through the configuration interface during system initialization. The specific values ​​of the frame rate thresholds are determined according to the panel specifications provided by the panel manufacturer, with each threshold level corresponding to a standard refresh rate supported by the panel. The table below provides a configuration example: Specifically, in the table above, "bypass path enabled" indicates that the image data of the refresh frame is simultaneously sent to the panel along the bypass path, while "bypass path disabled" indicates that the panel data source during the self-refresh stage is the output of the frame buffer after decoding by the decompression and decoding module. In some embodiments, multiple threshold levels can be further set to support more refined refresh rate grading, for example, setting the first threshold to 60Hz and the second threshold to 90Hz: when the AP input frame rate is higher than 90Hz, the DDIC refreshes the panel at 120Hz; when the AP input frame rate is between 60Hz and 90Hz, the DDIC refreshes the panel at 80Hz; when the AP input frame rate is lower than 60Hz, the DDIC performs self-refresh at a rate not lower than 60Hz. The interval between each threshold level is determined based on actual test data of the panel leakage characteristics. Specifically, the pixel voltage retention rate at different refresh rates is measured on the panel sample, and the refresh rate inflection point where the pixel voltage retention rate begins to decrease significantly is found. This inflection point is used as the basis for threshold division.

[0064] Through the aforementioned dynamic link switching method, in most operating scenarios with high AP input frame rates, image data is directly sent to the panel via a bypass path within each refresh frame cycle, and the decompression / decoding module is turned off, eliminating its power consumption. During the frame skipping phase, the compression / encoding module, frame buffer, and decompression / decoding module consume no power; only during the self-refresh phase is the frame buffer required to perform read operations and the decompression / decoding module required to perform decoding. Referring to the aforementioned power consumption breakdown data under the 55nm process, compared to the traditional link scheme where each frame of data must pass through the compression / encoding module, frame buffer, and decompression / decoding module completely, this method reduces the workload of the decompression / decoding module by at least 25% during most operating times. Simultaneously, the self-refresh mechanism in S4 periodically replenishes pixel charge to maintain normal display in low frame rate scenarios for LTPS panels, and the frame discarding strategy in S5 maintains data integrity during frame buffer read / write conflicts. For LTPO panels, the complete shutdown of all three modules is achieved through a full bypass mode to obtain the lowest power consumption. This method is implemented with pure digital logic inside the DDIC. The gate circuit area and power consumption occupied by the newly added frame detection logic, continuous skip frame counter, path selection switch and conflict judgment logic are negligible compared with the power consumption saved by the module.

[0065] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0066] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A power-saving display chip link processing method, applied to a display driver integrated circuit, wherein the display driver integrated circuit is provided with a compression encoding module, a frame buffer, and a decompression / decoding module, characterized in that, include: In each cycle of the frame synchronization signal, it detects whether the application processor has input image data and determines whether the current frame is a refresh frame or a skip frame. When a refresh frame is detected, the image data is transmitted simultaneously along the bypass path and the storage path; in the bypass path, the image data bypasses the compression encoding module, the frame buffer and the decompression decoding module and is sent to the panel; In the storage path, the image data is compressed by the compression encoding module and written to the frame buffer, and the decompression decoding module is turned off; When a frame is determined to be skipped, the compression encoding module, the frame buffer, and the decompression decoding module do not perform data processing. When the number of consecutive skipped frames since the last refresh frame reaches a threshold determined based on the minimum available refresh rate of the panel, a self-refresh is triggered. Compressed data written through the storage path is read from the frame buffer, decoded by the decompression and decoding module, and then sent to the panel.

2. The method according to claim 1, characterized in that, During the self-refresh process, when the decompression decoding module is reading compressed data from the frame buffer, if the application processor sends in new image data, the display driver integrated circuit will discard the new image data, not send it to the compression encoding module or the frame buffer, and not send it to the panel through the bypass path.

3. The method according to claim 2, characterized in that, After the self-refresh is completed, the display driver integrated circuit re-detects whether the application processor has input image data when the next frame synchronization signal arrives, and selects the corresponding link working mode according to the detection result.

4. The method according to claim 1, characterized in that, The threshold is obtained by dividing the frequency of the frame synchronization signal by the minimum available refresh rate of the panel, and the threshold represents the number of frame synchronization signal cycles allowed to pass from the last refresh frame to the triggering of the self-refresh.

5. The method according to claim 1, characterized in that, The display driver integrated circuit counts the number of cycles of the frame synchronization signal between two adjacent refresh frames, and divides the frequency of the frame synchronization signal by the number of cycles of the frame synchronization signal to obtain the current input frame rate of the application processor.

6. The method according to claim 1, characterized in that, The display driver integrated circuit maintains a continuous skip frame counter, increments the continuous skip frame counter when a skip frame is determined, and clears the continuous skip frame counter to zero when a refresh frame is determined; when the value of the continuous skip frame counter reaches the threshold, the self-refresh is triggered.

7. The method according to claim 1, characterized in that, When the frame synchronization signal arrives, if the image data being transmitted by the application processor is in the middle or later part of a frame, the display driver integrated circuit will filter and discard the image data, and re-detect the data input status of the application processor when the next frame synchronization signal arrives.

8. The method according to claim 1, characterized in that, The display driver integrated circuit selects the operating mode of the data link according to the type of the connected panel; when the type of the panel is a low-temperature polycrystalline oxide panel, the image data is bypassed by the compression encoding module, the frame buffer and the decompression decoding module and sent to the panel, and the compression encoding module, the frame buffer and the decompression decoding module are all turned off.

9. The method according to claim 8, characterized in that, When the panel is a low-temperature polycrystalline silicon panel, the minimum available refresh rate of the panel is determined based on the pixel storage capacitor capacity and thin-film transistor leakage current level of the panel.

10. The method according to claim 1, characterized in that, The display driver integrated circuit is configured with multiple frame rate thresholds, and different frame rate thresholds correspond to different panel output refresh rates; the multiple frame rate thresholds are set according to the standard refresh rate levels supported by the connected panel.

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