Two-dimensional transistor 1t-1 flash driving circuit array structure and driving control method thereof

Abstract

This invention provides a 1T-1 Flash driver circuit array structure based on two-dimensional transistors and its driving control method. The driver circuit array structure includes a substrate layer and pixel units arranged in an array. Each pixel unit includes vertically stacked two-dimensional switching transistors and two-dimensional non-volatile memory devices. The stacked structure, from bottom to top, consists of a first gate layer, a charge blocking layer, a charge trapping layer, a second gate layer, a charge tunneling layer, and a two-dimensional semiconductor channel layer. Each row has first and second control signal lines, and each column has data signal lines. The first and second gate layers of the pixel units in the same row are respectively coupled to the first and second control signal lines of the corresponding row. The two ends of the two-dimensional semiconductor channel layer in the same column are respectively connected to the data signal lines and the load device. This application achieves high-density integration of pixel units and non-volatile driving retention, with the LED driving frequency as low as 0.001 Hz, reducing system power consumption.

Description

Technical Field

[0001] This invention relates to the field of display driving circuit technology, specifically to a two-dimensional transistor 1T-1 Flash driving circuit array structure and its driving control method. Background Technology

[0002] As display technology evolves towards higher resolution, flexibility, and transparency, higher demands are placed on the integration, power consumption, and mechanical performance of backplane driving circuits. Traditional thin-film transistor (TFT) driving circuits face problems such as increased leakage current and significant short-channel effects during size miniaturization, leading to increased static power consumption and difficulty in meeting the driving requirements of ultra-high pixel density. Although silicon-based CMOS driving circuits have high integration, they are limited by rigid substrates and difficult to apply to flexible or transparent display scenarios. Two-dimensional semiconductor materials, due to their atomic-level thickness and excellent electrical properties, provide a new path for novel display driving. However, existing two-dimensional material driving solutions are mostly still in the stage of unit device verification, lacking mature arrayed integrated structures and matching driving control methods, making it difficult to achieve independent addressing and low power consumption of large-scale pixel units, thus limiting their application in practical display systems.

[0003] In summary, the existing technology has the following problems: it is difficult to achieve both miniaturization and flexible integration of existing display driving circuits; and the new two-dimensional transistor 1T-1Flash device can only operate in units and cannot drive LED dot matrices in an array. Summary of the Invention

[0004] This invention addresses the problems of existing display driving circuits, which struggle to achieve both miniaturization and flexible integration, and the fact that the novel 1T-1Flash two-dimensional transistor can only operate as a single unit and cannot drive LED dot matrices in an array.

[0005] To this end, on the one hand, embodiments of the present invention provide a two-dimensional transistor 1T-1Flash driving circuit array structure, including: a substrate layer and a plurality of pixel units arrayed on the substrate layer;

[0006] Each pixel unit includes a two-dimensional switching transistor and a two-dimensional non-volatile memory device;

[0007] The two-dimensional switching transistor and the two-dimensional non-volatile memory device are stacked in a direction perpendicular to the substrate layer, wherein the stacked arrangement from bottom to top consists of: a first gate layer, a charge blocking layer, a charge trapping layer, a second gate layer, a charge tunneling layer, and a two-dimensional semiconductor channel layer.

[0008] The multiple pixel units are arranged in a multi-row, multi-column array, with each row having a first control signal line and a second control signal line, and each column having a data signal line;

[0009] In the same row, the first gate layer of all the pixel units is electrically coupled to the first control signal line corresponding to that row, and the second gate layer of all the pixel units is electrically coupled to the second control signal line corresponding to that row;

[0010] In the same column, the first end of the two-dimensional semiconductor channel layer is connected to the corresponding data signal line, and the second end of the two-dimensional semiconductor channel layer is connected to the load device. By using a vertically stacked 1T-1 Flash structure, switching transistors and non-volatile memory devices are integrated into the same pixel area, effectively reducing the pixel footprint and improving the aperture ratio. Simultaneously, utilizing the two-dimensional semiconductor channel layer as a shared active region simplifies the manufacturing process. Furthermore, the orthogonal addressing architecture of row and column signal lines lays the physical foundation for independent control of large-scale arrays.

[0011] Furthermore, the first gate layer includes a control gate electrode and a first metal interconnect electrically coupled to the control gate electrode; the control gate electrode of each pixel unit is connected to the first control signal line of the corresponding row through the first metal interconnect in the same layer. The low-resistance connection between the control gate electrode and the row signal is achieved through the metal interconnect in the same layer, reducing the number of interlayer vias and lowering parasitic capacitance and process complexity.

[0012] Furthermore, the second gate layer includes: a metal gate electrode and a second metal interconnect electrically coupled to the metal gate electrode;

[0013] The metal gate electrodes of each pixel unit are connected to the second control signal line of the corresponding row via a second metal interconnect on the same layer. By arranging the gate interconnects and control gate interconnects of the switching transistors in layers, signal crosstalk is avoided, ensuring the integrity and stability of the scan signal transmission.

[0014] Furthermore, the thickness of the charge tunneling layer is 5nm~10nm; the thickness of the charge trapping layer is 3nm~10nm. By precisely controlling the thickness of the dielectric layer, sufficient data retention capability is ensured while maintaining nanosecond-level charge tunneling speed, thus balancing write / erase speed and storage reliability.

[0015] Furthermore, the array size of the pixel units is an 8×8 matrix, a 16×16 matrix, or a 32×32 matrix. This verifies the scalability of the structure at different scales and provides a modular basis for the design of higher resolution display panels.

[0016] Furthermore, the conductive channel width of the two-dimensional switching transistor is 5μm to 15μm, and the length is 2μm to 5μm; the conductive channel width of the two-dimensional non-volatile memory device is 10μm to 30μm, and the length is 2μm to 5μm. The aspect ratio of these devices is optimized, enabling the switching transistor to have sufficient drive current for rapid charging and discharging, while simultaneously providing the memory device with a suitable storage window and read margin.

[0017] Furthermore, the charge blocking layer is made of hafnium dioxide, aluminum oxide, or silicon dioxide; the thickness of the charge blocking layer is 10 nm to 30 nm. This effectively suppresses gate leakage current and improves the device's energy efficiency ratio.

[0018] Furthermore, the charge trapping layer is made of platinum, gold, or palladium; the thickness of the charge trapping layer is 1 nm to 5 nm. By using an inert metal nanolayer as the charge trapping center, its discrete energy level traps achieve efficient charge capture and long-term retention, while exhibiting good chemical stability and avoiding performance degradation caused by interfacial reactions.

[0019] Furthermore, the substrate layer is a p-type heavily doped silicon / silicon dioxide substrate. This provides a flat, insulating, and thermally stable growth platform, which is beneficial for high-quality transfer of two-dimensional materials and consistency of device performance.

[0020] On the other hand, embodiments of the present invention provide a drive control method based on a two-dimensional transistor 1T-1 Flash drive circuit array structure, including:

[0021] An erase pulse signal is applied to the first control signal line to erase the stored charge in the two-dimensional non-volatile memory device, so that the two-dimensional semiconductor channel layer is in the conducting state.

[0022] A scan enable signal is applied to the second control signal line row by row to enable the two-dimensional switching transistor, and a data write signal is applied to the data signal line column by column to write the target driving state to the corresponding pixel unit.

[0023] Stop applying the scan enable signal to turn off the two-dimensional switching transistor. The pixel unit relies on the charge held in the two-dimensional non-volatile memory device to maintain the load device in the working state corresponding to the target driving state.

[0024] By utilizing the charge retention characteristics of non-volatile memory devices, the system can maintain its operating state without continuous refresh after data is written, which significantly reduces the driving frequency and system power consumption. Through separate erasure, scan and data writing timing, independent and precise addressing of any pixel in the array is achieved.

[0025] The above technical solution has the following beneficial effects:

[0026] This invention integrates two-dimensional switching transistors and two-dimensional non-volatile memory devices in the same vertical space through a vertically stacked 1T-1 Flash pixel unit architecture, significantly reducing the physical footprint of the pixel unit and solving the area bottleneck and leakage problems faced by traditional planar TFT circuits during miniaturization. Utilizing the atomic-level thickness and dangling-bond-free surface characteristics of two-dimensional semiconductor materials, combined with charge tunneling and charge trapping layers of specific thicknesses, nanosecond-level high-speed erasure and writing and long-term data retention are achieved. This enables the driving circuit to maintain stable operation of the load device at extremely low refresh rates, fundamentally reducing the dynamic and static power consumption of the display system. Through orthogonal signal line layout and time-division driving control strategy, independent addressing and state locking of each pixel unit in a large-scale array are achieved, verifying the engineering feasibility of the two-dimensional material driving circuit transitioning from unit devices to array-based system integration. This provides core hardware architecture and driving paradigm support for future ultra-low power, highly integrated Micro-LED and flexible transparent display technologies. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a two-dimensional transistor 1T-1 Flash drive circuit array structure provided by an embodiment of the present invention;

[0028] Figure 2 This is a flowchart illustrating the fabrication process of a 1T-1 Flash driver circuit array structure based on a two-dimensional transistor, as provided in an embodiment of the present invention.

[0029] Figure 3a This is an optical microscope image of an embodiment of the present invention based on a two-dimensional transistor 1T-1 Flash driving circuit array structure;

[0030] Figure 3b yes Figure 3a A magnified view of a portion of the image;

[0031] Figure 3c yes Figure 3b A magnified view of a portion of the image;

[0032] Figure 4 This is a circuit connection diagram of the 1T-1 Flash driver circuit array structure based on two-dimensional transistors provided in an embodiment of the present invention;

[0033] Figure 5 The MoS2 in the 1T-1 Flash driver circuit array structure based on two-dimensional transistors provided in this embodiment of the invention. 2- FETs in V DS Transfer characteristic curve at 1 V;

[0034] Figure 6The storage window width of the MoS2-channel ultrafast flash memory in the 1T-1 Flash driver circuit array structure based on two-dimensional transistors provided in this embodiment of the invention is V. CG = Curve varying within the ±8 V scanning range;

[0035] Figure 7a This is a schematic diagram of the circuit connection of the 1T-1 Flash driver circuit array based on two-dimensional transistors provided in the embodiment of the present invention when the LED is lit.

[0036] Figure 7b for Figure 7a Equivalent circuit diagram of the LED in the lit state;

[0037] Figure 8a The current I flowing through the LED in the LED-lit state is provided by the two-dimensional transistor 1T-1 Flash driving circuit array driving circuit provided in this embodiment of the invention. LED Retention characteristics over 1000 s;

[0038] Figure 8b This corresponds to the current I flowing through the LED. LED With V SCAN The curve of voltage change;

[0039] Figure 9a This is a schematic diagram of the circuit connection of the 1T-1 Flash driving circuit based on two-dimensional transistors provided in the embodiment of the present invention in the LED off state;

[0040] Figure 9b for Figure 9a Equivalent circuit diagram of the LED in the lit state;

[0041] Figure 10 The embodiment of this invention provides a 1T-1 Flash driver circuit based on a two-dimensional transistor, which, when the LED is off, generates the current I flowing through the LED. LED Retention characteristics over 1000 s;

[0042] Figure 11 This is a schematic diagram of the circuit connection between the two-dimensional transistor 1T-1Flash driving circuit array structure and the LED dot matrix provided in the embodiment of the present invention;

[0043] Figure 12 This is a structural block diagram of the multi-channel testing system provided in an embodiment of the present invention;

[0044] Figure 13 This is a physical diagram of the interconnection between the 1T-1 Flash driver circuit array structure and the LED dot matrix provided in the embodiment of the present invention;

[0045] Figure 14 This is a physical image of the 1T-1 Flash driver circuit array structure provided in this embodiment of the invention after packaging.

[0046] Figure 15 The multi-channel test system provided in this embodiment of the invention synchronously outputs 8 V channels. PULSE Timing diagram of pulse signal;

[0047] Figure 16 The multi-channel test system provided in this embodiment of the invention outputs 8 V channels. SCAN Timing diagram of voltage signal;

[0048] Figure 17 The multi-channel test system provided in this embodiment of the invention synchronously outputs 8 V channels. DATA Timing diagram of voltage signal;

[0049] Figure 18 This is a physical image of the 1T-1 Flash driver circuit array structure provided in this embodiment of the invention illuminating a single column of LED dot matrix;

[0050] Figure 19 This is a physical image of the 1T-1 Flash driver circuit array structure provided in this embodiment of the invention, which illuminates 8 columns of LED dot matrix across the entire screen.

[0051] Figure 20 This is a flowchart illustrating the fabrication process of a two-dimensional transistor 1T-1 Flash drive circuit array structure provided in an embodiment of the present invention.

[0052] Explanation of icon numbers:

[0053] 01. Substrate layer; 02. Control gate electrode; 03. First metal interconnect; 04. Charge blocking layer; 05. Charge trapping layer; 06. Metal gate electrode; 07. Second metal interconnect; 08. Charge tunneling layer; 09. Two-dimensional semiconductor channel layer; 10. Drain electrode; 11. Top metal interconnect. Detailed Implementation

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0055] In embodiments of the present invention, such as Figure 1This paper presents a 1T-1 Flash driver circuit array structure based on two-dimensional transistors. The structure includes a substrate layer 01 and multiple pixel units arrayed on the substrate layer 01. Specifically, the substrate layer 01 serves as the mechanical support and electrical insulation platform for the entire driver circuit array, and its surface flatness directly affects the transfer quality of subsequent two-dimensional materials and the consistency of device performance. Multiple pixel units are regularly arranged in a matrix on the substrate layer 01, forming the minimum addressable unit set for display driving. This arrayed layout provides the physical basis for high-resolution displays.

[0056] Each pixel unit includes a two-dimensional switching transistor and a two-dimensional non-volatile memory device. In this embodiment, the two-dimensional switching transistor and the two-dimensional non-volatile memory device are not arranged side-by-side as in a traditional planar TFT circuit, but are stacked in a direction perpendicular to the substrate layer 01. Specifically, as shown... Figure 1 The stacked structure, from bottom to top, consists of: a first gate layer, a charge blocking layer 04, a charge trapping layer 05, a second gate layer, a charge tunneling layer 08, and a two-dimensional semiconductor channel layer 09. This vertical stacking order is carefully designed: the first gate layer is located at the bottom and serves as the control gate for the non-volatile memory device, used to regulate the charge state in the charge trapping layer 05; the charge blocking layer 04 is adjacent to the first gate layer and is used to prevent charge leakage to the substrate; the charge trapping layer 05 is located above the blocking layer and serves as the core medium for storing charge; the second gate layer is located above the trapping layer and serves as the gate of the two-dimensional switching transistor, used to control the conduction and turn-off of the channel; the charge tunneling layer 08 covers the second gate layer and serves as both the gate medium of the switching transistor and the tunneling medium of the memory device; the topmost two-dimensional semiconductor channel layer 09 serves as the active region shared by the two devices.

[0057] To achieve independent control of each pixel unit in the array, multiple pixel units are arranged in a multi-row, multi-column array. Each row has a first control signal line and a second control signal line, and each column has a data signal line. Within the same row, the first gate layer of all pixel units is electrically coupled to the corresponding first control signal line, and the second gate layer of all pixel units is electrically coupled to the corresponding second control signal line. Figure 4 As can be seen from the circuit connection diagram, the first control signal line (e.g., V) PULSE ) is specifically used to apply erase / write pulses to the first gate layer to change the threshold voltage state of the non-volatile memory device; while the second control signal line (e.g., V) SCAN The second gate layer is specifically used to apply a scan voltage to the second gate layer to select or turn off the corresponding row of switching transistors. This physical realization of independent dual-gate control benefits from the characteristic that the two gate layers are naturally isolated by the intermediate dielectric layer in the vertical stacked structure, which makes the storage operation and the addressing operation electrically decoupled.

[0058] In the same column, the first end of the two-dimensional semiconductor channel layer 09 is connected to the corresponding data signal line, and the second end of the two-dimensional semiconductor channel layer 09 is connected to the load device. Specifically, when a row is selected by the second control signal line and the non-volatile memory device in the pixel unit of that row is in the on state, the voltage signal (e.g., V) on the data signal line... DATA The signal can then be transmitted to the load device (such as an LED) through the two-dimensional semiconductor channel layer 09, thereby driving the load to emit light or perform other functions. Since the two-dimensional semiconductor channel layer 09 simultaneously acts as the conductive channel for the switching transistor and the read channel for the memory device, this shared channel design eliminates the need for additional capacitors or transistors in traditional 1T1C or 2T1C pixel circuits, greatly simplifying the fabrication process. Furthermore, the column-direction data signal lines and row-direction control signal lines form a positive cross-connect topology, which, together with the vertically stacked pixel units, constructs a high-density, low-power active matrix driving array. It should be noted that the type of load device is not limited to LEDs; it can also be Micro-LEDs, OLEDs, or other display or sensing elements requiring current / voltage driving, as long as their connection to the second end of the channel layer meets the driving requirements.

[0059] Based on the above embodiments, the interconnection structure of the row signal lines is further refined. Specifically, the first gate layer includes a control gate electrode 02 and a first metal interconnect 03 electrically coupled to the control gate electrode 02. The control gate electrode 02 of each pixel unit is connected to the first control signal line of the corresponding row through the first metal interconnect 03 on the same layer. Figure 1 and Figure 3c The microstructure shown indicates that the control gate electrode 02 and the first metal interconnect 03 are not discrete components connected across layers via interlayer vias, but rather an integrated continuous structure patterned using the same conductive thin film material in the same process step. For example, this integrated structure can be achieved by depositing a chromium / gold (Cr / Au) or titanium / gold (Ti / Au) composite metal thin film, followed by a single photolithography and etching process to simultaneously define the electrode region and the wiring region. Preferably, the metal thin film is Cr / Au with a thickness of 5 nm / 15 nm; preferably, the width of the first metal interconnect 03 is 5 μm.

[0060] This same-layer interconnect design eliminates the interlayer vias required in traditional multilayer interconnect architectures. This not only significantly reduces contact resistance and open-circuit risks caused by via alignment misalignment, but also effectively reduces parasitic capacitance at interconnect nodes, thereby improving the first control signal line (V... PULSE The integrity and response speed of the nanosecond-level erase / write pulse signal transmission. It should be understood that although the figure shows a linear interconnect shape, the first metal interconnect 03 can also be designed as a polygonal, grid, or other topological shape according to the array layout requirements.

[0061] In one implementation, the second gate layer includes a metal gate electrode 06 and a second metal interconnect 07 electrically coupled to the metal gate electrode 06. The metal gate electrode 06 of each pixel unit is connected to a second control signal line of the corresponding row via the second metal interconnect 07 in the same layer. The metal gate electrode 06 and the second metal interconnect 07 may be made of materials such as chromium / gold (Cr / Au) and titanium / gold (Ti / Au). Preferably, the metal thin film of the metal gate electrode 06 is Cr / Au with a thickness of 5 nm / 15 nm; preferably, the width of the second metal interconnect 07 is 5 μm.

[0062] Reference Figure 1 The diagram illustrates the layering, with the second gate layer positioned above the first gate layer, physically separated by dielectric layers such as charge blocking layer 04 and charge trapping layer 05. This layered arrangement allows for the carrying of scan signals (V... SCAN The second metal interconnect 07 carries the erase / write pulse signal (V). PULSE The first metal interconnect 03 achieves spatial decoupling in the vertical direction. Specifically, the metal gate 06 of each row of two-dimensional transistors is connected to V via metal interconnect 07. SCAN Connected. Among them, V SCAN Used to generate a frequency-adjustable square wave voltage signal to turn the two-dimensional transistor on or off; correspondingly, V SCAN The voltage range is -6 V to 6 V; preferably, V SCAN The low level is -3 V, and the high level is 5 V. Compared to the traditional design that arranges the two types of signal lines on the same plane, this embodiment uses vertically stacked dielectric layers as a natural shielding layer, which significantly reduces capacitive coupling and crosstalk to sensitive memory nodes during high-frequency scanning signal transitions, ensuring that the data retention characteristics of non-volatile memory devices are not affected by addressing operations. Simultaneously, the second gate layer is also fabricated using an integrated patterning process similar to the control gate electrode, ensuring a low-impedance path for the switching transistor gate drive. In actual manufacturing, the metal materials of the first and second gate layers can be the same or different. For example, both can be low-resistivity Au-based composite metals, or different metal systems can be selected according to work function matching requirements. This flexibility in materials and processes provides additional degrees of freedom for optimizing the device's threshold voltage and driving capability.

[0063] As one implementation, the material and thickness parameters of the charge control layer in the pixel unit are further described in detail. Specifically, the charge barrier layer 04 is made of hafnium dioxide, aluminum oxide, or silicon dioxide, and its thickness is 10 nm to 30 nm. Preferably, the charge barrier layer 04 is made of HfO2 and has a thickness of 20 nm. The charge barrier layer 04 is located between the first gate layer and the charge trapping layer 05, and its core function is to build a sufficiently high barrier to prevent the stored charge from leaking to the control gate electrode 02, while also serving as a capacitor dielectric to couple the control voltage. In specific implementations, hafnium dioxide (HfO2) is preferably used as the material of the charge barrier layer 04 because, compared to conventional silicon dioxide, hafnium dioxide has a higher dielectric constant (k value of approximately 20 to 25), which can provide a larger physical thickness with the same equivalent oxide layer thickness, thereby effectively suppressing gate leakage current while ensuring sufficient gate control capacitance. Regarding the thickness selection, if the thickness of the charge barrier layer 04 is less than 10 nm, it is difficult to completely block charge penetration under high field strength, leading to degradation of data retention characteristics. If the thickness is greater than 30 nm, it will significantly reduce the coupling efficiency of the control gate to the channel, forcing an increase in the erase and write voltage, which increases the power consumption and design complexity of the peripheral drive circuit. Therefore, controlling the thickness of the charge barrier layer 04 within the range of 10 nm to 30 nm achieves the best balance between leakage current suppression and drive efficiency.

[0064] In one implementation, the charge trapping layer 05 is made of platinum, gold, or palladium, and its thickness is 1 nm to 5 nm. Preferably, the metal thin film of the charge trapping layer 05 is Pt with a thickness of 3 nm. In other embodiments of this application, the thickness of the charge trapping layer 05 can be extended to the range of 3 nm to 10 nm to adapt to different process conditions or storage density requirements. As the core medium for non-volatile storage, the charge trapping layer 05 utilizes discrete defect states or metal / dielectric interface states in the metal nanolayer to trap and store charges. Inert noble metals such as platinum (Pt), gold (Au), or palladium (Pd) are chosen because they have extremely high chemical stability and are not prone to oxidation or harmful interfacial diffusion reactions with adjacent dielectric layers under subsequent high-temperature processes or long-term electrical stress, thereby ensuring the cleanliness of the storage interface and device lifespan. From a microscopic perspective, these metal nanolayers provide deep-level traps, allowing the trapped charges to have a longer relaxation time. Regarding the critical balance of thickness, experimental verification shows that when the thickness of the charge trapping layer 05 is less than 1 nm, the metal film tends to form discrete island structures rather than a continuous layer, resulting in insufficient and uneven distribution of effective trap density and a significantly narrowed storage window. When the thickness exceeds 5 nm (especially when approaching or exceeding 10 nm), the shielding effect of the metal layer itself is enhanced, which not only weakens the control gate electric field's ability to regulate the channel but also prolongs the response path for charge injection and extraction, leading to a significant hysteresis in erase and write speeds. Therefore, 1 nm to 5 nm is the preferred range for balancing high-density traps and fast response, while 3 nm to 10 nm provides broader process tolerance protection.

[0065] Furthermore, the charge tunneling layer 08 has a thickness of 5 nm to 10 nm. Directly adjacent to the two-dimensional semiconductor channel layer 09, the charge tunneling layer 08 is a critical bottleneck layer determining the device's erase / write speed and data retention time. The thickness of this layer is essentially a search for a nonlinear balance between quantum tunneling probability and thermally excited leakage. The charge tunneling layer 08 is made of dielectric materials such as hafnium dioxide (HfO2), aluminum oxide (Al2O3), and silicon dioxide (SiO2). HfO2 is preferred, and the thickness of the charge tunneling layer 08 is 10 nm. This ensures that, at a typical operating voltage of approximately ±15 V, both ultrafast erase / write speeds on the order of 20 ns and stable retention times exceeding 1000 seconds are achieved.

[0066] like Figure 6The MoS2 channel ultrafast flash memory memory window characteristic curves shown confirm the effectiveness of the above parameter system. In this test, using a 20nm thick HfO2 layer as the charge blocking layer 04, a 3nm thick Pt layer as the charge trapping layer 05, and a 10nm thick HfO2 layer as the charge tunneling layer 08, a clear and broad memory window hysteresis curve was observed under the condition that the control gate voltage VCG scan range was -8V to +8V. This curve shows that, under the above-mentioned optimal parameter combination, the device has a sufficiently large threshold voltage drift to distinguish between the "0" and "1" states, and the curves are highly consistent, demonstrating the robustness of the three-layer dielectric synergy mechanism in actual array fabrication.

[0067] As one implementation method, the optional configurations of array size, device dimensions, and substrate type are further described in detail to demonstrate the modular scalability and process adaptability of the technical solution in different application scenarios. The array size composed of pixel units is an 8×8 matrix, a 16×16 matrix, or a 32×32 matrix. Figure 3a The optical microscope image shown illustrates the array arrangement of an 8×8 matrix, a scale sufficient to verify the effectiveness of the row-column orthogonal addressing logic and full-screen illumination function. However, the vertically stacked 1T-1 Flash architecture of this application is inherently highly scalable and is not limited to the aforementioned verification-level scale. In practical high-resolution Micro-LED or flexible display applications, this array size can be seamlessly expanded to 16×16, 32×32, or even higher-order matrix forms. Since each pixel unit integrates switching and storage functions in the vertical direction, and the inter-row and inter-column signal lines employ an orthogonal decoupling design, this modular expansion does not introduce additional planar area overhead or complex signal crosstalk problems, thus providing a solid hardware foundation for the design of future ultra-high pixel density display panels. It should be understood that although this embodiment lists a specific matrix size, without departing from the concept of this application, any regular or irregular array arrangement based on this vertically integrated unit, as long as it can achieve independent addressing and state maintenance functions, should be considered an equivalent implementation of this application.

[0068] As one implementation method, to optimize the match between driving performance and storage reliability, the conductive channel width of the two-dimensional switching transistor is 5μm~15μm and the length is 2μm~5μm; the conductive channel width of the two-dimensional non-volatile memory device is 10μm~30μm and the length is 2μm~5μm. This differentiated size design is based on the distinct physical functions of the two devices. For the two-dimensional switching transistor, its core task is to act as a gating switch to quickly respond to scan signals and provide sufficient drive current to write data or drive the load. Therefore, controlling its channel width within the range of 5μm~15μm ensures sufficient transconductance and on-state current while keeping parasitic capacitance at a low level, thereby supporting nanosecond-level switching speeds and high-frequency scan operations. In contrast, the core task of the two-dimensional non-volatile memory device is to provide a stable and sufficiently wide storage window to ensure long-term data retention, which requires a larger charge trapping area and stronger gate coupling capability. Therefore, designing the channel width to be 10μm~30μm, significantly larger than the width of the switching transistor, can effectively increase the number of effective traps in the charge trapping layer, improve the threshold voltage drift (i.e., the memory window), and the larger channel area also helps to average out any microscopic defects that may exist in the two-dimensional semiconductor channel layer 09, improving device yield and uniformity. If the channel width of the memory device is too small, the narrowing of the memory window will lead to insufficient read / write margin; if the channel width of the switching transistor is too large, it will cause a surge in the load capacitance of the row scan line, limiting the refresh rate. Therefore, the combination of the above size ranges is the preferred solution for achieving high-speed driving and high-reliability memory working together.

[0069] Furthermore, the substrate 01 is a p-type heavily doped silicon / silicon dioxide substrate. In this embodiment, the substrate 01 not only serves as a mechanical support carrier but also undertakes the dual functions of electrical isolation and interface optimization. Specifically, the p-type heavily doped silicon substrate has good conductivity and can serve as a global back gate or electromagnetic shielding layer, effectively suppressing the interference of external environmental noise on sensitive two-dimensional devices. It also facilitates back gate modulation during the testing phase to characterize the intrinsic properties of the material. The silicon dioxide layer (preferably 300 nm thick) covering the surface of the silicon substrate provides crucial insulation and atomically flat interface. For the fabrication of the two-dimensional semiconductor channel layer 09, the surface roughness of the substrate directly determines the lattice integrity and interface state density of the two-dimensional material after transfer. After thermal oxidation or chemical vapor deposition, the silicon dioxide layer can achieve extremely low surface roughness, which is crucial for ensuring high-quality transfer of large-area two-dimensional thin films and reducing interface scattering and charge trapping. If the substrate flatness is insufficient, wrinkles, cracks, or bubbles are easily generated in the two-dimensional material during the transfer process, leading to increased leakage current, decreased mobility, or even complete device failure. In other embodiments, depending on the application requirements, the substrate 01 can also be replaced with glass, polyimide (PI), sapphire, or other insulating or flexible substrates, as long as its surface can provide the flatness and insulation required for two-dimensional material transfer. This flexibility in substrate selection allows the technical solution of this application to be widely adapted to various emerging application fields such as rigid displays, flexible wearable electronics, and transparent displays.

[0070] Furthermore, in embodiments of the present invention, such as Figure 20 Furthermore, a drive control method based on a two-dimensional transistor 1T-1 Flash drive circuit array structure is provided, which is applied to the aforementioned two-dimensional transistor 1T-1 Flash drive circuit array structure. For example... Figure 15 , Figure 16 , Figure 17 As shown, this driving control method achieves independent addressing and non-volatile state maintenance of pixel units through specific timing logic, specifically including the following steps:

[0071] S101: An erase pulse signal is applied to the first control signal line to erase the stored charge in the two-dimensional non-volatile memory device, thereby putting the two-dimensional semiconductor channel layer into a conductive state; specifically, in conjunction with Figure 15 The timing diagram, the first control signal line (i.e., V) PULSEA negative pulse voltage with a specific amplitude and width is applied. For example, in this embodiment, the amplitude of the erase pulse signal is -15V and the pulse width is 20ns. From a microscopic physical perspective, this negative high-voltage pulse establishes a strong electric field in the vertically stacked structure, causing the charge (such as electrons) originally stored in the charge trapping layer 05 to be released back to the two-dimensional semiconductor channel layer 09 through quantum tunneling, or inducing hole injection to neutralize the stored charge, thereby eliminating the threshold voltage drift caused by previous programming operations. This process resets the two-dimensional non-volatile memory device to its initial low threshold voltage state, allowing the two-dimensional semiconductor channel layer 09 to exhibit a high conductivity conduction state without additional gate voltage assistance, providing a unified reference starting point for subsequent data writing operations. It should be understood that although a negative pulse is preferably used for erasure in this embodiment, in other embodiments, depending on the charge trapping layer material and the type of two-dimensional semiconductor, a positive pulse or a pulse signal of other polarities can also be used to achieve the charge erasure function, as long as it can achieve the reset of the storage state. Furthermore, the erasure operation can be performed simultaneously on all rows of the entire array, or on specific rows as needed. This flexibility allows the system to adapt to different display refresh strategies.

[0072] S102: A scan enable signal is applied row by row to the second control signal line to turn on the two-dimensional switching transistor, and a data write signal is applied column by column to the data signal line to write the target driving state to the corresponding pixel unit; after completing the erase operation, the system enters the active addressing write stage. Combined with... Figure 16 and Figure 17 The timing diagram, the second control signal line (i.e., V) SCAN The system outputs a high-level scan enable signal (e.g., 5V) line by line according to a preset scan frequency to select the two-dimensional switching transistors in all pixel units of the current row; simultaneously, the data signal lines (i.e., V) of each column... DATA Based on the image data to be displayed, corresponding high and low level data write signals are synchronously output (e.g., 4V for on, 0V for off). When a row is selected, the two-dimensional switching transistors of all pixel units in that row are turned on, and the voltage on the data signal line is transmitted through the two-dimensional semiconductor channel layer 09 to the control terminal of the two-dimensional non-volatile memory device, thereby changing the charge distribution state in the charge trapping layer 05 and "locking" the target driving state inside the pixel unit. Due to the adoption of a row-column orthogonal addressing architecture, only when simultaneously selected by V SCAN Gated and V DATAOnly pixels with an active voltage level will undergo a state transition; rows that are not selected will remain in their original state undisturbed. This time-division multiplexing write method not only achieves precise independent control of each pixel in a large-scale array but also effectively reduces instantaneous power consumption and signal line load. It should be noted that although the diagram shows the sequence of row-by-row scanning, in practical applications, interlaced scanning, block scanning, or random addressing can be used to replace the timing sequence, as long as the scan signal and data signal are correctly matched in time and space at the time of writing.

[0073] S103: Stop applying the scan enable signal to turn off the two-dimensional switching transistor. The pixel unit relies on the charge held in the two-dimensional non-volatile memory device to maintain the load device in the working state corresponding to the target driving state. Specifically, when the data of a certain row is written, V SCAN When the signal returns to a low level (e.g., -3V), all two-dimensional switching transistors in that row are immediately turned off, severing the electrical connection between the data signal line and the pixel unit. Unlike traditional DRAM or 1T1C pixel circuits that rely on capacitors to store charge and require frequent refreshes to prevent data loss, the pixel unit in this embodiment utilizes the charge trapping characteristics of two-dimensional non-volatile memory devices to preserve the driving state. Even when completely isolated from external signal lines, the written charge can still be stably trapped in the deep-level traps of the charge trapping layer 05, thereby maintaining the conductivity of the two-dimensional semiconductor channel layer 09 for a long time, allowing the load device (such as an LED) to continuously emit light or remain off. Actual measurement data shows that at room temperature, the current retention time of this pixel unit can exceed 1000 seconds. This means that the system theoretically only requires an ultra-low refresh rate of 0.001Hz to maintain a static image display. Compared to traditional driving schemes with refresh rates of 60Hz or even higher, the system's dynamic power consumption can be reduced by several orders of magnitude. This non-volatile driving mechanism, which allows the display to remain active even after scanning stops, is the core feature that distinguishes this application from existing technologies. It fundamentally decouples the strong bond between display retention and signal refresh, providing a completely new technical path for ultra-low power display applications. It should be noted that although this embodiment uses an LED as the load device, this driving control method is equally applicable to Micro-LEDs, OLEDs, electrophoretic displays, or any other load type requiring non-volatile voltage / current driving. Its applicability should not be limited to specific load types.

[0074] In one implementation, the second end of the two-dimensional semiconductor channel layer 09 is connected to a load device. Preferably, the load device is an 8×8 LED dot matrix screen. However, it should be understood that this is only an exemplary application of the technical solution of this application. In other implementations, the load device can also be a Micro-LED, OLED, electrophoretic display unit, or any other light-emitting or display element that requires current or voltage driving, as long as it can form an effective electrical connection with the second end of the two-dimensional semiconductor channel layer 09 and be controlled by the driving state of the pixel unit.

[0075] like Figure 11 The diagram shows the circuit connection schematic of the 1T-1 Flash driver circuit array structure and the LED dot matrix interconnection. In this interconnection architecture, the drain of each column of two-dimensional switching transistors is connected to the corresponding data signal line V through the top metal interconnect 11. DATA The two-dimensional switching transistors are connected, with the source of each column connected to the anode of the corresponding LED, and the cathodes of all LEDs grounded. This connection method constitutes a typical active matrix drive topology, where the 1T-1 Flash pixel unit acts as a current-driven valve with non-volatile memory. When a row is selected and the two-dimensional non-volatile memory device in the corresponding pixel unit is in the on state, the data signal line V... DATA The voltage applied to the LED can be transmitted through the two-dimensional semiconductor channel layer 09 to the LED anode, causing it to emit light; conversely, if the memory device is in a turned-off state or the row is not selected, the LED remains off. It is worth emphasizing that, because the two-dimensional non-volatile memory device has charge retention capability, even during scanning signal V... SCAN After removal, the on / off state of the LED can still be maintained by the charge stored in the charge trapping layer 05, without relying on capacitors to store charge and perform high-frequency refresh as in traditional DRAM-type pixels. This is the physical basis for achieving ultra-low power display in this application.

[0076] To achieve precise timing control and performance characterization of the array, this embodiment employs the following... Figure 12 The hardware architecture of the multi-channel test system is shown. The core of this system is based on an FPGA control unit, coupled with a high-precision DAC module and analog output conditioning circuitry, enabling synchronous output of 64 analog voltage signals with a voltage amplitude range covering ±15V, fully meeting the requirements of a 1T-1 Flash array for V... PULSE V SCAN and V DATA Signal amplitude and accuracy requirements. For example... Figure 13As shown in the physical connection diagram, the 1T-1Flash driver circuit array under test is connected to the test system via a ZIF socket, and the LED dot matrix screen is interconnected with the array output terminal via a breadboard. It should be noted that although this embodiment uses a discrete multi-channel test system for verification, this is only a characterization method during the R&D stage; in actual mass-produced products, the driver circuit array can be directly integrated with dedicated display driver ICs, ASIC chips, or peripheral circuits on a flexible substrate, and the existence of the test system should not be considered a limitation on the scope of protection of this application.

[0077] In the specific driver demonstration, the independent addressing capability of a single-row LED was first verified. For example... Figure 18 As shown, the V of a specific column is tested using a multi-channel testing system. DATA Apply a 4V high level, and simultaneously apply a 4V high level to the corresponding row's V. SCAN Apply a 5V turn-on signal and control V. PULSE Applying a -15V / 20ns erase pulse to ensure the memory window is open successfully enabled precise lighting of 8 LEDs in a single column, while unselected columns remained completely off. This demonstrates the correctness of the row-column orthogonal addressing logic and the good isolation between pixel units, with no significant crosstalk. Furthermore, as... Figure 19 As shown, when the test system synchronously scans 8 lines of V at a frequency of 1kHz... SCAN Signal and corresponding V DATA During data streaming, the 8×8 LED dot matrix screen achieved uniform illumination across the entire screen, with no visible flicker. This result not only verifies that the response speed of the 1T-1 Flash array under dynamic scanning is sufficient to support conventional display refresh rates, but also demonstrates the uniformity and yield of the fabrication process on large-area arrays.

[0078] More importantly, this embodiment demonstrates the advantages of non-volatile architecture in terms of power consumption through actual measurement data. For example... Figure 8a As shown, when the LED is lit, the current ILED flowing through the LED maintained extremely high stability for up to 1000 seconds, with no significant attenuation observed; simultaneously, as Figure 10 As shown, the off-state leakage current is as low as 10 when the LED is off. -12 On the order of magnitude A. These two sets of data together reveal an important technical fact: because pixel units rely on the charge held in a two-dimensional non-volatile memory device to maintain the load device in the working state corresponding to the target driving state, the system theoretically only needs to perform the next refresh after 1000 seconds to compensate for possible charge loss after writing a frame of image data. This means that for static image display, the driving refresh rate of this application can be as low as 0.001Hz, which is 4 to 5 orders of magnitude lower than the 60Hz or even higher refresh rates typically required by traditional LCD or OLED displays.

[0079] Example 1:

[0080] In an embodiment of the present invention, a two-dimensional transistor 1T-1Flash driving circuit array structure is provided, including: a substrate layer 01 and a plurality of pixel units arrayed on the substrate layer 01;

[0081] Specifically, two-dimensional transistors (T) and two-dimensional ultrafast flash memory are integrated on the substrate layer, and cell interconnection and array expansion are achieved to form a 1T-1 Flash array structure, which includes:

[0082] Patterned Cr / Au electrodes were deposited on a SiO2 / Si substrate to serve as the control gate electrode and metal interconnect of a two-dimensional ultrafast flash memory, respectively; wherein the Cr layer thickness was 5 nm, the Au layer thickness was 15 nm, and the metal interconnect width was 5 μm.

[0083] A 20 nm thick HfO2 film was deposited using an atomic layer deposition (ALD) device as a charge blocking layer for a two-dimensional ultrafast flash memory.

[0084] A patterned Pt thin film is deposited on the surface of the charge blocking layer as a charge trapping layer. The thickness of the charge blocking layer ranges from 3 to 10 nm, preferably from 1 to 5 nm. In addition, the thickness of the Pt layer can be 3 nm or 8 nm.

[0085] Patterned Cr / Au electrodes are deposited on the surface of the charge barrier layer to serve as the metal gate and metal interconnect of the two-dimensional transistor, respectively; wherein the Cr layer is 5 nm thick, the Au layer is 15 nm thick, and the metal interconnect is 5 μm wide.

[0086] A 10 nm thick HfO2 film was deposited using atomic layer deposition (ALD) as the charge tunneling layer 08 of the two-dimensional ultrafast flash memory. A monolayer MoS2 film grown by chemical vapor deposition (CVD) was transferred to the surface of the charge tunneling layer 08. The MoS2 film was then etched into the desired patterned array using a photolithography-exposure method. The etching equipment was reactive ion etching (RIE), the carrier gas was a mixture of O2 and Ar, the etching power was 30 W, and the etching time was 10 s.

[0087] Patterned Cr / Au electrodes are deposited and used as the source electrode, drain electrode 10, and metal interconnect of MoS2, respectively, to obtain a 1T-1 Flash array structure based on two-dimensional transistors and two-dimensional ultrafast flash memory. The source electrode, drain electrode 10, and metal interconnect include chromium / gold (Cr / Au) and titanium / gold (Ti / Au), etc. Preferably, the Cr layer thickness is 5 nm, the Au layer thickness is 45 nm, and the metal interconnect width is 5 μm. The 1T-1 Flash array has an 8 × 8 array size, the channel size (length × width) of the MoS2-FETs is 10 μm × 3 μm, and the channel size (length × width) of the MoS2 ultrafast flash memory is 20 μm × 3 μm.

[0088] Specifically, the control gate of each row of two-dimensional ultrafast flash memory is connected to V via a metal interconnect. PULSE Connected, the metal gate of each row of two-dimensional transistors is connected to V via metal interconnects. SCAN Connected, specifically including:

[0089] The control gate of each row of MoS2 channel ultrafast flash memory is connected in series with V. PULSE Connect them, and you will eventually get V. PULSE1 V PULSE2 V PULSE3 V PULSE4 V PULSE5 V PULSE6 V PULSE7 and V PULSE8 The metal gates of each row of MoS2-FETs are connected in series with V. SCAN Connect them, and you will eventually get V. SCAN1 V SCAN2 V SCAN3 V SCAN4 V SCAN5 V SCAN6 V SCAN7 and V SCAN8 Specifically, the drain of each column of two-dimensional transistors is connected to V via a metal interconnect. DATA The source of each column of two-dimensional transistors is connected to the anode of the LED screen, and the cathode of the LED screen is grounded. Specifically, this includes:

[0090] The drain of each row of MoS2-FETs is connected in series with V. DATA Connect them, and you will eventually get V. DATA1 V DATA2 V DATA3 V DATA4 V DATA5 V DATA6 V DATA7 and V DATA8The source of each row of MoS2-FETs is connected to the anode of the LED, and the cathode of the corresponding LED is grounded. Specifically, for V... PULSE A 20-nanosecond negative pulse voltage is applied to erase the data, and V is scanned line by line. SCAN Column-by-column scan V DATA This enables independent addressing and full-screen illumination of the LED dot matrix screen, specifically including: simultaneously testing 8 rows of V through a multi-channel testing system. PULSE (V) PULSE1 To V PULSE8 When a negative pulse voltage with a pulse width of 20 ns and a pulse voltage amplitude of -15 V is applied, the stored data is erased and the MoS2 channel is opened.

[0091] By changing the 8 lines of V using a multi-channel testing system SCAN (V) SCAN1 To V SCAN8 The voltage level changes from low (-3V) to high (5V), corresponding to the 8 MoS2-FETs in the row being turned on; the V in the first column is tested using a multi-channel test system. DATA1 When a 4V voltage is applied, the eight 1T-1 Flash arrays in the first column are selected, and the corresponding LEDs in the first column are lit. Using a multi-channel testing system, the voltage in the nth row is changed... SCAN (8 ≥ n ≥ 1) level states, the nth column V DATA A level state of (8 ≥ n ≥ 1) enables individual addressing of the 1T-1 Flash in row n; through a multi-channel test system, V is synchronously scanned. SCAN1 To V SCAN8 V DATA1 To V DATA8 The LED screen is fully illuminated when the scanning frequency is 1 kHz.

[0092] Example 2:

[0093] The present invention also provides a method for fabricating a two-dimensional transistor 1T-1 Flash driving circuit array structure, such as Figure 2 As shown, it includes the following steps:

[0094] Step S11: A patterned metal thin film is deposited on the substrate layer 01 as a control gate electrode 02 and a metal interconnect 03, and a gate dielectric thin film is deposited using an atomic layer deposition device as a charge blocking layer 04.

[0095] Step S12: deposit patterned metal thin films as charge trapping layer 05, metal gate electrode 06 and metal interconnect 07 respectively, and then deposit gate dielectric thin film as charge tunneling layer 08.

[0096] Step S13: Transfer the two-dimensional semiconductor thin film 09, pattern the two-dimensional semiconductor thin film using photolithography, and then deposit source electrodes, drain electrodes 10, and metal interconnects 11 to obtain a (1T-1Flash) driving circuit array structure based on two-dimensional transistors and two-dimensional ultrafast flash memory. The two-dimensional semiconductor thin film contains materials such as MoS2, WS2, MoSe2, and WSe2, and the number of layers of the two-dimensional semiconductor material ranges from 1 to 3. Preferably, the two-dimensional semiconductor material is MoS2, and the number of layers is 1. In addition, the source electrode of each column of two-dimensional transistors is connected to the anode of the LED screen, and the cathode of the LED screen is grounded. Wherein, V DATA Used to generate a frequency-adjustable square wave voltage signal to turn the LED on or off; correspondingly, V DATA The voltage range is 0 V to 6 V; preferably, V SCAN A low level is 0V (off), and a high level is 4V (on). (Regarding V) PULSE A 20-nanosecond negative pulse voltage is applied to erase the data, and V is scanned line by line. SCAN Column-by-column scan V DATA This enables independent addressing and full-screen illumination of the LED dot matrix screen. The LED dot matrix screen is an 8×8 matrix or other type; V SCAN The scanning frequency range is 0.001 Hz to 10 kHz or other.

[0097] In step S14, the control gate 02 of each row of two-dimensional ultrafast flash memory is connected to V via metal interconnect 03. PULSE Connected, the metal gate 06 of each row of two-dimensional transistors is connected to V via metal interconnect 07. SCAN Connected;

[0098] In step S15, the drain 10 of each column of two-dimensional transistors is connected to V via metal interconnect 11. DATA The source 10 of each column of two-dimensional transistors is connected to the anode of the LED screen, and the cathode of the LED screen is grounded.

[0099] Step S16, for V PULSE A 20-nanosecond negative pulse voltage is applied to erase the data, and V is scanned line by line. SCAN Column-by-column scan V DATA This enables independent addressing and full-screen illumination of the LED dot matrix screen.

[0100] like Figure 1 As shown, the substrate 1 is mainly a p-type heavily doped silicon / silicon dioxide (SiO2 / Si) substrate with a silicon dioxide layer thickness of 300 nm.

[0101] The silicon dioxide layer plays two key roles in the device: first, as an insulating layer, it isolates the silicon substrate from the charge trapping layer and suppresses charge leakage to the substrate; second, it provides a highly flat and low-defect interface for the subsequent stacking of two-dimensional semiconductor materials.

[0102] The deposited patterned metal thin film serves as the control gate electrode (02) and the metal interconnect (03); the metal thin film comprises a chromium (Cr) or titanium (Ti) thin film layer with strong adhesion and a gold (Au) thin film layer with conductive properties; wherein the thickness of the adhesion layer is 5-10 nm and the thickness of the conductive layer is 20-40 nm. Preferably, the thickness of the adhesion layer is 5 nm and the thickness of the conductive layer is 20 nm.

[0103] The optional materials for the charge blocking layer 04 and the charge tunneling layer 08 include high dielectric constant materials such as HfO2, Al2O3, and MoO3. HfO2 is preferred for the blocking layer and the charge tunneling layer, with thicknesses of 20 nm and 10 nm, respectively.

[0104] Due to its high dielectric constant and wide bandgap, HfO2 can reduce gate leakage current to extremely low levels, which is crucial for ensuring long-term data retention in memory cells. The dielectric constant of hafnium oxide (k ~ 20 - 25) is much higher than that of conventional SiO2 (k ~ 3.9). With the same physical thickness, HfO2 can provide a smaller equivalent oxide thickness (EOT), thus offering higher capacitance and superior gate control performance.

[0105] The thickness of the charge tunneling layer 08 is crucial to its performance. If the thickness is too thin (e.g., less than 5 nm), the barrier width is insufficient, and the charge may tunnel through leakage current even under zero-field conditions, resulting in a data retention time far below the required 1000 seconds. Conversely, if the thickness is too thick (e.g., greater than 10 nm), the barrier width is too large, and a sufficiently strong electric field cannot be established under a typical pulse voltage of 15V, causing the charge tunneling time to exceed 100 ns, which cannot meet the nanosecond-level operation requirements. Furthermore, forcibly increasing the voltage will risk barrier layer breakdown. Therefore, the thickness of the charge tunneling layer is precisely controlled within the range of 5–10 nm, stabilizing the charge tunneling response time at 20–200 ns, thus matching the ultrafast erase and write performance requirements of the device.

[0106] The charge trapping layer film 05 is made of an inert metal such as platinum (Pt), palladium (Pd), or gold (Au). Pt is preferably used as the charge trapping layer film.

[0107] If highly chemically reactive metals such as aluminum (Al) and copper (Cu) are used as electrodes, they are prone to oxidation or diffusion into the two-dimensional material layer during device fabrication (e.g., transfer, annealing) or operation. These interfacial reactions can disrupt the structural integrity of the charge tunneling layer and conductive channel, ultimately leading to device failure. In contrast, noble metals such as Pt, Pd, and Au have extremely strong chemical inertness and do not undergo harmful reactions such as oxidation or diffusion when in contact with the charge tunneling layer, thus maintaining an atomically flat and clean interface and effectively suppressing charge leakage caused by interfacial defects. Furthermore, from an electrical performance perspective, the resistivity of Pt, Pd, and Au is much lower than that of metal oxides, resulting in extremely low transmission loss of pulse voltage. This not only ensures that the electric field can act quickly and without damage on the charge tunneling layer to achieve instantaneous charge tunneling, but also avoids the generation of significant parasitic capacitance in the metal electrodes themselves, thereby preventing pulse signal distortion, ensuring the rapid response of the driving circuit, and ultimately supporting nanosecond-level erase and write operations.

[0108] The thickness of the charge trapping layer 4 is from 1 nm to 10 nm. Preferably, the thickness of the charge trapping layer 05 is 8 nm.

[0109] The thickness of the charge trapping layer is a key parameter for controlling the charge injection / extraction response time. Precisely controlling the thickness within the range of 3 nm to 10 nm ensures the continuity of the underlying metal electrode film and precisely matches the charge transport path length with the time scale of the nanosecond pulse. This enables both instantaneous charge trapping and release and stable support for erase and write operation speeds of 20 ns to 100 ns.

[0110] A monolayer MoS2 film grown by chemical vapor deposition (CVD) is transferred to the upper surface of the charge tunneling layer O8 using a transfer method. The conductive channel can have 2, 3, or more layers. Multilayer MoS2 can be prepared directly by CVD or indirectly by multi-step transfer of monolayer MoS2. As a controllable and scalable fabrication technology, chemical vapor deposition (CVD) can grow high-quality, large-area two-dimensional material films at a reasonable cost. This method significantly improves the uniformity and microstructure controllability of MoS2 films by decomposing the gaseous precursor at high temperature and depositing it on the substrate, thereby preparing large-area, high-quality monolayer or few-layer two-dimensional materials.

[0111] The MoS2 thin film was etched into the desired pattern array using a photolithography-exposure method. The etching equipment was reactive ion etching (RIE), the carrier gas was a mixture of O2 and Ar, the etching power was 30 W, and the etching time was 10 s.

[0112] In this structure, deposited patterned Cr / Au electrodes serve as the source electrode, drain electrode, and top metal interconnect 11 of MoS2, respectively, resulting in a 1T-1 Flash array structure based on two-dimensional transistors and two-dimensional ultrafast flash memory. The Cr layer has a thickness of 5 nm, the Au layer has a thickness of 45 nm, and the top metal interconnect 11 has a width of 5 μm. The 1T-1 Flash array has an 8 × 8 array size, the channel size (length × width) of MoS2-FETs is 10 μm × 3 μm, and the channel size (length × width) of MoS2 ultrafast flash memory is 20 μm × 3 μm.

[0113] like Figure 1 , Figure 3a , Figure 3b , Figure 3c The image shows a schematic diagram and an optical microscope image of a 1T-1 Flash driver circuit array structure based on a two-dimensional transistor.

[0114] The control gate of each row of two-dimensional ultrafast flash memory is connected to V via a metal interconnect. PULSE Connected, the metal gate of each row of two-dimensional transistors is connected to V via metal interconnects. SCAN Connected, specifically including:

[0115] The control gate of each row of MoS2 channel ultrafast flash memory is connected in series with V. PULSE Connect them, and you will eventually get V. PULSE1 V PULSE2 V PULSE3 V PULSE4 V PULSE5 V PULSE6 V PULSE7 and V PULSE8 ;

[0116] The metal gates of each row of MoS2-FETs are connected in series with V. SCAN Connect them, and you will eventually get V. SCAN1 V SCAN2 V SCAN3 V SCAN4 V SCAN5 V SCAN6 V SCAN7 and V SCAN8 ;

[0117] The drain of each column of two-dimensional transistors is connected to V via a metal interconnect. DATA The source of each column of two-dimensional transistors is connected to the anode of the LED screen, and the cathode of the LED screen is grounded. Specifically, this includes:

[0118] The drain of each row of MoS2-FETs is connected in series with V. DATA Connect them, and you will eventually get V. DATA1 VDATA2 V DATA3 V DATA4 V DATA5 V DATA6 V DATA7 and V DATA8 ;

[0119] like Figure 4 The diagram shown is a circuit connection schematic based on a two-dimensional transistor 1T-1 Flash driver circuit array structure, which includes row selection V. PULSE V SCAN and the selected V DATA ;

[0120] like Figure 5 As shown, the transfer characteristic curves of MoS2-FETs in the 1T-1Flash driver circuit array structure based on two-dimensional transistors are displayed; the transfer characteristic curves of multiple devices were tested respectively, showing good consistency.

[0121] According to literature reports, field-effect transistors (MoS2-FETs) fabricated from CVD-grown MoS2 thin films exhibit excellent overall electrical performance. On the one hand, their on-state current density (I0) is... ON (≈ 1.27 mA / μm) and mobility (122.6 cm⁻¹) 2 V -1 s -1 Its performance is comparable to that of low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs); on the other hand, its off-state leakage current (as low as 10) is significantly lower. -13 Its A / μm (ampere-to-micron) ratio is comparable to that of indium gallium zinc oxide transistors (IGZO-TFTs). In particular, its high ratio of 10... 8 The on / off ratio far exceeds that of traditional LTPS-TFTs. Therefore, introducing two-dimensional materials into real-world driving circuits has the potential to break through the limitations of traditional TFT circuits at the material, device, and architecture levels, providing a new path for driving novel displays.

[0122] like Figure 6 As shown, the storage window width of MoS2-ultrafast flash memory in a two-dimensional transistor 1T-1 Flash driver circuit array structure varies with the control gate voltage (V). CG The curve showing the change in the scanning range, where V CG The range is -8 V to 8 V. The large storage window indicates that the Pt charge trapping layer has good charge storage characteristics; at the same time, the characteristic curves have good consistency, indicating the reliability of the 1T-1 Flash array fabrication process.

[0123] like Figure 7aThe diagram shows a typical circuit connection of a 1T-1 Flash driver circuit in the LED lit state, with the corresponding V... PULSE The pulse voltage amplitude is -15V, and the pulse width is 20 ns. DATA Fixed at 4 V, V SCAN The gate voltage is 5 V; Figure 7b The equivalent circuit diagram is shown when the LED is lit.

[0124] like Figure 8a The diagram shows the current I flowing through the LED in the 1T-1 Flash driver circuit when the LED is lit. LED Retention characteristics over 1000 s; Figure 8b The corresponding current I flows through the LED LED With V SCAN The curve of voltage change;

[0125] Leveraging the non-volatile storage characteristics of the 1T-1 Flash structure based on two-dimensional transistors, the holding function of traditional storage capacitors can be replaced, thereby simplifying the driving circuit structure and improving the pixel aperture ratio. The programming time of MoS2-channel ultrafast flash memory can reach 20 ns, which is much faster than the writing method of traditional TFTs that relies on RC charging and discharging, thus significantly improving the refresh rate. After programming, MoS2-channel ultrafast flash memory can remain in the conducting state for a long time (1000 s) without frequent refreshes, achieving a refresh rate as low as 0.001 Hz, thereby significantly reducing system power consumption.

[0126] Figure 9 shows a typical circuit connection diagram of a 1T-1 Flash driver circuit in the LED off state, with the corresponding V... PULSE The pulse voltage amplitude is -15V, and the pulse width is 20 ns. DATA Fixed at 4 V, V SCAN The gate voltage is -3 V; Figure 7b The equivalent circuit diagram is shown when the LED is lit.

[0127] like Figure 10 The figure shows the current I flowing through the LED in the LED off state in the 1T-1 Flash driver circuit. LED Retention characteristics over 1000 s;

[0128] When the switching transistor MoS2-FET is in the off state, the current I DS There was essentially no change, and the leakage current was approximately 10. -12 A indicates that the fastest shutdown speed of the 1T-1Flash structure is as high as 20 ns;

[0129] like Figure 11The diagram shows the circuit connection diagram between the 1T-1 Flash driver circuit array structure and the LED dot matrix interconnection.

[0130] Figure 12 The diagram shows a block diagram of a multi-channel test system. This test system can simultaneously output 64 analog voltage signals with an amplitude range of ±15 V.

[0131] Figure 13 The image shown is a physical diagram illustrating the interconnection between the 1T-1 Flash driver circuit array structure and the LED dot matrix.

[0132] Figure 14 The image shown is a physical diagram of the 1T-1 Flash driver circuit array structure after packaging.

[0133] Figure 15 As shown, this demonstrates the synchronous output of 8 V channels by a multi-channel test system. PULSE Timing diagram of pulse signal, corresponding V PULSE The pulse voltage amplitude is -15 V;

[0134] Figure 16 As shown, this demonstrates the 8-channel V output of the multi-channel test system. SCAN Timing diagram of voltage signal, corresponding V SCAN The low level of the voltage is -3 V, and the high level is 5 V;

[0135] Figure 17 As shown, this demonstrates the synchronous output of 8 V channels by a multi-channel test system. DATA Timing diagram of voltage signal, corresponding V DATA The low level of the voltage is 0 V, and the high level is 4 V;

[0136] The V PULSE A 1 μs negative pulse voltage is applied to erase the data, and V is scanned line by line. SCAN Column-by-column scan V DATA This enables independent addressing and full-screen illumination of the LED dot matrix screen.

[0137] The V-code of 8 lines was tested simultaneously using a multi-channel testing system. PULSE (V) PULSE1 To V PULSE8 When a negative pulse voltage with a pulse width of 1 μs and a pulse voltage amplitude of -15 V is applied, the stored data is erased and the MoS2 channel is opened.

[0138] The 1 μs pulse width was chosen because the fastest write speed that the multi-channel test system can generate is 1 μs when multiple analog voltage signals are output synchronously. This does not mean that the 1T-1 Flash driver circuit array does not have the ability to erase and write quickly at 20 ns.

[0139] By changing the 8 lines of V using a multi-channel testing system SCAN (V) SCAN1 To V SCAN8 The voltage level changes from low (-3V) to high (5V), and the corresponding row of 8 MoS2-FETs is turned on.

[0140] The first column V was tested using a multi-channel testing system. DATA1 When a 4V voltage is applied, the eight 1T-1 Flash arrays in the first column are selected, and the corresponding LEDs in the first column are lit, as shown below. Figure 18 As shown;

[0141] By using a multi-channel testing system, change the nth row V SCAN (8 ≥ n ≥ 1) level states, the nth column V DATA The level state of (8 ≥ n ≥ 1) enables individual addressing of the 1T-1 Flash in the nth row and nth column;

[0142] Through a multi-channel testing system, V is scanned synchronously. SCAN1 To V SCAN8 V DATA1 To V DATA8 The level state is such that when the scanning frequency is 1 kHz, the LED screen is fully illuminated, as shown below. Figure 19 As shown.

[0143] The 1T-1Flash display driver circuit can drive LEDs at a frequency as low as 0.001 Hz, with a maximum switching speed of 20 ns. By fabricating a 1T-1Flash driver circuit array and combining it with a multi-channel testing system, independent addressing of the LED dot matrix and full-screen illumination were achieved. These results demonstrate the scalability and engineering feasibility of the 1T-1Flash driver architecture in display systems, providing important theoretical basis and technical support for future ultra-low power, highly integrated Micro-LED display driver technology based on two-dimensional semiconductor materials.

[0144] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A two-dimensional transistor 1T-1 Flash driving circuit array structure, characterized in that, include: A base layer (01) and a plurality of pixel units arranged in an array on the base layer (01); Each pixel unit includes a two-dimensional switching transistor and a two-dimensional non-volatile memory device; The two-dimensional switching transistor and the two-dimensional non-volatile memory device are stacked in a direction perpendicular to the substrate layer, wherein the stacked arrangement from bottom to top is as follows: a first gate layer, a charge blocking layer (04), a charge trapping layer (05), a second gate layer, a charge tunneling layer (08), and a two-dimensional semiconductor channel layer (09). The multiple pixel units are arranged in a multi-row, multi-column array, with each row having a first control signal line and a second control signal line, and each column having a data signal line; In the same row, the first gate layer of all the pixel units is electrically coupled to the first control signal line corresponding to that row, and the second gate layer of all the pixel units is electrically coupled to the second control signal line corresponding to that row; In the same column, the first end of the two-dimensional semiconductor channel layer (09) is connected to the corresponding data signal line, and the second end of the two-dimensional semiconductor channel layer (09) is connected to the load device.

2. The two-dimensional transistor 1T-1 Flash driving circuit array structure according to claim 1, characterized in that, The first gate layer includes: a control gate electrode (02) and a first metal interconnect (03) electrically coupled to the control gate electrode (02). The control gate electrode (02) of each pixel unit is connected to the first control signal line of the corresponding row through the first metal interconnect (03) of the same layer.

3. The two-dimensional transistor 1T-1 Flash drive circuit array structure according to claim 1, characterized in that, The second gate layer includes: a metal gate electrode (06) and a second metal interconnect (07) electrically coupled to the metal gate electrode (06). The metal gate electrode (06) of each pixel unit is connected to the second control signal line of the corresponding row through the second metal interconnect (07) of the same layer.

4. The 1T-1 Flash driver circuit array structure based on two-dimensional transistors according to claim 1, characterized in that, The thickness of the charge tunneling layer (08) is 5 nm to 10 nm.

5. The 1T-1 Flash driver circuit array structure based on two-dimensional transistors according to claim 1, characterized in that, The array size formed by the pixel units is an 8×8 matrix, a 16×16 matrix, or a 32×32 matrix.

6. The two-dimensional transistor 1T-1 Flash driving circuit array structure according to claim 1, characterized in that, The conductive channel width of the two-dimensional switching transistor is 5μm to 15μm and the length is 2μm to 5μm; the conductive channel width of the two-dimensional non-volatile memory device is 10μm to 30μm and the length is 2μm to 5μm.

7. The two-dimensional transistor 1T-1 Flash drive circuit array structure according to claim 1, characterized in that, The charge blocking layer (04) is made of hafnium dioxide, aluminum oxide, or silicon dioxide. The thickness of the charge blocking layer (04) is 10 nm to 30 nm.

8. The two-dimensional transistor 1T-1 Flash driving circuit array structure according to claim 1, characterized in that, The charge trapping layer (05) is made of platinum, gold or palladium.

9. The 1T-1 Flash driver circuit array structure based on two-dimensional transistors according to claim 1, characterized in that, The substrate (01) is a p-type heavily doped silicon / silicon dioxide substrate.

10. A driving control method based on a two-dimensional transistor 1T-1 Flash driving circuit array structure, characterized in that, include: An erase pulse signal is applied to the first control signal line to erase the stored charge in the two-dimensional non-volatile memory device, so that the two-dimensional semiconductor channel layer is in the conducting state. A scan enable signal is applied to the second control signal line row by row to enable the two-dimensional switching transistor, and a data write signal is applied to the data signal line column by column to write the target driving state to the corresponding pixel unit. Stop applying the scan enable signal to turn off the two-dimensional switching transistor. The pixel unit relies on the charge held in the two-dimensional non-volatile memory device to maintain the load device in the working state corresponding to the target driving state.

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