Time-sharing power-on / off control method, device, and display device for display panel

Abstract

This invention discloses a time-division multiplexing power-on / off control method, apparatus, and display device for a display panel. The method involves setting up a first column of channels and a second column of channels alternately distributed along the pixel column arrangement direction in the same source driving circuit, and controlling each column through independent enable signals. Upon power-on, the first column of channels is first powered on, and during its power-on period, in response to the gate driving circuit completing at least one complete scan frame, the second column of channels is then powered on. Upon power-off, one group is first de-powered, and while the other group is powered on, in response to the completion of at least one complete scan frame, the other group is de-powered. This staggers the charging and discharging processes of the two column channels, reducing the number of column channels switching simultaneously, thereby reducing the inrush current during the power-on / off process of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display driving control technology, and in particular to a time-division power-on / off control method, apparatus, and display device for a display panel. Background Technology

[0002] Reflective cholesteric liquid crystal display technology achieves image display by applying a corresponding driving voltage to the display panel, causing liquid crystal molecules to be in different alignment states. During the power-on, power-off, or display state switching processes of the display device, the relevant driving circuits in the display panel need to be powered on or off.

[0003] During power-on and power-off cycles, multiple drive channels in existing display devices may switch states at similar times, easily generating large instantaneous currents. This increases the power supply burden and may cause voltage fluctuations, affecting the stable operation of the display device. Frequent large instantaneous currents also increase the instantaneous electrical stress on the drive circuits, power supply traces, and related connection paths. Therefore, reducing the inrush current generated during power-on and power-off cycles is a problem that existing technologies need to address. Summary of the Invention

[0004] The purpose of this invention is to provide a time-division power-on / off control method, device, and display device for a display panel, so as to reduce the inrush current generated during the power-on / off process of the display panel.

[0005] In a first aspect, this application provides a time-division multiplexing power-on / off control method for a display panel, comprising: responding to a power-on control command, controlling a first column channel group to enter a power-on state via a first enable signal; during the period when the first column channel group is in a power-on state, responding to the completion of at least one complete scan frame by a gate driving circuit, controlling a second column channel group to enter a power-on state via a second enable signal; responding to a power-off control command, controlling one column channel group of the first column channel group and the second column channel group to exit the power-on state, while keeping the other column channel group in a power-on state; during the period when the other column channel group is in a power-on state, responding to the completion of at least one complete scan frame by a gate driving circuit, controlling the other column channel group to exit the power-on state; wherein the first column channel group and the second column channel group are different column channel groups in the same source driving circuit, the first column channel group and the second column channel group are respectively used to drive different pixel columns, adjacent pixel columns correspond to different column channel groups, so that the first column channel group and the second column channel group are alternately distributed along the pixel column arrangement direction, and the first column channel group and the second column channel group are independently controlled by the first enable signal and the second enable signal, respectively.

[0006] Secondly, this application provides a time-division power-on / off control device for a display panel, including a timing control module, a source driving circuit, and a gate driving circuit; the source driving circuit includes a first column channel group and a second column channel group, the first column channel group and the second column channel group are respectively used to drive different pixel columns, adjacent pixel columns correspond to different column channel groups, so that the first column channel group and the second column channel group are alternately distributed along the pixel column arrangement direction, and the first column channel group and the second column channel group are independently controlled by a first enable signal and a second enable signal respectively; the timing control module is used to control the first column channel group and the second column channel group according to the time-division power-on / off process described in the first aspect.

[0007] Thirdly, this application provides a display device, including a display panel and a time-division power-on / off control device for the display panel as described in the second aspect, wherein a source driving circuit is used to drive the pixel columns of the display panel, and a gate driving circuit is used to scan the pixel rows of the display panel line by line.

[0008] This application provides a time-division multiplexing power-on / off control method, apparatus, and display device for a display panel. The method involves setting up a first column of channels and a second column of channels alternately distributed along the pixel column arrangement direction in the same source driving circuit, and controlling each column through independent enable signals. Upon power-on, the first column of channels is first powered on, and during its power-on period, in response to the gate driving circuit completing at least one complete scan frame, the second column of channels is then powered on. Upon power-off, one group is first de-powered, and while the other group is powered on, in response to the completion of at least one complete scan frame, the other group is de-powered. This staggers the charging and discharging processes of the two column channels, reducing the number of column channels switching simultaneously, thereby reducing the inrush current during the power-on / off process of the display panel. Attached Figure Description

[0009] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A flowchart of a time-division power-on / off control method for a display panel provided by the present invention; Figure 2 This invention provides a common power-on / off timing diagram; Figure 3 This invention provides a time-sharing power-on / off timing diagram; Figure 4 A common timing current test diagram provided by the present invention; Figure 5A time-division current test diagram provided by the present invention; Figure 6 This is a schematic diagram of an alternating grouping of odd and even columns and independent enabling provided by the present invention; Figure 7 This is a schematic diagram of a frame-level time-division power-on / off mechanism provided by the present invention; Figure 8 This is a schematic diagram of the H-state, P-state, and FC-state coordination provided by the present invention; Figure 9 This is a schematic diagram of a time-sharing power-on / off control device for a display panel provided by the present invention. Detailed Implementation

[0011] The core of this invention is to provide a time-division power-on / off control method, device, and display device for a display panel, so as to reduce the inrush current generated during the power-on / off process of the display panel.

[0012] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0013] In a first aspect, this application provides a time-division multiplexing power-on / off control method for a display panel. This method can be executed by a timing control module in the display device, which establishes a control connection with a source drive circuit and a gate drive circuit. The source drive circuit provides source voltage to the pixel columns of the display panel, and the gate drive circuit scans the corresponding pixel rows of the display area line by line according to a set scanning order. Multiple physical column channels in the source drive circuit are divided into a first column channel group and a second column channel group, with each group driving different pixel columns and alternately distributed along the pixel column arrangement direction. The first column channel group corresponds to a first enable signal, and the second column channel group corresponds to a second enable signal, allowing the timing control module to change the power enable state of the two column channels respectively.

[0014] like Figure 1 As shown, the time-sharing power-on and time-sharing power-off processes can sequentially include steps S11 to S14, specifically: S11: In response to the power-on control command, the first column of channels is controlled to enter the power-on state through the first enable signal.

[0015] In this step, after the display device receives the power-on control command, the timing control module activates the first enable signal, thereby controlling the first column channel group to enter the power-on state. The first column channel group entering the power-on state means that the column channel corresponding to the first column channel group establishes a power-enabled state for display driving, enabling that column channel to apply source voltage to its corresponding pixel column. The first enable signal can be directly output by the timing control module, or it can be generated by the timing control module and then processed by the drive control logic to form a corresponding enable signal. Regardless of the signal generation method, the first enable signal corresponds to the power-enabled state of the first column channel group.

[0016] S12: During the period when the first column of channels remains in the powered-on state, in response to the completion of at least one complete scan frame by the gate drive circuit, the second column of channels is controlled to enter the powered-on state by the second enable signal.

[0017] In this step, while the first column of channels remains powered on, the gate driving circuit continues to scan the pixel rows according to the set scanning sequence. After the gate driving circuit completes at least one full scan frame, the timing control module controls the second column of channels to enter the power-on state via the second enable signal. A full scan frame refers to the gate driving circuit completing one full scan of each gate row corresponding to the display area. Therefore, after the power-on state of the first column of channels changes, the second column of channels does not immediately change its state synchronously. Instead, the first column of channels remains in its current power-on state for at least one full scan frame before the power enable state of the second column of channels is changed. After the second column of channels enters the power-on state, both columns of channels are powered on and can continue to operate according to the existing display driving process of the display device.

[0018] During the power-on process described above, the first and second channel groups correspond to different pixel columns and are alternately distributed along the pixel column arrangement direction. Therefore, when the first channel group is powered on, only a portion of its corresponding column channels establish voltage, while the second channel group establishes voltage only after a subsequent complete scan frame. Compared to the method where multiple column channels establish source voltage simultaneously at similar times, this application distributes the originally concentrated column channel charging load to different time periods, reducing the number of column channels participating in state switching at the same time. Since the two groups of column channels are alternately distributed within the pixel column range of the display panel, when one group operates, its corresponding column channels are not concentrated in a continuous local area of ​​the display panel, but are distributed throughout the entire pixel column arrangement range.

[0019] S13: In response to the power-down control command, control one of the first and second column channel groups to exit the power-on state, while keeping the other column channel group in the power-on state.

[0020] In this step, when the display device receives a power-down control command, the timing control module controls one of the first and second column channel groups to exit the power-on state, while keeping the other column channel group powered on. Exiting the power-on state of a column channel group means changing the enable state corresponding to that column channel group, causing that column channel to stop maintaining its powered-on state. At this time, the other column channel group does not change synchronously with the first column channel group; instead, it continues to maintain its existing power-on state after the first column channel group exits the power-on state, thus separating the shutdown processes of the two column channel groups in time.

[0021] S14: While another column channel group remains powered on, in response to the gate drive circuit completing at least one full scan frame, control the other column channel group to exit the powered-on state.

[0022] In this step, while the other column channel group remains powered on, the gate drive circuit continues to complete at least one full scan frame. Once the full scan frame condition is met, the timing control module then controls the other column channel group to exit the power-on state. Thus, time-division multiplexing power-off and time-division multiplexing power-on employ the same basic control principle: at least one full row-by-row scan process must be spanned between two adjacent column channel group state transitions. For the power-off process, the column channel group that exits first can be either the first column channel group or the second column channel group; the specific order is determined by the corresponding implementation method. However, in either case, the turn-off times of the two column channel groups are staggered.

[0023] Figure 2 This illustrates a typical timing scenario where the source drives the relevant channels to undergo state changes simultaneously. Figure 3 The timing diagram illustrates the implementation of time-division multiplexing control according to this application. The state changes of the two sets of source drive column channels are staggered, while the gate drive still scans row by row according to the pixel row. Figure 2 and Figure 3 As can be seen, this application changes the enable timing of the source drive column channels, eliminating the need to group the gate drive signals according to column channel groups. The gate drive circuit is still used for pixel row scanning, while the first and second column channel groups of the source drive circuit establish or remove the source voltage at different times based on independent enable signals.

[0024] In some embodiments, the first and second channel groups can be housed within the same source driver chip. Two independently changeable enable control paths within this source driver chip control the two physical channel groups respectively. Thus, the time-division control targets the channel groups within the same source driver circuit, rather than dividing the display panel into multiple independently powered display areas. In cases where multiple source driver chips jointly drive a larger display panel, each source driver chip can have its first and second channel groups configured in the same way, with their enable states coordinated by a corresponding timing control module.

[0025] In other embodiments, after powering on the two sets of column channels, the timing control module maintains both sets in the target power-on state until a subsequent power-off control command is received; after powering off the two sets of column channels, it maintains both sets in the target power-off state until the next power-on control command is received. This holding method prevents repeated triggering of the column channel group's charging and discharging switching during the state holding phase, avoiding the formation of new instantaneous currents due to repeated changes in the enable state. For periods where only display content refresh occurs without power-on / off control, the existing gate scanning and source data output process of the display device can be used, without needing to repeat steps S11 to S14.

[0026] When using the above method, after the first column channel group undergoes a state switch, the second column channel group will not undergo a corresponding state switch until at least one complete scan frame has elapsed. Therefore, the charging and discharging processes of the two column channels are separated into different time periods. This process reduces the number of column channels simultaneously participating in voltage establishment or removal, thereby reducing the peak current during power-on and power-off processes. In an exemplary embodiment, for a reflective cholesteric liquid crystal display panel, under the same test conditions, current was collected at 8 voltage-corresponding measurement points for both normal timing and time-division timing. The peak current measured by the normal timing was approximately 4.62A, while the peak current measured by the time-division timing was approximately 810.78mA, or approximately 0.811A, representing a decrease of approximately 82.5% based on peak value. This test result demonstrates that dispersing the state switching of the column channels across different time periods can directly reduce the peak current during power-on and power-off phases.

[0027] In the above main process, the power-on control command and power-off control command serve as inputs for two types of power state switching, respectively. Upon receiving the power-on control command, the timing control module first outputs the target state of the first enable signal and uses the fact that the first column of channels has entered the power-on state as the starting condition for subsequent complete scan frame judgment. After the complete scan frame condition is met, the enable control result for the second column of channels is formed. Similarly, upon receiving the power-off control command, the state of one column of channels is changed first, and this state change is used as the starting condition for subsequent shutdown judgment of the other column of channels. Thus, the column channel state and gate scan result generated in the previous step are actually used in the subsequent step, and the entire power-on / off process is executed in the order of control command, state switching, scan judgment, and subsequent state switching.

[0028] The source drive circuit and the gate drive circuit play different roles in the above process. The source drive circuit is responsible for the voltage output and power enable state changes on the pixel column side, while the gate drive circuit is responsible for the row-by-row scanning on the pixel row side. Time-division control does not require splitting the gate row into two groups corresponding to the first and second column channel groups, nor does it change the original scanning sequence of the gate row. The complete scan frame is only used as the scanning reference between two source column channel group state switches. In this way, the power state changes of the source column channels can be distributed across different scan cycles while retaining the row-by-row scanning mode.

[0029] For a complete power-on process, after the first column channel group transitions from the power-off state to the power-on state, the second column channel group maintains its original state. Therefore, in the first stage, only the physical column channel corresponding to the first column channel group experiences the main voltage establishment. After the complete scan frame is completed, the second column channel group enters the power-on state again, and the first column channel group does not perform a power-on action again. For a complete power-off process, similarly, only one column channel group is changed first, while the other column channel group maintains its original power-on state and continues to undergo the complete scan frame, before the second shutdown is performed. Thus, each time-division stage corresponds to a specific column channel group state change.

[0030] In one exemplary embodiment, the first and second channel groups are divided into odd and even columns according to the pixel column arrangement order of the display panel. Taking the pixel columns as numbered sequentially starting from the first column as an example, the column channels corresponding to odd-numbered columns are assigned to the first channel group, and the column channels corresponding to even-numbered columns are assigned to the second channel group. If the column number of any odd-numbered column is represented as n, then n can be represented as 2k-1, where k is a positive integer; the next column adjacent to the odd-numbered column is numbered n+1, corresponding to the even-numbered column. This division continues sequentially to the last column of the display panel, creating an alternating distribution of the two channel groups in the pixel column arrangement direction.

[0031] like Figure 6As shown, a first column channel group and a second column channel group can be set inside the same source driver chip. The first column channel group corresponds to odd-numbered columns, and the second column channel group corresponds to even-numbered columns. The column channels of the first column channel group are connected to the odd-numbered pixel columns such as the 1st, 3rd, and 5th columns, respectively, and the column channels of the second column channel group are connected to the even-numbered pixel columns such as the 2nd, 4th, and 6th columns, respectively. Figure 6 The column numbers in the diagram are only used to illustrate the alternating distribution relationship. The actual number of pixel columns on the display panel can be determined based on the panel resolution.

[0032] When grouping by odd and even columns, the number of channels in two groups is usually the same or differs by one column, resulting in similar equivalent loads. When voltage is established in all columns simultaneously, the charging current of all pixel columns will be superimposed at approximately the same time. After alternating between odd and even columns, only the enable state of one group of channels is changed each time, so the number of column channels corresponding to one state switch is approximately half of the total number of column channels. Furthermore, a group of column channels is distributed alternately along the width of the panel, rather than being concentrated in a single continuous column area.

[0033] In some embodiments, the first channel group may correspond to odd-numbered columns, and the second channel group may correspond to even-numbered columns. In other embodiments, the names of the two groups may be interchanged, so that the first channel group corresponds to even-numbered columns and the second channel group corresponds to odd-numbered columns, as long as adjacent pixel columns correspond to different channel groups and maintain an alternating distribution. The naming of the first and second channel groups is used to distinguish two sets of channel groups controlled by independent enable signals, and it is not required that a certain fixed name necessarily correspond to a certain parity attribute.

[0034] For display panels with an odd number of pixel columns, one group can have one more column channel than the other. For display panels with an even number of pixel columns, both groups can have the same number of column channels. This difference in number does not change the alternating distribution of odd and even columns. The timing control module still executes control according to the order of the first group acting first, the second group acting later, or the corresponding power-down sequence, ensuring that the state switching of the two groups of column channels is staggered in time.

[0035] Alternating odd and even column grouping also ensures that the two column channel groups are spaced apart within the pixel column arrangement range. Taking six consecutive columns as an example, the first column channel group can correspond to columns 1, 3, and 5, and the second column channel group can correspond to columns 2, 4, and 6. When the state of the first column channel group changes, the corresponding columns of the adjacent second column channel group maintain their original state. When the state of the second column channel group changes subsequently, the first column channel group has already completed the corresponding maintenance process. For more pixel columns, the above relationship continues to repeat according to the column sequence number, so the basic grouping method does not change as the number of columns in the panel increases.

[0036] With the column channel arrangement of the source driver chip corresponding one-to-one with the pixel columns of the panel, the odd-even column grouping can be directly implemented as the alternating grouping of the physical output channels inside the chip. Therefore, when the first enable signal changes, it corresponds to the first group of physical output channels dispersed among multiple adjacent pixel columns; when the second enable signal changes, it corresponds to another group of physical output channels. This relationship allows time-division control to directly act on the channels that actually handle the charging and discharging of the pixel columns, rather than simply creating groups in the control logic that do not correspond to physical output channels.

[0037] In one exemplary embodiment, the first channel group and the second channel group are independently controlled by a first enable signal and a second enable signal, respectively. The first enable signal establishes a fixed correspondence with the first channel group and is used to change the power enable state of the first channel group; the second enable signal establishes a fixed correspondence with the second channel group and is used to change the power enable state of the second channel group. Figure 6 EN_O represents the first enable signal, and EN_E represents the second enable signal. The two signals are respectively connected to two column channel groups within the same source driver chip.

[0038] By changing the active state of the first enable signal, the first column of channels can be powered on or off. By changing the active state of the second enable signal, the second column of channels can be powered on or off. The active state of the enable signals can be active high or active low, depending on the interface definition of the source drive circuit used. This application focuses on the ability of the two enable signals to change the power enable state of the two column channels separately, without limiting any particular active level polarity.

[0039] When the first enable signal undergoes a valid state change, the second enable signal can maintain its current state. Therefore, the first channel group can independently change its power enable state without synchronous switching of the second channel group. Correspondingly, when the second enable signal undergoes a valid state change, the first enable signal can maintain its current state. Thus, the two enable signals are independent of each other in control, and the timing control module can issue the two enable state changes according to a predetermined sequence, without requiring the two groups of channels to simultaneously establish or remove their source voltages.

[0040] During power-up, for example, the first enable signal enters the active state first, while the second enable signal maintains the corresponding state after power-down. Once the conditions for a complete scan frame are met, the second enable signal then enters the active state, while the first enable signal remains active. During power-down, one enable signal can be deactivated while the other remains unchanged. After at least one complete scan frame, the other enable signal is deactivated. This control process can be implemented by the state control logic in the timing control module.

[0041] Two independent enable controls make the physical column channels inside the source driver chip an actual time-division multiplexing object. Unlike methods that only delay the transmission of image data, this embodiment changes the power enable state of the column channel group, thus directly changing the number of physical channels participating in charging and discharging simultaneously when the column channel voltage is established or removed. The correspondence between the first enable signal and the second enable signal can be multiplexed during power-on and power-off processes, so that the same column channel group is controlled by the same enable signal during different power state switching processes.

[0042] During specific signal control, the timing control module can save the current states of the first and second enable signals. When it is necessary to change the first column channel group, only the state information corresponding to the first enable signal is updated, while the original state of the second enable signal is maintained. When it is necessary to change the second column channel group, only the state information corresponding to the second enable signal is updated, while the original state of the first enable signal is maintained. This clearly distinguishes between the first and second action groups, avoiding the need to resynchronize the two column channel groups by updating the enable states of both channels simultaneously in a single control operation.

[0043] For both power-on and power-off directions, the same enable signal can represent the entry and exit of the corresponding column channel group into the power-on state, respectively. The first enable signal does not need to be changed to control the second column channel group when power is off, and the second enable signal does not need to change its corresponding object. The fixed signal-to-channel group correspondence ensures that the same column channel identification relationship can be used in multiple cycles of power-on, hold, power-off, and power-on again. The timing control module only needs to determine when to change each enable signal based on the current power state and control commands.

[0044] In one exemplary embodiment, whether at least one complete scan frame has been completed is determined by frame counting. A complete scan frame refers to the gate driving circuit completing one scan of each gate row corresponding to the display area according to a set scanning order. The timing control module starts counting complete scan frames after a column channel group undergoes a state switch. When the count value reaches a preset holding frame number, it is determined that the condition for the next column channel group to undergo a state switch has been met.

[0045] During power-up, a power-up hold count can be initiated when the first channel group enters the power-up state. Let the duration of a complete scan frame be T_F, and the number of complete scan frames to be held during power-up be N_F,on, where N_F,on is an integer greater than or equal to 1. The time when the first channel group enters the power-up state can be denoted as t_O,on, and the time when the second channel group enters the power-up state can be denoted as t_E,on. The time interval between the two power-up state transitions satisfies the following formula: ΔT_on = t_E,on - t_O,on ≥ N_F,on × T_F.

[0046] According to the above relationship, after the first channel group enters the power-on state, the gate drive circuit must complete at least N_F,on complete scan frames before the second channel group enters the power-on state. When N_F,on equals 1, at least one complete scan frame corresponds to the power-on state transition between the two groups. When N_F,on is greater than 1, multiple complete scan frames can be held before changing the second enable signal. The preset number of frames to hold can be preset according to the existing refresh parameters of the display panel. The counting object is the completed complete scan frames, rather than just a fixed time counted in milliseconds.

[0047] During power-down, a power-down retention counter can be initiated when a column channel group exits the power-on state. The number of complete scan frames that need to be retained during power-down can be represented as N_F,off, where N_F,off is an integer greater than or equal to 1. When the times when two column channel groups exit the power-on state are denoted as t_O,off and t_E,off respectively, the absolute time interval between their state transition times can satisfy the following formula: |ΔT_off|=|t_E,off-t_O,off|≥N_F,off×T_F.

[0048] The first hold frame number N_F,on and the second hold frame number N_F,off can be the same or set separately. For the same display panel, the two hold frame numbers can be determined according to the actual driving timing of the power-on and power-off processes. For display panels with different refresh parameters, the hold frame number can be changed without changing the alternating distribution and independent enable relationship of the first and second channel groups.

[0049] The frame counting method ensures that the state switching of the next channel group is based on the number of completed row-by-row scans. When the interval is less than a complete scan frame, the first channel group may not have undergone a complete gate row-by-row scan before the second channel group begins switching, and the switching current of the two channel groups may fall into the same incomplete scan interval. This embodiment uses a complete scan frame as the counting unit to ensure a clear scan boundary between the state switching of two consecutive channel groups.

[0050] Frame counting can restart after each previous channel group completes its state transition. Upon power-up, the first channel group entering the power-up state serves as the starting point for power-up counting. Once the count reaches N_F,on, the second channel group enters the power-up state, ending the power-up counting. Upon power-down, the channel group that exits the power-up state first completes its state transition, serving as the starting point for power-down counting. Once the count reaches N_F,off, the other channel group that was previously in the power-up state is then controlled to exit. Thus, the number of frames held during power-up and power-down corresponds to their respective defined start and end events.

[0051] If a complete scan frame of a display panel consists of one scan from the first gate row to the last gate row, the frame count should be incremented only after all gate rows within that range have been scanned, rather than incrementing once for each completed row. Using this counting method, even if different display panels have different numbers of rows or different actual frame durations, as long as the end of a complete scan frame can be determined, the same frame count relationship can still be used to control the state switching of the two column channel groups.

[0052] In another exemplary embodiment, it can be determined whether at least one complete scan frame has been completed based on the complete scan end flag or frame completion flag corresponding to the gate drive circuit. Unlike waiting at a preset time interval, the timing control module reads or receives status information indicating that the gate drive circuit has completed the full frame scan, and controls the next column of channel groups to change its power enable state when the status information meets preset conditions.

[0053] In one implementation, the gate drive control logic generates a complete scan end flag after completing the scan of the last row of the display area. The timing control module waits for this flag after the first column channel group powers on. Upon detecting the complete scan end flag, it updates the number of completed scan frames. When the required number of complete scan frames is reached, the timing control module changes the second enable signal, powering on the second column channel group. The power-off process can use the same flag reading method: after one column channel group exits the power-on state, the complete scan end flag is detected, and after the required number of frames is met, the other column channel group is de-powered.

[0054] In another implementation, the display timing control logic can output a frame completion flag. The frame completion flag can be generated at the end of a display scan frame, and the timing control module determines that a complete scan frame has ended by receiving the frame completion flag. For cases where multiple complete scan frames need to be maintained, the number of occurrences of the frame completion flag can be counted. For cases where only one complete scan frame needs to be maintained, the next column channel group state switch can be triggered after a valid frame completion flag is detected.

[0055] Figure 7 The GATE scan diagram illustrates that the gate drive circuit completes one full scan row by row. After the first column channel group undergoes a power-on state transition, the power-on time of the second column channel group is set at least one full scan frame later. Similarly, the power-off phase ensures that the state transition times of the two column channel groups are at least one full scan frame apart. When using the actual scan completion state as the trigger basis, the full scan boundary can continue to be used as the switching reference even if the display panel refresh cycle changes, without relying solely on a fixed absolute time value.

[0056] In response to determining that the gate drive circuit has completed at least one full scan frame, the timing control module controls the second column channel group to enter the power-on state during the power-on phase, and controls the other column channel group that has been in the power-on state to exit the power-on state during the power-off phase. Therefore, the full scan end flag or frame completion flag is not only used to record the display state, but also directly participates in the control of the power enable state of the subsequent column channel group, and its judgment result is actually used by the next enable control.

[0057] When using a scan end flag or frame completion flag, the timing control module can first record the scan state corresponding to the state switch of the previous channel group, and allow the next group to act only after valid full frame completion information is detected. If the state switch of the previous channel group occurs before the start of a complete scan frame, the next group can be triggered after that frame is completed. If the state switch occurs near the end boundary of the previous frame, the subsequent completed full scan process should be used as the judgment object to ensure that the next channel group does not switch prematurely before the previous channel group has undergone a complete line-by-line scan.

[0058] The complete scan end flag and frame completion flag can be derived from the existing scan timing information of the display device. When the timing control module uses this information, it does not change the scan meaning represented by the flag itself, but only uses it as the input for enabling state switching during time-sharing power-on / off states. During normal display, if it is not in a stage of waiting for the state switching of another column of channel groups, the flag can still be used for its existing display control purpose and will not trigger the time-sharing power-on / off process again.

[0059] In one exemplary embodiment, power-on and power-off employ the same column channel group operation sequence, i.e., the first column channel group operates first, followed by the second column channel group. Upon power-on, in response to a power-on control command, the first column channel group is powered on via a first enable signal. After the first column channel group remains powered on and the gate drive circuit completes at least one full scan frame, the second column channel group is powered on via a second enable signal.

[0060] Upon power-down, in response to the power-down control command, the first enable signal controls the first column of channel groups to exit the power-on state, while keeping the second column of channel groups powered on. The second column of channel groups continues to maintain its current power-enabled state. After the gate drive circuit completes at least one full scan frame, the second enable signal controls the second column of channel groups to exit the power-on state. Thus, power-on and power-down are performed in the order of the first column of channel groups and the second column of channel groups.

[0061] When using the same sequence, power-on and power-off can reuse the same set of column channel numbering relationships and the correspondence between the first enable signal and the second enable signal. In both power-on and power-off state transitions, the timing control module uses the first column channel group as the first action group and the second column channel group as the last action group, only needing to determine the target state of the enable signal based on whether the currently received control command is a power-on or power-off command. The corresponding complete scan frame counting logic can also use the same set of channel correspondences.

[0062] In other embodiments that do not employ the same order limitation of this example, power-down can also be performed in the reverse order of power-up, i.e., the second channel group exits the power-up state first, and the first channel group exits the power-up state after at least one complete scan frame. In this method, the shutdown times of the two groups of channels are still staggered, thus achieving time-division power-down. This embodiment uses sequential power-down as a specific implementation to reduce the processing of re-determining channel mapping relationships during power-down.

[0063] In one exemplary embodiment, after the second channel group enters the power-on state, the first and second channel groups remain powered on until a power-off control command is received. That is, after the time-sharing power-on process is completed, the timing control module does not re-execute the power-on state switching of the first and second channel groups due to normal image refresh, and the two enable signals maintain the corresponding power-on target state.

[0064] During the normal display period, the gate drive circuit can continue to be turned on line by line according to the existing scanning sequence, and the source drive circuit can output source voltage to the corresponding pixel column according to the current display content. This normal display process is distinct from the time-division power-on trigger condition; the timing control module only enters the time-division power-off process when a new power-off control command is received. Therefore, the first and second channel groups will not repeatedly switch power-on states during the state holding phase.

[0065] After completing the time-sharing power-down, both the first and second channel groups remain powered down until the next power-up control command is received. The first and second enable signals maintain their corresponding signal states to prevent the channel voltage from being re-established without a new power-up request. Upon receiving the next power-up control command, the power-up process restarts from the first channel group.

[0066] By dividing the control flow into power-on trigger, power-on completion hold, power-off trigger, and power-off completion hold, each channel group charge / discharge switch corresponds to a clear power state change request. During the state hold period, there are no repeated switches, ensuring that the effect of time-sharing control in reducing peak current is not negated by unnecessary repeated charging and discharging.

[0067] In one exemplary embodiment, the display panel is a reflective cholesteric liquid crystal display panel. The reflective cholesteric liquid crystal display panel uses different driving voltages to align liquid crystal molecules in corresponding states to form a display. During display driving, the gate driving circuit is used to scan by pixel row, and the source driving circuit is used to provide the corresponding source voltage to the pixel column. The time-division control of this application operates on the power-enabled state of the source driving column channel, while the gate driving still completes line-by-line scanning according to pixel rows.

[0068] like Figure 8 As shown, in a cholesteric liquid crystal driving process, the display driving states can be executed in the order of H state, P state, and FC state. In the H state, ACVCOM (common electrode voltage) and SOURCE voltage (source voltage) are applied, where the GATE signal is the gate scan signal. The P state serves as an intermediate state in the existing driving process, and the FC state applies the SOURCE voltage. For the processes involving the establishment or removal of the SOURCE voltage in the above states, the timing control module can control two column channel groups according to the time-division multiplexing sequence of the first enable signal and the second enable signal; while one group of column channels is switching states, the other group of column channels maintains its current output state. The specific voltage amplitude, the duration of each state (frames), and the order of other power rails can be adopted from the existing driving parameters of the corresponding display panel.

[0069] In a cholesteric liquid crystal TFT panel, each pixel column forms a corresponding charging load when the voltage is established. When the columns switch synchronously, the charging currents of multiple column channels are superimposed at similar times. After the first and second column channel groups are alternately distributed and their enable states are changed in a time-division manner, only one group of column channels experiences the main voltage establishment or removal at any given time. Since the number of columns and equivalent loads contained in the two groups can remain close, each of the two state switching phases bears a portion of the instantaneous load.

[0070] Figure 4 The figure shows the current collected at eight voltage-corresponding measurement points under normal timing conditions, with the peak current being approximately 4.62 A. Figure 5 The figure shows the current collected at corresponding measurement points under the same test conditions after adopting time-division multiplexing, with a peak value of approximately 810.78 mA, or about 0.811 A. Based on this peak value, the peak current decreases by approximately 82.5%. This data demonstrates that under these test conditions, the staggered switching of the two sets of channels can reduce the peak current during the power-on phase.

[0071] With a reduced peak current, the instantaneous load that the power supply path needs to bear in a short period of time is correspondingly reduced, which can reduce the risk of instantaneous voltage drops or fluctuations and reduce the instantaneous electrical stress on the source drive circuit, power supply traces, and related connection paths during power-on and power-off processes. During power-down, the enable states of the two sets of column channels change at different times, separating the turn-off processes of each set in time, which can reduce the risk of transient load superposition when multiple column channels are turned off simultaneously.

[0072] This application does not require the gate drive signals to be grouped according to an odd-even relationship. For reflective cholesteric liquid crystal display panels, the gate signals are still distributed according to pixel rows and turned on sequentially. The grouping object is the pixel column channel corresponding to the source drive circuit. Therefore, during image refresh, the row pixels continue to be scanned row by row, while the first and second column channel groups corresponding to the column pixels change their power enable states according to a time-division multiplexing power-on / off sequence. In this way, peak-shifting control of the source column channels can be achieved without changing the basic gate row-by-row scanning method.

[0073] In reflective cholesteric liquid crystal display panels, the source voltage and ACVCOM participate in the liquid crystal driving state changes. In normal timing, when multiple source columns experience voltage changes at the same time, the corresponding charging loads simultaneously act on the power supply path, easily resulting in large instantaneous currents. Time-division timing separates the enable changes of the first and second channel groups and ensures at least one complete gate scan between the two changes, preventing the corresponding current changes from concentrating at the same state switching moment.

[0074] Figure 2 and Figure 3 This can be used to compare the signal relationships between normal timing and time-division timing. In normal timing, the SOURCE-related outputs undergo state changes as a whole. In time-division timing, the two sets of column channels corresponding to the SOURCE undergo state changes at different times, while ACVCOM and gate scan are still executed according to the corresponding display driving process. Figure 7 The time interval between the first enable signal and the second enable signal is further shown. Figure 8 The coordination relationships between the H state, P state, and FC state are shown. Figure 8 The H, P, and FC states shown are used to illustrate a specific cholesteric liquid crystal driving process, without changing the control relationship of independent enable and complete scan frame interval for the first and second channel groups.

[0075] In one exemplary embodiment, for the test data, multiple measurement points in a standard timing diagram reflect current changes under the corresponding voltage state, with a peak value of approximately 4.62 A. After employing time-division timing, the maximum current in the corresponding test is approximately 0.811 A. Both sets of data were obtained under the same test conditions, and therefore can be used to compare the peak values ​​corresponding to the two power-on / off timing sequences. This comparison focuses on the change in the maximum instantaneous current during the power-on / off state transition, and does not require that each measurement point change at the same proportion.

[0076] like Figure 9 As shown, in a second aspect, this application provides a time-division multiplexing power-on / off control device for a display panel 904, including a timing control module 901, a source drive circuit 902, and a gate drive circuit 903. The source drive circuit 902 is connected to the pixel columns of the display panel 904 and is used to apply source voltages to the corresponding pixel columns; the gate drive circuit 903 is connected to the pixel rows of the display panel 904 and is used to drive the pixel rows sequentially according to a set scanning order; the timing control module 901 is connected to the source drive circuit 902 and the gate drive-related control logic respectively, and is used to control the column channel group in the source drive circuit 902 according to the power-on control command, the power-off control command, and the complete scan frame state.

[0077] The source driver circuit 902 includes a first column channel group and a second column channel group. The two column channels are connected to different pixel columns, with adjacent pixel columns corresponding to different column channel groups, causing the two column channel groups to alternate along the pixel column arrangement direction. The first column channel group is controlled by a first enable signal, and the second column channel group is controlled by a second enable signal. The two enable signals can respectively change the power enable state of the corresponding column channel group. The source driver circuit 902 can be implemented using a single source driver IC, with the two column channel groups housed within the same IC, and control paths corresponding to the first and second enable signals respectively configured.

[0078] When the timing control module 901 receives a power-on control command, it first changes the first enable signal to power on the first column channel group. Then, the timing control module 901 maintains the first column channel group in its current power-on state and waits for or determines that the gate drive circuit 903 has completed at least one complete scan frame. Once this condition is met, it changes the second enable signal to power on the second column channel group. When the timing control module 901 receives a power-off control command, it first de-powers one column channel group, keeps the other column channel group powered on, and then de-powers the other column channel group only after the gate drive circuit 903 has completed at least one complete scan frame.

[0079] The timing control module 901 may include a control interface for receiving power-on control commands and power-off control commands, enable control logic for generating a first enable signal and a second enable signal, and frame state processing logic for determining the completion status of a complete scan frame. The frame state processing logic may use a complete scan frame count, or it may receive a gate complete scan end flag or a frame completion flag. These functions can be implemented in the display timing controller, or by a control circuit that works in conjunction with the source drive circuit 902, as long as the power enable states of the two sets of column channels can be changed according to the aforementioned timing sequence.

[0080] In this application, the gate drive circuit 903 maintains a pixel-row progressive scan mode. The timing control module 901 uses the gate scan completion state to determine the switching interval between source column channel groups. Therefore, the source drive circuit 902 and the gate drive circuit 903 do not execute independent processes. The result of the gate drive circuit 903 completing a full scan frame is used by the timing control module 901 to determine the timing of the second column channel group state switching, so that the time-division enabling of the source column channels corresponds to the actual display scanning process.

[0081] In terms of hardware relationships, the first and second channel groups can be formed by different sets of output channels within the source drive circuit 902. Each output channel is connected to the corresponding pixel column of the display panel 904, and the two sets are arranged alternately according to the relationship that adjacent pixel columns are assigned to different groups. The first enable control path is connected to the power enable control terminal corresponding to the first channel group, and the second enable control path is connected to the power enable control terminal corresponding to the second channel group. The timing control module 901 provides enable states to the two control paths respectively, so that when the state of one group changes, the other group can maintain its current state.

[0082] The timing control module 901 can also maintain current power stage information when performing time-sharing control. For example, when no power-on control command is received, both groups of column channels remain powered down. Upon receiving the power-on control command, it enters the first group's power-on and scan hold stage. After the complete scan frame condition is met, it enters a state where both groups are powered on. Upon receiving the power-off control command, it enters a stage where one group is powered off first and the other group remains held. After the complete scan frame condition is met again, it enters a state where both groups are powered off. The above stage information is used to determine which enable signal should be changed and to prevent repeated changes to column channel groups already in the target state during incorrect stages.

[0083] For complete scan frame information, the gate drive circuit 903 or its associated scan control logic can provide the timing control module 901 with a signal reflecting the completion of the entire frame scan. The timing control module 901 does not need to read the specific display data of each pixel row; it only needs to determine whether a complete line-by-line scan has been completed, or to accumulate the number of complete scan frames that have been completed. Therefore, the time-division multiplexing power-on / off control only needs to establish a correspondence with the scan completion status to control the sequential switching of the two source column channel groups.

[0084] Thirdly, this application provides a display device, including a display panel 904 and a time-division power-on / off control device for the display panel 904. The display panel 904 can be a reflective cholesteric liquid crystal display panel 904. The source driving circuit 902 is used to drive the pixel columns of the display panel 904, the gate driving circuit 903 is used to scan the pixel rows of the display panel 904 line by line, and the timing control module 901 is used to control the simultaneous power-on and time-division power-off of the first column channel group and the second column channel group.

[0085] When the display device receives a power-on control command, the timing control module 901 first powers on the first column of channels, and then powers on the second column of channels at intervals of at least one complete scan frame. When the display device receives a power-off control command or a power-down command corresponding to a state switch, the timing control module 901 causes the two column of channels to exit the power-on state at different times. Therefore, the display device does not need to change the power enable state of all source columns at approximately the same time.

[0086] The specific product form of the display device does not affect the aforementioned time-division control relationship of the source column channels. For display products using reflective cholesteric liquid crystal panels, two independent enable controls can be added to the existing display driving state and gate line-by-line scanning process, so that the column channel charging and discharging load during power-on and power-off processes is distributed to different time periods. The signal relationship between the source driving circuit 902, the gate driving circuit 903, and the timing control module 901 can be arranged according to the circuit implementation of the display device, and the first column channel group and the second column channel group still maintain alternating distribution and independent enable control.

[0087] The display panel 904, source drive circuit 902, gate drive circuit 903, and timing control module 901 in the display device can be components of the same display product. The output side of the source drive circuit 902 is connected to the pixel column, the output side of the gate drive circuit 903 is connected to the pixel row, and the timing control module 901 provides two independent enable controls to the source drive circuit 902 and acquires or receives information related to the complete scan frame. In this way, in addition to performing normal image display, the display device can also complete time-division power-on and power-off according to the aforementioned steps when the power state changes.

[0088] After the power-on process is complete, both column channels remain powered on, and the display continues to refresh normally. Power-off is performed only when the device is powered off or needs to exit its operating state. Since time-sharing power-on and power-off are only executed when the corresponding control command arrives, it is not necessary to repeatedly change the power enable state of the two column channel groups during each frame of normal display. The normal display process and the power state switching process are distinguished by the corresponding control commands.

[0089] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0090] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A time-division power-on / off control method for a display panel, characterized in that, include: In response to the power-on control command, the first column of channels is controlled to enter the power-on state via the first enable signal; While the first column of channels remains powered on, in response to the gate drive circuit completing at least one complete scan frame, the second column of channels is controlled to enter the powered-on state by the second enable signal. In response to a power-down control command, one of the first and second column channel groups is controlled to exit the power-on state, while the other column channel group remains in the power-on state; While the other column channel group remains powered on, in response to the gate drive circuit completing at least one full scan frame, the other column channel group is controlled to exit the powered-on state. The first column channel group and the second column channel group are different column channel groups in the same source driving circuit. The first column channel group and the second column channel group are used to drive different pixel columns. Adjacent pixel columns correspond to different column channel groups, so that the first column channel group and the second column channel group are alternately distributed along the pixel column arrangement direction. The first column channel group and the second column channel group are independently controlled by the first enable signal and the second enable signal, respectively.

2. The time-sharing power-on / off control method for a display panel according to claim 1, characterized in that, The first and second channel groups are alternately distributed along the pixel column arrangement direction, including: According to the pixel column arrangement order of the display panel, the column channels corresponding to odd-numbered columns are assigned to the first column channel group, and the column channels corresponding to even-numbered columns are assigned to the second column channel group.

3. The time-sharing power-on / off control method for a display panel according to claim 1, characterized in that, The first column channel group and the second column channel group are independently controlled by the first enable signal and the second enable signal, respectively, including: By changing the effective state of the first enable signal, the power enable state of the first column channel group is controlled to change; By changing the effective state of the second enable signal, the power enable state of the second column channel group is controlled to change. When the active state of one of the first and second enable signals is changed, the current state of the other enable signal is maintained.

4. The time-sharing power-on / off control method for a display panel according to claim 1, characterized in that, The response to the gate drive circuit completing at least one complete scan frame includes: After controlling the first column of channels to enter the power-on state or controlling the column of channels to exit the power-on state, the complete scan frames completed by the gate drive circuit are counted. When the count value reaches a preset holding frame number, it is determined that the gate drive circuit has completed at least one complete scan frame, wherein the preset holding frame number is an integer greater than or equal to 1.

5. The time-sharing power-on / off control method for a display panel according to claim 1, characterized in that, The response to the gate drive circuit completing at least one complete scan frame includes: Obtain the complete scan end flag or frame completion flag corresponding to the gate drive circuit; Based on the complete scan end flag or the frame completion flag, it is determined that the gate drive circuit has completed at least one complete scan frame; In response to determining that the gate drive circuit has completed at least one full scan frame, the second column channel group is controlled to enter the power-on state, or the other column channel group is controlled to exit the power-on state.

6. The time-sharing power-on / off control method for a display panel according to claim 1, characterized in that, The step of responding to a power-down control command to control one of the first and second column channel groups to exit the power-on state while keeping the other column channel group in the power-on state includes: In response to the power-down control command, the first column channel group is controlled to exit the power-on state through the first enable signal, while the second column channel group remains in the power-on state; While the other column channel group remains powered on, in response to the gate drive circuit completing at least one full scan frame, controlling the other column channel group to exit the powered-on state includes: While the second column channel group remains powered on, in response to the gate drive circuit completing at least one full scan frame, the second enable signal controls the second column channel group to exit the powered-on state.

7. The time-sharing power-on / off control method for a display panel according to claim 1, characterized in that, After controlling the second column of channels to enter the power-on state via the second enable signal, the method further includes: Keep the first column channel group and the second column channel group in the powered-on state until the power-off control command is received; After controlling the other column channel group to exit the power-on state, the method further includes: The first and second channel groups remain powered down until the next power-on control command is received.

8. The time-sharing power-on / off control method for a display panel according to any one of claims 1 to 7, characterized in that, The display panel is a reflective cholesteric liquid crystal display panel.

9. A time-sharing power-on / off control device for a display panel, characterized in that, Includes a timing control module, a source drive circuit, and a gate drive circuit; The source driving circuit includes a first column channel group and a second column channel group. The first column channel group and the second column channel group are used to drive different pixel columns. Adjacent pixel columns correspond to different column channel groups, so that the first column channel group and the second column channel group are alternately distributed along the pixel column arrangement direction. The first column channel group and the second column channel group are independently controlled by a first enable signal and a second enable signal, respectively. The timing control module is used to execute the steps in the time-sharing power-on / off control method for the display panel as described in any one of claims 1 to 8.

10. A display device, characterized in that, The device includes a display panel and a time-division power-on / off control device for the display panel as described in claim 9. The source driving circuit in the time-division power-on / off control device is used to drive the pixel column of the display panel, and the gate driving circuit in the time-division power-on / off control device is used to scan the pixel row of the display panel line by line.

Images