Method and apparatus for managing input / output interface

Abstract

Methods, apparatus, devices, and systems for managing input / output interfaces are provided. In one aspect, a method includes: obtaining a voltage level of an input signal received from a host device; configuring a power domain of an interface of a slave device coupled to the host device based on the voltage level of the input signal; and sending an output signal to the host device, wherein the voltage level of the output signal is set based on the power domain.

Description

Technical Field

[0001] This disclosure generally relates to electronic devices, and more specifically to the management of input / output (I / O) interfaces of electronic devices. Background Technology

[0002] A slave device (such as a removable storage medium including an SD card or flash memory) can be connected to a host device such as a personal computer. A slave device can access and store data while receiving power from the host device. Summary of the Invention

[0003] This disclosure relates to methods, apparatus, and systems for managing input / output (I / O) interfaces of slave devices.

[0004] One aspect of this disclosure provides a method. The method includes: obtaining a voltage level of an input signal received from a host; configuring a power domain of an interface of a slave device coupled to the host based on the voltage level of the input signal; and sending an output signal to the host, wherein the voltage level of the output signal is set based on the power domain.

[0005] In some implementations, the voltage level of the output signal is the same as the voltage level of the input signal.

[0006] In some implementations, the input signal and the output signal are transmitted via one or more pins of the interface. These pins belong to a power domain group and are configured to have the same voltage when the voltage level of these pins is set high.

[0007] In some implementations, the method includes obtaining a voltage level at a first pin of one or more pins belonging to a power domain group of the interface, wherein the voltage level of the first pin is set to high.

[0008] In some implementations, configuring the power domain includes: latching a first indicator indicating the voltage level of the input signal into a latch; sending a second indicator from the latch to a voltage regulator, wherein the second indicator is determined based on the first indicator and indicates the power domain; and configuring the power domain according to the second indicator by configuring the output of the voltage regulator.

[0009] In some implementations, the voltage regulator is a low-dropout (LDO) regulator or a buck regulator.

[0010] In some embodiments, the method further includes releasing a reset signal after the power domain is configured to match the voltage level of the input signal.

[0011] In some implementations, the input signal and the output signal are sideband input / output signals or system management bus (SMBUS) signals.

[0012] In some implementations, the voltage level of the input signal is obtained during a reset period, and the output signal to the host device is transmitted during a communication period following the reset period.

[0013] In some implementations, the slave device is a memory system.

[0014] Another aspect of this disclosure is a slave device having an interface. The interface includes: a first circuit configured to obtain a voltage level of an input signal received from a host device; a second circuit configured to determine a power domain of the interface based on the voltage level of the input signal; and a third circuit configured to send an output signal to the host device, wherein the voltage level of the output signal is set based on the power domain.

[0015] In some embodiments, the first circuit includes a first comparator configured to receive the input signal and a first reference signal, and output a first bit indicating whether the voltage level of the input signal is set high. The first circuit also includes a second comparator configured to receive the input signal and a second reference signal, and output a second bit indicating whether the voltage level of the input signal corresponds to a second bit in a first power domain or a second power domain.

[0016] In some embodiments, the second circuit includes: a latch configured to receive and store the second bit; and a voltage regulator configured to output a voltage corresponding to either the first power domain or the second power domain based on the second bit.

[0017] In some implementations, the output of the second circuit is coupled to the third circuit and provides power to the third circuit.

[0018] In some implementations, the first circuit and the second circuit are configured to receive a power supply voltage.

[0019] In some implementations, the voltage level of the output signal is the same as the voltage level of the input signal.

[0020] In some implementations, the interface includes one or more pins belonging to a power domain group, wherein the one or more pins are configured to transmit the input signal and the output signal. When the voltage level of the one or more pins is set high, the one or more pins are configured to have the same voltage.

[0021] Another aspect of this disclosure is a memory system including a memory device, control circuitry, and an interface. The interface is configured to: receive a voltage level of an input signal received from a host device; determine a power domain of the interface based on the voltage level of the input signal; and send an output signal to the host device, wherein the voltage level of the output signal is set based on the power domain.

[0022] In some implementations, the interface includes: a first circuit configured to obtain the voltage level of the input signal; a second circuit configured to determine the power domain of the interface based on the voltage level of the input signal; and a third circuit configured to send the output signal to the host device.

[0023] In some embodiments, the first circuit includes: a first comparator configured to: receive the input signal and a first reference signal; and output a first bit indicating whether the voltage level of the input signal is set high; and a second comparator configured to: receive the input signal and a second reference signal; and output a second bit indicating whether the voltage level of the input signal corresponds to a second bit of a first power domain or a second power domain.

[0024] An additional aspect of this disclosure features a system comprising a host device and a slave device, the slave device being coupled to the host device via an interface. The interface is configured to: obtain a voltage level of an input signal received from the host device; determine a power domain of the interface based on the voltage level of the input signal; and send an output signal to the host device, wherein the voltage level of the output signal is set based on the power domain.

[0025] While typically described as computer-implemented software embodied on a tangible medium for processing and transforming corresponding data, some or all of these aspects may be computer-implemented methods or further included in a corresponding system or other device for performing the functions described. These and other aspects of this disclosure, as well as details of implementation, are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0026] Figure 1 Example input / output (IO) interfaces of the master device and example input / output interfaces of the slave device are shown in a master-slave system.

[0027] Figure 2 A block diagram of an example circuit from the device's I / O interface is shown.

[0028] Figure 3 A schematic timing diagram of an example signal transmission process is shown.

[0029] Figure 4 A schematic diagram of an example IO voltage detection circuit is shown.

[0030] Figure 5 A block diagram of an example IO power configuration circuit is shown.

[0031] Figure 6 An example process for managing the I / O interface of a device is shown.

[0032] Figure 7 A block diagram of an example system with an example memory system is shown.

[0033] Figures 8A to 8B An example storage product is shown.

[0034] Figure 9 A flowchart illustrating an example method for managing the input / output interfaces of a device is shown.

[0035] In the various figures, the same reference numerals and designations indicate the same elements. Detailed Implementation

[0036] In a master-slave system, a slave device can communicate with the master device through its I / O interface, which is coupled to the master device's input / output (I / O) interface. The I / O interface may experience voltage mismatches between the master and slave devices, potentially leading to compatibility issues or unexpected current leakage. For example, if the slave device's I / O voltage configuration does not match the master device's voltage configuration, signals may not be effectively transmitted between the master and slave devices (e.g., due to incorrect voltage level determination), the device may malfunction or even be damaged, and / or quiescent current due to current leakage may increase the power consumption of the master-slave system.

[0037] Typically, master and slave devices can operate under a communication protocol configured with a specified I / O interface voltage. By adhering to the communication protocol, master and slave devices can communicate effectively with each other. However, compatibility issues may still arise, for example, due to differences between older and newer versions of the protocol.

[0038] For example, in the consumer solid-state drive (cSSD) field, different host devices may have different voltage configurations for sideband I / O signals and / or system management bus (SMBUS) signals. For instance, some host devices may use 1.8V as a high voltage level when transmitting sideband I / O signals, while others may use 3.3V. Furthermore, when designing cSSDs, some manufacturers may not strictly adhere to communication protocols.

[0039] In some cases, wide voltage sensing methods can be implemented to address compatibility issues by allowing I / O interfaces to tolerate and operate within a range of voltage levels. However, wide voltage sensing methods may introduce the risk of current leakage due to voltage mismatch, which could increase power consumption.

[0040] In some cases, additional signal lines can be included in a master-slave system to match the voltage configurations of the master and slave devices. For example, hardware signals on the additional signal lines can be used to identify the voltage configurations of the master and slave devices, such as the voltage levels of sideband I / O signals. Furthermore, a communication link can be established to exchange information between the master and slave devices to enable a software-based negotiation process. As an example, an SMBUS link can be established to negotiate the I3C mode of the master-slave system. However, adding additional signal lines can increase the complexity of the hardware design, and the hardware signals may be susceptible to interference. Additionally, the master and slave devices may need to strictly adhere to the latest versions of the protocol. Otherwise, the master and slave devices may interpret the hardware signals differently.

[0041] This disclosure provides techniques for managing the I / O interfaces of slave devices. In some implementations, once the slave device is coupled to the host device, it can enter a reset phase. During the reset phase, the slave device's I / O interface can obtain the voltage level of the input signal received from the host device and configure a power domain to match the voltage level of the input signal. Thus, when the slave device's I / O interface transmits an output signal during a communication phase following the reset phase, the output signal can be transmitted based on the power domain, ensuring that the voltage level of the output signal is the same as the voltage level of the input signal.

[0042] The described techniques can achieve one or more technical effects (e.g., technical advantages and / or benefits). For example, by configuring the power domain to match the voltage level of the input signal received from the host device, the voltage configurations of the slave and host devices can be matched, which can alleviate compatibility issues and current leakage problems. As another example, the described techniques can be implemented by adding IO voltage sensing circuitry while maintaining the existing design of the power configuration and power control circuitry, which is cost-effective. Furthermore, the described techniques do not require adding additional signal lines to the hardware design and do not require defining negotiation links in the software / firmware design. Additionally, in some implementations, the IO interface can adjust its voltage configuration itself without being strictly dependent on the communication protocol. In some implementations, additional or different technical effects can be achieved.

[0043] Figure 1 Example input / output (IO) interface 102 of the host device and example input / output interface 104 of the slave device are shown in the master-slave system 100.

[0044] A host device (also called a master device) can be coupled to one or more slave devices and is configured to initiate and control communication with the slave devices. For example, the host device can manage the timing, data flow, and overall operation of the master-slave system 100. Slave devices (also called peripheral devices) can operate under instructions from the host device. For example, a slave device can receive commands and / or requests from the host device and perform specific tasks accordingly. Examples of host devices include computers, smartphones, or microcontroller units (MCUs) in embedded systems. For example, a computer acting as a host can communicate with external storage media (e.g., flash memory cards, hard drives), printers, or keyboards that can be used as slave devices.

[0045] like Figure 1 As shown, the host device may include I / O interface 102. I / O interface 102 may have multiple pins, such as pin 0 and pin n. The slave device may include I / O interface 104. I / O interface 104 may have multiple pins, such as pin 0 and pin n. The slave device can connect to the host device by coupling I / O interface 104 to I / O interface 102. For example, each pin of I / O interface 104 may be coupled to a corresponding pin of I / O interface 102, enabling the transmission of input signals (e.g., signals from the host device to the slave device) and output signals (e.g., signals from the slave device to the host device) between the host device and the slave device. Example signals may include clock signals, command signals, and data signals.

[0046] In some implementations, signals can be transmitted via one or more pins of I / O interfaces 102, 104. For example, signal 1 (e.g., a command signal) can be transmitted via pins 1 through 4, and signal 2 (e.g., a clock signal) can be transmitted via pin 5. A high voltage level at a pin can represent logic "1", and a low voltage level at a pin can represent logic "0". For example, when the voltage levels of pins 1 through 4 are set to high, high, low, low, respectively, this can indicate a first command; when the voltage levels of pins 1 through 4 are set to low, high, low, high, respectively, this can indicate a second command. Pins used together to transmit a signal can belong to the same power domain group, such that the pins can be powered by the same power domain and operate within the same voltage range during signal transmission (e.g., between the same low voltage level (e.g., 0V or other voltage value) and the same high voltage level (e.g., 1.8V, 3.3V or other suitable voltage value)). In other words, pins belonging to the same power domain group can have the same voltage when their voltage levels are set to high. In some implementations, the same voltage regulator is used to power pins belonging to the same power domain group.

[0047] In some implementations, I / O interface 102 and I / O interface 104 can interact with each other under a communication protocol. The communication protocol can set rules and standards for signal transmission between the host and slave devices, such as which pins are used to transmit specific signals, the timing of signal transitions, and how signals are encoded and decoded. Example communication protocols include inter-integrated circuit (I / O) protocols. 2 C) Protocols such as the Serial Peripheral Interface (SPI) protocol, the PCIe (Peripheral Component Interconnect) protocol, and the Serial Advanced Technology Attachment (SATA) protocol. As an example, under the PCIe protocol, sideband I / O signals may include a reset signal (PERST#), a wake-up signal (PEWAKE#), and a clock request signal (CLKREQ#); system management bus (SMBUS) signals may include a data signal (SMB_DATA) and a clock signal (SMB_CLK).

[0048] In some cases, different communication protocols, or different versions of the same communication protocol, may define the high voltage level of a signal in different ways. For example, different versions of the PCIe protocol may define the high voltage level differently for pins transmitting sideband I / O signals and / or SMBUS signals. To efficiently transmit signals (e.g., sideband I / O signals and / or SMBUS signals), additional steps may be required to configure the power domain of I / O interface 104. Therefore, the high voltage level of a pin of I / O interface 104 when transmitting an output signal may be the same as the high voltage level of the corresponding pin of I / O interface 102 when transmitting an input signal. For example, the high voltage level of an input signal from a host device may be either 1.8V or 3.3V. In response to detecting that the high voltage level of the input signal is 1.8V, I / O interface 104 may set the high voltage level of its output signal to 1.8V, enabling efficient signal transmission between I / O interface 102 and I / O interface 104.

[0049] Figure 2 A block diagram of an example circuit for an I / O interface 104 from a device is shown. In some embodiments, the I / O interface may include: an I / O voltage detection circuit 202 configured to obtain the voltage level of an input signal received from a host device; an I / O power configuration circuit 204 configured to determine a power domain of the I / O interface 104 based on the voltage level of the input signal; and an I / O interface circuit 206 configured to send an output signal to the host device. The power domain may be configured to provide power to pins in the I / O interface 104 used for transmitting the output signal, such that the voltage level of the output signal can be set based on the power domain.

[0050] In some implementations, the I / O interface 104 may have more than one power domain. For example, pins used to transmit different signals may be powered by different power domains. For example, a first signal may be transmitted via pin n-1 and pin n with a low voltage level of 0V and a high voltage level of 1.8V, and a second signal may be transmitted via pin 2, pin 3, and pin 4 with a low voltage level of 0V and a high voltage level of 3.3V.

[0051] In some implementations, the IO voltage detection circuit 202 and the IO power configuration circuit 204 can receive a power supply voltage (Vcc). As an example, the power supply voltage can be 5V or other suitable voltage values. The IO voltage detection circuit 202 also receives a reset signal and an input signal from the host device. During the reset period of the IO interface 104, which can configure its power domain based on the voltage level of the input signal, the reset signal can be set high. After the power domain is configured, the reset signal can be released, and the IO interface 104 can send a signal to the host device during the communication period following the reset period.

[0052] Furthermore, the IO voltage detection circuit 202 can send a signal to the IO power configuration circuit 204, enabling the IO power configuration circuit 204 to configure the power domain of the IO interface 104 and supply power to the IO interface circuit 206. The IO voltage detection circuit 202 can also send signals, for example, as feedback signals. The IO interface circuit 206 can communicate with the host device by receiving input signals from the host device and sending output signals to the host device.

[0053] Figure 3 A schematic timing diagram illustrating an example signal transmission process is shown. Example voltages during the signal transmission process include the supply voltage (Vcc) 302, the voltage of the reset signal 304, the voltage of the input signal 306 received from the host device, the voltage of the output signal 308 sent to the host device, and the power domain interfaces 310a and 310b (collectively referred to as 310) of the I / O interface 104. In some embodiments, the supply voltage 302 and the voltage of the reset signal 304 may be applied to the I / O interface 104, while the voltages of the input signal 306 and the output signal 308 may be applied to specific pins of the I / O interface 104 for transmitting the corresponding signals. In some embodiments, the input and output signals may be sideband I / O signals or SMBUS signals.

[0054] like Figure 3 As shown, after being coupled from the slave device to the host device, the slave device's I / O interface 104 can receive a supply voltage (e.g., 5V or other suitable voltage value) from the host device. Furthermore, the I / O interface 104 can receive input signals from the host device, for example, through one or more pins of the I / O interface 104. During a reset period when the reset signal is set low, the I / O interface can configure its power domain based on the voltage of the input signal 306.

[0055] In some implementations, during the first period (T1) of the reset period, the I / O interface 104 can obtain the voltage level of the input signal 306. For example, the I / O voltage detection circuit 202 can obtain the voltage level of the input signal 306. In some implementations, the input signal 306 can be received through more than one pin of the I / O interface 104, and when the input signal is transmitted, only a portion of the more than one pin is set to a high voltage level. In this case, the I / O voltage detection circuit 202 can obtain the voltage level of the pin that is set to a high voltage level. As an example, if the input signal is transmitted via pins 1-4 by setting pins 1-4 to high, high, low, low respectively, the I / O voltage detection circuit 202 can obtain the voltage level of pin 1 or pin 2.

[0056] During the second period (T2) of the reset period, the I / O interface 104 can configure the power domain 310 based on the voltage level of the input signal. For example, if the voltage level of the input signal is 1.8V, the I / O power configuration circuit 204 can configure the power domain 310 to 1.8V, or if the voltage level of the input signal is 3.3V, the I / O power configuration circuit 204 can configure the power domain 310 to 3.3V. The power domain can be configured to supply a high voltage level to the pins used to transmit the input signal and the corresponding output signal. Therefore, the I / O interface 104 can transmit the output signal corresponding to the input signal at the same voltage level as the input signal. In some embodiments, as shown in 310a, the voltage of the power domain is maintained at 0V during T1, and during T2, the I / O power configuration circuit 204 can set the voltage of the power domain 310a from 0V to the voltage level of the input signal. In some other implementations, as shown in 310b, the voltage of the power domain is set to a default voltage (e.g., 1.8V) during T1, and during T2, the IO power configuration circuit 204 can adjust the voltage of the power domain 310b from the default voltage to the voltage level of the input signal (e.g., 3.3V).

[0057] After configuring the power domain to match the voltage level of the input signal, during the third period (T3), the reset signal 304 can be released (e.g., set to high) to end the reset period and begin the communication period.

[0058] During the communication period, signals can be transmitted between the I / O interface 104 of the slave device and the I / O interface 102 of the host device. The I / O interface 104 can send output signals to the host device, wherein the voltage level of the output signal can be set based on the power domain. For example, input signal 306 and output signal 308 can be transmitted within the same voltage range (e.g., between the same low voltage level and the same high voltage level).

[0059] Similarly, I / O interface 104 can configure more than one power domain by configuring each power domain based on the voltage level of the corresponding input signal. For example, if pins X1 and X2 are powered by a first power domain and configured to transmit a first signal, I / O interface 104 can configure the first power domain based on the voltage level of the first signal received from the host device during the reset period; if pins Y1, Y2, and Y3 are powered by a second power domain and configured to transmit a second signal, I / O interface 104 can configure the second power domain based on the voltage level of the second signal received from the host device during the reset period.

[0060] Figure 4 An example IO voltage detection circuit is shown (e.g., Figure 2 A schematic diagram of the IO voltage detection circuit 202.

[0061] In some implementations, the IO voltage detection circuit 202 may include one or more comparators. For example, such as Figure 4 As shown, the IO voltage detection circuit 202 may include a first comparator 402 and a second comparator 404. Each comparator may be an operational amplifier with two input terminals and an output terminal.

[0062] In some implementations, the first comparator 402 may receive an input signal and a first reference signal (e.g., at 1.5V or other suitable voltage level). The first comparator 402 may compare the voltage level of the input signal with the voltage level of the first reference signal to determine whether the voltage level of the input signal is set high. Furthermore, the first comparator 402 may output a first bit indicating whether the voltage level of the input signal is set high. For example, a first bit of "1" indicates that the voltage level of the input signal is set high, while a first bit of "0" indicates that the voltage level of the input signal is set low.

[0063] In some implementations, the second comparator 404 may receive an input signal and a second reference signal (e.g., at 3V or other suitable voltage level). The second comparator 404 may compare the voltage level of the input signal with the voltage level of the second reference signal to determine whether the input signal corresponds to a first power domain (e.g., 1.8V) or a second power domain (e.g., 3.3V). For example, a second bit of "0" may indicate that the input signal corresponds to the first power domain, while a second bit of "1" may indicate that the input signal corresponds to the second power domain.

[0064] It should be noted that Figure 4 The schematic diagram is for illustrative purposes only. Different components and / or modules can be used to design the IO voltage detection circuit 202.

[0065] Figure 5 An example IO power configuration circuit is shown (e.g., Figure 2 Block diagram of the IO power configuration circuit 204.

[0066] In some implementations, the IO power configuration circuit 204 may include a latch 502 and a voltage regulator 504. The latch 502 may receive a result (e.g., a second bit) of the voltage level of the detected input signal from the IO voltage detection circuit 202. The latch 502 may latch the result, for example, in response to a time lag or a trigger signal.

[0067] The latch can also send a voltage regulation signal (e.g., an indicator generated based on the second bit) to the voltage regulator 504. The voltage regulation signal can indicate whether to convert the supply voltage (e.g., 5V) to a first output voltage (e.g., 3.3V) or a second output voltage (e.g., 1.8V). The output voltage of the voltage regulator 504 can be provided to the I / O interface circuitry 206.

[0068] Examples of voltage regulator 504 include low dropout (LDO) regulators, buck regulators, or another type of regulator that converts a DC power supply from one voltage level to another. In some implementations, voltage regulator 504 may be embedded in a power management chip to regulate the voltage in a specific power domain.

[0069] Figure 6 The diagram illustrates the I / O interface for managing slave devices (e.g., Figure 1 Example procedure 600 for the IO interface 104).

[0070] The operations shown in process 600 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 6 The different sequences of execution are shown. In some implementations, some operations may be performed by one or more components of the device or system, such as the controller of the device.

[0071] At 602, the slave device is coupled to the master device (e.g., via hot-plugging), energizing the slave device. The slave device can enter the reset phase, for example, by setting the voltage of the reset signal high (H).

[0072] At 604, the voltage level of the input signal received from the host device is obtained from the device's I / O interface. For example, the device's I / O interface can detect the voltage level of a pin that is set high when the input signal is transmitted during the reset period (e.g., by detecting a high voltage level (VIH) of the input signal during the reset period).

[0073] At 606, the slave device's I / O interface can be configured with a power domain to match the voltage level of the input signal, such that when the slave device sends an output signal to the master device, the voltage level of the output signal is the same as the voltage level of the input signal. In some implementations, the power domain can be configured to a default voltage if the slave device fails to detect a valid voltage level of the input signal.

[0074] At 608, after configuring the power domain to match the voltage level of the input signal, the device's I / O interface is ready for signal transmission, and the reset period ends.

[0075] At 610, the slave device's I / O interface operates, for example, by communicating with the host device. For instance, the slave device's I / O interface receives input signals from the host device and sends output signals to the host device based on a power domain configured to match the voltage level of the input signals detected during a reset period.

[0076] Figure 7 A block diagram of an example master-slave system 700 with an example memory system 702 is shown. Figure 7 As shown, the master-slave system 700 may include a master device 708 and a memory system 702 as a slave device. The memory system 702 may have one or more memory devices 704 and a memory controller 706. Examples of memory devices 704 may include volatile memory devices (such as dynamic random access memory (DRAM) and static random access memory (SRAM)) or non-volatile memory devices (such as NAND flash memory, NOR flash memory, electrically erasable programmable read-only memory (EEPROM), magnetoresistive RAM (MRAM), and resistive RAM (Re RAM)).

[0077] In some implementations, host device 708 may be a processor (such as a central processing unit (CPU)) or a system-on-a-chip (SoC) (such as an application processor (AP)). Host device 708 may be configured to send data to or receive data from memory device 704. Host device 708 may include an interface 712 configured to communicate with memory system 702. Figure 1 The IO interface 102 can be an example of interface 712.

[0078] Memory controller 706 is coupled to memory device 704 and host device 708 and is configured to control memory device 704. Memory controller 706 can manage data stored in memory device 704 and communicate with host device 708. In some embodiments, memory controller 706 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 706 is designed to operate in high duty cycle environments, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which serve as data storage for mobile devices such as smartphones, tablets, laptops, etc., and enterprise storage arrays. Memory controller 706 can be configured to control the operation of memory device 704, such as read, erase, and program operations. The memory controller 706 can also be configured to manage various functions relating to data stored in or to be stored in the memory device 704, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 706 is also configured to process error correction codes (ECC) relative to data read from or written to the memory device 704. The memory controller 706 can also perform any other suitable functions, such as formatting the memory device 704.

[0079] In some embodiments, memory system 702 does not include memory controller 706, and host device 708 is directly coupled to memory device 704. For example, memory controller 706 may be located in host device 708. Alternatively, host device 708 may not include memory controller 706, but may be configured to perform functions similar to those performed by memory controller 706 as described above.

[0080] The memory controller 706 may include one or more processors 716, a host interface 714, a memory interface 720, and a cache 718. Figure 1 and Figure 2 The IO interface 104 can be an example of the host interface 714.

[0081] The memory controller 706 can communicate with external devices (e.g., host device 708) according to a specific communication protocol. Figure 7As shown, processor 716 is coupled to host device 708 via host interface 714. Host interface 714 allows memory controller 706 to communicate with external devices via at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0082] Processor 716 may be coupled to cache 718. Cache 718 may be configured to store temporary information, such as data prior to being written from host device 708 to memory device 704, or data prior to being sent from memory device 704 to host device 708.

[0083] In some embodiments, memory device 704 may include a memory cell array 724 and peripheral circuitry 722 coupled to the memory cell array 724. For example, the memory cells may include memory cells provided in the form of arrays of memory strings, each extending vertically above a substrate. In some embodiments, each memory string includes a plurality of memory cells that are series-coupled and vertically stacked. Each memory cell may hold a continuous analog value representing a logical state (i.e., data). Peripheral circuitry 722 may include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array. For example, peripheral circuitry 722 may include page buffers / sensor amplifiers, column decoders / bit line drivers, row decoders / word line drivers, voltage generators, control logic, registers, interfaces, and data buses.

[0084] A memory system 702, having a memory controller 706 and one or more memory devices 704, can be integrated into various types of storage devices, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of end electronic products. Figure 8A In one example shown, the memory controller 706 and a single memory device 704 can be integrated into a memory card 802. The memory card 802 may include a PC card (PCMCIA (Personal Computer Memory Card International Association)), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 may also include a memory card connector 804 that connects the memory card 802 to a host computer (e.g., ...). Figure 7 The host device 708 in the system is coupled. In such a case... Figure 8B In another example shown, the memory controller 706 and multiple memory devices 704 can be integrated into the SSD 806. The SSD 806 may also include an SSD connector 808 that connects the SSD 806 to a host computer (e.g., ...). Figure 7 The host device 708 is coupled to the SSD. In some implementations, the storage capacity and / or operating speed of the SSD 806 is greater than the storage capacity and / or operating speed of the memory card 802.

[0085] Figure 9 The diagram illustrates the I / O interface for managing slave devices (e.g., Figures 1 to 2 The flowchart shows an example method 900 of the I / O interface 104. Method 900 can be provided by any suitable device or system as described herein (e.g., according to the relevant provisions). Figures 1 to 8B The example techniques described herein may be used to perform this. For example, method 900 may be performed by the I / O interface of a slave device. The I / O interface may include: a first circuit (e.g., Figure 2 and Figure 4 The IO voltage detection circuit 202), the first circuit is configured to obtain the voltage level of the input signal received from the host device; the second circuit (e.g., Figure 2 and Figure 5 The second circuit is configured to determine the power domain of the interface based on the voltage level of the input signal; and the third circuit (e.g., IO power configuration circuit 204), the third circuit being configured to determine the power domain of the interface based on the voltage level of the input signal; and the fourth circuit being configured to determine the power domain of the interface based on the voltage level of the input signal. Figure 2 The third circuit (IO interface circuit 206) is configured to send an output signal to the host device.

[0086] The operations shown in method 900 are not exhaustive, and other operations can be performed before, after, or between any of the shown operations. Furthermore, some operations can be performed simultaneously, or in conjunction with... Figure 9 The different sequences of execution are shown. In some implementations, some operations in the operation may be performed by one or more components in the device or system (such as a first circuit, a second circuit, and / or a third circuit of the I / O interface).

[0087] At 902, the voltage level of the input signal received from the host device is obtained from the device's I / O interface. In some implementations, the input signal can be received through one or more pins of the I / O interface. The I / O interface can obtain the voltage level of the input signal by detecting the voltage level at one or more pins that are set high when the input signal is received.

[0088] At 904, the slave device's I / O interface configures the power domain based on the voltage level of the input signal. In some implementations, one or more pins used to transmit the input signal belong to the same power domain group and are powered by the same power domain when transmitting output signals to the host device. The power domain supplying one or more pins can be configured, for example, to match the voltage level of the input signal during a reset period, which precedes a communication period in which signals are transmitted between the host device and the slave device.

[0089] In some implementations, configuring the power domain includes: setting a first indicator (e.g., indicating the voltage level of the input signal) to... Figure 4 The second bit) is latched into a latch (e.g., Figure 5 The latch 502), from the latch to the voltage regulator (e.g., Figure 5 The voltage regulator 504 sends a second indicator, which is determined based on the first indicator and indicates the power domain. The power domain can be configured according to the second indicator by configuring the output of the voltage regulator. In some embodiments, the voltage regulator is a low-dropout (LDO) regulator or a buck regulator.

[0090] In some implementations, a reset signal is released after the power domain is configured to match the voltage level of the input signal, indicating that the reset period transitions into a communication period. An output signal to the host device is then transmitted during the communication period following the reset period.

[0091] At 906, the I / O interface can send an output signal to the host device (e.g., during a communication period), wherein the voltage level of the output signal is set based on the power domain, such that the voltage level of the output signal can be the same as the voltage level of the input signal.

[0092] In some implementations, the input and output signals are sideband input / output signals or system management bus (SMBUS) signals.

[0093] While this specification contains numerous details of specific embodiments, these should not be construed as limiting the scope of the claims, but rather as descriptions of features that may be specific to particular embodiments. Certain features described herein in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any sub-combination in multiple embodiments. Furthermore, although previously described features may be described as functioning in certain combinations and even initially claimed, in some cases, one or more features from the claimed combination may be removed from the combination, and the claimed combination may be for sub-combinations or variations thereof.

[0094] As used in this disclosure, unless the context clearly indicates otherwise, the terms “a,” “an,” or “the” are used to include one or more. Unless otherwise indicated, the term “or” is used to mean a non-exclusive “or.” The phrase “at least one of A and B” has the same meaning as “A, B, or A and B.” Furthermore, all wording and terms used in this disclosure unless otherwise defined are for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading the document and is not to be construed as restrictive; information relating to a section heading may appear within or outside that particular section.

[0095] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in a value or range, for example, within 10%, 5%, or 1% of a specified value or range.

[0096] As used in this disclosure, the term “substantially” means the majority or most, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or higher.

[0097] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly stated as the limits of the range, but also all individual numerical values ​​or subranges contained within that range, as if each numerical value and subrange were explicitly stated. For example, the range “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as the individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise stated, the statement “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0098] Specific embodiments of the subject matter have been described. Other embodiments, variations, and arrangements of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are depicted in a specific order in the drawings or claims, such operations need not be performed in the specific order shown or in a sequential order, or all shown operations need to be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and considered appropriate.

[0099] Furthermore, not all implementations require the separation or integration of the various system modules and components described in the previously described implementations, and the described components and systems can typically be integrated together or packaged into multiple products.

[0100] Therefore, the exemplary embodiments described above do not limit or restrict the scope of this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

Claims

1. A method comprising: Obtain the voltage level of the input signal received from the host device; Configure the power domain of the slave device interface coupled to the host device based on the voltage level of the input signal; as well as An output signal is sent to the host device, wherein the voltage level of the output signal is set based on the power domain.

2. The method according to claim 1, wherein, The voltage level of the output signal is the same as the voltage level of the input signal.

3. The method according to claim 1 or 2, wherein, The input signal and the output signal are transmitted through one or more pins of the interface, wherein the one or more pins belong to a power domain group and are configured to have the same voltage when the voltage level of the one or more pins is set high.

4. The method according to any one of claims 1 to 3, comprising: A voltage level is obtained at a first pin of one or more pins belonging to the power domain group of the interface, wherein the voltage level of the first pin is set to high.

5. The method according to any one of claims 1 to 4, wherein, Configuring the power domain includes: The first indicator, which indicates the voltage level of the input signal, is latched into the latch; A second indicator is sent from the latch to the voltage regulator, wherein the second indicator is determined based on the first indicator and indicates the power domain; and The power domain is configured according to the second indicator by configuring the output of the voltage regulator.

6. The method according to claim 5, wherein, The voltage regulator is a low-dropout (LDO) regulator or a buck regulator.

7. The method according to any one of claims 1 to 6, further comprising: After the power domain is configured to match the voltage level of the input signal, the reset signal is released.

8. The method according to any one of claims 1 to 7, wherein, The input signal and the output signal are sideband input / output signals or system management bus (SMBUS) signals.

9. The method according to any one of claims 1 to 8, wherein, The voltage level of the input signal is obtained during a reset period, and the output signal to the host device is transmitted during a communication period following the reset period.

10. The method according to any one of claims 1 to 9, wherein, The slave device is a memory system.

11. A slave device having an interface, wherein, The interface includes: A first circuit is configured to obtain the voltage level of an input signal received from a host device. A second circuit, configured to determine the power domain of the interface based on the voltage level of the input signal; and A third circuit is configured to send an output signal to the host device, wherein the voltage level of the output signal is set based on the power domain.

12. The slave device according to claim 11, wherein, The first circuit includes: The first comparator is configured as follows: Receive the input signal and the first reference signal; and The output indicates whether the voltage level of the input signal is set to high (first bit); and The second comparator is configured as follows: Receive the input signal and the second reference signal; and The output indicates whether the voltage level of the input signal corresponds to the second bit of the first power domain or the second power domain.

13. The slave device according to claim 12, wherein, The second circuit includes: A latch, configured to receive and store the second bit; and A voltage regulator configured to output a voltage corresponding to either the first power domain or the second power domain based on the second bit.

14. The slave device according to any one of claims 11 to 13, wherein, The output of the second circuit is coupled to the third circuit and provides power to the third circuit.

15. The slave device according to any one of claims 11 to 14, wherein, The first circuit and the second circuit are configured to receive power supply voltage.

16. The slave device according to any one of claims 11 to 15, wherein, The voltage level of the output signal is the same as the voltage level of the input signal.

17. The slave device according to any one of claims 11 to 16, wherein, The interface includes one or more pins belonging to a power domain group, wherein the one or more pins are configured to transmit the input signal and the output signal, and When the voltage level of one or more pins is set high, the one or more pins are configured to have the same voltage.

18. A memory system comprising: Memory devices; Control circuit; as well as The interface is configured as follows: Obtain the voltage level of the input signal received from the host device; The power domain of the interface is determined based on the voltage level of the input signal; as well as An output signal is sent to the host device, wherein the voltage level of the output signal is set based on the power domain.

19. The memory system according to claim 18, wherein, The interface includes: A first circuit is configured to detect the voltage level of the input signal; A second circuit, configured to determine the power domain of the interface based on the voltage level of the input signal; and A third circuit is configured to send the output signal to the host device.

20. The memory system of claim 19, wherein, The first circuit includes: A first comparator, configured to: receive the input signal and a first reference signal, and output a first bit indicating whether the voltage level of the input signal is set high; and A second comparator is configured to receive the input signal and a second reference signal, and to output a second bit indicating whether the voltage level of the input signal corresponds to a first power domain or a second power domain.

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