Amplification circuit, control method, and memory

Abstract

This disclosure relates to the field of semiconductor circuit design, and particularly to an amplifier circuit, control method, and memory, comprising: a sensing amplifier circuit including a readout node, a complementary readout node, a first node, and a second node, wherein the first node is used to receive a high level and the second node is used to receive a low level during a sensing amplification phase and an offset cancellation phase; a first power supply circuit coupled to the first node, including a first power supply and a second power supply; the first power supply circuit being configured to provide a first power supply to the first node during the offset cancellation phase and a second power supply to the second node during the sensing amplification phase, thereby adjusting the processing time of the offset cancellation phase and the sensing amplification phase to optimize the performance of the memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor circuit design, and in particular to an amplifier circuit, a control method, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) stores data through the charge in cell capacitors; cell capacitors couple bit lines and complementary bit lines. In DRAM, when performing read, write, or refresh operations, the amplifier circuit needs to read and amplify the voltage difference between the bit lines and complementary bit lines.

[0003] Transistors that make up an amplifier circuit may have different device characteristics due to factors such as process variations and temperature. For example, compatible transistors may have different threshold voltages. These different device characteristics can cause offset noise in the amplifier circuit. The presence of offset noise in the amplifier circuit reduces the effective read margin of the amplifier circuit, thereby reducing the performance of DRAM. Summary of the Invention

[0004] By adding an offset cancellation stage before the sensing amplification stage, offset noise in the amplification circuit can be eliminated. However, the offset cancellation stage requires additional data processing time, which will affect the data processing timing of the memory. Ensuring the accuracy of offset cancellation and reducing the processing time of the offset cancellation stage is of great significance to improving the performance of the memory.

[0005] This disclosure provides an amplifier circuit, a control method, and a memory that, while ensuring the accuracy of offset elimination, shortens the processing time of the offset elimination stage, thereby optimizing the performance of the memory.

[0006] This disclosure provides an amplification circuit coupled to a bit line and a complementary bit line, comprising: a sensing amplification circuit including a readout node, a complementary readout node, a first node, and a second node, wherein the first node is used to receive a high level and the second node is used to receive a low level during a sensing amplification phase and an offset cancellation phase; an isolation circuit coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase; an offset cancellation circuit coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the offset cancellation circuit is configured to couple the bit line to the complementary readout node and the complementary bit line to the readout node during the offset cancellation phase; and a first power supply circuit coupled to the first node, including a first power supply and a second power supply, wherein the power supply voltage of the first power supply is higher than the power supply voltage of the second power supply; the first power supply circuit is configured to couple the first power supply to the first node during the offset cancellation phase and the second power supply to the first node during the sensing amplification phase.

[0007] During the offset cancellation phase, a first power supply is coupled to the first node, providing a high level to the first node. The sensing amplifier circuit amplifies the voltage difference between the bit line and the complementary bit line based on the high level provided by the first node. During the sensing amplification phase, a second power supply is coupled to the first node, providing a high level to the first node. The sensing amplifier circuit amplifies the voltage difference between the bit line and the complementary bit line based on the high level provided by the first node. Since the power supply voltage of the first power supply is greater than that of the second power supply, compared to using the same power supply in both the offset cancellation and sensing amplification phases, this embodiment increases the voltage difference between the first and second nodes during the offset cancellation phase by providing a first power supply with a larger power supply voltage. This increases the rate at which the sensing amplifier circuit generates compensation voltage between the bit line and the complementary bit line, eliminating the deviation caused by manufacturing differences in the transistor pairs within the amplifier circuit. This reduces the time required to complete offset cancellation, thereby shortening the offset cancellation phase time during memory design and optimizing memory performance.

[0008] Additionally, the first power supply circuit includes: a first power control circuit coupled to the power node and the first node; the first power control circuit is configured to couple the power node to the first node during the offset cancellation phase and the sensing amplification phase; a first selection circuit coupled to the power node, including a first power supply and a second power supply; the first selection circuit is configured to provide the first power supply to the power node during the offset cancellation phase and provide the second power supply to the power node during the sensing amplification phase.

[0009] Additionally, the first power supply control circuit includes: a first control transistor, one of its source or drain terminals coupled to a power supply node, and the other terminal coupled to a first node; a pull-up control circuit coupled to the gate of the first control transistor; the pull-up control circuit is configured to turn on the first control transistor during the offset cancellation phase and the sensing amplification phase.

[0010] Additionally, the first selection circuit includes: a first control sub-circuit configured to provide a first selection signal or a second selection signal based on a first control command; a first selection sub-circuit coupled to the first control sub-circuit, a power node, and a first power supply; the first selection sub-circuit configured to provide a first power supply to the power node based on the first selection signal; a second selection sub-circuit coupled to the first control sub-circuit, the power node, and a second power supply; the second selection sub-circuit configured to provide a second power supply to the power node based on the second selection signal.

[0011] Additionally, the first selection sub-circuit includes: a first selection transistor; one terminal of the source or drain of the first selection transistor is coupled to a first power supply, the other terminal is coupled to a power supply node, and the gate is coupled to a first control sub-circuit for receiving a first selection signal; the second selection sub-circuit includes: a second selection transistor; one terminal of the source or drain of the second selection transistor is coupled to a second power supply, the other terminal is coupled to a power supply node, and the gate is coupled to the first control sub-circuit for receiving a second selection signal.

[0012] Additionally, the amplification circuit further includes: a second power supply control circuit coupled to a ground node and a second node; a second selection circuit coupled to the second power supply control circuit, including a first control power supply and a second control power supply, wherein the power supply voltage of the first control power supply is higher than the power supply voltage of the second control power supply; the second selection circuit is configured to couple the first control power supply to the second power supply control circuit during the offset elimination phase and to couple the second control power supply to the second power supply control circuit during the sensing amplification phase; the second power supply control circuit is configured to couple the ground node to the second node based on either the first control power supply or the second control power supply.

[0013] During the offset elimination phase, a ground node is coupled to a second node via a first control power supply. The ground node provides a low level to the second node, and the sensing amplifier circuit amplifies the voltage difference between the bit line and the complementary bit line based on the low level provided by the second node. During the sensing amplification phase, a ground node is coupled to a second node via a second control power supply. The ground node provides a low level to the second node, and the sensing amplifier circuit amplifies the voltage difference between the bit line and the complementary bit line based on the low level provided by the second node. Since the power supply voltage of the first control power supply is greater than that of the second control power supply, compared to using the same control power supply in both the offset elimination and sensing amplification phases, this embodiment provides a first control power supply with a larger power supply voltage during the offset elimination phase. This increases the rate at which compensation voltage is generated between the amplified bit line and the complementary bit line in the sensing amplifier circuit, eliminating the deviation caused by manufacturing differences in the transistor pairs within the amplifier circuit. This reduces the time required to complete offset elimination, and consequently, shortens the setup time of the offset elimination phase during memory setup, thereby optimizing memory performance.

[0014] Additionally, the second power supply control circuit includes: a second control transistor, one of its source or drain terminals coupled to a second node, the other terminal coupled to a ground node, and a gate coupled to a second selection circuit.

[0015] Additionally, the second selection circuit includes: a second control sub-circuit configured to provide a third selection signal or a fourth selection signal based on a second control command; a third selection sub-circuit coupled to the second control sub-circuit, the first control power supply, and the second power supply control circuit; the third selection sub-circuit configured to provide a first control power supply to the second power supply control circuit based on the third selection signal; and a fourth selection sub-circuit coupled to the second control sub-circuit, the second control power supply, and the second power supply control circuit; the fourth selection sub-circuit configured to provide a second control power supply to the second power supply control circuit based on the fourth selection signal.

[0016] Additionally, the third selection sub-circuit includes: a third selection transistor; one terminal of the source or drain of the third selection transistor is coupled to a first control power supply, the other terminal is coupled to a second power supply control circuit, and the gate is coupled to a second control sub-circuit for receiving a third selection signal; the fourth selection sub-circuit includes: a fourth selection transistor; one terminal of the source or drain of the fourth selection transistor is coupled to a second control power supply, the other terminal is coupled to a second power supply control circuit, and the gate is coupled to a second control sub-circuit for receiving a fourth selection signal.

[0017] Additionally, the sensing amplification circuit includes: a first P-type transistor, with one terminal of its source or drain coupled to a first node, the other terminal coupled to a complementary readout node, and a gate coupled to a readout node; a second P-type transistor, with one terminal of its source or drain coupled to the first node, the other terminal coupled to a readout node, and a gate coupled to a complementary readout node; a first N-type transistor, with one terminal of its source or drain coupled to a second node, the other terminal coupled to a complementary readout node, and a gate coupled to a bit line; and a second N-type transistor, with one terminal of its source or drain coupled to the second node, the other terminal coupled to a readout node, and a gate coupled to a bit line. A coupled complementary bit line; an isolation circuit, comprising: a first isolation transistor, one terminal of which is coupled to the bit line and the other terminal of which is coupled to a readout node, and a gate for receiving an isolation signal; the first isolation transistor is configured to, during a sense amplification phase, couple the readout node to the bit line based on the isolation signal being turned on; a second isolation transistor, one terminal of which is coupled to the complementary bit line and the other terminal of which is coupled to a complementary readout node, and a gate for receiving an isolation signal; the second isolation transistor is configured to, during a sense amplification phase, couple the complementary readout node to the complementary readout bit line based on the isolation signal being turned on.

[0018] Additionally, the offset cancellation circuit includes: a first offset cancellation transistor, with one terminal of its source or drain coupled to a bit line and the other terminal coupled to a complementary readout node, and a gate for receiving an offset cancellation signal; the first offset cancellation transistor is configured to, during the offset cancellation phase, couple the complementary readout node to the bit line based on the offset cancellation signal being turned on; a second offset cancellation transistor, with one terminal of its source or drain coupled to the complementary bit line and the other terminal coupled to the readout node, and a gate for receiving the offset cancellation signal; the second offset cancellation transistor is configured to, during the offset cancellation phase, couple the readout node to the complementary bit line based on the offset cancellation signal being turned on.

[0019] Additionally, the amplification circuit further includes: a preprocessing circuit coupled to the readout node and the complementary readout node; during the charging phase, the preprocessing circuit coupled to at least one of the readout node or the complementary readout node is configured to precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on a precharge signal; during the equalization phase, the preprocessing circuit coupled to both the readout node and the complementary readout node is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on an equalization signal.

[0020] Additionally, the preprocessing circuit includes: a charging transistor, one of its source or drain terminals coupled to a readout node or a complementary readout node, and the other terminal coupled to a node providing a preset voltage, with its gate used to receive a charging signal; the charging transistor is configured to precharge the bit line, complementary bit line, readout node, and complementary readout node to the preset voltage based on the charging signal being turned on during the charging phase; and an equalization transistor, one of its source or drain terminals coupled to a readout node, and the other terminal coupled to a complementary readout node, with its gate used to receive an equalization signal; the equalization transistor is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal being turned on during the equalization phase.

[0021] This disclosure provides a control method applied to the amplification circuit provided in the above embodiments, including: in an offset elimination stage, providing a high level to a first node based on a first power supply; in a sensing amplification stage, providing a high level to the first node based on a second power supply; wherein the power supply voltage of the first power supply is higher than the power supply voltage of the second power supply.

[0022] In addition, during the offset elimination phase, the first power supply is coupled to the first control transistor based on the first selection signal; during the sensing amplification phase, the second power supply is coupled to the first control transistor based on the second selection signal; during the offset elimination phase and the sensing amplification phase, the first control transistor is turned on based on the pull-up control signal provided by the pull-up control power supply, and the first power supply or the second power supply is coupled to the first node.

[0023] In addition, the control method further includes: in the offset elimination stage, coupling the second node to the ground node based on the first control power supply; in the sensing amplification stage, coupling the second node to the ground node based on the second control power supply; the power supply voltage of the first control power supply is higher than the power supply voltage of the second control power supply.

[0024] Additionally, during the offset cancellation phase, the first control power supply is coupled to the second control transistor based on the third selection signal; during the sensing amplification phase, the second control power supply is coupled to the second control transistor based on the fourth selection signal; during both the offset cancellation and sensing amplification phases, the second control transistor is turned on based on the pull-down control signal provided by the first or second control power supply, coupling the ground node to the second node.

[0025] This disclosure provides a memory that includes the amplification circuit provided in the above embodiments. The amplification circuit is configured to perform data read and write operations to shorten the processing time of the offset elimination stage while ensuring the accuracy of offset elimination, thereby optimizing the performance of the memory. Attached Figure Description

[0026] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0027] Figure 1 A virtual structural diagram of an amplifier circuit provided in an embodiment of this disclosure; Figure 2 A schematic diagram of a circuit structure for an amplifier circuit provided in an embodiment of this disclosure; Figure 3 A schematic diagram of another circuit structure of the amplifier circuit provided in one embodiment of the present disclosure; Figure 4 A schematic diagram of the structure of a first power supply circuit provided in an embodiment of this disclosure; Figure 5 This is a schematic diagram of the structure of a second power supply control circuit provided in an embodiment of the present disclosure; Figure 6 This is a schematic diagram of the structure of a second selection circuit provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of the timing of each signal during data reading and writing of an amplifier circuit provided in another embodiment of this disclosure; Figure 8 A schematic flowchart illustrating a control method provided in another embodiment of this disclosure; Figure 9 This is a schematic diagram of the structure of a memory according to another embodiment of the present disclosure. Detailed Implementation

[0028] Transistors that make up an amplifier circuit may have different device characteristics due to factors such as process variations and temperature. For example, compatible transistors may have different threshold voltages. These different device characteristics can cause offset noise in the amplifier circuit. The presence of offset noise in the amplifier circuit reduces the effective read margin of the amplifier circuit, thereby reducing the performance of DRAM.

[0029] By adding an offset cancellation stage before the sensing amplification stage, offset noise in the amplification circuit can be eliminated. However, the offset cancellation stage requires additional data processing time, which will affect the data processing timing of the memory. Ensuring the accuracy of offset cancellation and reducing the processing time of the offset cancellation stage is of great significance to improving the performance of the memory.

[0030] One embodiment of this disclosure provides an amplifier circuit that, while ensuring the accuracy of offset elimination, shortens the processing time of the offset elimination stage, thereby optimizing the performance of the memory.

[0031] It will be understood by those skilled in the art that many technical details have been provided in the various embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.

[0032] Figure 1 This is a virtual structural diagram of the amplifier circuit provided in this embodiment. Figure 2 This is a schematic diagram of a circuit structure for the amplifier circuit provided in this embodiment. Figure 3 This is a schematic diagram of another circuit structure for the amplifier circuit provided in this embodiment. Figure 4 This is a schematic diagram of the structure of the first power supply circuit provided in this embodiment. Figure 5 This is a schematic diagram of the structure of the second power supply control circuit provided in this embodiment. Figure 6 This is a schematic diagram of the second selection circuit provided in this embodiment. The amplifier circuit provided in this embodiment will be further described in detail below with reference to the accompanying drawings: refer to Figures 1-3 An amplifier circuit, coupled to bit line BL and complementary bit line BLB, includes: The sensing amplifier circuit 101 includes a readout node SABL, a complementary readout node SABLB, a first node PCS, and a second node NCS. During the sensing amplification stage and the offset cancellation stage, the first node PCS is used to receive a high level, and the second node NCS is used to receive a low level.

[0033] Specifically, the first node PCS is coupled to the power node to receive a high level provided by the power node; the second node NCS is coupled to the ground node to receive a low level provided by the ground node.

[0034] The isolation circuit 102 is coupled to the readout node SABL, the complementary readout node SABLB, the bit line BL, and the complementary bit line BLB. The isolation circuit 102 is configured to couple the readout node SABL to the bit line BL and the complementary readout node SABLB to the complementary bit line BLB during the sensing amplification phase.

[0035] Offset cancellation circuit 103 is coupled to read node SABL, complementary read node SABLB, bit line BL and complementary bit line BLB. Offset cancellation circuit 103 is configured to couple bit line BL to complementary read node SABLB and complementary bit line BLB to read node SABL during offset cancellation phase.

[0036] A first power supply circuit 200, coupled to a first node PCS, includes a first power supply and a second power supply, wherein the power supply voltage of the first power supply is higher than that of the second power supply; the first power supply circuit is configured to couple the first power supply to the first node PCS during an offset cancellation phase and to couple the second power supply to the first node PCS during a sensing amplification phase.

[0037] During the offset cancellation phase, a first power supply is coupled to the first node PCS, providing a high level to the first node PCS. The sensing amplifier circuit amplifies the voltage difference between bit line BL and complementary bit line BLB based on the high level provided by the first node PCS. During the sensing amplification phase, a second power supply is coupled to the first node PCS, providing a high level to the first node PCS. The sensing amplifier circuit amplifies the voltage difference between bit line BL and complementary bit line BLB based on the high level provided by the first node PCS. Since the power supply voltage of the first power supply is greater than that of the second power supply, compared to using the same power supply in both the offset cancellation and sensing amplification phases, this embodiment increases the voltage difference between the first node PCS and the second node NCS during the offset cancellation phase by providing a first power supply with a larger power supply voltage. This increases the rate at which the sensing amplifier circuit 101 generates compensation voltage between bit line BL and complementary bit line BLB, eliminating the deviation caused by manufacturing differences in transistor pairs within the amplifier circuit. This reduces the time required to complete offset cancellation, thereby shortening the offset cancellation phase time during memory design and optimizing memory performance.

[0038] refer to Figure 2 , Figure 2 The sensing amplifier circuit 101 shown includes only one first node PCS and one second node NCS, see reference. Figure 3 , Figure 3 The sensing amplifier circuit 101 shown includes multiple first nodes PCS and multiple second nodes NCS, which respectively provide high and low levels; it should be noted that, Figure 3 The circuit structure shown is illustrated using three first nodes (PCS) and three second nodes (NCS) as an example, and does not constitute a limitation on this embodiment.

[0039] refer to Figure 3 and combined Figure 4 The first power supply circuit 200 includes: A first power control circuit 201 is coupled to a power node V and a first node PCS; the first power control circuit 201 is configured to couple the power node V to the first node PCS during the offset cancellation phase and the sensing amplification phase.

[0040] A first selection circuit 202, coupled to a power node V, includes a first power supply V1 and a second power supply V2; the first selection circuit 202 is configured to provide the first power supply V1 to the power node V during the offset elimination phase and to provide the second power supply V2 to the power node V during the sensing amplification phase.

[0041] refer to Figure 4The first power control circuit 201 includes: a first control transistor. <41> One terminal of the source or drain is coupled to the power supply node V, and the other terminal is coupled to the first node PCS; the pull-up control circuit 211 is connected to the first control transistor. <41> With gate coupling, the pull-up control circuit 211 is configured to turn on the first control transistor during the offset cancellation phase and the sensing amplification node. <41> .

[0042] Specifically, the pull-up control circuit 211 is turned on based on the pull-up control signal K1, which is provided by the memory of the amplifier circuit. During the offset elimination stage and the sensing amplification stage, the memory provides the pull-up control signal K1 to turn on the first control transistor. <41> This is to couple the power node V to the first node PCS.

[0043] In addition, this embodiment is based on Figure 3 The circuit shown is explained in the diagram, therefore it is adapted to Figure 3 The circuit shown has three first nodes (PCS) with three controllers that implement control over the three first control transistors. <41> The pull-up control signal K1 is used to select and turn on the first control transistor in some embodiments. <41> .

[0044] It should be noted that the first control transistor <41> It can be set to an NMOS transistor or a PMOS transistor. Since the pull-up capability of a PMOS transistor is better than that of an NMOS transistor, in this embodiment, the first control transistor is... <41> PMOS transistors are used.

[0045] refer to Figure 4 The first selection circuit 202 includes: a first control sub-circuit 232, configured to provide a first selection signal or a second selection signal based on a first control command; a first selection sub-circuit 212, coupled to the first control sub-circuit 232, power node V, and a first power supply V1; the first selection sub-circuit 212 is configured to provide the first power supply V1 to power node V based on the first selection signal; and a second selection sub-circuit 222, coupled to the first control sub-circuit 232, power node V, and a second power supply V2; the second selection sub-circuit 222 is configured to provide the second power supply V2 to power node V based on the second selection signal.

[0046] Specifically, the first control sub-circuit 232 generates a corresponding selection signal based on the first control command to turn on the first selection sub-circuit 212 or the second selection sub-circuit 222. The first control command is provided by the memory of the amplifier circuit. In the offset elimination stage and the sensing amplification stage, the memory selects to turn on the first selection sub-circuit 212 or the second selection sub-circuit 222 through the first control command, thereby providing the first power supply V1 to the first node PCS in the offset elimination stage and providing the second power supply V2 to the first node PCS in the sensing amplification stage.

[0047] refer to Figure 4 The first selection sub-circuit 212 includes: a first selection transistor. <51> First selection transistor <51> One terminal of the source or drain is coupled to a first power supply V1, and the other terminal is coupled to a power node V. The gate is coupled to a first control sub-circuit 232 for receiving a first selection signal. The second selection sub-circuit 222 includes a second selection transistor. <52> Second selection transistor <52> One of the source or drain terminals is coupled to the second power supply V2, and the other terminal is coupled to the power supply node V. The gate is coupled to the first control sub-circuit 232 for receiving the second selection signal.

[0048] Specifically, the first selection transistor <51> Based on the first selection signal being turned on, the first power supply V1 is coupled to the power node V, and the second selection transistor... <52> Based on the second selection signal being turned on, the second power supply V2 is coupled to the power node V.

[0049] refer to Figure 5 and Figure 6 and combined Figure 3 The amplifier circuit further includes: a second power supply control circuit 301 coupled to ground node GND and second node NCS. A second selection circuit 311, coupled to the second power supply control circuit 301, includes a first control power supply VK1 and a second control power supply VK2, wherein the power supply voltage of the first control power supply VK1 is higher than the power supply voltage of the second control power supply VK2. The second selection circuit 311 is configured to couple the first control power supply VK1 to the second power supply control circuit 301 during the offset cancellation phase and to couple the second control power supply VK2 to the second power supply control circuit 301 during the sensing amplification phase. The second power supply control circuit 301 is configured to couple ground node GND to the second node NCS based on either the first control power supply VK1 or the second control power supply VK2.

[0050] During the offset cancellation phase, ground node GND is coupled to the second node NCS via the first control power supply VK1. Ground node GND provides a low level to the second node NCS, and the sensing amplification circuit 101 amplifies the voltage difference between bit line BL and complementary bit line BLB based on the low level provided by the second node NCS. During the sensing amplification phase, ground node GND is coupled to the second node NCS via the second control power supply VK2. Ground node GND provides a low level to the second node NCS, and the sensing amplification circuit 101 amplifies the voltage difference between bit line BL and complementary bit line BLB based on the low level provided by the second node NCS. Since the power supply voltage of the first control power supply VK1 is greater than the power supply voltage of the second control power supply VK2, compared with the method of using the same control power supply in the offset elimination stage and the sensing amplification stage, this embodiment provides a first control power supply VK1 with a larger power supply voltage in the offset elimination stage, so as to increase the rate at which the sensing amplification circuit 101 generates a compensation voltage between the bit line BL and the complementary bit line BLB, eliminate the deviation caused by the manufacturing difference of the transistors in the transistor pair in the amplification circuit, thereby reducing the time required to complete the offset elimination, and thus shortening the time of the offset elimination stage when designing the memory to optimize the performance of the memory.

[0051] It should be noted that, in some embodiments, the performance of the memory can be optimized solely through the first power supply circuit 200 provided above; in some embodiments, the performance of the memory can be optimized solely through the second power control circuit 301 and the second selection circuit 311 provided above; in some embodiments, the first power supply circuit 200, the second power control circuit 301, and the second selection circuit 311 provided above can be implemented in combination to further optimize the performance of the memory.

[0052] refer to Figure 5 The second power supply control circuit 301 includes: a second control transistor. <42> One of the source or drain terminals is coupled to the second node NCS, and the other terminal is coupled to the ground node GND. The gate is coupled to the second selection circuit 311.

[0053] Specifically, the second control transistor <42> Based on the second selection provided by 311, the pull-down control signal K2 is turned on, wherein the pull-down control signal K2 is provided by the first control power supply VK1 or the second control power supply VK2. During the offset elimination phase, the second control transistor... <42> Based on the pull-down control signal K2 provided by the first control power supply VK1, the ground node GND is coupled to the second node NCS. During the sensing amplification stage, the second control transistor... <42> Based on the pull-down control signal K2 provided by the second control power supply VK2, the ground node GND is coupled to the second node NCS; since the power supply voltage of the first control power supply VK1 is greater than the power supply voltage of the second control power supply VK2, the second control transistor... <42> When the first control power supply VK1 is turned on, compared to the second control transistor... <42> When the second control power supply VK2 is turned on, the second control transistor <42> The channel width is larger.

[0054] It should be noted that this embodiment uses a second control transistor. <42> Based on high-level conduction, i.e., the second control transistor <42> Taking an NMOS transistor as an example does not constitute a limitation of this embodiment. Since the pull-down capability of an NMOS transistor is superior to that of a PMOS transistor, the second control transistor... <42> Setting the transistor to an NMOS transistor can increase the rate at which the sensing amplifier circuit 101 generates a compensation voltage between the bit line BL and the complementary bit line BLB; in other embodiments, the second control transistor can also be set to a PMOS transistor, in which case the power supply voltage of the first control power supply is less than the power supply voltage of the second control power supply.

[0055] refer to Figure 5 and Figure 6 The second selection circuit 311 includes: a second control sub-circuit 332, configured to provide a third selection signal or a fourth selection signal based on a second control command; a third selection circuit 312, coupled to the second control sub-circuit 332, a first control power supply VK1, and a second power control circuit 301; the third selection circuit 312 is configured to provide the first control power supply VK1 to the second power control circuit 301 based on the third selection signal; and a fourth selection circuit 322, coupled to the second control sub-circuit 332, a second control power supply VK2, and the second power control circuit 301; the fourth selection circuit 322 is configured to provide the second control power supply VK2 to the second power control circuit 301 based on the fourth selection signal.

[0056] Specifically, the second control sub-circuit 332 generates a corresponding selection signal based on the second control command to turn on the third selection sub-circuit 312 or the fourth selection sub-circuit 322. The second control command is provided by the memory of the amplifier circuit. In the offset elimination stage and the sensing amplification stage, the memory selects to turn on the third selection sub-circuit 312 or the fourth selection sub-circuit 322 through the second control command, thereby realizing that in the offset elimination stage, the ground node GND is coupled to the second node NCS based on the first control power supply VK1, and in the sensing amplification stage, the ground node GND is coupled to the second node NCS based on the second control power supply VK2.

[0057] refer to Figure 6 The third selection sub-circuit 312 includes: a third selection transistor. <53> Third selection transistor <53> One terminal of the source or drain is coupled to the first control power supply VK1, and the other terminal is coupled to the second power supply control circuit 301. The gate is coupled to the second control sub-circuit 311 for receiving the third selection signal. The fourth selection sub-circuit 322 includes: a fourth selection transistor. <54> Fourth selection transistor <54> One of the source or drain terminals is coupled to the second control power supply VK2, the other terminal is coupled to the second power supply control circuit 301, and the gate is coupled to the second control sub-circuit 311 for receiving the fourth selection signal.

[0058] Specifically, the third selection transistor <53> Based on the conduction of the third selection signal, the first control power supply VK1 is coupled to the second power control circuit 301; the fourth selection transistor <54> Based on the conduction of the fourth selection signal, the second control power supply VK2 is coupled to the second power control circuit 301.

[0059] Continue to refer to Figure 2 and Figure 3 In this embodiment, the sensing amplifier circuit 101 includes: a first P-type transistor. <p1>One terminal of the source or drain is coupled to the first node PCS, and the other terminal is coupled to the complementary readout node SABLB; the gate is coupled to the readout node SABL; the second P-type transistor <p2>One terminal of the source or drain is coupled to the first node PCS, and the other terminal is coupled to the readout node SABL; the gate is coupled to the complementary readout node SABLB; the first N-type transistor <n1>One terminal of the source or drain is coupled to the second node NCS, and the other terminal is coupled to the complementary readout node SABLB. The gate is coupled to the bit line BL. (Second N-type transistor) <n2>One of the terminals in the source or drain is coupled to the second node NCS, and the other terminal is coupled to the readout node SABL. The gate is coupled to the complementary bit line BLB.

[0060] Continue to refer to Figure 2 and Figure 3 In this embodiment, the isolation circuit 102 includes: a first isolation transistor. <11> One terminal of the source or drain is coupled to the bit line BL, and the other terminal is coupled to the readout node SABL. The gate is used to receive the isolation signal (Isolation Cancellation, ISO); the first isolation transistor. <11> It is configured to couple the readout node SABL to the bit line BL based on the isolation signal ISO being turned on during the sensing amplification phase. Second isolation transistor <12> One terminal of the source or drain is coupled to the complementary bit line BLB, and the other terminal is coupled to the complementary readout node SABLB. The gate is used to receive the isolation signal ISO; the second isolation transistor... <12> It is configured to couple the complementary readout node SABLB to the complementary bit line BLB based on the isolation signal ISO being turned on during the sensing amplification phase.

[0061] Continue to refer to Figure 2 and Figure 3 In this embodiment, the offset cancellation circuit 103 includes: a first offset cancellation transistor. <21> One terminal of the source or drain is coupled to the bit line BL, and the other terminal is coupled to the complementary readout node SABLB. The gate is used to receive the offset cancellation signal (OC). The first offset cancellation transistor... <21> It is configured to couple the complementary readout node SABLB to the bit line BL based on the offset cancellation signal OC being turned on during the offset cancellation phase. The second offset cancellation transistor... <22> One terminal of the source or drain is coupled to the complementary bit line BLB, and the other terminal is coupled to the readout node SABL. The gate is used to receive the offset cancellation signal OC; the second offset cancellation transistor... <22> It is configured to couple the readout node SABL to the complementary bit line BLB based on the offset cancellation signal OC being turned on during the offset cancellation phase.

[0062] It should be noted that the first isolation transistor <11> Second isolation transistor <12> First offset cancellation transistor <21> Second offset cancellation transistor <22> It can be set to an NMOS transistor or a PMOS transistor. This embodiment does not specify the first isolation transistor. <11> Second isolation transistor <12> First offset cancellation transistor <21> Second offset cancellation transistor <22> The specific type is limited.

[0063] Continue to refer to Figure 2 and Figure 3 In this embodiment, the amplification circuit further includes: a preprocessing circuit 104 coupled to the readout node SABL and the complementary readout node SABLB; during the charging phase, the preprocessing circuit 104 is coupled to at least one of the readout node SABL or the complementary readout node SABLB and is configured to precharge the bit line BL, the complementary bit line BLB, the readout node SABL, and the complementary readout node SABLB to a preset voltage Vdd based on a precharge cancellation (PRE) signal; during the equalization phase, the preprocessing circuit 104 is coupled to both the readout node SABL and the complementary readout node SABLB and is configured to synchronize the node voltage of the readout node SABL and the node voltage of the complementary readout node SABLB based on an equalization cancellation (EQ) signal.

[0064] It should be noted that the preset voltage Vdd is the internal power supply voltage of the memory to which the amplifier circuit belongs.

[0065] Specifically, the preprocessing circuit includes: a charging transistor. <31> One terminal of the source or drain is coupled to a readout node SABL or a complementary readout node SABLB, and the other terminal is coupled to a node that provides a preset voltage Vdd. The gate is used to receive the charging signal PRE; charging transistor. <31> Configured to precharge bit line BL, complementary bit line BLB, readout node SABL, and complementary readout node SABLB to a preset voltage Vdd during the charging phase, based on the charging signal PRE being turned on. Equalization transistor <32> One terminal of the source or drain is coupled to the readout node SABL, and the other terminal is coupled to the complementary readout node SABLB. The gate is used to receive the equalization signal EQ; equalization transistor. <32> It is configured to, during the equalization phase, simultaneously read out the node voltage of node SABL and the node voltage of complementary node SABLB based on the equalization signal EQ being turned on.

[0066] It should be noted that the charging transistor <31> and equalization transistors <32> It can be set to an NMOS transistor or a PMOS transistor. This embodiment does not specify the charging transistor. <31> and equalization transistors <32> The specific type is limited.

[0067] In this embodiment, since the power supply voltage of the first power supply V1 is greater than that of the second power supply V2, compared to using the same power supply in both the offset elimination stage and the sensing amplification stage, this embodiment increases the voltage difference between the first node PCS and the second node NCS in the offset elimination stage by providing a first power supply V1 with a larger power supply voltage in the offset elimination stage. This increases the rate at which the sensing amplification circuit 101 generates compensation voltage between the bit line BL and the complementary bit line BLB, eliminates the deviation caused by the manufacturing differences of transistors in the transistor pair in the amplification circuit, thereby reducing the time required to complete the offset elimination. Consequently, when designing the memory, the time of the offset elimination stage can be shortened to optimize the memory performance.

[0068] Furthermore, since the power supply voltage of the first control power supply VK1 is greater than that of the second control power supply VK2, compared to using the same control power supply in both the offset elimination stage and the sensing amplification stage, this embodiment provides a first control power supply VK1 with a larger power supply voltage in the offset elimination stage. This increases the rate at which the sensing amplification circuit 101 generates a compensation voltage between the bit line BL and the complementary bit line BLB, eliminating the deviation caused by manufacturing differences in the transistor pairs within the amplification circuit. This reduces the time required to complete offset elimination, and consequently, shortens the offset elimination stage time during memory design to optimize memory performance.

[0069] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this disclosure, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this disclosure; however, this does not mean that other units are absent from this embodiment.

[0070] It should be noted that the features disclosed in the amplifier circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain new amplifier circuit embodiments.

[0071] Another embodiment of this disclosure provides a control method that uses the amplification circuit provided in the above embodiments to shorten the processing time of the offset elimination stage while ensuring the accuracy of offset elimination, thereby optimizing the performance of the memory.

[0072] Figure 7 This is a schematic diagram of the timing of each signal in the amplifier circuit provided in this embodiment during data reading and writing. Figure 8 This is a flowchart illustrating the control method provided in this embodiment. The control method provided in this embodiment will be further described in detail below with reference to the accompanying drawings: refer to Figure 7 and combined Figure 2 and Figure 3 Regarding the amplifier circuit provided in the above embodiments: In phase S1, i.e. the charging phase, an isolation signal ISO, an offset cancellation signal OC, and an equalization signal EQ are provided to couple the bit line BL, the complementary bit line BLB, the readout node SABL, and the complementary readout node SABLB to each other, and a charging signal PRE is provided to precharge the bit line BL, the complementary bit line BLB, the readout node SABL, and the complementary readout node SABLB to a preset voltage Vdd.

[0073] It should be noted that the preset voltage Vdd is the internal power supply voltage of the memory to which the amplifier circuit belongs.

[0074] In stage S2, the offset cancellation stage, offset noise in the amplifier circuit is eliminated.

[0075] Specifically, refer to Figure 8 Step 401: A high level is provided to the first node PCS based on the first power supply V1, and the power supply voltage of the first power supply V1 is greater than the power supply voltage of the second power supply V2.

[0076] More specifically, in combination Figure 4 Based on the first selection signal, the first power supply V1 is coupled to the first control transistor. <41> First control transistor <41> Based on the conduction of the pull-up control signal K1, the first power supply V1 is coupled to the first node PCS, wherein the pull-up control signal K1 is provided by the memory of the amplifier circuit.

[0077] Since the power supply voltage of the first power supply V1 is greater than that of the second power supply V2, compared to using the same power supply in both the offset elimination stage and the sensing amplification stage, this embodiment increases the voltage difference between the first node PCS and the second node NCS in the offset elimination stage by providing a first power supply V1 with a larger power supply voltage in the offset elimination stage. This increases the rate at which the sensing amplification circuit 101 generates compensation voltage between the bit line BL and the complementary bit line BLB, eliminating the deviation caused by the manufacturing differences of transistors in the transistor pair within the amplification circuit. This reduces the time required to complete offset elimination, and thus shortens the offset elimination stage time during memory design to optimize memory performance.

[0078] In some embodiments, reference Figure 8 Step 401 further includes: coupling the second node NCS to the ground node GND based on the first control power supply VK1, wherein the power supply voltage of the first control power supply VK1 is greater than the power supply voltage of the second control power supply VK2.

[0079] Specifically, in combination Figure 5 and Figure 6 Based on the third selection signal, the control couples the first control power supply VK1 to the second control transistor. <42> Second control transistor <42> Based on the pull-down control signal K2 provided by the first control power supply VK1, the ground node GND is coupled to the second node NCS.

[0080] Since the power supply voltage of the first control power supply VK1 is greater than that of the second control power supply VK2, compared to using the same control power supply in both the offset elimination stage and the sensing amplification stage, this embodiment provides a first control power supply VK1 with a larger power supply voltage in the offset elimination stage. This increases the rate at which compensation voltage is generated between the amplified bit line BL and the complementary bit line BLB in the sensing amplification circuit 101, eliminates the deviation caused by the manufacturing differences of transistors in the transistor pair in the amplification circuit, thereby reducing the time required to complete offset elimination. Consequently, when designing a memory, the time of the offset elimination stage can be shortened to optimize the memory performance.

[0081] In the S3 stage, which is the charge sharing stage, the word line WL is turned on to conduct the corresponding memory cell, and the charge stored in the memory cell is shared to the bit line BL or the complementary bit line BLB. Then, based on the isolation signal ISO, the bit line BL is coupled to the read node SABL, and the complementary bit line BLB is coupled to the complementary read node SABLB.

[0082] In the S4 stage, which is the sensing amplification stage, the voltage difference between the bit line BL and the complementary bit line BLB is amplified.

[0083] Specifically, refer to Figure 8 Step 402: A high level is provided to the first node PCS based on the second power supply V2, and the power supply voltage of the first power supply V1 is greater than the power supply voltage of the second power supply V2.

[0084] More specifically, in combination Figure 5 Based on the first selection signal, the second power supply V2 is coupled to the first control transistor. <41> First control transistor <41> Based on the conduction of the pull-up control signal K1, the second power supply V2 is coupled to the first node PCS, wherein the pull-up control signal K1 is provided by the memory of the amplifier circuit.

[0085] In some embodiments, reference Figure 8 Step 402 further includes: coupling the second node NCS to the ground node GND based on the second control power supply VK2, wherein the power supply voltage of the first control power supply VK1 is greater than the power supply voltage of the second control power supply VK2.

[0086] Specifically, in combination Figure 5 and Figure 6 Based on the fourth selection signal, the control couples the second control power supply VK2 to the second control transistor. <42> Second control transistor <42> Based on the pull-down control signal K2 provided by the second control power supply VK2, the ground node GND is coupled to the second node NCS.

[0087] In the S5 stage, which is at the end of the sensing amplification stage, data is read out / written.

[0088] It should be noted that, in some embodiments, memory performance can be optimized simply by providing a larger power supply to the first node PCS; in some embodiments, memory performance can be optimized simply by coupling the second node NCS to the ground node GND based on a larger power supply; in some embodiments, the above two control methods can be implemented in combination to further optimize memory performance.

[0089] It should be noted that the features disclosed in the control method provided in the above embodiments can be arbitrarily combined without conflict to obtain new control method embodiments.

[0090] Another embodiment of this disclosure provides a memory that includes the amplification circuit provided in the above embodiments. The amplification circuit is configured to perform data read and write operations to shorten the processing time of the offset elimination stage while ensuring the accuracy of offset elimination, thereby optimizing the performance of the memory.

[0091] Figure 9 This is a schematic diagram of the memory structure in this embodiment. The memory provided in this embodiment will be further described in detail below with reference to the accompanying drawings: refer to Figure 9 Memory can be a storage cell or device based on semiconductor devices or components. For example, a memory device can be volatile memory, such as Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR SDRAM), Graphics Double Data Rate Synchronous Dynamic Random Access Memory (GDDR SDRAM), Double Data Rate Type Dual Synchronous Dynamic Random Access Memory (DDR2 SDRAM), Double Data Rate Type Triple Synchronous Dynamic Random Access Memory (DDR3 SDRAM), Double Data Rate Type Fourth Generation Synchronous Dynamic Random Access Memory (DDR4 SDRAM), Thyristor Random Access Memory (TRAM), etc.; or it can be non-volatile memory, such as Phase Change Random Access Memory (PRAM), Magnetic Random Access Memory (MRAM), Resistive Random Access Memory (RRAM), etc.

[0092] The memory device can input / output data via the data line DQ in response to control commands CMD and address signals received from an external device, such as a memory controller. The memory device includes a memory cell array 10, a command decoder 30, control logic 40, an address buffer 20, a row decoder 21, a column decoder 22, an amplifier circuit 50, and a data input / output circuit 60.

[0093] The memory cell array 10 includes a plurality of memory cells provided in a matrix format arranged in multiple rows and columns. The memory cell array 10 includes a plurality of word lines WL and a plurality of bit lines BL connected to the memory cells. The plurality of word lines WL can be connected to rows of the memory cells, and the plurality of bit lines BL can be connected to columns of the memory cells.

[0094] Command decoder 30 can decode write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc. received from external devices such as memory controllers, and can allow control logic 40 to generate control signals corresponding to control command CMD.

[0095] The control command (CMD) can include activation commands, read commands, write commands, precharge commands, etc.

[0096] Address buffer 20 receives address signals from the memory controller, which is an external device. Address signals include a row address RA for addressing rows of the memory cell array 10 and a column address CA for addressing columns of the memory cell array 10. Address buffer 120 can send the row address RA to row decoder 21 and the column address CA to column decoder 22.

[0097] The row decoder 21 can select any one of the multiple word lines WL connected to the memory cell array 10. The row decoder 21 can decode the row address RA received from the address buffer 120, select any word line corresponding to the row address RA, and activate the selected word line WL.

[0098] The column decoder 22 can select a predetermined number of bit lines from a plurality of bit lines BL of the memory cell array 10. The column decoder 22 can decode the column address CA received from the address buffer 120 and select the predetermined number of bit lines BL corresponding to the received column address CA.

[0099] Amplifier circuit 50 is connected to the bit line BL of memory cell array 10. Amplifier circuit 50 can read the voltage change of selected bit line among multiple bit lines BL, amplify the voltage change, and output the amplified voltage change.

[0100] The data input / output circuit 60 can output data via the data line DQ based on the voltage read and amplified by the amplifier circuit 50.

[0101] Amplifier circuit 50 can receive isolation signal ISO and offset cancellation signal OC from control logic 40. Amplifier circuit 50 can perform offset cancellation operation in response to isolation signal ISO and offset cancellation signal OC. For example, offset represents the characteristic difference between the semiconductor devices constituting amplifier circuit 50, such as the difference between the threshold voltages of different semiconductor devices.

[0102] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.

Claims

1. An amplifier circuit coupled to bit lines and complementary bit lines, characterized in that, include: The sensing amplification circuit includes a readout node, a complementary readout node, a first node, and a second node. During the sensing amplification stage and the offset cancellation stage, the first node is used to receive a high level, and the second node is used to receive a low level. A first power supply circuit, coupled to the first node, includes a first power supply and a second power supply; the first power supply circuit is configured to provide the first power supply to the first node during the offset cancellation phase and to provide the second power supply to the second node during the sensing amplification phase.

2. The amplifier circuit according to claim 1, characterized in that, The first power supply circuit includes: A first power control circuit is coupled to a power node and the first node; the first power control circuit is configured to couple the power node to the first node during the offset cancellation phase and the sensing amplification phase. A first selection circuit, coupled to the power node, includes a first power supply and a second power supply; the first selection circuit is configured to provide the first power supply to the power node during the offset cancellation phase and to provide the second power supply to the power node during the sensing amplification phase.

3. The amplifier circuit according to claim 2, characterized in that, The first power control circuit includes: The first control transistor has one terminal of its source or drain coupled to the power supply node, and the other terminal coupled to the first node. A pull-up control circuit is coupled to the gate of the first control transistor; the pull-up control circuit is configured to turn on the first control transistor during the offset elimination phase and the sensing amplification phase.

4. The amplifier circuit according to claim 2, characterized in that, The first selection circuit includes: The first control sub-circuit is configured to provide a first selection signal or a second selection signal based on a first control command; A first selection sub-circuit is coupled to the first control sub-circuit, the power node, and the first power supply; the first selection sub-circuit is configured to provide the first power supply to the power node based on the first selection signal. A second selection sub-circuit is coupled to the first control sub-circuit, the power node, and the second power supply; the second selection sub-circuit is configured to provide the second power supply to the power node based on the second selection signal.

5. The amplifier circuit according to claim 4, characterized in that, include: The first selection sub-circuit includes: a first selection transistor; one terminal of the source or drain of the first selection transistor is coupled to the first power supply, the other terminal is coupled to the power supply node, and the gate is coupled to the first control sub-circuit for receiving the first selection signal; The second selection sub-circuit includes: a second selection transistor; one terminal of the source or drain of the second selection transistor is coupled to the second power supply, the other terminal is coupled to the power supply node, and the gate is coupled to the first control sub-circuit for receiving the second selection signal.

6. The amplifier circuit according to claim 1, characterized in that, The amplifier circuit further includes: The second power supply control circuit is coupled to the ground node and the second node; The second selection circuit is coupled to the second power control circuit and includes a first control power supply and a second control power supply, wherein the power supply voltage of the first control power supply is higher than the power supply voltage of the second control power supply. The second selection circuit is configured to couple the first control power supply to the second power control circuit during the offset elimination phase, and to couple the second control power supply to the second power control circuit during the sensing amplification phase. The second power control circuit is configured to couple the ground node to the second node based on the first control power supply or the second control power supply.

7. The amplifier circuit according to claim 6, characterized in that, The second power control circuit includes: a second control transistor, one of its source or drain terminals being coupled to the second node, the other terminal being coupled to the ground node, and its gate being coupled to the second selection circuit.

8. The amplifier circuit according to claim 6, characterized in that, The second selection circuit includes: The second control sub-circuit is configured to provide a third selection signal or a fourth selection signal based on the second control command; A third selection sub-circuit is coupled to the second control sub-circuit, the first control power supply, and the second power control circuit; the third selection sub-circuit is configured to provide the first control power supply to the second power control circuit based on the third selection signal. A fourth selection sub-circuit is coupled to the second control sub-circuit, the second control power supply, and the second power control circuit; the fourth selection sub-circuit is configured to provide the second control power supply to the second power control circuit based on the fourth selection signal.

9. The amplifier circuit according to claim 8, characterized in that, include: The third selection sub-circuit includes: a third selection transistor; one terminal of the source or drain of the third selection transistor is coupled to the first control power supply, the other terminal is coupled to the second power supply control circuit, and the gate is coupled to the second control sub-circuit for receiving the third selection signal; The fourth selection sub-circuit includes: a fourth selection transistor; one terminal of the source or drain of the fourth selection transistor is coupled to the second control power supply, the other terminal is coupled to the second power supply control circuit, and the gate is coupled to the second control sub-circuit for receiving the fourth selection signal.

10. The amplifier circuit according to claim 1, characterized in that, The amplifier circuit also includes: An isolation circuit is coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase. An offset cancellation circuit is coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the offset cancellation circuit is configured to, during the offset cancellation phase, couple the bit line to the complementary readout node and the complementary bit line to the readout node.

11. The amplifier circuit according to claim 10, characterized in that, The sensing amplification circuit includes: The first P-type transistor has one terminal of its source or drain coupled to the first node, the other terminal coupled to the complementary readout node, and its gate coupled to the readout node. The second P-type transistor has one of its source or drain terminals coupled to the first node, the other terminal coupled to the readout node, and its gate coupled to the complementary readout node. The first N-type transistor has one terminal of its source or drain coupled to the second node, the other terminal coupled to the complementary readout node, and its gate coupled to the bit line. The second N-type transistor has one of its source or drain terminals coupled to the second node, the other terminal coupled to the readout node, and its gate coupled to the complementary bit line; The isolation circuit includes: A first isolation transistor has one terminal of its source or drain coupled to the bit line and the other terminal coupled to the readout node, with its gate used to receive an isolation signal; the first isolation transistor is configured to, during the sensing amplification phase, conduct based on the isolation signal to couple the readout node to the bit line; The second isolation transistor has one terminal of its source or drain coupled to the complementary bit line and the other terminal coupled to the complementary readout node, and its gate is used to receive the isolation signal; the second isolation transistor is configured to, during the sensing amplification phase, conduct based on the isolation signal to couple the complementary readout node to the complementary bit line.

12. The amplifier circuit according to claim 10, characterized in that, The offset cancellation circuit includes: A first offset cancellation transistor has one terminal of its source or drain coupled to the bit line and the other terminal coupled to the complementary readout node, with its gate used to receive an offset cancellation signal; the first offset cancellation transistor is configured to, during the offset cancellation phase, conduct based on the offset cancellation signal to couple the complementary readout node to the bit line. The second offset cancellation transistor has one of its source or drain terminals coupled to the complementary bit line and the other terminal coupled to the readout node, and its gate is used to receive the offset cancellation signal; the second offset cancellation transistor is configured to, during the offset cancellation phase, conduct based on the offset cancellation signal to couple the readout node to the complementary bit line.

13. The amplifier circuit according to claim 1, characterized in that, The amplification circuit further includes: a preprocessing circuit coupled to the readout node and the complementary readout node; During the charging phase, the preprocessing circuit, coupled to at least one of the readout node or the complementary readout node, is configured to precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on a precharge signal. During the equalization phase, the preprocessing circuit, which is simultaneously coupled to the readout node and the complementary readout node, is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal.

14. The amplifier circuit according to claim 13, characterized in that, The preprocessing circuit includes: A charging transistor, with one terminal of its source or drain coupled to the readout node or the complementary readout node, and the other terminal coupled to a node that provides the preset voltage, and its gate used to receive the charging signal; The charging transistor is configured to, during the charging phase, precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on the charging signal being turned on; The equalization transistor has one terminal of its source or drain coupled to the readout node and the other terminal coupled to the complementary readout node, with its gate used to receive the equalization signal. The equalization transistor is configured to, during the equalization phase, synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal being turned on.

15. An amplifier circuit coupled to bit lines and complementary bit lines, characterized in that, include: The sensing amplification circuit includes a readout node, a complementary readout node, a first node, and a second node. During the sensing amplification stage and the offset cancellation stage, the first node is used to receive a high level, and the second node is used to receive a low level. The second power supply control circuit is coupled to the ground node and the second node; The second selection circuit is coupled to the second power control circuit and includes a first control power supply and a second control power supply, wherein the power supply voltage of the first control power supply is different from the power supply voltage of the second control power supply. The second power control circuit is configured to couple the ground node to the second node based on the first control power supply or the second control power supply.

16. The amplifier circuit according to claim 15, characterized in that, The power supply voltage of the first control power supply is higher than that of the second control power supply.

17. The amplifier circuit according to claim 15 or 16, characterized in that, The second selection circuit is further configured to couple the first control power supply to the second power control circuit during the offset elimination phase, and to couple the second control power supply to the second power control circuit during the sensing amplification phase.

18. The amplifier circuit according to claim 15, characterized in that, The amplifier circuit further includes: A first power supply circuit is coupled to the first node and includes a first power supply and a second power supply. The first power supply circuit is configured to couple the first power supply to the first node during the offset elimination phase and to couple the second power supply to the first node during the sensing amplification phase.

19. The amplifier circuit according to claim 18, characterized in that, The first power supply circuit includes: A first power control circuit is coupled to a power node and the first node; the first power control circuit is configured to couple the power node to the first node during the offset cancellation phase and the sensing amplification phase. A first selection circuit, coupled to the power node, includes a first power supply and a second power supply; the first selection circuit is configured to provide the first power supply to the power node during the offset cancellation phase and to provide the second power supply to the power node during the sensing amplification phase.

20. The amplifier circuit according to claim 19, characterized in that, The first power control circuit includes: The first control transistor has one terminal of its source or drain coupled to the power supply node, and the other terminal coupled to the first node. A pull-up control circuit is coupled to the gate of the first control transistor; the pull-up control circuit is configured to turn on the first control transistor during the offset elimination phase and the sensing amplification phase.

21. The amplifier circuit according to claim 19, characterized in that, The first selection circuit includes: The first control sub-circuit is configured to provide a first selection signal or a second selection signal based on a first control command; A first selection sub-circuit is coupled to the first control sub-circuit, the power node, and the first power supply; the first selection sub-circuit is configured to provide the first power supply to the power node based on the first selection signal. A second selection sub-circuit is coupled to the first control sub-circuit, the power node, and the second power supply; the second selection sub-circuit is configured to provide the second power supply to the power node based on the second selection signal.

22. The amplifier circuit according to claim 21, characterized in that, A first power supply circuit is coupled to the first node and includes a first power supply and a second power supply. The first power supply circuit is configured to couple the first power supply to the first node during the offset elimination phase and to couple the second power supply to the first node during the sensing amplification phase.

23. The amplifier circuit according to claim 21, characterized in that, include: The first selection sub-circuit includes: a first selection transistor; one terminal of the source or drain of the first selection transistor is coupled to the first power supply, the other terminal is coupled to the power supply node, and the gate is coupled to the first control sub-circuit for receiving the first selection signal; The second selection sub-circuit includes: a second selection transistor; one terminal of the source or drain of the second selection transistor is coupled to the second power supply, the other terminal is coupled to the power supply node, and the gate is coupled to the first control sub-circuit for receiving the second selection signal.

24. The amplifier circuit according to claim 15, characterized in that, The second power control circuit includes: a second control transistor, one of its source or drain terminals coupled to the second node, the other terminal coupled to the ground node, and its gate coupled to the second selection circuit.

25. The amplifier circuit according to claim 15, characterized in that, The second selection circuit includes: The second control sub-circuit is configured to provide a third selection signal or a fourth selection signal based on the second control command; A third selection sub-circuit is coupled to the second control sub-circuit, the first control power supply, and the second power control circuit; the third selection sub-circuit is configured to provide the first control power supply to the second power control circuit based on the third selection signal. A fourth selection sub-circuit is coupled to the second control sub-circuit, the second control power supply, and the second power control circuit; the fourth selection sub-circuit is configured to provide the second control power supply to the second power control circuit based on the fourth selection signal.

26. The amplifier circuit according to claim 25, characterized in that, include: The third selection sub-circuit includes: a third selection transistor; one terminal of the source or drain of the third selection transistor is coupled to the first control power supply, the other terminal is coupled to the second power supply control circuit, and the gate is coupled to the second control sub-circuit, for receiving the third selection signal; The fourth selection sub-circuit includes: a fourth selection transistor; one terminal of the source or drain of the fourth selection transistor is coupled to the second control power supply, the other terminal is coupled to the second power supply control circuit, and the gate is coupled to the second control sub-circuit, for receiving the fourth selection signal.

27. The amplifier circuit according to claim 15, characterized in that, The amplifier circuit also includes: An isolation circuit is coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the isolation circuit is configured to couple the readout node to the bit line and the complementary readout node to the complementary bit line during the sensing amplification phase. An offset cancellation circuit is coupled to the readout node, the complementary readout node, the bit line, and the complementary bit line; the offset cancellation circuit is configured to, during the offset cancellation phase, couple the bit line to the complementary readout node and the complementary bit line to the readout node.

28. The amplifier circuit according to claim 27, characterized in that, The sensing amplification circuit includes: The first P-type transistor has one terminal of its source or drain coupled to the first node, the other terminal coupled to the complementary readout node, and its gate coupled to the readout node; The second P-type transistor has one terminal of its source or drain coupled to the first node, the other terminal coupled to the readout node, and its gate coupled to the complementary readout node; The first N-type transistor has one terminal of its source or drain coupled to the second node, the other terminal coupled to the complementary readout node, and its gate coupled to the bit line; The second N-type transistor has one terminal of its source or drain coupled to the second node, the other terminal coupled to the readout node, and its gate coupled to the complementary bit line. The isolation circuit includes: A first isolation transistor has one terminal of its source or drain coupled to the bit line and the other terminal coupled to the readout node, with its gate used to receive an isolation signal; the first isolation transistor is configured to, during the sensing amplification phase, conduct based on the isolation signal to couple the readout node to the bit line; The second isolation transistor has one terminal of its source or drain coupled to the complementary bit line and the other terminal coupled to the complementary readout node, with its gate used to receive the isolation signal; the second isolation transistor is configured to, during the sensing amplification phase, conduct based on the isolation signal to couple the complementary readout node to the complementary bit line.

29. The amplifier circuit according to claim 27, characterized in that, The offset cancellation circuit includes: A first offset cancellation transistor has one terminal of its source or drain coupled to the bit line and the other terminal coupled to the complementary readout node, with its gate used to receive an offset cancellation signal; the first offset cancellation transistor is configured to, during the offset cancellation phase, conduct based on the offset cancellation signal to couple the complementary readout node to the bit line. A second offset cancellation transistor has one terminal of its source or drain coupled to the complementary bit line and the other terminal coupled to the readout node, with its gate used to receive the offset cancellation signal; the second offset cancellation transistor is configured to, during the offset cancellation phase, conduct based on the offset cancellation signal to couple the readout node to the complementary bit line.

30. The amplifier circuit according to claim 15, characterized in that, The amplification circuit further includes: a preprocessing circuit coupled to the readout node and the complementary readout node; During the charging phase, the preprocessing circuit, coupled to at least one of the readout node or the complementary readout node, is configured to precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on a precharge signal. During the equalization phase, the preprocessing circuit, which simultaneously couples the readout node and the complementary readout node, is configured to synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal.

31. The amplifier circuit according to claim 30, characterized in that, The preprocessing circuit includes: A charging transistor, with one terminal of its source or drain coupled to the readout node or the complementary readout node, and the other terminal coupled to a node that provides the preset voltage, and a gate for receiving the charging signal; The charging transistor is configured to, during the charging phase, precharge the bit line, the complementary bit line, the readout node, and the complementary readout node to a preset voltage based on the charging signal being turned on; The equalization transistor has one terminal of its source or drain coupled to the readout node and the other terminal coupled to the complementary readout node, with its gate used to receive the equalization signal. The equalization transistor is configured to, during the equalization phase, synchronize the node voltage of the readout node and the node voltage of the complementary readout node based on the equalization signal being turned on.

32. A control method applied to an amplifier circuit, characterized in that, include: The amplification circuit includes: a sensing amplification circuit; the sensing amplification circuit includes a readout node, a complementary readout node, a first node, and a second node. In the sensing amplification stage and the offset cancellation stage, the first node is used to receive a high-level signal, and the second node is used to receive a low-level signal. During the offset elimination phase, a high-level signal is provided to the first node based on the first power supply; During the sensing amplification phase, a high-level signal is provided to the first node based on the second power supply.

33. The control method according to claim 32, characterized in that, Also includes: During the offset elimination phase, based on the first selection signal, the first power supply is controlled to be coupled to the first control transistor; During the sensing amplification phase, based on the second selection signal, the second power supply is controlled to be coupled to the first control transistor; During the offset elimination phase and the sensing amplification phase, the first control transistor is turned on based on the pull-up control signal, and the first power supply or the second power supply is coupled to the first node to provide a high-level signal to the first node.

34. The control method according to claim 32, characterized in that, Also includes: Based on a first control power supply or a second control power supply, the control ground node is coupled to the second node, and the power supply voltage of the first control power supply is different from the power supply voltage of the second control power supply.

35. The control method according to claim 34, characterized in that, Also includes: During the offset elimination phase, the second node is coupled to the ground node based on the first control power supply. During the sensing amplification phase, the second node is coupled to the ground node based on the second control power supply.

36. The control method according to claim 35, characterized in that, The power supply voltage of the first control power supply is higher than that of the second control power supply.

37. The control method according to claim 35, characterized in that, During the offset elimination phase, based on the third selection signal, the first control power supply is coupled to the second control transistor. During the sensing amplification phase, based on the fourth selection signal, the second control power supply is controlled to be coupled to the second control transistor; During the offset elimination phase and the sensing amplification phase, the second control transistor is turned on based on the pull-down control signal provided by the first control power supply or the second control power supply, and the ground node is coupled to the second node to provide a low-level signal to the second node.

38. The control method according to claim 32, characterized in that, The control method further includes: During the charging phase, isolation signals and offset cancellation signals are provided to couple the bit lines, complementary bit lines, readout nodes and complementary readout nodes to each other, and charging signals are provided to precharge the bit lines, complementary bit lines, readout nodes and complementary readout nodes to a preset voltage; During the offset cancellation phase, the offset cancellation signal is provided to eliminate offset noise in the amplifier circuit; During the charge sharing phase, the word line WL is opened to share the charge stored in the corresponding memory cell to the bit line or the complementary bit line; During the sensing amplification phase, voltage signals from the power supply node and the ground node are provided to amplify the voltage difference between the bit line and the complementary bit line.

39. A control method applied to an amplifier circuit, characterized in that, include: The amplification circuit includes: a sensing amplification circuit; the sensing amplification circuit includes a readout node, a complementary readout node, a first node, and a second node. In the sensing amplification stage and the offset cancellation stage, the first node is used to receive a high-level signal, and the second node is used to receive a low-level signal. Based on a first control power supply or a second control power supply, the control ground node is coupled to the second node, and the power supply voltage of the first control power supply is different from the power supply voltage of the second control power supply.

40. The control method according to claim 39, characterized in that, Also includes: During the offset elimination phase, the second node is coupled to the ground node based on the first control power supply. During the sensing amplification phase, the second node is coupled to the ground node based on the second control power supply.

41. The control method according to claim 40, characterized in that, The power supply voltage of the first control power supply is higher than that of the second control power supply.

42. The control method according to claim 40, characterized in that, During the offset elimination phase, based on the third selection signal, the first control power supply is coupled to the second control transistor. During the sensing amplification phase, based on the fourth selection signal, the second control power supply is controlled to be coupled to the second control transistor; During the offset elimination phase and the sensing amplification phase, the second control transistor is turned on based on the pull-down control signal provided by the first control power supply or the second control power supply, and the ground node is coupled to the second node to provide a low-level signal to the second node.

43. The control method according to claim 39, characterized in that, Also includes: During the offset elimination phase, a high-level signal is provided to the first node based on the first power supply; During the sensing amplification phase, a high-level signal is provided to the first node based on the second power supply.

44. The control method according to claim 43, characterized in that, Also includes: During the offset elimination phase, based on the first selection signal, the first power supply is controlled to be coupled to the first control transistor; During the sensing amplification phase, based on the second selection signal, the second power supply is controlled to be coupled to the first control transistor; During the offset elimination phase and the sensing amplification phase, the first control transistor is turned on based on the pull-up control signal, and the first power supply or the second power supply is coupled to the first node to provide a high-level signal to the first node.

45. The control method according to claim 39, characterized in that, The control method further includes: During the charging phase, isolation signals and offset cancellation signals are provided to couple the bit lines, complementary bit lines, readout nodes and complementary readout nodes to each other, and charging signals are provided to precharge the bit lines, complementary bit lines, readout nodes and complementary readout nodes to a preset voltage; During the offset cancellation phase, the offset cancellation signal is provided to eliminate offset noise in the amplifier circuit; During the charge sharing phase, the word line WL is opened to share the charge stored in the corresponding memory cell to the bit line or the complementary bit line; During the sensing amplification phase, voltage signals from the power supply node and the ground node are provided to amplify the voltage difference between the bit line and the complementary bit line.

46. ​​A memory, characterized in that, The amplifier circuit includes any one of claims 1 to 31, and the amplifier circuit is configured to perform data read and write operations.

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