Memory device, method of operating a memory device, and memory system

Abstract

A memory device, a method of operating the memory device, and a memory system are provided. The memory device includes: a clock divider that receives a clock signal from a host and divides the clock signal to generate at least two internal clock signals; an internal clock selector that receives the at least two internal clock signals from the clock divider and selects one of the at least two internal clock signals as a target internal clock signal for sampling either a high or low level of a chip select signal; and a sampler that receives the chip select signal from the host, receives the target internal clock signal from the internal clock selector, and samples the chip select signal using the target internal clock signal.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2025-0047624, filed on April 11, 2025, and Korean Patent Application No. 10-2025-0138953, filed on September 25, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to memory devices, methods of operating memory devices, and memory systems. Background Technology

[0003] Mobile devices (such as smartphones, tablet PCs, digital cameras, MP3 players, PDAs, and wearable devices) are widely used. In line with mobile technology trends, semiconductor memory devices for use in mobile devices are being developed for high integration, enhanced performance, and low power consumption. As high-performance memory devices achieve faster operating speeds, the data exchanged between application processors and memory devices (e.g., DRAM devices) requires higher signal quality and reliability. To ensure data reliability, optimizing the clock timing of data or signals transmitted through the interface is important, and training can be performed to achieve the desired level of data reliability. Summary of the Invention

[0004] In some cases, chip select signal training can be used to optimize chip select and clock signals transmitted between the host and memory device. However, when the region where sampling failures are detected during the sampling processing of the chip select signal is too narrow, sampling failures may be skipped without being detected. Embodiments of this disclosure provide a memory device capable of efficiently performing chip select signal training by expanding the region where sampling failures are detected.

[0005] One aspect of the present invention provides a memory device, the memory device comprising: a clock divider configured to receive a clock signal from a host, divide the clock signal, and generate at least two internal clock signals; an internal clock selector configured to receive the at least two internal clock signals from the clock divider and select one of the at least two internal clock signals as a target internal clock signal; and a sampler configured to receive a chip selection signal from a host, receive the target internal clock signal from the internal clock selector, and sample the chip selection signal using the target internal clock signal.

[0006] Another aspect of this disclosure provides a method for operating a memory device. The method may include: during a training mode relating to a chip select signal, dividing a clock signal to generate at least two internal clock signals; selecting one of the at least two internal clock signals as a target internal clock signal; sampling the chip select signal using the target internal clock signal; and adjusting a delay time to be applied to the chip select signal based on the result of sampling the chip select signal.

[0007] Another aspect of the present invention provides a memory system, the memory system comprising: a memory device; and a host configured to provide a clock signal and a chip select signal to the memory device during training with respect to a chip select signal. The memory device may include: a clock divider configured to divide a clock signal received from the host and generate at least two internal clock signals; an internal clock selector configured to receive the at least two internal clock signals from the clock divider and select one of the at least two internal clock signals as a target internal clock signal; and a sampler configured to receive the chip select signal from the host, receive the target internal clock signal from the internal clock selector, and sample the chip select signal using the target internal clock signal.

[0008] According to the memory device of this disclosure, the expansion of the region where sampling failure is detected is realized, and therefore the chip selection signal training is effectively performed. Attached Figure Description

[0009] The above and other objects and features of this disclosure will become clear from a detailed description of specific embodiments with reference to the accompanying drawings.

[0010] Figure 1 This is a block diagram schematically illustrating an example memory system according to an embodiment of the present disclosure.

[0011] Figure 2A , Figure 2B , Figure 2C and Figure 2D This is a diagram illustrating a sampling operation according to an exemplary embodiment of the present disclosure and a failure detection region where sampling failures are detected during a CS training operation.

[0012] Figure 3A , Figure 3B , Figure 3C and Figure 3D This is a diagram illustrating the sampling operation based on the comparison example and the failure detection region where sampling failures were detected during the CS training operation.

[0013] Figure 4 This is a flowchart illustrating an example operation of performing CS training according to an embodiment of the present disclosure.

[0014] Figure 5 This is a block diagram schematically illustrating an example memory system according to an embodiment of the present disclosure.

[0015] Figure 6 This is a block diagram illustrating an example training circuit according to an embodiment of the present disclosure.

[0016] Figure 7 This is a block diagram illustrating an example sampling circuit according to an embodiment of the present disclosure.

[0017] Figure 8 It is shown Figure 7 A diagram illustrating an example operation of the sampling circuit to determine an even-numbered internal clock signal.

[0018] Figure 9A This is a diagram illustrating an example CS training operation according to an embodiment of the present disclosure.

[0019] Figure 9B This is a diagram illustrating the CS training operation based on the comparison example.

[0020] Figure 10 This is a flowchart illustrating an example operation of performing CS training according to an embodiment of the present disclosure.

[0021] Figure 11 This is a block diagram schematically illustrating an example memory system according to an embodiment of the present disclosure.

[0022] Figure 12 This is a diagram illustrating an example CS training operation according to an embodiment of the present disclosure.

[0023] Figure 13 This is a flowchart illustrating an example operation of performing CS training according to an embodiment of the present disclosure.

[0024] Figure 14 This is a block diagram schematically illustrating an example memory system according to an embodiment of the present disclosure.

[0025] Figure 15 This is a block diagram illustrating an example memory device according to an embodiment of the present disclosure. Detailed Implementation

[0026] The embodiments of this disclosure will now be described in detail and clearly to the extent that they can be readily implemented by those skilled in the art.

[0027] Figure 1 This is a block diagram schematically illustrating a memory system 1000 according to an embodiment of the present disclosure.

[0028] The chip select signal training (hereinafter referred to as CS training) according to embodiments of this disclosure can divide a clock signal into at least two internal clock signals, and a sampling operation can be performed on the chip select signal using one of the at least two internal clock signals. Therefore, regions where sampling failures (also referred to herein as sampling failures) are detected can be extended, and thus CS training can be performed efficiently.

[0029] For more details, please refer to Figure 1 The memory system 1000 may include a host 100 and a memory device 200.

[0030] Host 100 can perform access operations to write data DATA to memory device 200 or read data DATA stored in memory device 200. Host 100 can generate a clock signal CK, a chip select signal CS, a command CMD, and / or an address ADDR to write data DATA to memory device 200 or read data DATA stored in memory device 200. For example, host 100 can be at least one of a chipset, a system-on-a-chip (SoC) (such as a mobile application processor (AP) (hereinafter referred to as AP)), a central processing unit (CPU), a graphics processing unit (GPU), and a test device for controlling memory device 200.

[0031] Host 100 can perform CS training on memory device 200 under specific conditions (such as startup or initialization of memory device 200). For example, host 100 may include training circuitry 110.

[0032] Training circuit 110 can perform CS training on memory device 200. In this embodiment, CS training can refer to training that aligns the center of the chip select signal CS provided from host 100 to memory device 200 with the rising or falling edge of clock signal CK. Host 100 can then correctly send command CMD and / or address ADDR to memory device 200 via CS training.

[0033] During CS training, training circuit 110 provides a clock signal CK along with the chip select signal CS to memory device 200. The chip select signal CS can then be sampled using an internal clock signal divided from the clock signal CK in memory device 200, and training circuit 110 can receive the corresponding sampling result from memory device 200. Based on the sampling result, training circuit 110 can adjust the delay time applied to the chip select signal CS. For example, training circuit 110 can push or pull the chip select signal CS to align the center of the chip select signal CS with the rising or falling edge of the internal clock signal.

[0034] The memory device 200 can perform read or write operations under the control of the host 100. For example, during a read operation, the memory device 200 can receive a clock signal CK, a read operation request command CMD, and an address ADDR from the host 100. The memory device 200 can read the requested data DATA and can send the read data to the host 100. For example, during a write operation, the memory device 200 can receive data DATA, a clock signal CK, a write operation request command CMD, and an address ADDR from the host 100. The memory device 200 can store the data DATA in the requested location.

[0035] Memory device 200 may include a memory cell array (MCA) for storing data. For example, the memory cell array (MCA) of memory device 200 may be implemented to include volatile memory (such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.). For example, the memory cell array (MCA) of memory device 200 may be implemented to include non-volatile memory (such as electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic RAM (MRAM), phase-change RAM (PRAM), resistive RAM (RRAM), etc.). For example, a portion of the memory cell array (MCA) of memory device 200 may be implemented to include volatile memory, and another portion of the memory cell array (MCA) may be implemented to include non-volatile memory. In this disclosure, it is assumed that the memory cell array (MCA) of memory device 200 is a DRAM chip including DRAM.

[0036] During CS training, memory device 200 can receive a chip select signal CS and a clock signal CK from host 100. Memory device 200 can perform a sampling operation on the chip select signal CS based on the clock signal CK.

[0037] Specifically, when performing CS training according to embodiments of this disclosure, the memory device 200 may divide the clock signal CK to generate at least two internal clock signals, and may use one of the at least two internal clock signals to perform a sampling operation on the chip select signal CS. For example, the memory device 200 may include a sampling circuit 210, and the sampling circuit 210 may include a clock divider 211, an internal clock selector 212, and a sampler 213.

[0038] Clock divider 211 can receive a clock signal CK from training circuit 110 and can divide the clock signal CK to generate at least two internal clock signals. For example, clock divider 211 can divide the clock signal CK by 2 pairs to generate a first internal clock signal ICK_1 and a second internal clock signal ICK_2. However, this is merely an example. In other embodiments, clock divider 211 can divide the clock signal CK by 2N (where N is a natural number). As an example, clock divider 211 can divide the clock signal CK by 4 pairs to generate four internal clock signals, or it can divide the clock signal CK by 8 pairs to generate eight internal clock signals.

[0039] The internal clock selector 212 can receive at least two internal clock signals from the clock divider 211, and can select one of the internal clock signals as the signal used to sample the chip select signal CS. For example, the internal clock selector 212 can receive a first internal clock signal ICK_1 and a second internal clock signal ICK_2, and can select one of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as the signal used to sample the chip select signal CS.

[0040] In one embodiment, the internal clock selector 212 can receive a first internal clock signal ICK_1 and a second internal clock signal ICK_2, and can select one of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as a signal for sampling the high level of the chip select signal CS. In this case, the selected internal clock signal can be provided to the sampler 213, and the unselected internal clock signal can be excluded from being provided to the sampler 213.

[0041] In one embodiment, the internal clock selector 212 can receive a first internal clock signal ICK_1 and a second internal clock signal ICK_2, and can select one of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as the signal for sampling the low level of the chip select signal CS. In this case, the selected internal clock signal can be provided to the sampler 213, and the unselected internal clock signal can be excluded from being provided to the sampler 213.

[0042] In one embodiment, the internal clock selector 212 may receive a first internal clock signal ICK_1 and a second internal clock signal ICK_2, and may select one of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as a signal for sampling a high level of the chip select signal CS, and may select the other internal clock signal as a signal for sampling a low level of the chip select signal CS. In this case, the sampler 213 may include a first sampler and a second sampler, and the internal clock signal selected for sampling a high level may be provided to the first sampler, and the internal clock signal selected for sampling a low level may be provided to the second sampler.

[0043] Sampler 213 can receive a chip select signal CS from training circuit 110 and an internal clock signal from internal clock selector 212. Sampler 213 can perform a sampling operation on chip select signal CS based on internal clock signal. The sampling result obtained by sampler 213 can be sent to training circuit 110.

[0044] As described above, during CS training according to embodiments of the present disclosure, the memory device 200 can divide the clock signal into at least two internal clock signals, and can use one of the at least two internal clock signals to perform a sampling operation on the chip selection signal. Therefore, regions where sampling failures are detected can be expanded, and thus, CS training can be performed efficiently.

[0045] Figures 2A to 2D This is a diagram illustrating a sampling operation according to an embodiment of the present disclosure and a failure detection region where sampling failures are detected during a CS training operation. In detail, Figures 2A to 2C The sampling operation of the chip select signal CS with different delay times is shown as a representative example of the present disclosure. Figure 2D The failure detection area of ​​this disclosure is shown.

[0046] For ease of explanation, Figures 2A to 2D In this context, it is assumed that the clock signal is divided into two internal clock signals, ICK_1 and ICK_2, and the high level of the chip select signal CS is sampled using the rising edge of the first internal clock signal, ICK_1, of the two internal clock signals, ICK_1 and ICK_2.

[0047] Reference Figure 1 and Figures 2A to 2DClock divider 211 can receive differential clock signals CK_t and CK_c as clock signal CK. Clock divider 211 can divide the differential clock signals CK_t and CK_c according to step (2), thereby generating a first internal clock signal ICK_1 and a second internal clock signal ICK_2. In this case, the frequency of each of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 can be half (1 / 2) of the frequency of the differential clock signals CK_t and CK_c.

[0048] The internal clock selector 212 can select the first internal clock signal ICK_1 as the signal for sampling the high level of the chip select signal CS from the first internal clock signal ICK_1 and the second internal clock signal ICK_2.

[0049] Sampler 213 can receive a chip select signal CS and a first internal clock signal ICK_1. Sampler 213 can sample the chip select signal CS at the rising edge of the first internal clock signal ICK_1. In this case, when the chip select signal CS is high at the rising edge of the first internal clock signal ICK_1, the sampling result can be "pass" (i.e., successful sampling or successful sampling). When the chip select signal CS is low at the rising edge of the first internal clock signal ICK_1 or is in an uncertain region, the sampling result can be "failure" (i.e., sampling failure).

[0050] As an example, refer to Figure 2A In the first case, CASE 1, the rising edge of the first internal clock signal ICK_1 corresponds to time point 0 (t0), time point 2 (t2), time point 4 (t4), and time point n (tn). The chip select signal CS is high at time point 0 (t0), time point 2 (t2), time point 4 (t4), and time point n (tn). Therefore, the sampling results in the first case can all be "pass".

[0051] As an example, refer to Figure 2B In the second case, CASE 2, the delay time of the chip select signal CS is... Figure 2A The delay time of the chip select signal CS differs in the two cases. At time points 0 (t0), 2 (t2), 4 (t4), and n (tn), corresponding to the rising edge of the first internal clock signal ICK_1, the chip select signal CS is at a low level. Therefore, the sampling results in the second case can all be "failures".

[0052] As an example, refer to Figure 2C The third case, CASE 3, involves the delay time applied to the chip select signal CS compared to the delay time applied to... Figure 2A and Figure 2BThe delay time of the chip select signal CS differs in the following cases. At time points 0 (t0), 2 (t2), 4 (t4), and n (tn) corresponding to the rising edge of the first internal clock signal ICK_1, the chip select signal CS transitions from high to low. In other words, time points 0 (t0), 2 (t2), 4 (t4), and n (tn) corresponding to the rising edge of the first internal clock signal ICK_1 correspond to uncertain regions where the sampling results are difficult to determine. Therefore, the sampling results in the third case can all be "failures".

[0053] like Figures 2A to 2C As described in the first to third cases, the sampling operation of this disclosure can output "failure" as a sampling result not only when the rising edge of the first internal clock signal ICK_1 corresponds to the uncertain region of the chip select signal CS, but also when the rising edge of the first internal clock signal ICK_1 corresponds to the low level of the chip select signal CS.

[0054] Therefore, as Figure 2D As shown, the failure detection region may have a time interval corresponding to "Tf1". Here, the failure detection region may represent the region that outputs "failure" as a sampling result when the chip select signal CS is sampled using the internal clock signal used for sampling operations (i.e., the first internal clock signal ICK_1). For example, "Tf1" may be a time interval corresponding to 2tCK.

[0055] In addition, such as Figure 2D As shown, the detection area can have a time interval corresponding to "Tp1". Here, the detection area can represent the area that outputs "pass" as the sampling result when the chip selection signal CS is sampled using the internal clock signal used for sampling operation (i.e., the first internal clock signal ICK_1). Refer to the following... Figures 3A to 3D The failure detection area described may be larger than the failure detection area of ​​the comparison example.

[0056] Figures 3A to 3D This is a diagram illustrating the sampling operation based on the comparison example and the failure detection region detected during the CS training operation. In detail, Figures 3A to 3C The sampling operation is shown as a representative example, comparing chip select signals CS with different delay times. Figure 3D The failure detection area is shown in the comparison example.

[0057] For ease of explanation, and in conjunction with Figures 2A to 2D In the same manner, it is assumed that the clock signal is divided into two internal clock signals, ICK_1 and ICK_2. Additionally, it is assumed that... Figure 3A The delay time of the chip select signal CS in the middle and Figure 2A The delay time of the chip select signal CS is the same in all cases. Figure 3B The delay time of the chip select signal CS in the middle and Figure 2B The delay time of the chip select signal CS in the two chips is the same, and Figure 3C The delay time of the chip select signal CS in the middle and Figure 2C The delay time of the chip select signal CS is the same. However, compared with... Figures 2A to 2D Unlike the previous example, in the comparison example, it is assumed that the high level of the chip select signal CS is sampled using not only the rising edge of the first internal clock signal ICK_1 but also the rising edge of the second internal clock signal ICK_2.

[0058] First, refer to Figure 3A In the first case (CASE 1), the rising edge of the first internal clock signal ICK_1 corresponds to time point 0 (t0), time point 2 (t2), time point 4 (t4), and time point n (tn). The chip select signal CS is high at time point 0 (t0), time point 2 (t2), time point 4 (t4), and time point n (tn). Therefore, the sampling results in the first case can all be "pass".

[0059] Reference Figure 3B In the second case (CASE 2), the chip select signal CS is high at the first time point t1, the third time point t3, and the (n-1)th time point tn-1, corresponding to the rising edge of the second internal clock signal ICK_2. Therefore, the sampling results in the second case can all be "pass".

[0060] Reference Figure 3C In the third case (CASE 3), at time points 0 (t0), 2 (t2), 4 (t4), and n (tn) corresponding to the rising edge of the first internal clock signal ICK_1, the chip select signal CS changes from high to low. Additionally, at time points 1 (t1), 3 (t3), and (n-1) (tn-1) corresponding to the rising edge of the second internal clock signal ICK_2, the chip select signal CS changes from low to high. That is, all of the time points 0 (t0), 2 (t2), 4 (t4), and n (tn) corresponding to the rising edge of the first internal clock signal ICK_1, and the time points 1 (t1), 3 (t3), and (n-1) (tn-1) corresponding to the rising edge of the second internal clock signal ICK_2, correspond to the uncertain region. Therefore, the sampling results in the third case can all be "failures".

[0061] like Figures 3A to 3CAs described in the case, the sampling operation of the comparative example only outputs "failure" as the sampling result in the third case, in which the rising edge of the first internal clock signal ICK_1 and the rising edge of the second internal clock signal ICK_2 both correspond to the uncertain region.

[0062] Therefore, as Figure 3D As shown, the failure detection region in the comparison example may have a time interval corresponding to "Tf2". This can be a very short time compared to "Tf1", which is... Figure 2D The failure detection area of ​​the embodiments of this disclosure is shown.

[0063] In addition, such as Figure 3D As shown, the detection area in the comparison example may have a time interval corresponding to "Tp2+Tp3". This can be a very long time compared to "Tp1", which is... Figure 2D The embodiment of this disclosure shown is a detection area.

[0064] When the failure detection region is as short as in the comparative example, CS training may not be performed efficiently. In particular, when the delay time applied to the chip select signal CS is longer than the failure detection region, the failure detection region may go undetected and be skipped. Therefore, in the case of the comparative example, in order to prevent skipping the failure detection region, the delay time applied to the chip select signal CS needs to be set to a very short interval, and thus, the time required to perform CS training can increase.

[0065] In comparison, such as Figures 2A to 2D As shown, the CS training according to embodiments of this disclosure can divide the clock signals CK_t and CK_c into two internal clock signals ICK_1 and ICK_2, and the first internal clock signal ICK_1 can be used to perform a sampling operation on the chip selection signal CS. Therefore, regions where sampling failures are detected can be extended, and thus, CS training can be performed efficiently.

[0066] Figure 4 This is a flowchart illustrating the operation of performing CS training according to an embodiment of the present disclosure.

[0067] In operation S100, memory system 1000 (refer to...) Figure 1 You can enter CS training mode.

[0068] For example, memory system 1000 (reference) Figure 1 It can enter CS training mode under specific conditions (such as startup or initialization).

[0069] In operation S200, the clock signal can be divided to generate at least two internal clock signals.

[0070] For example, clock divider 211 (refer to...) Figure 1 The clock signal CK can be divided according to step (2) to generate two internal clock signals ICK_1 and ICK_2. In this case, the frequency of each of the two internal clock signals ICK_1 and ICK_2 can be half (1 / 2) of the frequency of the clock signal CK.

[0071] In operation of S300, a target internal clock signal for sampling the high level of the chip select signal can be selected from at least two internal clock signals.

[0072] For example, internal clock selector 212 (refer to...) Figure 1 The first internal clock signal ICK_1 can be selected from two internal clock signals ICK_1 and ICK_2 as the target internal clock signal for sampling the high level of the chip select signal CS.

[0073] In operating the S400, the target's internal clock signal can be used to perform the sampling operation.

[0074] For example, sampler 213 (refer to) Figure 1 The chip select signal CS can be sampled at the rising edge of the first internal clock signal ICK_1. When the chip select signal CS is high at the rising edge of the first internal clock signal ICK_1, the sampling result can be "pass". When the chip select signal CS is low or in the uncertain region at the rising edge of the first internal clock signal ICK_1, the sampling result can be "failure".

[0075] In operating the S500, the delay time of the chip selection signal can be adjusted based on the sampling results.

[0076] For example, training circuit 110 (refer to...) Figure 1 The delay time of the chip selection signal CS can be adjusted based on the sampling results of sampler 213. For example, training circuit 110 can push or pull the chip selection signal CS to align the center of the chip selection signal CS with the rising edge of the first internal clock signal ICK_1.

[0077] As described above, the CS training operation according to embodiments of this disclosure can divide the clock signal into at least two internal clock signals, and one of the at least two internal clock signals can be used to perform a sampling operation on the chip selection signal. Therefore, regions where sampling failures are detected can be extended, and thus, CS training can be performed efficiently.

[0078] Figure 5This is a block diagram schematically showing a memory system 2000 according to an embodiment of the present disclosure. Figure 5 The memory system 2000 is similar to Figure 1 The memory system 1000. Therefore, in Figure 5 In the figures, the same or similar reference numerals indicate Figure 1 The same or similar elements will be omitted, and therefore detailed descriptions of the same or similar elements will be omitted.

[0079] Reference Figure 5 The memory system 2000 may include a host 100A and a memory device 200A. The host 100A may include a training circuit 110, and the memory device 200A may include a sampling circuit 210 and a memory cell array (MCA). The sampling circuit 210 may include a clock divider 211, an internal clock selector 212, a sampler 213, and a clock synchronizer 214.

[0080] Clock synchronizer 214 can receive a chip select signal CS from training circuit 110 and at least two internal clock signals from clock divider 211. Clock synchronizer 214 can determine the even-numbered edges among the edges of the at least two internal clock signals based on the chip select signal CS. In one example, clock synchronizer 214 can classify the edges of the at least two internal clock signals into even-numbered and odd-numbered edges. For example, clock synchronizer 214 can classify the edges of the at least two internal clock signals into even-numbered and odd-numbered edges based on synchronization information between the chip select signal CS and the internal clock signals.

[0081] As an example, even-numbered edges can be defined as edges used as references for sending the command CMD. For instance, it can be predetermined that the command CMD will be sent from the host 100A to the memory device 200A only at even-numbered edges. In this case, it can be predetermined that commands sent at odd-numbered edges are invalid commands.

[0082] In one implementation, clock synchronizer 214 may determine the even-numbered edges among the edges of at least two internal clock signals based on synchronization information between the chip select signal CS and at least two internal clock signals.

[0083] For example, clock synchronizer 214 may determine an even-numbered edge based on the alignment between the rising edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 and the high level of the chip select signal CS. That is, clock synchronizer 214 may determine an even-numbered edge as the rising edge of the rising edge of one of the first internal clock signals ICK_1 and ICK_2 that is aligned with the high level of the chip select signal CS. When the first internal clock signal ICK_1 of the first internal clock signal ICK_1 and the high level of the chip select signal CS are aligned consecutively a predetermined number of times, clock synchronizer 214 may determine the rising edge of the first internal clock signal ICK_1 as an even-numbered edge. However, this is merely an example, and this disclosure is not limited thereto or thereby restricted.

[0084] According to the implementation, the clock synchronizer 214 can determine the even-numbered edges based on the alignment between the falling edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 and the high level of the chip select signal CS. That is, the clock synchronizer 214 can determine the falling edge of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 that is aligned with the high level of the chip select signal CS as the even-numbered edge.

[0085] According to the implementation, the clock synchronizer 214 can determine the even-numbered edges based on the alignment between the rising edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 and the low level of the chip select signal CS.

[0086] According to the implementation, the clock synchronizer 214 can determine the even-numbered edges based on the alignment between the falling edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 and the low level of the chip select signal CS.

[0087] Clock synchronizer 214 can provide synchronization information SYNC_INF about even-numbered edges to internal clock selector 212.

[0088] The internal clock selector 212 can receive synchronization information SYNC_INF regarding even-numbered edges from the clock synchronizer 214. Based on the synchronization information SYNC_INF regarding even-numbered edges, the internal clock selector 212 can identify internal clock signals with even-numbered edges from the first internal clock signal ICK_1 and the second internal clock signal ICK_2, and can determine the identified internal clock signals as even-numbered internal clock signals. In this case, the internal clock selector 212 can determine internal clock signals without even-numbered edges as odd-numbered internal clock signals.

[0089] In one embodiment, the internal clock selector 212 can select an even number of internal clock signals from the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as the signal for sampling the high level of the chip select signal CS.

[0090] In one embodiment, the internal clock selector 212 can select an even number of internal clock signals from the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as the signal for sampling the low level of the chip select signal CS.

[0091] In one embodiment, the internal clock selector 212 can select an even number of internal clock signals from the first internal clock signal ICK_1 and the second internal clock signal ICK_2 as signals for sampling the high level of the chip select signal CS, and can select an odd number of internal clock signals as signals for sampling the low level of the chip select signal CS.

[0092] As described above, the sampling circuit 210 may include a clock synchronizer 214, which provides synchronization information SYNC_INF regarding even-numbered edges to the internal clock selector 212. The internal clock selector 212 can determine the internal clock signal used to sample the chip select signal CS from the first internal clock signal ICK_1 and the second internal clock signal ICK_2 based on the synchronization information SYNC_INF regarding even-numbered edges. Therefore, during CS training, regions where sampling failures are detected can be expanded, and thus, CS training can be performed efficiently.

[0093] exist Figure 5 In this context, even-numbered edges are defined as edges used as references for sending the command CMD. However, this is merely an example, and the present disclosure is not limited thereto or thereby. According to an embodiment, it may be predetermined that the command CMD will be sent from the host 100A to the memory device 200A only at odd-numbered edges. In this case, the clock synchronizer 214 may determine the odd-numbered edge among the edges of at least two internal clock signals based on the chip select signal CS. In this case, an odd-numbered internal clock signal including the odd-numbered edge may be selected as the internal clock signal for sampling the high level of the chip select signal CS.

[0094] Figure 6 This is a block diagram showing the training circuit 110 according to an embodiment of the present disclosure in more detail. Figure 6 The training circuit 110 can correspond to Figure 5 The training circuit 110.

[0095] During CS training, training circuit 110 can provide chip select signal CS and clock signal CK to memory device 200A (see reference). Figure 5 Furthermore, during CS training, the memory device 200A can provide the training circuit 110 with sampled data SD, including the sampling results.

[0096] When the chip select signal CS is successfully sampled by the memory device 200A, the command / address CMD / ADDR can be normally sent to the memory device 200A.

[0097] On the other hand, when the chip select signal CS is not successfully sampled by the memory device 200A, the command / address CMD / ADDR may not be able to be sent to the memory device 200A normally.

[0098] Reference Figure 6 The training circuit 110 may include a training controller 111, a timing controller 112, a clock generator 113, a delay chip select signal generator 114, a chip select signal generator 115, a chip select signal output driver 116, a clock output driver 117, and an input driver 118. In the following text, the delay chip select signal generator 114 will be referred to as the delay CS generator 114, the chip select signal generator 115 will be referred to as the CS generator 115, and the chip select signal output driver 116 will be referred to as the CS output driver 116.

[0099] The training controller 111 can receive sampled data SD from the memory device 200A and determine the sampling result. Based on the sampling result, the training controller 111 can set the delay time to be applied to the chip select signal CS.

[0100] For example, when the sampling result is "pass," the training controller 111 can set a delay time to be applied to the chip select signal CS, causing the chip select signal CS to be pushed. In this case, the chip select signal CS can be pushed by a first delay time based on the sampling pass point. This will be referred to below. Figure 9A The first and second steps are described in more detail. However, this is merely an example, and according to the implementation, the chip select signal CS may be pulled by a first delay time based on the sampling pass point.

[0101] For example, when the sampling result is "failure," the training controller 111 can set a delay time to be applied to the chip select signal CS such that the edge of the internal clock signal is aligned with the center of the high level of the chip select signal CS. In this case, the chip select signal CS can be pulled by a second delay time based on the sampling failure point. The second delay time can be set based on the period of the internal clock signal. This will be referred to below. Figure 9A The second and third steps are described in more detail. However, this is merely an example, and according to the implementation, the chip select signal CS may be pushed by a second delay time based on the sampling failure point.

[0102] The training controller 111 can provide the timing controller 112 with a delay control signal CTRL_DT that includes information about the delay time.

[0103] The timing controller 112 can receive a delay control signal CTRL_DT from the training controller 111 and a clock signal CK from the clock generator 113. The timing controller 112 can generate a delayed clock signal DCK in response to the delay control signal CTRL_DT.

[0104] Clock generator 113 can generate a clock signal CK. Clock generator 113 can provide the clock signal CK to each of timing controller 112 and clock output driver 117.

[0105] The delayed CS generator 114 can receive a delayed clock signal DCK from the timing controller 112 and a chip select signal mode CSP from the CS generator 115. The delayed CS generator 114 can synchronize the chip select signal mode CSP with the delayed clock signal DCK to generate the chip select signal CS.

[0106] The CS generator 115 can generate the chip select signal pattern CSP to generate the chip select signal CS.

[0107] The CS output driver 116 can receive the chip select signal CS from the delayed CS generator 114 and can provide the chip select signal CS to the memory device 200A via the host CS pad (or solder pad) CS_h.

[0108] The clock output driver 117 can receive the clock signal CK from the clock generator 113 and can provide the clock signal CK to the memory device 200A via the host clock pad CK_h.

[0109] The input driver 118 can receive sampled data SD from the memory device 200A via the host data pad DQ_h, and can provide the sampled data SD to the training controller 111.

[0110] Figure 7 This is a block diagram showing the sampling circuit 210 according to an embodiment of the present disclosure in more detail. Figure 7 The sampling circuit 210 can correspond to Figure 5 The sampling circuit 210. As an example, Figure 7 The following implementation is shown: In this implementation, the first internal clock signal ICK_1 and the second internal clock signal ICK_2 are selected as even-numbered internal clock signals and odd-numbered internal clock signals, respectively, and the even-numbered internal clock signals and odd-numbered internal clock signals are used to sample the high level and low level of the chip select signal CS, respectively.

[0111] Reference Figure 7 The sampling circuit 210 may include a clock divider 211, an internal clock selector 212, a sampler 213, a clock synchronizer 214, and a register 215.

[0112] Clock divider 211 can receive clock signals from training circuit 110 (see reference CK_m) via memory clock pad CK_m. Figure 6 The clock signal CK is received. The clock divider 211 can divide the clock signal CK to generate the first internal clock signal ICK_1 and the second internal clock signal ICK_2.

[0113] Clock synchronizer 214 can receive the chip select signal CS from training circuit 110 via memory CS pad CS_m, and can receive the first internal clock signal ICK_1 and the second internal clock signal ICK_2 from clock divider 211. Clock synchronizer 214 can determine the even-numbered edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 based on the alignment between the rising edges of the first and second internal clock signals and the high level of the chip select signal CS. Clock synchronizer 214 can provide synchronization information SYNC_INF, including information about the even-numbered edges, to internal clock selector 212.

[0114] The internal clock selector 212 can receive synchronization information SYNC_INF from the clock synchronizer 214, which includes information about even-numbered edges. Based on the synchronization information SYNC_INF, the internal clock selector 212 can identify an internal clock signal with an even number of edges from the first internal clock signal ICK_1 and the second internal clock signal ICK_2, and can determine the identified internal clock signal as an even-numbered internal clock signal.

[0115] For example, the internal clock selector 212 can determine the first internal clock signal ICK_1 as an even-numbered internal clock signal for sampling the high level of the chip select signal CS. Alternatively, the internal clock selector 212 can determine the second internal clock signal ICK_2 as an odd-numbered internal clock signal for sampling the low level of the chip select signal CS.

[0116] Sampler 213 may include a first subsampler 213_1 and a second subsampler 213_2.

[0117] The first sub-sampler 213_1 can receive a chip select signal CS from the training circuit 110 and a first internal clock signal ICK_1 from the internal clock selector 212. The first sub-sampler 213_1 can perform a sampling operation on the high level of the chip select signal CS based on the first internal clock signal ICK_1.

[0118] For example, when the chip select signal CS is high at the rising edge of the first internal clock signal ICK_1, the first sub-sampler 213_1 can output data corresponding to "sampling passed". The data corresponding to "sampling passed" can be, for example, "1". In another example, when the chip select signal CS is low at the rising edge of the first internal clock signal ICK_1 or in an uncertain region, the first sub-sampler 213_1 can output data corresponding to "sampling failed". The data corresponding to "sampling failed" can be, for example, "0".

[0119] The second sub-sampler 213_2 can receive the chip select signal CS from the training circuit 110 and the second internal clock signal ICK_2 from the internal clock selector 212. The second sub-sampler 213_2 can perform a sampling operation on the low level of the chip select signal CS based on the second internal clock signal ICK_2.

[0120] For example, when the chip select signal CS is low at the rising edge of the second internal clock signal ICK_2, the second sub-sampler 213_2 can output data corresponding to "sampling passed". The data corresponding to "sampling passed" can be, for example, "1". In another example, when the chip select signal CS is high at the rising edge of the second internal clock signal ICK_2 or in an uncertain region, the second sub-sampler 213_2 can output data corresponding to "sampling failed". The data corresponding to "sampling failed" can be, for example, "0".

[0121] Register 215 can receive and store high-level sampled data of the chip select signal CS from the first sub-sampler 213_1. Register 215 can also receive and store low-level sampled data of the chip select signal CS from the second sub-sampler 213_2. In addition, register 215 can combine the high-level sampled data and the low-level sampled data of the chip select signal CS to generate sampled data SD, and the sampled data SD can be sent to the host (e.g., training circuit 110 in the host) via a data pad (e.g., memory data pad DQ_m).

[0122] Figure 8 It is shown Figure 7 A diagram illustrating the operation of the sampling circuit 210 to determine the even-numbered internal clock signal. For ease of explanation, Figure 8 Examples are shown where the first internal clock signal ICK_1 and the second internal clock signal ICK_2 are selected as even-numbered and odd-numbered internal clock signals, respectively.

[0123] Reference Figure 7 and Figure 8The clock divider 211 can divide the clock signals CK_t and CK_c to generate a first internal clock signal ICK_1 and a second internal clock signal ICK_2. In this case, the frequencies of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 can be half the frequencies of the clock signals CK_t and CK_c.

[0124] Clock synchronizer 214 can identify whether the rising edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 are aligned with the high level of the chip select signal CS. For example, at time points t0 and t2, the rising edge of the first internal clock signal ICK_1 can sample the high level of the chip select signal CS. In this case, clock synchronizer 214 can determine the rising edges at time points t0, t2, t4, t6, t8, etc., as even-numbered edges based on time point t0. Additionally, clock synchronizer 214 can determine the rising edges at time points t1, t3, t5, t7, etc., as odd-numbered edges.

[0125] The internal clock selector 212 can identify an internal clock signal with an even number of edges from the first internal clock signal ICK_1 and the second internal clock signal ICK_2, and can determine the identified internal clock signal as an even-numbered internal clock signal. For example, the internal clock selector 212 can determine the first internal clock signal ICK_1 as an even-numbered internal clock signal used to sample the high level of the chip select signal CS. Conversely, the internal clock selector 212 can determine the second internal clock signal ICK_2 as an odd-numbered internal clock signal used to sample the low level of the chip select signal CS.

[0126] Figure 9A This is a diagram illustrating a CS training operation according to an embodiment of the present disclosure. Figure 9A The CS training operation can correspond to Figures 5 to 8 The CS training operation. For ease of explanation, in... Figure 9A In this context, it is assumed that the first internal clock signal ICK_1 and the second internal clock signal ICK_2 are selected as even-numbered and odd-numbered internal clock signals, respectively.

[0127] Reference Figure 9A In the first step (step 1), the sampling result of the chip select signal CS can be "sampled through". For example, at time point t2, the rising edge of the first internal clock signal ICK_1 can sample the high level of the chip select signal CS. At time point t3, the rising edge of the second internal clock signal ICK_2 can sample the low level of the chip select signal CS. In this case, the training circuit 110 (refer to...) Figure 6The chip selection signal CS from the first step can be pushed for a first delay time D1. Then, the second step (step 2) can be performed.

[0128] In the second step (step 2), the sampling result of the chip select signal CS can be a "sampling failure". For example, at time point t2, the rising edge of the first internal clock signal ICK_1 can sample the low level of the chip select signal CS. At time point t3, the rising edge of the second internal clock signal ICK_2 can sample the high level of the chip select signal CS. In this case, the training circuit 110 can adjust the chip select signal CS in the second step by a second delay time D2 based on the sampling failure point, so that the center of the chip select signal CS is aligned with the rising edge of the first internal clock signal ICK_1. For example, when half of the period of the first internal clock signal ICK_1 is defined as "T", the second delay time D2 can correspond to "T / 2".

[0129] In the third step (step 3), since the center of the chip select signal CS is aligned with the rising edge of the first internal clock signal ICK_1, the sampling result of the chip select signal CS can be "sampled through". In addition, the high level of the chip select signal CS can have sufficient setup and hold time.

[0130] Figure 9B This is a diagram illustrating the CS training operation based on the comparison example. For ease of explanation, it is assumed that... Figure 9B The chip select signal in the first step and Figure 9B The chip selection signal in the second step is respectively with Figure 9A The chip select signal in the first step and Figure 9A The chip selection signal in the second step is the same. Furthermore, it is assumed that both the first internal clock signal ICK_1 and the second internal clock signal ICK_2 sample the high level of the chip selection signal.

[0131] Reference Figure 9B In the first step (step 1), the sampling result of the chip select signal CS can be "sampled through". For example, at time point t2, the rising edge of the first internal clock signal ICK_1 can sample the high level of the chip select signal CS. In this case, the chip select signal CS can be pushed by a first delay time D1. Then, the second step (step 2) can be performed.

[0132] In the second step (step 2), the sampling result of the chip select signal CS can be "sampled through". For example, at time point t3, the rising edge of the second internal clock signal ICK_2 can sample the high level of the chip select signal CS. In this case, the chip select signal CS can be pushed back by the first delay time D1. Then, the second step (step 2) can be executed.

[0133] and Figure 9A In comparison, Figure 9B In the comparison example, no sampling failure was detected and was skipped. This is because the time interval of the failure detection region in the comparison example is shorter than the first delay time D1. In this case, the time unit used to delay the chip selection signal CS needs to be set to a very short time interval to detect sampling failure. Therefore, the time required to perform CS training can be increased in the comparison example.

[0134] In comparison, such as Figures 5 to 9A As shown, in CS training according to an embodiment of this disclosure, the clock signal can be divided into two internal clock signals, ICK_1 and ICK_2. The first internal clock signal ICK_1 can be used to perform a sampling operation on the high level of the chip select signal CS, and the second internal clock signal ICK_2 can be used to perform a sampling operation on the low level of the chip select signal CS. Therefore, regions where sampling failures are detected can be extended, and thus, CS training can be performed efficiently.

[0135] Figure 10 This is a flowchart illustrating the operation of performing CS training according to an embodiment of the present disclosure. Figure 10 The CS training operation can be Figures 5 to 9A An example of CS training operations for a memory system.

[0136] In operation S100, memory system 2000 (refer to...) Figure 5 You can enter CS training mode.

[0137] For example, Memory System 2000 (reference) Figure 5 It can enter CS training mode under specific conditions (such as startup or initialization).

[0138] In operation S210, the clock signal can be divided to generate at least two internal clock signals.

[0139] For example, clock divider 211 (refer to...) Figure 7 The clock signal CK can be divided according to step (2) to generate two internal clock signals ICK_1 and ICK_2. In this case, the frequency of each of the two internal clock signals ICK_1 and ICK_2 can be half (1 / 2) of the frequency of the clock signal CK.

[0140] In operation of S220, even-numbered edges can be determined based on the synchronization information between the clock signal and the chip select signal.

[0141] For example, clock synchronizer 214 (see reference) Figure 7 The even-numbered edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 can be determined based on the alignment between the rising edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 and the high level of the chip select signal CS.

[0142] In operation S300, an internal clock signal with an even number of edges from at least two internal clock signals can be selected as the target internal clock signal for sampling the high level of the chip selection signal.

[0143] For example, internal clock selector 212 (refer to...) Figure 7 The first internal clock signal, ICK_1, which has an even number of edges among the two internal clock signals ICK_1 and ICK_2, can be determined as the even-numbered internal clock signal. In this case, the first internal clock signal ICK_1 can be used to sample the high level of the chip select signal CS.

[0144] In operating the S400, the target's internal clock signal can be used to perform the sampling operation.

[0145] For example, sampler 213 (refer to) Figure 7 The chip select signal CS can be sampled at the rising edge of the first internal clock signal ICK_1. When the chip select signal CS is high at the rising edge of the first internal clock signal ICK_1, the sampling result can be "pass". When the chip select signal CS is low or in an uncertain region at the rising edge of the first internal clock signal ICK_1, the sampling result can be "failure".

[0146] In operating the S500, the delay time of the chip selection signal can be adjusted based on the sampling results.

[0147] For example, training circuit 110 (refer to...) Figure 5 The delay time of the chip selection signal CS can be adjusted based on the sampling results of sampler 213. For example, training circuit 110 can push or pull the chip selection signal CS so that the center of the chip selection signal CS is aligned with the rising edge of the first internal clock signal ICK_1.

[0148] As described above, in the CS training operation according to the embodiments of this disclosure, the clock signal can be divided into two internal clock signals, and one of the two internal clock signals can be used to perform a sampling operation on the chip selection signal. Therefore, regions where sampling failures are detected can be extended, and thus, CS training can be performed efficiently.

[0149] Figure 11 This is a block diagram schematically showing a memory system 3000 according to an embodiment of the present disclosure. Figure 11 The memory system 3000 is similar to Figure 1 and Figure 5 The memory system 1000 and memory system 2000. Therefore, in Figure 11 In the figures, the same or similar reference numerals indicate Figure 1 and Figure 5 The same or similar elements in the text, and therefore, detailed descriptions of the same or similar elements will be omitted.

[0150] Reference Figure 11 The memory system 3000 may include a host 100B and a memory device 200B. The host 100B may include a training circuit 110, and the memory device 200B may include a sampling circuit 210 and a memory cell array (MCA). The sampling circuit 210 may include a clock divider 211, an internal clock selector 212, a sampler 213, and a clock synchronizer 214.

[0151] In embodiments of this disclosure, training circuit 110 may support coarse search and fine search operations. For example, when performing CS training, training circuit 110 may first perform a coarse search operation. When a sampling failure is detected by the coarse search operation, training circuit 110 may perform a fine search operation. For example, training circuit 110 may include coarse delay setting logic (CDSL) and fine delay setting logic (FDSL).

[0152] The coarse delay setting logic (CDSL) sets the delay time to be applied to the chip select signal CS during the coarse search operation. The fine delay setting logic (FDSL) sets the delay time to be applied to the chip select signal CS during the fine search operation. The delay time in the coarse search operation can be longer than the delay time in the fine search operation.

[0153] Figure 12 This is a diagram illustrating a CS training operation according to an embodiment of the present disclosure. Figure 12 The CS training operation can correspond to Figure 11 The CS training operation of the memory system. For ease of explanation, in Figure 12In this context, it is assumed that the first internal clock signal ICK_1 and the second internal clock signal ICK_2 are selected as even-numbered and odd-numbered internal clock signals, respectively.

[0154] Reference Figure 12 The first step (step 1) can correspond to a coarse search operation. In the first step (step 1), the sampling result of the chip select signal CS can be "sampled through". For example, the rising edge of the first internal clock signal ICK_1 can sample the high level of the chip select signal CS at time point t2, and the rising edge of the second internal clock signal ICK_2 can sample the low level of the chip select signal CS at time point t3.

[0155] In this case, training circuit 110 (reference) Figure 11 The chip selection signal CS from the first step can be pushed to a first delay time D1. In this embodiment, the first delay time D1 can be the delay time in the coarse search operation. Then, the second step (step 2) can be performed.

[0156] The second step (step 2) can correspond to a coarse search operation. In the second step (step 2), the sampling result of the chip select signal CS can be "sampling failure". For example, the rising edge of the first internal clock signal ICK_1 can sample the low level of the chip select signal CS at time point t2, and the rising edge of the second internal clock signal ICK_2 can sample the high level of the chip select signal CS at time point t3.

[0157] When a sampling failure is detected during the coarse search operation, the training circuit 110 can stop the coarse search operation and perform a fine search operation. The training circuit 110 can perform the fine search operation based on the chip selection signal CS from the first step instead of the chip selection signal CS from the second step. For example, the training circuit 110 can push the chip selection signal CS from the first step by a second delay time D2. In this embodiment, the second delay time D2 can be a delay time in the fine search operation and can be shorter than the first delay time. Then, a third step (step 3) can be performed.

[0158] The third step (step 3) can correspond to a fine-grained search operation. In the third step (step 3), the sampling result of the chip select signal CS can be "sampling failure". For example, the rising edge of the first internal clock signal ICK_1 can sample the uncertain region of the chip select signal CS at time point t2, and the rising edge of the second internal clock signal ICK_2 can sample the uncertain region of the chip select signal CS at time point t3.

[0159] When a sampling failure is detected during the fine-tuning search operation, the training circuit 110 can adjust the chip selection signal CS of the third step by a third delay time D3 based on the sampling failure point, so that the center of the chip selection signal CS is aligned with the rising edge of the first internal clock signal ICK_1. For example, when half of the period of the first internal clock signal ICK_1 is defined as "T", the third delay time D3 can correspond to "T / 2".

[0160] In the fourth step (step 4), since the center of the chip select signal CS is aligned with the rising edge of the first internal clock signal ICK_1, the sampling result of the chip select signal CS can be "sampled through". In addition, the high level of the chip select signal CS can have sufficient setup and hold time.

[0161] For reference Figure 11 and Figure 12 The CS training according to the embodiments of this disclosure supports both coarse and fine search operations. Therefore, sampling failure points can be quickly located, and CS training time can be reduced. Furthermore, based on the CS training according to the embodiments of this disclosure, the clock signal can be divided into at least two internal clock signals, and one of the at least two internal clock signals can be used to perform a sampling operation on the chip selection signal. Therefore, the detected sampling failure regions can be expanded, and thus, CS training can be performed efficiently.

[0162] Figure 13 This is a flowchart illustrating the operation of performing CS training according to an embodiment of the present disclosure. Figure 13 The CS training operation can be Figure 11 and Figure 12 An example of CS training operations for a memory system.

[0163] In operation S100, memory system 3000 (refer to...) Figure 11 You can enter CS training mode.

[0164] For example, memory system 3000 (reference) Figure 11 It can enter CS training mode under specific conditions (such as startup or initialization).

[0165] In operation S210, the clock signal can be divided to generate at least two internal clock signals.

[0166] For example, clock divider 211 (refer to...) Figure 11The clock signal CK can be divided according to step (2), thereby generating two internal clock signals ICK_1 and ICK_2. In this case, the frequency of each of the two internal clock signals ICK_1 and ICK_2 can be half (1 / 2) of the frequency of the clock signal CK.

[0167] In operation of S220, even-numbered edges can be determined based on the synchronization information between the clock signal and the chip select signal.

[0168] For example, clock synchronizer 214 (see reference) Figure 11 The even-numbered edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 can be determined based on the alignment between the rising edges of the first internal clock signal ICK_1 and the second internal clock signal ICK_2 and the high level of the chip select signal CS.

[0169] In operation S300, an internal clock signal with an even number of edges from at least two internal clock signals can be selected as the target internal clock signal for sampling the high level of the chip selection signal.

[0170] For example, internal clock selector 212 (refer to...) Figure 11 The first internal clock signal, ICK_1, which has an even number of edges among the two internal clock signals ICK_1 and ICK_2, can be determined as the even-numbered internal clock signal. In this case, the first internal clock signal ICK_1 can be used to sample the high level of the chip select signal CS.

[0171] In operation of S410, a coarse delay time can be provided to the chip select signal CS.

[0172] For example, coarse delay setting logic CDSL (see reference) Figure 11 A coarse delay time can be set, and the chip select signal CS can be pushed by a coarse delay time.

[0173] In operation of S420, the target internal clock signal can be used to perform a sampling operation on the chip select signal CS, which is subject to a coarse delay.

[0174] For example, sampler 213 (refer to) Figure 11 The chip select signal CS can be sampled at the rising edge of the first internal clock signal ICK_1.

[0175] In operation S430, it can be determined whether the sampling result is "failed".

[0176] When the chip select signal CS is high at the rising edge of the first internal clock signal ICK_1, the sampling result can be "pass". In this case, a coarse search operation can be performed continuously. That is, operation S410 can be executed again, and the coarse delay time of the chip select signal CS can be further pushed.

[0177] When the chip select signal CS is low or in the uncertain region at the rising edge of the first internal clock signal ICK_1, the sampling result may be "failure". In this case, a coarse search operation can be performed, and a fine search operation can be executed. That is, operation S440 can be executed.

[0178] In operation of S440, a fine delay time can be provided to the chip select signal CS.

[0179] For example, Fine Delay Setting Logic (FDSL) (see reference) Figure 11 The fine delay time can be set, and the chip select signal CS can be driven by the fine delay time.

[0180] In operation of S450, the target internal clock signal can be used to perform a sampling operation on the chip select signal CS, which has been subjected to a fine delay.

[0181] For example, sampler 213 can sample the chip select signal CS at the rising edge of the first internal clock signal ICK_1.

[0182] In operation S460, it can be determined whether the sampling result is "failed".

[0183] When the chip select signal CS is high at the rising edge of the first internal clock signal ICK_1, the sampling result can be "pass". In this case, a fine search operation can be performed continuously. That is, operation S440 can be executed again, and the chip select signal CS can be further pushed with a fine delay time.

[0184] When the chip select signal CS is low or in an uncertain region at the rising edge of the first internal clock signal ICK_1, the sampling result may be "failure". In this case, a fine search operation can be performed, and the center of the chip select signal CS can be aligned with the rising edge. That is, operation S500 can be executed.

[0185] In operating the S500, the delay time of the chip selection signal can be adjusted based on the sampling results.

[0186] For example, training circuit 110 (refer to...) Figure 11The delay time of the chip selection signal CS can be adjusted based on the sampling results of sampler 213. For example, training circuit 110 can push or pull the chip selection signal CS to align the center of the chip selection signal CS with the rising edge of the first internal clock signal ICK_1.

[0187] As described above, the CS training operation according to the embodiments of this disclosure supports both coarse and fine search operations. Therefore, sampling failure points can be quickly located, and CS training time can be reduced. Furthermore, the CS training operation according to the embodiments of this disclosure can divide the clock signal into two internal clock signals, and one of the two internal clock signals can be used to perform a sampling operation on the chip selection signal. Therefore, the detected sampling failure region can be expanded, and thus, CS training can be performed efficiently.

[0188] Figure 14 This is a block diagram schematically showing a memory system 4000 according to an embodiment of the present disclosure. Figure 14 The memory system 4000 is similar to Figure 1 , Figure 5 and Figure 11 The memory systems 1000, 2000, and 3000. Therefore, in Figure 14 In the figures, the same or similar reference numerals indicate Figure 1 , Figure 5 and Figure 11 The same or similar elements in the text, and therefore, detailed descriptions of the same or similar elements will be omitted.

[0189] Reference Figure 14 The memory system 4000 may include a host 100C and a memory device 200C. The host 100C may include training circuitry 110, and the memory device 200C may include sampling circuitry 210 and a memory cell array (MCA). The sampling circuitry 210 may include a clock divider 211, an internal clock selector 212, a sampler 213, and a mode register 216.

[0190] In embodiments of this disclosure, mode register 216 can receive at least two internal clock signals from clock divider 211. Mode register 216 can determine the even-numbered edges among the edges of the at least two internal clock signals. In other words, when the mode register is set, mode register 216 can receive at least two internal clock signals from clock divider 211 and can classify the edges of the at least two internal clock signals as even-numbered edges and odd-numbered edges. Mode register 216 can provide synchronization information SYNC_INF regarding the even-numbered edges to internal clock selector 212.

[0191] In one implementation, information for determining the even-numbered edges among the edges of at least two internal clock signals (e.g., information for classifying the edges of at least two internal clock signals as even-numbered and odd-numbered edges) may be previously stored in mode register 216. Memory device 200C may determine the even-numbered edges among the edges of at least two internal clock signals based on the information stored in mode register 216.

[0192] As described above, the sampling circuit 210 can use the mode register 216 instead of a clock synchronizer to determine the even-numbered edges.

[0193] Figure 15 This is a block diagram illustrating a memory device 200 according to an embodiment of the present disclosure. Figure 15 The memory device 200 may correspond to Figures 1 to 14 The memory devices 200, 200A, 200B and 200C.

[0194] Reference Figure 15 The memory device 200 may include a sampling circuit 210, a memory cell array 310, a data input / output (I / O) buffer 320, an error correction code (ECC) engine 350, a refresh control circuit 400, a control logic circuit 510, an address register 520, a memory bank control circuit (or logic) 530, a row address multiplexer (RA Mux) 540, a column address (CA) latch 550, a row decoder 560, a column decoder 570, a sense amplifier component 585, and an input / output gating circuit 590.

[0195] In this embodiment, during CS training, the sampling circuit 210 can divide the clock signal into at least two internal clock signals, and can use one of the at least two internal clock signals to perform a sampling operation on the chip selection signal. The sampling circuit 210 may correspond to a reference... Figures 1 to 14 The sampling circuit 210 is described.

[0196] The memory cell array 310 may include a plurality of memory bank arrays 310_1 to 310_n. Each of the memory bank arrays 310_1 to 310_n may include a plurality of memory cells. For example, each of the memory cells may be formed at the point where a corresponding word line intersects a bit line.

[0197] The row decoder 560 may include a plurality of sub-row decoders 560_1 to 560_n. Each of the sub-row decoders 560_1 to 560_n may be connected to a corresponding memory array among the memory arrays 310_1 to 310_n.

[0198] The sensing amplifier component 585 may include a plurality of sensing amplifiers 585_1 to 585_n. Each of the sensing amplifiers 585_1 to 585_n may be connected to a corresponding memory array among the memory arrays 310_1 to 310_n.

[0199] The column decoder 570 may include multiple sub-column decoders 570_1 to 570_n. Each of the sub-column decoders 570_1 to 570_n may be connected to a corresponding memory array among the memory arrays 310_1 to 310_n via a corresponding sense amplifier.

[0200] The memory bank arrays 310_1 to 310_n, the sensing amplifiers 585_1 to 585_n, the sub-column decoders 570_1 to 570_n, and the sub-row decoders 560_1 to 560_n can constitute multiple memory banks. For example, the first memory bank array 310_1, the first sensing amplifier 585_1, the first sub-column decoder 570_1, and the first sub-row decoder 560_1 can constitute a first memory bank.

[0201] Address register 520 can receive address ADDR, including bank address BANK_ADDR, row address ROW_ADDR, and column address COL_ADDR, from the memory controller. Address register 520 can provide the received bank address BANK_ADDR to the bank control logic 530, the received row address ROW_ADDR to the row address multiplexer 540, and the received column address COL_ADDR to the column address latch 550.

[0202] The memory bank control logic 530 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. For example, the sub-row decoders 560_1 to 560_n corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal. The sub-column decoders 570_1 to 570_n corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0203] The row address multiplexer 540 can receive the row address ROW_ADDR from the address register 520 and the refresh row address REF_ADDR from the refresh control circuit 400. The row address multiplexer 540 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 540 can be applied to each of the sub-row decoders 560_1 to 560_n.

[0204] The refresh control circuit 400 can sequentially increase or decrease the refresh row address REF_ADDR in normal refresh mode in response to a refresh signal from the control logic circuit 510.

[0205] In hammer refresh mode, refresh control circuit 400 can receive hammer address HADDR. Based on hammer address HADDR, refresh control circuit 400 can output the address of the neighboring memory cell row adjacent to the attacker's memory cell row as refresh row address REF_ADDR.

[0206] The sub-row decoder selected by the memory bank control logic 530 among sub-row decoders 560_1 to 560_n can activate the word line corresponding to the row address RA output from the row address multiplexer 540. For example, the selected row decoder can apply a word line drive voltage to the word line corresponding to the row address.

[0207] Column address latch 550 can receive column address COL_ADDR from address register 520 and can temporarily store the received column address COL_ADDR. Additionally, for example, in burst mode, column address latch 550 can gradually increment the received column address COL_ADDR. Column address latch 550 can apply the temporarily stored or gradually incremented column address COL_ADDR to each of sub-column decoders 570_1 to 570_n.

[0208] The sub-row decoders 570_1 to 570_n activated by the memory bank control logic 530 can activate the sense amplifiers corresponding to the memory bank address BANK_ADDR and the column address COL_ADDR through the input / output gate circuit 590.

[0209] The input / output gating circuit 590 may include circuitry for gating input and output data. Additionally, the input / output gating circuit 590 may include a data latch for storing codewords output from the memory arrays 310_1 to 310_n and a write driver for writing data into the memory arrays 310_1 to 310_n.

[0210] In one implementation, during a read operation, a codeword CW read from a selected memory array among memory arrays 310_1 to 310_n can be sensed by a sense amplifier corresponding to the selected memory array and stored in a data latch of the input / output gate circuit 590. Additionally, the codeword CW stored in the data latch can be provided as a data DTA by ECC decoding of the ECC engine 350 to the data input / output buffer 320. The data input / output buffer 320 can generate a data signal DQ based on the data DTA and can provide the data signal DQ together with a strobe signal DQS to the memory controller.

[0211] In one implementation, during a write operation, the data DTA to be written to a selected memory array among memory arrays 310_1 to 310_n can be received as a data signal DQ by a data input / output buffer 320. The data input / output buffer 320 can convert the data signal DQ into a data DTA and provide the data DTA to the ECC engine 350. The ECC engine 350 can generate parity bits (or parity data) based on the data DTA and can provide a codeword CW including the data DTA and the parity bits to an input / output gating circuit 590. The input / output gating circuit 590 can write the codeword CW to the selected memory array.

[0212] During a write operation, the data input / output buffer 320 can convert the data signal DQ into a data DTA and provide the data DTA to the ECC engine 350. During a read operation, the data input / output buffer 320 can convert the data DTA provided from the ECC engine 350 back into the data signal DQ.

[0213] The ECC Engine 350 can perform ECC encoding on the data DTA during write operations. The ECC Engine 350 can perform ECC decoding on the codeword CW during read operations.

[0214] In addition, the ECC engine 350 can perform ECC encoding and ECC decoding on the counting data CNTD provided by the row hammer management circuit 500 (not shown).

[0215] Control logic circuitry 510 controls the operation of memory device 200. For example, control logic circuitry 510 can generate control signals that cause memory device 200 to perform write operations, read operations, normal refresh operations, and hammer refresh operations. Control logic circuitry 510 may include command decoder (or CMD decoder) 511 and mode register set (MRS) 512. Command decoder 511 is used to decode commands (CMD) received from memory controller, and mode register set (MRS) 512 is used to set the operating mode of memory device 200.

[0216] Command decoder 511 can decode command CMD to generate internal command signals (such as internal activation signal IACT, internal precharge signal IPRE, internal read signal IRD, and internal write signal IWR). Additionally, command decoder 511 can decode chip select signals and command / address signals to generate control signals corresponding to command CMD.

[0217] The above description relates to specific embodiments for implementing this disclosure. This disclosure is not limited to the embodiments described above, but also includes embodiments that can be implemented through simple design modifications or easy alterations.

[0218] For example, in Figures 1 to 15 In this document, the technical concept of this disclosure has been described as being applied to CS training. However, it will be readily understood that the technical concept of this disclosure can also be applied to the training processing of command / address signals CMD / ADDR or data DATA, and to the apparatus for performing such training.

[0219] Additionally, for example, in Figures 1 to 15 In this context, memory devices have been primarily described as single chips. However, it will be readily understood that the technical concepts of this disclosure can also be applied to memory modules (such as UDIMM (unbuffered dual in-line memory modules), RDIMM (registered DIMMs), and LRDIMM (load-reduced DIMMs)) or to HBM (high-bandwidth memory) (such as HBM1, HBM2, HBM3, and HBM4).

[0220] Additionally, for example, in Figures 1 to 15 In the previous description, the function of the internal clock signal was described as being specified by the memory device. However, this is merely an example, and the present disclosure is not limited thereto. According to an embodiment, the function of the internal clock signal may be specified by the host according to a selection method mutually agreed upon between the memory device and the host. Furthermore, as mentioned above, the functions of the internal clock signals can be interchanged.

[0221] While this specification contains numerous specific implementation details, these should not be construed as limiting the scope of any invention or the scope of any claims, but rather as descriptions of features specific to particular implementations of a particular invention. Some features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in combinations, in some cases one or more features from the combination may be removed from the combination, and the combination may be for sub-combinations or variations thereof.

[0222] Furthermore, this disclosure may include techniques that can be easily modified and implemented using the above-described embodiments. Therefore, the scope of this disclosure should not be limited to the above-described embodiments, but should be determined by the appended claims and their equivalents.

Claims

1. A memory device, comprising: A clock divider is configured to receive a clock signal from the host, divide the clock signal, and generate at least two internal clock signals. An internal clock selector is configured to receive the at least two internal clock signals from a clock divider and select one of the at least two internal clock signals as a target internal clock signal. as well as The sampler is configured to receive a chip select signal from the host, receive a target internal clock signal from the internal clock selector, and sample the chip select signal using the target internal clock signal.

2. The memory device of claim 1, wherein, The at least two internal clock signals generated by the clock divider include a first internal clock signal and a second internal clock signal, and The internal clock selector is configured as follows: The first internal clock signal is selected as the first target internal clock signal for sampling the high level of the chip select signal, and The second internal clock signal is selected as the second target internal clock signal for sampling the low level of the chip select signal.

3. The memory device as claimed in claim 2, wherein, The sampler includes: The first sub-sampler is configured to receive a first target internal clock signal and a chip select signal, and to sample the high level of the chip select signal using the first target internal clock signal; and The second sub-sampler is configured to receive the internal clock signal of the second target and the chip select signal, and to sample the low level of the chip select signal using the internal clock signal of the second target.

4. The memory device of claim 3, further comprising: The register is configured to store the first sub-sampling result received from the first sub-sampler and the second sub-sampling result received from the second sub-sampler. The first and second sub-sampling results are sent to the host as sampling data via a data pad.

5. The memory device of claim 1, further comprising: A clock synchronizer is configured to receive the at least two internal clock signals from a clock divider, receive a chip select signal from a host, and classify the edges of the at least two internal clock signals into even edges and odd edges.

6. The memory device of claim 5, wherein, The clock synchronizer is configured to determine the even-numbered edges among the edges of the at least two internal clock signals based on synchronization information between the chip select signal and the at least two internal clock signals.

7. The memory device of claim 6, wherein, The internal clock selector is configured to select an internal clock signal, including an even number of edges, from the at least two internal clock signals as the target internal clock signal.

8. The memory device of claim 5, wherein, Commands are received from the host at even-numbered edges.

9. The memory device of claim 1, further comprising: The mode register is configured to receive the at least two internal clock signals from the clock divider and to store information for classifying the edges of the at least two internal clock signals as even edges and odd edges.

10. The memory device of claim 1, wherein, The chip select signal is delayed by a first delay time during the coarse search operation and by a second delay time during the fine search operation, with the first delay time being longer than the second delay time.

11. The memory device of claim 1, wherein, The frequency of each of the at least two internal clock signals is half the frequency of the clock signal.

12. A method of operating a memory device, comprising: During the training mode for the chip selection signal, the clock signal is divided to generate at least two internal clock signals; Select one of the at least two internal clock signals as the target internal clock signal; The chip selection signal is sampled using the target's internal clock signal; as well as The delay time to be applied to the chip select signal is adjusted based on the sampling results of the chip select signal.

13. The method of claim 12, further comprising: The even-numbered edges among the edges of the at least two internal clock signals are determined based on the synchronization information between the clock signal and the internal clock signal of the at least two internal clock signals.

14. The method of claim 13, wherein, The step of selecting one of the at least two internal clock signals includes: Select an internal clock signal including an even number of edges from the at least two internal clock signals as the target internal clock signal.

15. The method of claim 12, further comprising: A coarse delay time is applied to the chip select signal to generate the first chip select signal; The first chip selection signal is sampled using the target's internal clock signal; Determine whether the sampling result of the first chip selection signal is a pass or a failure; as well as Based on the sampling result of the first chip selection signal, a coarse delay time is applied to the first chip selection signal to generate the second chip selection signal.

16. The method of claim 15, further comprising: Since sampling the first chip selection signal failed, a fine delay time is applied to the chip selection signal to generate a third chip selection signal.

17. The method of claim 16, further comprising: Determine whether the sampling result of the third chip selection signal is a pass or a failure; as well as Based on the sampling result of the third chip selection signal, a fine delay time is applied to the third chip selection signal to generate the fourth chip selection signal.

18. The method of claim 17, wherein, Based on the failure of sampling the third chip selection signal, the delay time to be applied to the third chip selection signal is adjusted based on the sampling failure point of the third chip selection signal.

19. The method of claim 16, wherein, The coarse delay time is longer than the fine delay time.

20. A memory system, comprising: Memory devices; as well as The host is configured to provide clock and chip select signals to the memory device during training with respect to the chip select signal. The memory device includes: A clock divider is configured to divide the clock signal received from the host and generate at least two internal clock signals; An internal clock selector is configured to receive the at least two internal clock signals from a clock divider and select one of the at least two internal clock signals as a target internal clock signal; and The sampler is configured to receive a chip select signal from the host, receive a target internal clock signal from the internal clock selector, and sample the chip select signal using the target internal clock signal.

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