Memory device and operating method thereof, memory system

Abstract

This application provides a memory device and its operation method, as well as a memory system. The memory device includes: a memory cell array comprising multiple memory blocks; peripheral circuitry coupled to the memory cell array and configured to: perform a first read operation on memory cells included in edge pages of the memory cell array, based on the condition that the block to be read among the multiple memory blocks is an open block; the first offset read voltage has a first offset relative to a first read voltage; the first read voltage is a read voltage corresponding to the first read operation among the default read voltages of the block to be read.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are storage equipment used to preserve information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production costs, suitable erasure speed, and retention characteristics. However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a memory device and its operation method, as well as a memory system.

[0004] In a first aspect, embodiments of this application provide a memory device, the memory device comprising: a memory cell array including a plurality of memory blocks, peripheral circuitry coupled to the memory cell array, and configured to: perform a first read operation on memory cells included in edge pages of the memory cell array to be read, based on the fact that the block to be read among the plurality of memory blocks is an open block, using a first offset read voltage; the first offset read voltage having a first offset relative to a first read voltage; the first read voltage being a read voltage corresponding to the first read operation among the default read voltages of the block to be read.

[0005] In some embodiments, an open block includes at least one blank page and at least one programmed page; the storage units included in the blank page are not programmed, and the storage units included in the programmed page are programmed; at least one programmed page includes an edge page, which is adjacent to a blank page in the stacking direction of the block to be read.

[0006] In some embodiments, the peripheral circuitry is configured to: determine a first offset based on the number of programming pages and a first coefficient; the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; and obtain a first offset read voltage based on the difference between a first read voltage and the first offset.

[0007] In some embodiments, the peripheral circuit is further configured to: perform a first correction on a first coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determine the first coefficient as a first value; perform a second correction on the first coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determine the first coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0008] In some embodiments, the open block includes a plurality of programming pages; the plurality of programming pages include edge pages and inner pages; the peripheral circuitry is further configured to: perform a second read operation on the memory cells included in the inner pages using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage corresponding to the second read operation among default read voltages; wherein the second offset is less than a first offset.

[0009] In some embodiments, the peripheral circuitry is configured to: determine a second offset based on the number of programming pages and a second coefficient; the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; and obtain a second offset read voltage based on the difference between a second read voltage and the second offset.

[0010] In some embodiments, the peripheral circuit is further configured to: perform a first correction on the second coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determine the second coefficient as a first value; perform a second correction on the second coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determine the second coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0011] In some embodiments, the peripheral circuit is further configured to: define a plurality of preset intervals according to a preset number of erase / write cycles of the memory device, wherein the plurality of preset intervals are M intervals from the first interval to the Mth interval; wherein the number of M intervals is positively correlated with the number of preset erase / write cycles; wherein M is a positive integer and M≥2.

[0012] In some embodiments, the peripheral circuitry is further configured to: determine a first offset or a second offset based on additional information; wherein the additional information includes whether the data stored in the memory cells included in the edge page or the inner page is in a hold-up state or a disturbance state.

[0013] In some embodiments, the peripheral circuitry is further configured to: perform a third read operation on a memory cell included in a page of a block to be read, based on the fact that the block to be read among a plurality of memory blocks is a closed block; the third read voltage is a read voltage corresponding to the third read operation among default read voltages; and the memory cell included in any page of the closed block has been programmed.

[0014] In some embodiments, the storage unit has N bits and 2^N bits. N One storage state; 2 N The storage states include erase state and 2. N -1 non-erasable state; where N is a positive integer; the default read voltage includes the first-level read voltage up to the second-level read voltage. N -1 level reading voltage 2 N -1 read voltage; the first read voltage is 2. N -1 of the read voltages; the first offset is associated with the first read voltage.

[0015] In some embodiments, the first read voltage is 2 N One of the -1 read voltages is used to determine the first offset as the first value; based on the first read voltage being 2... N -1 Read voltages that are different from one of the read voltages, determine the first offset as a second value that is different from the first value.

[0016] Secondly, embodiments of this application provide an operation method for a memory device, the operation method comprising: a peripheral circuit of the memory device coupled to a memory cell array of the memory device performing a first read operation on memory cells included in edge pages of a memory cell block to be read, based on the condition that a block to be read among a plurality of memory blocks in the memory cell array is an open block; the first offset read voltage having a first offset relative to a first read voltage; the first read voltage being a read voltage corresponding to the first read operation among the default read voltages of the block to be read.

[0017] In some embodiments, an open block includes at least one blank page and at least one programmed page; the storage units included in the blank page are not programmed, and the storage units included in the programmed page are programmed; at least one programmed page includes an edge page, which is adjacent to a blank page in the stacking direction of the block to be read.

[0018] In some embodiments, the operation method includes: determining a first offset based on the number of programming pages and a first coefficient; the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; and obtaining a first offset read voltage based on the difference between a first read voltage and the first offset.

[0019] In some embodiments, the operation method further includes: performing a first correction on a first coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determining the first coefficient as a first value; performing a second correction on the first coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determining the first coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0020] In some embodiments, the operation method further includes: performing a second read operation on the memory cells included in the internal page using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage in the default read voltages corresponding to the second read operation; wherein the second offset is less than a first offset; wherein the open block includes a plurality of programmed pages; the plurality of programmed pages include edge pages and internal pages.

[0021] In some embodiments, the operation method includes: determining a second offset based on the number of programming pages and a second coefficient; the second offset being positively correlated with the number of programming pages and negatively correlated with the second coefficient; and obtaining a second offset read voltage based on the difference between a second read voltage and the second offset.

[0022] In some embodiments, the operation method further includes: performing a first correction on a second coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determining the second coefficient as a first value; performing a second correction on the second coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determining the second coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0023] In some embodiments, the operation method further includes: defining a plurality of preset intervals according to a preset number of erase / write cycles of the memory device, wherein the plurality of preset intervals are M intervals from the first interval to the Mth interval; wherein the number of M intervals is positively correlated with the number of preset erase / write cycles; wherein M is a positive integer and M≥2.

[0024] In some embodiments, the operation method further includes: determining a first offset or a second offset based on additional information; wherein the additional information includes whether the data stored in the storage unit included in the edge page or the inner page is in a hold-in state or a disturbed state.

[0025] In some embodiments, the method further includes: performing a third read operation on a memory cell included in a page of a block of a plurality of memory blocks, based on the fact that the block to be read is a closed block; the third read voltage is a read voltage corresponding to the third read operation among default read voltages; and the memory cell included in any page of the closed block has been programmed.

[0026] Thirdly, embodiments of this application provide a memory system including a memory device and a memory controller coupled to and controlling the memory device; the memory controller is configured to: send a read command; the memory device is further configured to: receive the read command and perform a first read operation on memory cells included in edge pages of a block to be read in the memory device using a first offset read voltage; the first offset read voltage has a first offset relative to a first read voltage; the first read voltage is a read voltage corresponding to the first read operation among the default read voltages of the block to be read.

[0027] In some embodiments, the memory controller is further configured to: send a first instruction; the first instruction instructs the acquisition of a first offset read voltage; the memory device is further configured to: receive the first instruction, acquire first information characterizing the first offset read voltage; and send second information characterizing the completion of acquiring the first information to the memory controller; the memory controller is further configured to: send a read command based on the second information; the memory device is further configured to: receive the read command, generate the first offset read voltage based on the first information, and control the memory device to perform a first read operation based on the first offset read voltage.

[0028] In some embodiments, the memory controller is configured to: send a first instruction; the first instruction includes open block information; the open block information includes information characterizing that the block to be read is an open block, information characterizing that the page to be read in the block to be read is an edge page, and information characterizing that a first offset is associated with an edge page; the memory device is configured to: receive the first instruction, acquire first information characterizing a first offset read voltage based on the open block information, and send second information characterizing the acquisition of the first information to the memory controller.

[0029] In some embodiments, the memory controller is further configured to: send a read command; the read command includes a first instruction; the first instruction indicates that a first offset read voltage is acquired; the memory device is further configured to: receive the read command, acquire first information characterizing the first offset read voltage; and generate the first offset read voltage based on the first information, and control the memory device to perform a first read operation based on the first offset read voltage.

[0030] In some embodiments, the memory controller is configured to: send a read command; the read command includes a first instruction; the first instruction includes open block information; the open block information includes information indicating that the block to be read is an open block, information indicating that the page to be read in the block to be read is an edge page, and information indicating that a first offset is associated with the edge page; the memory device is configured to: receive the read command and obtain first information indicating a first offset read voltage based on the open block information.

[0031] In some embodiments, the open block information further includes information representing the number of programming pages in the block to be read and information representing a first coefficient; the information relating the first offset to the edge page includes information representing that the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; the memory device is configured to: determine information representing the first offset based on the information representing the number of programming pages and the information representing the first coefficient, and the information representing that the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; and obtain information representing the first offset read voltage based on the information representing the first read voltage and the information representing the first offset.

[0032] In some embodiments, the open block includes at least one blank page and at least one programmed page; the memory cells included in the blank page are not programmed, and the memory cells included in the programmed page are programmed; at least one programmed page includes an edge page, which is adjacent to a blank page in the stacking direction of the block to be read; the open block includes a plurality of programmed pages; the plurality of programmed pages include edge pages and inner pages; the memory device is further configured to: perform a second read operation on the memory cells included in the inner pages using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage in the default read voltage corresponding to the second read operation; wherein the second offset is less than a first offset.

[0033] In some embodiments, the open block information further includes information representing the number of programming pages in the block to be read and information representing a second coefficient; the information relating the second offset to the edge page includes information representing that the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; the memory device is configured to: determine information representing the second offset based on the information representing the number of programming pages and the information representing the second coefficient, and the information representing that the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; obtain information representing the second offset read voltage based on the information representing the second read voltage and the information representing the second offset; wherein the second offset is less than the first offset.

[0034] In various embodiments of this application, based on the fact that the page to be read is an edge page of an open block, a first read operation is performed on the memory cells included in the edge page using a first offset read voltage. This simplifies the logic of the peripheral circuit of the memory device in processing the first read operation of the open block, and helps to reduce the complexity of the first read operation processing. For example, it helps to reduce the storage space occupied by the first offset table (including the mapping relationship between the first offset and the edge word line) corresponding to the first offset read voltage, and helps to reduce the failure bit count (FBC) of the first read operation. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application;

[0036] Figure 2A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this application;

[0037] Figure 2B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application;

[0038] Figure 3A This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of this application;

[0039] Figure 3B This is a schematic three-dimensional circuit diagram of an exemplary memory device of this application;

[0040] Figure 3C This is a schematic two-dimensional circuit diagram of an exemplary memory device of this application;

[0041] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND-type memory strings according to an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of this application;

[0043] Figure 6 A schematic diagram illustrating an exemplary read operation flow of a memory system provided in this application;

[0044] Figure 7 A schematic diagram of the threshold voltage distribution corresponding to a memory cell with 3 memory bits is provided as an embodiment of this application.

[0045] Figure 8A A schematic diagram of an open block with edge pages in a memory device provided in this application;

[0046] Figure 8BA schematic diagram of an open block of a memory device having edge pages and internal pages provided in this application;

[0047] Figure 8C A schematic diagram of an open block having edge pages and internal pages in another memory device provided in this application;

[0048] Figure 9 One of the schematic diagrams illustrating an exemplary setting offset read voltage process for a memory device provided in this application;

[0049] Figure 10 A second schematic diagram illustrating an exemplary setting offset read voltage process for a memory device provided in this application;

[0050] Figure 11 A third schematic diagram illustrating an exemplary setting offset read voltage process for a memory device provided in this application;

[0051] Figure 12 A schematic diagram illustrating the relationship between the index of the self-word line coupled to the edge page in an open block of a memory device provided in this application and the voltage value of a first offset;

[0052] Figure 13 A schematic diagram illustrating the relationship between the index of the self-word line coupled to an internal page in an open block of a memory device provided in this application and the voltage value of a second offset;

[0053] Figure 14 A diagram illustrating an exemplary threshold voltage distribution in a first read operation and a second read operation of a memory device provided in this application;

[0054] Figure 15 This is a schematic diagram of an exemplary composition of a memory system provided in an embodiment of this application. Detailed Implementation

[0055] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0057] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0058] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] The memory devices in the embodiments of this application include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0061] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this application is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0062] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0063] In some implementations, the memory controller 106 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0064] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104.

[0065] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0066] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0067] In such Figure 2A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0068] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0069] Figure 3A An exemplary schematic diagram of a storage cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3A As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cells parallel to the gate isolation structure. Each two rows are separated by a gate isolation structure and a top-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple blocks. Multiple second gate isolation structures can divide a block into multiple finger regions. A top-select gate isolation structure located in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two memory chips. In practical applications, the number of finger regions contained in a memory block can be adjusted according to the actual situation, such as 2, 3, 4, 5, etc.

[0070] It should be noted that, Figure 3A The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this application. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0071] Figure 3B A schematic three-dimensional circuit diagram of an exemplary memory device according to this application is shown. The memory device may be... Figure 1 An example of a memory device 104 is provided. The memory device may include a memory cell array and peripheral circuitry coupled to the memory cell array. Taking a three-dimensional NAND-type memory cell array as an example, where the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0072] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0073] It should be noted that the storage state mentioned here is the same as the storage state of the storage cell in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has two storage states (i.e., two memory states), which include one programming state and one erase state. Another example is an MLC type storage cell with four storage states, including one erase state and three programming states. Yet another example is a TLC type storage cell with eight storage states, including one erase state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, including one erase state and fifteen programming states.

[0074] like Figure 3BAs shown, each memory string 308 may include a lower selection transistor 310 (also referred to as a source-side selection transistor) at its source end and an upper selection transistor 312 (also referred to as a drain-side selection transistor) at its drain end. The gate of the lower selection transistor 310 is connected to the lower selection gate line (BSG), and the gate of the upper selection transistor 312 is connected to the upper selection gate line (TSG). The lower selection transistor 310 and the upper selection transistor 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 in the same memory block are coupled through the same source line (SL) 314 (e.g., an array common source (ACS)). In other words, according to some embodiments, all memory strings 308 in the same memory block are coupled to an array common source (ACS). According to some embodiments, the drain end of the upper selection transistor 312 of each memory string 308 is connected to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the selection transistor 312) or a deselection voltage (e.g., 0V) to the corresponding selection transistor 312 via one or more selection gate lines 313 (corresponding to one or more selection transistors 312) and / or by applying a selection voltage (e.g., higher than the threshold voltage of the selection transistor 310) or a deselection voltage (e.g., 0V) to the corresponding selection transistor 310 via one or more selection gate lines 315 (corresponding to one or more selection transistors 310).

[0075] like Figure 3B As shown, NAND memory strings 308 can be organized into multiple memory blocks, each of which can have a common source line 314 (e.g., coupled to ground). In some implementations, each memory block is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which can be coupled with read and programmable voltages V. WL(For example, read voltage (e.g., 0.3V) and programming voltage (e.g., 3V)) biases are coupled to the selected word line, selecting which row of memory cell 306 is affected by read and programming operations.

[0076] refer to Figure 3B The gate of each memory cell 306 in the plurality of memory cells is connected to the corresponding word line 318, and each memory string 308 is coupled to the corresponding bit line 316 via the corresponding upper selection transistor 312 and the corresponding source line 314 via the lower selection transistor 310.

[0077] refer to Figure 3B The memory block comprises an array of memory strings coupled to stacked word lines WL0, WL1, ..., WLn, WLn+1, and WLn+2. Each memory string in a column of the memory string array is connected to a bit line (e.g., bit line BL0) via a corresponding up-select transistor and to the array common source ACS via a corresponding down-select transistor. The gates of the up-select transistors in a column of memory strings are connected to their respective up-select gate lines. The gates of the down-select transistors in a column of memory strings are collectively connected to the down-select gate line BSG. Each memory string in a row of the memory string array is connected to a corresponding bit line via a corresponding up-select transistor and to the array common source ACS via a corresponding down-select transistor. The gates of the up-select transistors in a row of memory strings are collectively connected to an up-select gate line (e.g., up-select gate line TSG0). The gates of the down-select transistors in a row of memory strings are collectively connected to the down-select gate line BSG. In some embodiments, a row of memory strings can be selected via an up-select gate line, and multiple memory cells coupled to a word line in a memory string coupled to an up-select gate line (e.g., up-select gate line TSG0) can be defined as a page. In some embodiments, a memory cell coupled to a word line can include multiple pages, each of which is selected / deselected via a corresponding up-select gate line.

[0078] Figure 3C This is a schematic two-dimensional circuit diagram of an exemplary memory device of this application. (Refer to...) Figure 3CThe memory device includes multiple memory chips, and each memory chip includes multiple memory strings. Different memory strings within a memory chip are connected to corresponding bit lines via corresponding up-select transistors and to the array common source via corresponding down-select transistors. For example, the memory device includes memory chips str0, str1, str2, str3, str4, str5, str6, and str7. N different memory strings within the memory chips are connected to bit lines BL0 to BLN-1, where N is a natural number. Along the direction of the bit lines, each bit line is connected to a memory string in a different memory chip; for example, one bit line is connected to the second end of a memory string in memory chips str0, str1, str2, str3, str4, str5, str6, and str7. The gates of the top-select transistors in a memory string from memory chips str0 to str7 are respectively connected to top-select gate lines TSG0, TSG1, TSG2, TSG3, TSG4, TSG5, TSG6, and TSG7. The gates of the bottom-select transistors in a memory string from memory chips str0 to str7 are commonly connected to the bottom-select gate line BSG. That is, a memory cell coupled to a word line can include eight pages selected via corresponding top-select gate lines. Although Figure 3C The figure shows a number of 8 memory chips, but the number of memory chips can also be less than 8 or greater than 8, such as 4 or 10.

[0079] Figure 4 A cross-sectional schematic diagram of an exemplary memory cell array, including a memory string 308 exemplified by NAND, is shown according to some aspects of this application. Figure 4 As shown, the NAND memory cell array may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure perpendicularly penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and adjacent gate layers 411 are separated by an insulating layer 412.

[0080] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line.

[0081] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0082] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0083] Return to reference Figure 3BThe peripheral circuitry can be coupled to the memory cell array via bit line 316, word line 318, source line 314, lower select gate line 315, and upper select gate line 313. The peripheral circuitry can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory cell array by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, lower select gate line 315, and upper select gate line 313. The peripheral circuitry can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0084] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of this application. For example, Figure 5 Some exemplary peripheral circuitry of the memory device 300 is shown, including a page cache / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0085] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory cell array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage obtained from voltage generator 510.

[0086] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages obtained from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the lower select gate line 315 and the upper select gate line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to obtain word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0087] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0088] In some embodiments, the host 108 sends a read command (or read instruction, read request) to the memory controller 106 according to the current user command requirements. The memory controller 106 transmits the read control command, including information such as a logical address-physical address mapping table, to the memory device 104 through interface 516, controlling the memory device 104 to perform a read operation on the memory cell corresponding to the corresponding physical address. The memory device 104 then sends the read data back to the memory controller 106 through interface 516. The memory controller 106 then feeds the data back to the host 108 via an interface such as PCIe or SATA. Specifically, the memory controller 106 sends the read control command to the control logic of the memory device through interface 516. The control logic applies a relevant operating voltage to the selected word line or bit line according to the relevant physical address, thereby performing a read operation on the corresponding memory cell. The operating voltage can be generated by the control logic according to the relevant read voltage mapping table, controlled by a voltage generator, and then applied to the word line of the corresponding address after decoding by a row decoder, or applied to the bit line of the corresponding address after decoding by a column decoder.

[0089] In some embodiments, when the memory device 104 reads a corresponding memory cell under the control of the memory controller 106, a read error occurs. At this time, the memory controller 106 responds to the read operation failure by controlling the memory (or the error correction module in the memory controller 106). The error correction mode may include error correction code (ECC) error correction.

[0090] Figure 6 A schematic diagram illustrating an exemplary read operation flow of a memory system is shown. Combined with... Figure 6 As shown, when the memory controller controls the memory device to perform a read operation, it first performs a default read operation on the memory cell at the corresponding physical address. If the default read operation fails, a read retry operation is performed. If the read retry operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation stops and fails because it cannot correct errors. The memory controller sends a read fail signal to the host 108. The read retry operation and the default read operation can be applied to hard decode.

[0091] In some implementations, rereading is typically performed by querying a retry table provided by the manufacturer. Essentially, rereading is an error correction mechanism. The retry table provides a reference voltage for reading data. By querying the retry table, the system attempts to read each memory cell again with a voltage deviating from the normal threshold, and uses an ECC error correction algorithm to correct the error, attempting to read the data correctly. If the erroneous data is corrected, the querying of the retry table stops. If the erroneous data cannot be corrected, the querying of the retry table continues until the entire retry table is traversed.

[0092] In some embodiments, the memory cell array of the memory device 104 may include multiple memory blocks, each memory block including multiple word lines and multiple memory cells coupled to each word line. The multiple memory cells coupled to a certain word line in each memory block may serve as one or more physical pages. (See reference...) Figure 3A Multiple memory cells coupled to a single word line in a memory block can serve as six physical pages (corresponding to six memory chips). One of the six memory chips can be selected as the chosen physical page by selecting a single word line via an upper select gate line. The memory device 104 can perform programming (write) operations at the page level, programming all memory cells within the selected physical page. Depending on whether all physical pages in the memory block have been programmed, the memory block can be either a close block or an open block.

[0093] Due to the so-called background pattern effect, under the same read conditions, the threshold voltage of memory cells in an open block may shift compared to the threshold voltage of memory cells in a closed block due to differences in the total stored charge, parasitic capacitance, and charge coupling. For example, during a read operation, under the same read conditions, the threshold voltage of memory cells in a closed block may be higher than that of memory cells in an open block. The memory device 104 can set its internal read conditions (e.g., default read voltage) according to the closed block situation. When reading memory cells in an open block, applying the internal read conditions to the open block may cause more read errors due to the negative shift threshold voltage in the open block.

[0094] In some embodiments, the memory device 104 may read data of memory cells in a closed block according to a default read voltage or according to an offset read voltage that has an offset relative to the default read voltage, in order to reduce read errors, such as reducing failure bits.

[0095] Figure 9This is one of the schematic diagrams illustrating an exemplary set offset read voltage process for a memory device provided in this application. (Reference) Figure 9 To cover read operations in all open block scenarios, the multi-layer word lines of the open block need to be divided into multiple word line groups, each with a corresponding offset read voltage. The memory device is configured to set the offset read voltage. An exemplary process includes the following steps: Step S101: Start setting the offset read voltage; Step S102: Receive a read command; Step S103: Determine whether the block to be read is an open block based on the read command index; Step S104: Obtain the position of the last programmed page based on the open block; Step S105: Set the offset of the read voltage corresponding to the word line group based on the word line group to which the last programmed page belongs; Step S106: The offset read voltage setting ends, and the offset read voltage is the difference between the default read voltage and the offset.

[0096] As memory devices increase in storage capacity and integration density—for example, the number of stacked word lines (corresponding to the number of stacked memory cells) in NAND flash memory also increases—the reading of memory cells in open blocks becomes increasingly affected by background pattern effects. To cover read operations in all open block scenarios, it is necessary to divide the multi-layered word lines of the open block into multiple word line groups. The increasing number of word line groups in open blocks makes the logic for handling open block read operations increasingly complex, and the corresponding offset read voltage table (including the mapping relationship between word line groups and read voltage offsets) also becomes increasingly large. Therefore, finding a simple method to handle open block read operations is particularly important.

[0097] According to one or more of the above-mentioned problems, in a first aspect, embodiments of this application provide a memory device. The memory device includes: a memory cell array including a plurality of memory blocks; peripheral circuitry coupled to the memory cell array and configured to: perform a first read operation on memory cells comprising edge pages of the memory cell array in the memory cell array, based on the assumption that a block to be read among the plurality of memory blocks is an open block, using a first offset read voltage; the first offset read voltage having a first offset relative to a first read voltage; the first read voltage being a read voltage corresponding to the first read operation among the default read voltages of the memory cell array.

[0098] In this embodiment, based on the fact that the page to be read is an edge page of an open block, a first read operation is performed on the memory cells included in the edge page using a first offset read voltage. This simplifies the logic of the peripheral circuitry of the memory device in processing the first read operation of the open block, helping to reduce the complexity of the first read operation processing. For example, it helps to reduce the storage space occupied by the first offset table (including the mapping relationship between the first offset and the edge page) corresponding to the first offset read voltage, and helps to reduce the failure bit count of the first read operation. This embodiment does not require dividing the multi-layer word lines of the open block into multiple word line groups, avoiding the situation where the increasing number of word line groups in the open block makes the logic of the memory device in processing the open block's read operation increasingly complex.

[0099] Here and below, memory devices may be referred to Figure 1 , Figure 2A , Figure 2B For a better understanding of the memory device 104 shown, please refer to the relevant description. The memory cell array and peripheral circuits can be found separately. Figure 3B , Figure 5 Understand the relevant descriptions of the shown memory cell array and peripheral circuits.

[0100] In some embodiments, the memory device includes a three-dimensional NAND flash memory. The storage cells of the three-dimensional NAND flash memory chip include single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), and quadruple-level cells (QLC). Each storage cell from SLC to QLC can store 1, 2, 3, and 4 bits of data, respectively. Correspondingly, the voltage states of the NAND flash memory chip's storage cells are 2, 4, 8, and 16, respectively. Since the number of voltage states of the storage cells increases from 2 to 16 in the SLC mode to the QLC mode of the memory device, the increased number of different voltage states makes them more difficult to control, resulting in longer programming time, reduced read / write speeds, and decreased voltage state stability. Correspondingly, the theoretical number of erase / write cycles decreases. For example, the theoretical number of erase / write cycles (or the preset number of erase / write cycles) of the memory device in SLC, MLC, TLC, and QLC modes can be 100,000, 3,000 to 10,000, 500 to 1,000, and 150, respectively. Although some NAND flash memory chips may still be usable after exceeding the theoretical number of erase / write cycles, this has caused instability in the stored bit data.

[0101] In some embodiments, the memory cell array includes N-bit memory cells, where each N bit corresponds to an N-page. The N-bit memory cell reads its N bits of stored data via a Q-level read voltage; N and Q are both integers greater than 1, and Q = 2. N-1. The default read voltages for the memory device in SLC, MLC, TLC, and QLC modes are respectively the level 1 read voltage, level 3 read voltage, level 7 read voltage, and level 15 read voltage.

[0102] Figure 7 This is a schematic diagram illustrating the threshold voltage distribution corresponding to a memory cell with three memory bits, provided as an embodiment of this application. (Reference) Figure 7 Taking the default read voltage of the memory device in TLC mode as an example, with 7 read voltage levels, when the memory cell has 3 bits, the corresponding memory states include states 0 to 7. These 8 states are state 0 (also known as erase state) E, state 1 (also known as storage state) P1, state 2 (also known as storage state) P2... state 7 (also known as storage state) P7, and the binary data corresponding to these 8 states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages: the lower page (LP), the middle page (MP), and the upper page (UP).

[0103] Three-bit memory cells are read through 7 levels of voltage ( Figure 7 The diagram shows the first-level read voltage L1, second-level read voltage L2, third-level read voltage L3, fourth-level read voltage L4, fifth-level read voltage L5, sixth-level read voltage L6, and seventh-level read voltage L7, which read three bits of octet of stored data. Each page corresponds to multiple read voltage levels. The binary data corresponding to the next page is 10000111, and reading the next page requires the corresponding first-level read voltage L1 and fifth-level read voltage L5. The binary data corresponding to the middle page is 11001100, and reading the middle page requires the corresponding second-level read voltage L2, fourth-level read voltage L4, and sixth-level read voltage L6. The binary data corresponding to the previous page is 11100001, and reading the previous page requires the corresponding third-level read voltage L3 and seventh-level read voltage L7.

[0104] In TLC mode, the default read voltage for the memory device consists of seven levels: the first level read voltage L1 and the fifth level read voltage L5 for reading the next page; the second level read voltage L2, the fourth level read voltage L4, and the sixth level read voltage L6 for reading the middle page; and the third level read voltage L3 and the seventh level read voltage L7 for reading the previous page. The first read voltage is one of these seven levels. For example, a first read operation corresponding to reading a portion of the binary data of the next page using the first level read voltage L1 is called the first read voltage L1, and the first offset read voltage is the difference between the first level read voltage L1 and a first offset.

[0105] In some embodiments, the storage unit has N bits and 2^N bits. N One storage state; 2 N The storage states include erase state and 2. N -1 non-erasable state; where N is a positive integer; the default read voltage includes the first-level read voltage up to the second-level read voltage. N -1 level reading voltage 2 N -1 read voltage; the first read voltage is 2. N -1 of the read voltages; the first offset is associated with the first read voltage.

[0106] In some embodiments, the first read voltage is 2 N One of the -1 read voltages is used to determine the first offset as the first value; based on the first read voltage being 2... N -1 Read voltages that are different from one of the read voltages are used to determine a first offset, which is a second value different from the first value. For example, in the TLC mode of the memory device, in the read operation corresponding to the next page, the first read voltage is the first level read voltage L1, the first offset is the first value, and the first offset read voltage is the difference between the first level read voltage L1 and the first value of the first offset; in the read operation corresponding to the middle page, the first read voltage is the second level read voltage L2, the first offset is the second value, and the first offset read voltage is the difference between the second level read voltage L2 and the second value of the first offset, wherein the second value is less than the first value.

[0107] In some embodiments, the first offset is not related to the first read voltage, based on the first read voltage being 2. N For different levels of read voltages within a given read voltage range, the first offset value is the same. For example, in TLC mode, the default read voltages of a memory device are the first-level read voltage L1 to the seventh-level read voltage L7, and the first offset read voltage is the difference between one of the first-level read voltages L1 to the seventh-level read voltage L7 and the first offset value.

[0108] Figure 8A A schematic diagram of an open block with edge pages in a memory device provided in this application. Figure 8B This application provides a schematic diagram of an open block of a memory device having edge pages and inner pages. Figure 8C A schematic diagram of an open block having edge pages and internal pages for another memory device provided in this application.

[0109] refer to Figure 8A , Figure 8B and Figure 8CIn some embodiments, the open block includes at least one blank page and at least one programmed page; the memory cells included in the blank page are not programmed, while the memory cells included in the programmed page are programmed; at least one programmed page includes an edge page, which is adjacent to a blank page in the stacking direction of the block to be read. The stacking direction of the block to be read can be understood as the direction of extension of a memory string or the direction of stacking of multiple word lines.

[0110] A blank page consists entirely of memory cells in an erased state. A programmed page (or write page) consists of memory cells that are not all in an erased state (at least partially in a programmed state). An edge page can be represented as a word line in a programmed page that is adjacent to a blank page in the stacking direction of the block to be read.

[0111] In some embodiments, a closed block includes programming pages but does not include blank pages. The memory cells included in the programming pages have been programmed, and the programming pages do not include edge word lines. Because open blocks have edge pages, i.e., there are cases where blank pages are adjacent to programming pages, the threshold voltage of memory cells in open blocks will have a more complex threshold voltage offset compared to that in closed blocks due to the charge difference between the memory cells included in the programming pages and those included in the adjacent blank pages. The different positions of programming pages and blank pages in the memory block further complicate the threshold voltage offset.

[0112] For example, in conjunction with reference Figure 3C , Figure 8A , Figure 8B and Figure 8CThe open block includes an array of memory strings coupled to stacked word lines WL0, WL1, ..., WLn, WLn+1, and WLn+2. The memory string containing the memory cell coupled to each word line includes memory chips str0, str1, str2, str3, str4, str5, str6, and str7, selectable via corresponding up-select gate lines. Each word line can locate a page (or physical page) with memory chips str0 through str7. For example, word line WLn can locate pages PGn0, PGn1, PGn2, PGn3, PGn4, PGn5, PGn6, and PGn7 with memory chips str0 through str7, respectively. That is, the memory cell coupled to each word line is divided into pages PGn0 through PGn7, which can be independently read or programmed. The peripheral circuitry is configured to activate a selected memory chip within a selected word line via a selected up-select gate line during read and program operations. For example, the peripheral circuitry is configured to activate a selected memory chip str0 within a selected word line WL0 via a selected up-select gate line TSG0 during a read or program operation. Word line WL0 and memory chip str0 locate a page PG00, and read or program operations are performed on the memory cell coupled to page PG00. In practical applications, the number of word lines contained in a memory block can be adjusted according to actual needs, such as 16, 32, 64, 128, etc. In practical applications, the number of pages included in a memory cell coupled to a word line can be adjusted according to actual needs, such as 2, 4, 6, 8, 10, 12, etc.

[0113] For example, during programming operations, either the top word line or the bottom word line can be used as the starting programming word line; wherein the top word line and the bottom word line are located at opposite ends of the memory string, the top word line can be located at the end relatively closer to the bit line, and the bottom word line can be located at the end relatively farther from the bit line; in a programming word line, either the left end memory string or the right end memory string can be used as the starting programming page of that programming word line; wherein the top word lines of the left end memory string and the right end memory string are located at opposite ends of a column of memory strings connected to a bit line. Pages in a storage block can be indexed. In the case of a storage block comprising 8 memory chips, the storage unit coupled to a word line comprises 8 pages, with the index of the starting page PG00 as 0 and the index of the last page PGn+27 as (8*(n+3)-1), numbered sequentially according to the programming order of the pages (the order in which programming voltages are applied). For example, when n is 5, the storage block includes 8 word lines stacked from word line WL0 to word line WL7, and the storage block includes 64 pages with indices from 0 to 63; when n is 13, the storage block includes 16 word lines stacked from word line WL0 to word line WL15, and the storage block includes 128 pages with indices from 0 to 127; when n is 125, the storage block includes 128 word lines stacked from word line WL0 to word line WL127, and the storage block includes 1024 pages with indices from 0 to 1023; or, the storage block includes other numbers of pages with indexes.

[0114] For example, during programmatic writing, one can start writing sequentially from the page with index 0 to ensure that a single storage block can be filled, thus reducing addressing pressure. However, this only applies to physical addresses; logical addresses are not limited to contiguousness. (See reference) Figure 8B and Figure 8C For open blocks, the programming pages of an open block can correspond to consecutive physical addresses. A page adjacent to an unprogrammed blank page along the word line stacking direction (or memory string extension direction) within a programming page can be denoted as an edge page, and the remaining programming pages are denoted as inner pages. Optionally, the programming pages of an open block include edge pages but exclude inner pages (e.g., ...). Figure 8A As shown), unprogrammed blank pages in an open block can be referred to as blank pages. Taking a word-line coupled memory cell comprising 8 pages selected via corresponding up-select gate lines, and a memory block comprising 128 pages indexed from 0 to 127 as an example, refer to... Figure 8A Programming pages are pages with indices 0 to 2, and do not have internal pages; edge pages are pages with indices 0 to 2; blank pages are pages with indices 3 to 127; Reference Figure 8B Programming pages are pages with indices 0-115, internal pages are pages with indices 0-107, edge pages are pages with indices 108-115, and blank pages are pages with indices 116-127; Reference Figure 8CProgramming pages are pages with indices 0 to 123, internal pages are pages with indices 0 to 115 and 120 to 123, edge pages are pages with indices 116 to 119, and blank pages are pages with indices 124 to 127.

[0115] In some embodiments, edge pages and blank pages are adjacent along the word line stacking direction, and edge pages are most affected by blank pages. For example, the offset value of the threshold voltage of the memory cell of the edge page is greater than the offset value of the threshold voltage of the memory cell of the inner page.

[0116] In some embodiments, the peripheral circuitry can be configured to generate edge pages based on the position or index of the last program page in the open block. (See reference...) Figure 8A The last programmed page is the page with index 2, and the edge pages are the pages with indices 0 to 2; see reference. Figure 8B The final programming page is the page with index 115, and the edge pages are the pages with indexes 108 to 115; or, refer to... Figure 8C The final programming page is the page with index 123, and the edge pages are the pages with indexes 116 to 119.

[0117] Figure 10 This is a second schematic diagram illustrating an exemplary setting offset read voltage process for a memory device provided in this application. Figure 12 This is a schematic diagram illustrating the relationship between the self-word line index of an edge page coupled to an open block of a memory device provided in this application and a first offset voltage value.

[0118] refer to Figure 10 The peripheral circuit is also configured to perform the following steps: Step S201: Start setting the offset read voltage; Step S202: Receive a read command; Step S203: Determine whether the block to be read is an open block based on the read command index; Step S204: Determine whether the page to be read in the open block is an edge page based on the open block being an open block; Step S205: Select the first coefficient corresponding to the edge page based on the open block being an edge page; Step S206: Set the offset of the read voltage based on the first coefficient; Step S207: The offset read voltage setting ends, and the offset read voltage is used to perform a read operation on the memory cells included in the page to be read.

[0119] Reference Figure 10 and Figure 12 In some embodiments, the peripheral circuitry is configured to perform the following steps: steps S205 and S206, determining a first offset based on the number of programming pages and a first coefficient; the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; obtaining a first offset read voltage based on the difference between a first read voltage and the first offset.

[0120] In some embodiments, the peripheral circuitry can be configured to generate the number of programming pages based on the location of the last programming page in the open block. The location of the last programming page can be generated based on the index of the last programming page, referencing... Figure 8A The final programming page is the page with index 2, and the number of programming pages is 3. Alternatively, refer to... Figure 8B Finally, the programming page is the page with index 115, and the number of programming pages is 116.

[0121] In some embodiments, the first coefficient may be an empirical value; or it may be a default value configured at the time of manufacture of the memory device, which is obtained through a large number of simulation experiments before the memory device leaves the factory. In some embodiments, the range of the first coefficient is 5 to 25, preferably 10 to 20, and exemplaryly, the first coefficient is 11, 12, 13, 14, 15, 16, 17, 18, or 19.

[0122] refer to Figure 8B , Figure 10 and Figure 12 In some embodiments, the peripheral circuitry can be configured to obtain the value of the first offset by adding the ratio between the number of programming pages and a first coefficient to the value of the initial offset. For example, if the initial offset is RV, the number of programming pages is 116, and the first coefficient is 16, then the value of the first offset is initial RV + 116 / 16, and its unit is DAC, i.e., the first offset is (initial RV + 116 / 16)DAC. It can be understood that the physical meaning of the first coefficient is that for every 16 increases in the number of programming pages, the first offset increases by 1 DAC. The initial offset can be a default value configured at the factory of the memory device, which is obtained through extensive simulation experiments before the memory device leaves the factory. In some embodiments, the smallest unit for setting the first offset is 1 DAC (e.g., the conversion between DAC and millivolts (mV) is 1 DAC = 10 mV). Setting the first offset more finely helps to reduce the failure bit count of the first read operation.

[0123] In an alternative embodiment, the peripheral circuitry may be configured to determine a first offset based on the index of the word line coupled to the last programmed page in the open block and a first coefficient. (See reference...) Figure 8A Finally, the index of the word line WL0 coupled to the programming page is 0, see reference. Figure 8B Finally, the word line WLn+1 coupled to the programming page has an index of n+1. (See reference...) Figure 8CFinally, the word line WLn+2 of the programming page is indexed as n+2. For example, with Figure 8B For example, the initial offset value is initial RV, the index of the word line WLn+1 coupled to the last programming page is 116, and the first coefficient is 16. Then the value of the first offset is initial RV+116 / 16, and its unit is DAC. That is, the first offset is (initial RV+116 / 16)DAC. It can be understood that the physical meaning of the first coefficient is that for every 16 increases in the index of the word line coupled to the last programming page, the first offset increases by 1 DAC.

[0124] In some embodiments, the first offset table includes the number of programming pages and a mapping relationship between a first coefficient and a first offset. Peripheral circuitry can be configured to manage the first offset table, and the difference between a first read voltage and the first offset is used to read programming pages of the block to be read. Thus, when a first read operation is performed on memory cells included in an edge page of an open block, the first offset corresponding to the first read operation can be obtained based on the number of programming pages and the first offset table.

[0125] Figure 11 This is the third schematic diagram of an exemplary setting offset read voltage process for a memory device provided in this application.

[0126] refer to Figure 11 In some embodiments, the peripheral circuit is further configured to: perform a first correction on a first coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determine the first coefficient as a first value; perform a second correction on the first coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determine the first coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0127] The first and second preset intervals are two distinct and non-overlapping ranges within the theoretical erase / write cycle count range of a memory device. For example, the first preset interval can be understood as the range of erase / write cycles corresponding to the beginning of the memory device's product life (BOL), and the second preset interval can be understood as the range of erase / write cycles corresponding to the end of the memory device's product life (EOL). For instance, if the theoretical erase / write cycle count of a memory device in MLC mode is 3000, the first preset interval could be a range of 0–1000 cycles, and the second preset interval could be a range of 2000–3000 cycles; alternatively, the first preset interval could be a range of 100–800 cycles, and the second preset interval could be a range of 1500–2800 cycles.

[0128] In some embodiments, the value of the first coefficient may vary depending on the specific scenario of the memory device. The value of the first coefficient differs when the number of erase / write cycles is low, such as in early-stage reliability scenarios of the memory device, and when the number of erase / write cycles increases, such as in late-stage reliability scenarios of the memory device.

[0129] In some embodiments, different lifecycle (e.g., BOL / EOL) reliability scenarios of the memory device are associated with the first offset read voltage of the memory device. A corresponding first offset read voltage is generated for each different lifecycle stage of the memory device, reasonably balancing the reliability requirements of different lifecycle (e.g., BOL / EOL) scenarios. For example, in the BOL reliability scenario of the memory device, the first coefficient is a first value; in the EOL reliability scenario of the memory device, the first coefficient is a second value, wherein the first value is greater than the second value (e.g., the first value is 18 and the second value is 14).

[0130] refer to Figure 11In some embodiments, the peripheral circuit is further configured to perform the following steps: Step S301: Start setting the offset read voltage; Step S302: Receive a read command; Step S303: Determine whether the block to be read is an open block based on the read command index; Step S304: Based on whether the block to be read is an open block and whether the corresponding erase / write cycle count of the block to be read belongs to a first preset interval; Step S305: Based on whether the corresponding erase / write cycle count of the block to be read belongs to the first preset interval and whether the page to be read of the open block is an edge page; Step S306: Based on whether the page to be read of the open block is an edge page, select the first value of the first coefficient corresponding to the edge page; Step S307: Set the offset of the read voltage based on the first value of the first coefficient; Step S308: The offset read voltage setting ends, and the offset read voltage is used to perform a read operation on the memory cell included in the edge page.

[0131] refer to Figure 11 In some embodiments, the peripheral circuit is further configured to perform the following steps: Step S301: Start setting the offset read voltage; Step S302: Receive a read command; Step S303: Based on the read command index, determine whether the block to be read is an open block; Step S304: Based on whether the block to be read is an open block, and whether the corresponding erase / write cycle count of the block to be read belongs to a first preset interval; Step S310: Based on whether the corresponding erase / write cycle count of the block to be read does not belong to the first preset interval, i.e., the corresponding erase / write cycle count of the block to be read belongs to a second preset interval, and whether the page to be read of the open block is an edge page; Step S311: Based on whether the page to be read of the open block is an edge page, select the second value of the first coefficient corresponding to the edge page; Step S307: Set the offset of the read voltage based on the second value of the first coefficient; Step S308: The offset read voltage setting ends, and the offset read voltage is used to perform a read operation on the memory cells included in the page to be read.

[0132] Figure 14 This illustration shows an exemplary threshold voltage distribution in a first read operation and a second read operation of a memory device provided in this application.

[0133] refer to Figure 8B , Figure 10 and Figure 14 In some embodiments, the open block includes multiple programming pages; the multiple programming pages include edge pages and internal pages; the peripheral circuitry is further configured to: perform a second read operation on the memory cells included in the internal pages using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage in the default read voltages corresponding to the second read operation; wherein the second offset is less than a first offset.

[0134] refer to Figure 14 In the read operation that distinguishes between programming and erasing states, a read voltage V0 in the default read voltage is used to perform a read operation on the memory cells included in a closed block and a page; a first offset read voltage V1 is used to perform a first read operation on the memory cells included in an open block and an edge page, the first offset read voltage V1 having a first offset amount ΔV1 relative to the read voltage V0 in the default read voltage; a second offset read voltage V2 is used to perform a second read operation on the memory cells included in an open block and an inner page, the second offset read voltage V2 having a second offset amount ΔV2 relative to the read voltage V0 in the default read voltage; wherein, the second offset amount ΔV2 is less than the first offset amount ΔV1.

[0135] In some embodiments, the default read voltage includes the first-level read voltage up to the second-level read voltage. N -1 level reading voltage 2 N -1 read voltage; the second read voltage is the 2 N -1 is one of the read voltages, where N is a natural number. In some embodiments, the relationship between the second offset and the second read voltage can be understood with reference to the relationship between the first offset and the first read voltage described above, and will not be repeated here.

[0136] In this embodiment, it is not necessary to divide the multi-layer word lines of the open block into multiple word line groups. The first offset read voltage is used to perform the first read operation on the memory cells included in the edge page, and the second offset read voltage is used to perform the second read operation on the memory cells included in the inner page. This simplifies the logic of the peripheral circuit in processing the first read operation of the open block and helps to reduce the complexity of the first read operation. For example, it helps to reduce the storage space occupied by the corresponding first offset table (including the mapping relationship between the first offset and the edge page) and the second offset table (including the mapping relationship between the second offset and the inner page), and helps to reduce the failure bit count of the first read operation and the second read operation.

[0137] refer to Figure 10 In some embodiments, the peripheral circuit is further configured to perform the following steps: Step S201: Start setting the offset read voltage; Step S202: Receive a read command; Step S203: Index the block to be read according to the read command, and determine whether the block to be read is an open block; Step S204: If the block to be read is an open block, determine whether the page to be read in the open block is an edge page; Step S205: If the page to be read in the open block is not an edge page, i.e., the page to be read is an internal page, select the second coefficient corresponding to the internal page; Step S206: Set the offset of the read voltage according to the second coefficient; Step S207: The offset read voltage setting ends, and the offset read voltage is used to perform a read operation on the memory cells included in the page to be read.

[0138] Figure 13 This is a schematic diagram illustrating the relationship between the self-word line index of an internal page coupled in an open block of a memory device provided in this application and a second offset voltage value.

[0139] refer to Figure 10 and Figure 13 In some embodiments, the peripheral circuitry is configured to perform the following steps: S208 and S206, determining a second offset based on the number of programming pages and a second coefficient; the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; obtaining a second offset read voltage based on the difference between the second read voltage and the second offset.

[0140] In this embodiment of the application, the content related to the number of programming pages can be understood by referring to the content of the first coefficient mentioned above, and will not be repeated here.

[0141] In some embodiments, the second coefficient may be an empirical value; or it may be a default value configured at the time of manufacture of the memory device, which is obtained through extensive simulation experiments before the memory device leaves the factory. In some embodiments, the range of the second coefficient is 10 to 30, preferably 15 to 25, and exemplaryly, the second coefficient is 16, 17, 18, 19, 20, 21, 22, 23, or 24. In some embodiments, the value of the second coefficient is greater than the value of the first coefficient. For example, the second coefficient is 20, and the first coefficient is 16.

[0142] refer to Figure 8B , Figure 10 and Figure 13 In some embodiments, the peripheral circuitry can be configured to obtain the value of the second offset by adding the ratio between the number of programming pages and the second coefficient to the value of the initial offset. For example, if the initial offset is RV, the number of programming pages is 116, and the second coefficient is 20, then the value of the second offset is initial RV + 116 / 20, and its unit is DAC, i.e., the second offset is (initial RV + 116 / 20)DAC. It can be understood that the physical meaning of the second coefficient is that for every 20 increases in the number of programming pages, the second offset increases by 1 DAC. The minimum unit for setting the second offset is 1 DAC, and the conversion between DAC and millivolts (mV) can be 1 DAC = 10 mV. The details regarding the initial offset can be understood by referring to the first coefficient mentioned above, and will not be repeated here.

[0143] In some embodiments, the second offset table includes a mapping between the number of programming pages and a second coefficient and a second offset. Peripheral circuitry can be configured to manage the second offset table, and the difference between a second read voltage and the second offset is used to obtain a second offset read voltage for reading the memory cell coupled to the programming page of the block to be read.

[0144] refer to Figure 11 In some embodiments, the peripheral circuit is further configured to: perform a first correction on the second coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determine the second coefficient as a first value; perform a second correction on the second coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determine the second coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0145] In this embodiment, the relevant descriptions of the first preset interval and the second preset interval can be found in the above embodiments, and will not be repeated here.

[0146] In some embodiments, different lifecycle (e.g., BOL / EOL) reliability scenarios of the memory device are associated with a second offset read voltage of the memory device. A corresponding second offset read voltage is generated for each different lifecycle stage of the memory device, reasonably balancing the reliability requirements of different lifecycle (e.g., BOL / EOL) scenarios. For example, in the BOL reliability scenario of the memory device, the second coefficient is the first value; in the EOL reliability scenario of the memory device, the second coefficient is the second value, where the first value is greater than the second value (e.g., the first value is 22 and the second value is 18).

[0147] refer to Figure 11In some embodiments, the peripheral circuit is further configured to perform the following steps: Step S301: Start setting the offset read voltage; Step S302: Receive a read command; Step S303: Determine whether the block to be read is an open block based on the read command index; Step S304: Determine whether the corresponding erase / write cycle count of the block to be read belongs to a first preset interval based on the fact that the block to be read is an open block; Step S305: Determine whether the page to be read in the open block is an edge page based on the fact that the corresponding erase / write cycle count of the block to be read belongs to the first preset interval; Step S309: Select the first value of the second coefficient corresponding to the internal page based on the fact that the page to be read in the open block is not an edge page, i.e., the page to be read in the open block is an internal page; Step S307: Set the offset of the read voltage based on the first value of the second coefficient; Step S308: The offset read voltage setting ends, and the offset read voltage is used to perform a read operation on the memory cell included in the page to be read.

[0148] refer to Figure 11 In some embodiments, the peripheral circuit is further configured to perform the following steps: Step S301: Start setting the offset read voltage; Step S302: Receive a read command; Step S303: Determine whether the block to be read is an open block based on the read command index; Step S304: Determine whether the corresponding erase / write cycle count of the block to be read belongs to a first preset interval based on whether the block to be read is an open block; Step S310: Determine whether the corresponding erase / write cycle count of the block to be read belongs to a second preset interval based on whether the corresponding erase / write cycle count of the block to be read is an edge page based on whether the page to be read of the open block is an edge page; Step S312: Determine the second value of the second coefficient corresponding to the internal page based on whether the page to be read of the open block is an internal page based on whether the page to be read of the open block is an internal page; Step S307: Set the offset of the read voltage based on the second value of the second coefficient; Step S308: The offset read voltage setting ends, and the offset read voltage is used to perform read operations on multiple memory cells coupled to the programming page.

[0149] refer to Figure 11 In some embodiments, the peripheral circuit is further configured to: define a plurality of preset intervals according to a preset number of erase / write cycles of the memory device, wherein the plurality of preset intervals are M intervals from the first interval to the Mth interval; wherein the number of M intervals is positively correlated with the number of preset erase / write cycles; wherein M is a positive integer and M≥2.

[0150] For example, the preset number of erase / write cycles for a memory device is defined as three consecutive preset intervals, namely a first preset interval, a third preset interval, and a second preset interval. The interval values ​​of the first preset interval, the third preset interval, and the second preset interval can be the same or different. The first preset interval can be understood as the range of erase / write cycles corresponding to the BOL of the memory device, the second preset interval can be understood as the range of erase / write cycles corresponding to the EOL of the memory device, and the third preset interval can be understood as the range of erase / write cycles corresponding to the middle of life (MOL) of the memory device.

[0151] In some embodiments, different lifecycle (e.g., BOL / MOL / EOL) reliability scenarios of the memory device are associated with a first offset read voltage or a second offset read voltage of the memory device. A corresponding first offset read voltage or second offset read voltage is generated for each different lifecycle stage of the memory device, thus reasonably accommodating the reliability requirements of different lifecycle (e.g., BOL / MOL / EOL) scenarios of the memory device. For example, in the BOL reliability scenario of the memory device, the first coefficient is 18; in the MOL reliability scenario, the first coefficient is 16; and in the EOL reliability scenario, the first coefficient is 14.

[0152] refer to Figure 10 and Figure 11 In some embodiments, the peripheral circuitry is further configured to: determine a first offset or a second offset based on additional information; wherein the additional information includes whether the data stored in the memory cells included in the edge page or the inner page is in a hold-in state or an interference state.

[0153] In some embodiments, the different states (holding state or interference state) of the data stored in the memory device are associated with a first offset read voltage or a second offset read voltage of the memory device. A corresponding first offset read voltage or second offset read voltage is generated for each of the different states of the data stored in the memory device, reasonably accommodating the reliability requirements of scenarios where the stored data is in different states. For example, in a read operation, if the data stored in multiple memory cells coupled to the word line (select word line) in the open block of the memory device is in a holding state, a first coefficient is set to a third value; if the data stored in multiple memory cells coupled to the word line (select word line) in the open block of the memory device is in an interference state, a first coefficient is set to a fourth value; wherein the third value and the fourth value are different, and the first offset read voltage generated based on the third value and the fourth value is different according to the distribution.

[0154] refer to Figure 10and Figure 11 In some embodiments, the peripheral circuitry is further configured to: perform a third read operation on a memory cell included in a page of a block of memory, based on the fact that the block to be read among a plurality of memory blocks is a closed block; the third read voltage is a read voltage among default read voltages corresponding to the third read operation; and the memory cell included in any page of the closed block has been programmed.

[0155] In some embodiments, the default read voltage includes the first-level read voltage up to the second-level read voltage. N -1 level reading voltage 2 N -1 read voltage; the third read voltage is the 2 N -1 is one of the reading voltages, where N is a natural number.

[0156] refer to Figure 10 In some embodiments, the peripheral circuitry is further configured to perform the following steps: Step S201, start setting the offset read voltage; Step S202, receive a read command; Step S203, index the block to be read according to the read command, and determine whether the block to be read is an open block; Step S207, if the block to be read is not an open block, i.e., the block to be read is a closed block, the offset read voltage setting ends, and a third read operation is performed on the memory cells included in a page of the block to be read using a third read voltage. Alternatively, refer to... Figure 11 In some embodiments, the peripheral circuit is further configured to perform the following steps: Step S301, start setting the offset read voltage; Step S302, receive a read command; Step S303, index the block to be read according to the read command, and determine whether the block to be read is an open block; Step S308, if the block to be read is not an open block, i.e., the block to be read is a closed block, the offset read voltage setting ends, and a third read operation is performed on the memory cells included in a page of the block to be read using a third read voltage.

[0157] Secondly, embodiments of this application provide an operation method for a memory device, the operation method comprising: a peripheral circuit of the memory device coupled to a memory cell array of the memory device performing a first read operation on memory cells included in edge pages of a memory cell block to be read, based on the condition that a block to be read among a plurality of memory blocks in the memory cell array is an open block; the first offset read voltage having a first offset relative to a first read voltage; the first read voltage being a read voltage corresponding to the first read operation among the default read voltages of the block to be read.

[0158] In some embodiments, an open block includes at least one blank page and at least one programmed page; the storage units included in the blank page are not programmed, and the storage units included in the programmed page are programmed; at least one programmed page includes an edge page, which is adjacent to a blank page in the stacking direction of the block to be read.

[0159] In some embodiments, the operation method includes: determining a first offset based on the number of programming pages and a first coefficient; the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; and obtaining a first offset read voltage based on the difference between a first read voltage and the first offset.

[0160] In some embodiments, the operation method further includes: performing a first correction on a first coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determining the first coefficient as a first value; performing a second correction on the first coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determining the first coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0161] In some embodiments, the operation method further includes: performing a second read operation on the memory cells included in the internal page using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage in the default read voltages corresponding to the second read operation; wherein the second offset is less than a first offset; wherein the open block includes a plurality of programmed pages; the plurality of programmed pages include edge pages and internal pages.

[0162] In some embodiments, the operation method includes: determining a second offset based on the number of programming pages and a second coefficient; the second offset being positively correlated with the number of programming pages and negatively correlated with the second coefficient; and obtaining a second offset read voltage based on the difference between a second read voltage and the second offset.

[0163] In some embodiments, the operation method further includes: performing a first correction on a second coefficient based on a first preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals, and determining the second coefficient as a first value; performing a second correction on the second coefficient based on a second preset interval where the number of erase / write cycles corresponding to the block to be read falls within a plurality of preset intervals that is different from the first preset interval, and determining the second coefficient as a second value different from the first value; wherein each preset interval includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

[0164] In some embodiments, the operation method further includes: defining a plurality of preset intervals according to a preset number of erase / write cycles of the memory device, wherein the plurality of preset intervals are M intervals from the first interval to the Mth interval; wherein the number of M intervals is positively correlated with the number of preset erase / write cycles; wherein M is a positive integer and M≥2.

[0165] In some embodiments, the operation method further includes: determining a first offset or a second offset based on additional information; wherein the additional information includes whether the data stored in the storage unit included in the edge page or the inner page is in a hold-in state or a disturbed state.

[0166] In some embodiments, the method further includes: performing a third read operation on a memory cell included in a page of a block of a plurality of memory blocks, based on the fact that the block to be read is a closed block; the third read voltage is a read voltage corresponding to the third read operation among default read voltages; and the memory cell included in any page of the closed block has been programmed.

[0167] The memory device used in the operation method of the memory device provided in this application embodiment is the same as or similar to the memory device in the embodiments of the first aspect above. For technical features not disclosed in detail in this application embodiment, please refer to the memory device in the embodiments of the first aspect above for understanding, and will not be repeated here.

[0168] Figure 15 This is a schematic diagram of an exemplary composition of a memory system provided in an embodiment of this application.

[0169] Thirdly, embodiments of this application provide a memory system, with reference to Figure 15 The memory system 102 includes a memory device 104 and a memory controller 106 coupled to and controlling the memory device 104; the memory controller is configured to send a read command; the memory device is further configured to receive the read command and perform a first read operation on the memory cells included in the edge pages of the block to be read in the memory device using a first offset read voltage; the first offset read voltage has a first offset relative to a first read voltage; the first read voltage is a read voltage corresponding to the first read operation in the default read voltage of the block to be read.

[0170] Memory device 104 may be referenced Figure 1 , Figure 2A , Figure 2B Please refer to the description of the memory device 104 shown.

[0171] like Figure 15 As shown, in some specific embodiments, the memory system 102 is coupled to the host, responds to host instructions, and performs various feedback. The memory system 102 may include a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform read, write, erase, and other operations. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner.

[0172] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is the connection interface between the host 108 and the memory controller 106, allowing the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is the connection interface between the memory controller 106 and the memory device 104, and is used to implement data transfer between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory controller 106 as a whole. The specific steps performed by the memory controller mentioned above are mainly executed and completed by the control unit 1063. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU) or a microprocessor (MCU). The ROM 1069 typically contains the firmware (FW) or firmware program code of the memory controller 106. This code is used to initialize and operate the various components of the memory controller. The RAM 1070 is typically used to cache data. The error correction module 1064 may further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain verification data, and the decoding unit is used to decode the verification data to detect and correct possible erroneous data during data transmission. In some embodiments, the firmware may be a program stored in the electrically erasable programmable read-only memory (EEPROM) or FLASH chip of the memory system, and can be upgraded by the host through a specific refresh program. The firmware controls the read / write and transmission algorithms of the memory system and rationally allocates the storage of data.

[0173] In some embodiments, the memory system is configured to implement one or more methods of operating a memory device as provided in the second aspect via firmware. This allows for linear adjustment of the first offset without specifically distinguishing multiple word line groups, reducing the complexity of the firmware's algorithmic logic, decreasing code development difficulty, and simultaneously reducing the storage space occupied by the managed first offset table. This provides more granular management of the first offset for open blocks and reduces the failure bit count of the first read operation.

[0174] In some embodiments, the memory system 102 includes: one or more memory devices 104 of any of the first aspects; and a memory controller 106 coupled to and controlling the memory devices 104. In some embodiments, the memory device includes: a memory cell array including a plurality of memory blocks; peripheral circuitry coupled to the memory cell array; and configured to: perform a first read operation on memory cells comprising edge pages of a read block using a first offset read voltage, based on the condition that the block to be read among the plurality of memory blocks is an open block; the first offset read voltage has a first offset relative to a first read voltage; the first read voltage is a read voltage corresponding to the first read operation among the default read voltages of the block to be read.

[0175] In some embodiments, the memory controller is further configured to: send a first instruction; the first instruction instructs the acquisition of a first offset read voltage; the memory device is further configured to: receive the first instruction, acquire first information characterizing the first offset read voltage; and send second information characterizing the completion of acquiring the first information to the memory controller; the memory controller is further configured to: send a read command based on the second information; the memory device is further configured to: receive the read command, generate the first offset read voltage based on the first information, and control the memory device to perform a first read operation based on the first offset read voltage.

[0176] In some embodiments, the first instruction can be implemented via the Set Feature command.

[0177] In some embodiments, the memory controller is configured to: send a first instruction; the first instruction includes open block information; the open block information includes information characterizing that the block to be read is an open block, information characterizing that the page to be read in the block to be read is an edge page, and information characterizing that a first offset is associated with an edge page; the memory device is configured to: receive the first instruction, acquire first information characterizing a first offset read voltage based on the open block information, and send second information characterizing the acquisition of the first information to the memory controller.

[0178] In some embodiments, the memory controller is further configured to: send a read command; the read command includes a first instruction; the first instruction indicates acquiring a first offset read voltage; the memory device is further configured to: receive the read command, acquire first information characterizing the first offset read voltage; and generate the first offset read voltage based on the first information, and control the memory device to perform a first read operation based on the first offset read voltage. In some embodiments, a portion of the read command is used to set the first instruction; the first instruction can be implemented by setting a function command.

[0179] In some embodiments, the memory controller is configured to: send a read command; the read command includes a first instruction; the first instruction includes open block information; the open block information includes information indicating that the block to be read is an open block, information indicating that the page to be read in the block to be read is an edge page, and information indicating that a first offset is associated with the edge page; the memory device is configured to: receive the read command and obtain first information indicating a first offset read voltage based on the open block information.

[0180] In some embodiments, the open block information further includes information representing the number of programming pages in the block to be read and information representing a first coefficient; the information relating the first offset to the edge page includes information representing that the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; the memory device is configured to: determine information representing the first offset based on the information representing the number of programming pages and the information representing the first coefficient, and the information representing that the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; and obtain information representing the first offset read voltage based on the information representing the first read voltage and the information representing the first offset.

[0181] In some embodiments, the open block includes at least one blank page and at least one programmed page; the memory cells included in the blank page are not programmed, and the memory cells included in the programmed page are programmed; at least one programmed page includes an edge page, which is adjacent to a blank page in the stacking direction of the block to be read; the open block includes a plurality of programmed pages; the plurality of programmed pages include edge pages and inner pages; the memory device is further configured to: perform a second read operation on the memory cells included in the inner pages using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage in the default read voltage corresponding to the second read operation; wherein the second offset is less than a first offset.

[0182] In some embodiments, the open block information further includes information representing the number of programming pages in the block to be read and information representing a second coefficient; the information relating the second offset to the edge page includes information representing that the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; the memory device is configured to: determine information representing the second offset based on the information representing the number of programming pages and the information representing the second coefficient, and the information representing that the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; obtain information representing the second offset read voltage based on the information representing the second read voltage and the information representing the second offset; wherein the second offset is less than the first offset.

[0183] refer to Figure 15 and Figure 5 In some embodiments, in response to a restart of the memory system 102, the memory cell array 301 is scanned (e.g., ...). Figure 5 (As shown) or by restoring a backup copy of the open block information to initialize the open block information, wherein the open block information includes information that the block to be read is an open block, information that the pages to be read in the block to be read are edge pages, information about the number of programmed pages in the block to be read, information about a first coefficient, and information that a first offset is positively correlated with the number of programmed pages and negatively correlated with the first coefficient. In some embodiments, the host 108 (e.g. Figure 15 The block information (as shown) is configured to initialize open block information. In some embodiments, open block information for one or more open blocks from a plurality of storage blocks can be stored, for example, in register 514 (e.g., Figure 5 As shown in the figure. In some embodiments, the open block information can be updated by the control logic 512 during the programming operation of the memory cell array 301.

[0184] In some embodiments, the block to be read in a plurality of memory blocks is an open block, the page to be read in the block to be read is an edge page, the number of programmed pages in the block to be read, information of a first coefficient, and a first offset that is positively correlated with the number of programmed pages and negatively correlated with the first coefficient are used to determine information characterizing the first offset; information characterizing the first offset read voltage is obtained based on the information characterizing the first read voltage and the information characterizing the first offset; a first offset read voltage is generated based on the information characterizing the first offset read voltage, and a first read operation is performed on the memory cell in the block to be read using the first offset read voltage having a first offset relative to the first read voltage; wherein, the first read voltage is a read voltage corresponding to the first read operation among the default read voltages of the block to be read. For example, control logic 512 can determine the first offset based on open block information, determine the first offset read voltage based on the first offset and the first read voltage, control voltage generator 510 to provide the first offset read voltage, and control word line driver 508 to apply the first offset read voltage to the word line coupled to the memory cell in the open block.

[0185] In some embodiments, the open block information further includes information about a second coefficient, and information that the second offset is positively correlated with the number of programmed pages and negatively correlated with the second coefficient. In some embodiments, the block to be read in a plurality of memory blocks is an open block, the page to be read in the block to be read is an internal page, the number of programmed pages in the block to be read, the information about the second coefficient, and the information that the second offset is positively correlated with the number of programmed pages and negatively correlated with the second coefficient are used to determine information characterizing the second offset; information characterizing the second offset read voltage is obtained based on the information characterizing the second read voltage and the information characterizing the second offset; a second offset read voltage is generated based on the information characterizing the second offset read voltage, and a second read operation is performed on the memory cell in the block to be read using the second offset read voltage having a second offset relative to the second read voltage, wherein the second read voltage is a read voltage corresponding to the second read operation among the default read voltages of the block to be read. For example, control logic 512 can determine the second offset based on the open block information, determine the second offset read voltage based on the second offset and the second read voltage, control voltage generator 510 to provide the second offset read voltage, and control word line driver 508 to apply the second offset read voltage to the word line coupled to the memory cell in the open block.

[0186] In some embodiments, the block to be read among a plurality of memory blocks is a closed block, and a third read operation is performed on the memory cells included in the page to be read in the block to be read using a third read voltage, wherein the third read voltage is a read voltage corresponding to the third read operation among the default read voltages of the block to be read. For example, control logic 512 may determine the third read voltage, control voltage generator 510 to provide the third read voltage, and control word line driver 508 to apply the third read voltage to the word line coupled to the memory cell in the closed block.

[0187] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0188] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A memory device, characterized in that, include: A storage cell array, comprising multiple storage blocks, The peripheral circuitry, coupled to the memory cell array, is configured as follows: Based on the premise that the block to be read among the plurality of storage blocks is an open block, a first read operation is performed on the storage cells included in the edge pages of the block to be read using a first offset read voltage; the first offset read voltage has a first offset amount relative to the first read voltage; The first read voltage is a read voltage corresponding to the first read operation from the default read voltages of the block to be read.

2. The memory device according to claim 1, characterized in that, The open block includes at least one blank page and at least one programmed page; the storage units included in the blank page are not programmed, while the storage units included in the programmed page are programmed. The at least one programming page includes the edge page, which is adjacent to a blank page in the stacking direction of the block to be read.

3. The memory device according to claim 2, characterized in that, The peripheral circuit is configured as follows: The first offset is determined based on the number of programming pages and the first coefficient; the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient. The first offset read voltage is obtained based on the difference between the first read voltage and the first offset.

4. The memory device according to claim 3, characterized in that, The peripheral circuit is also configured to: Based on the first preset interval among multiple preset intervals where the corresponding erase / write cycle number of the block to be read falls, the first coefficient is firstly corrected to determine the first coefficient as a first value. Based on the fact that the number of erase / write cycles of the block to be read falls within a second preset interval that is different from the first preset interval among a plurality of preset intervals, the first coefficient is secondly corrected to determine that the first coefficient is a second value that is different from the first value. Each of the preset intervals includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

5. The memory device according to claim 2, characterized in that, The open block includes a plurality of programming pages; the plurality of programming pages include edge pages and internal pages; the peripheral circuitry is further configured to: A second read operation is performed on the memory cells included in the internal page using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage among the default read voltages corresponding to the second read operation; wherein the second offset is less than the first offset.

6. The memory device according to claim 5, characterized in that, The peripheral circuit is configured as follows: The second offset is determined based on the number of programming pages and the second coefficient; the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient. The second offset read voltage is obtained based on the difference between the second read voltage and the second offset.

7. The memory device according to claim 6, characterized in that, The peripheral circuit is also configured to: Based on the first preset interval among multiple preset intervals where the corresponding erase / write cycle number of the block to be read falls, the second coefficient is firstly corrected to determine the second coefficient as a first value. Based on the fact that the number of erase / write cycles of the block to be read falls within a second preset interval that is different from the first preset interval among the plurality of preset intervals, the second coefficient is modified in the second way to determine that the second coefficient is a second value that is different from the first value; Each of the preset intervals includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

8. The memory device according to claim 4 or claim 7, characterized in that, The peripheral circuit is also configured to: The plurality of preset intervals are defined according to the preset number of erase / write cycles of the memory device, and the plurality of preset intervals are M intervals from the first interval to the Mth interval; wherein, the number of the M intervals is positively correlated with the number of preset erase / write cycles; wherein, M is a positive integer and M≥2.

9. The memory device according to claim 5, characterized in that, The peripheral circuit is also configured to: The first offset or the second offset is determined based on additional information; wherein the additional information includes whether the data stored in the storage unit included in the edge page or the inner page is in a hold-in state or a disturbed state.

10. The memory device according to claim 2, characterized in that, The peripheral circuit is also configured to: Based on the premise that the block to be read among the plurality of storage blocks is a closed block, a third read operation is performed on the storage unit included in a page of the block to be read using a third read voltage; the third read voltage is a read voltage corresponding to the third read operation among the default read voltages; the storage unit included in any page of the closed block has been programmed.

11. The memory device according to claim 1, characterized in that, The storage unit has N bits and 2^N / N. N One storage state; the 2 N The storage states include erase state and 2. N -1 non-erasable states; where N is a positive integer; The default read voltage includes the first-level read voltage up to the second-level read voltage. N -1 level reading voltage 2 N -1 read voltage; the first read voltage is the 2 N -1 of the read voltages; the first offset is associated with the first read voltage.

12. The memory device according to claim 11, characterized in that, Based on the first read voltage, the 2 N -1 read voltage, determine the first offset as the first value; Based on the first read voltage, the 2 N -1 Reading voltages that are different from the first reading voltage, determine the first offset as a second value that is different from the first value.

13. A method of operating a memory device, characterized in that, include: The peripheral circuitry of the memory device, coupled to the memory cell array of the memory device, performs a first read operation on the memory cells included in the edge pages of the memory cell array based on the fact that the block to be read among the multiple memory blocks of the memory cell array is an open block, using a first offset read voltage; the first offset read voltage has a first offset amount relative to a first read voltage; The first read voltage is a read voltage corresponding to the first read operation from the default read voltages of the block to be read.

14. The operating method according to claim 13, characterized in that, The open block includes at least one blank page and at least one programmed page; the storage units included in the blank page are not programmed, while the storage units included in the programmed page are programmed. The at least one programming page includes the edge page, which is adjacent to a blank page in the stacking direction of the block to be read.

15. The operating method according to claim 14, characterized in that, The operation method includes: The first offset is determined based on the number of programming pages and the first coefficient; the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient. The first offset read voltage is obtained based on the difference between the first read voltage and the first offset.

16. The operating method according to claim 15, characterized in that, The operation method further includes: Based on the first preset interval among multiple preset intervals where the corresponding erase / write cycle number of the block to be read falls, the first coefficient is firstly corrected to determine the first coefficient as a first value. Based on the fact that the number of erase / write cycles of the block to be read falls within a second preset interval that is different from the first preset interval among a plurality of preset intervals, the first coefficient is secondly corrected to determine that the first coefficient is a second value that is different from the first value. Each of the preset intervals includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

17. The operating method according to claim 16, characterized in that, The operation method further includes: A second read operation is performed on the memory cells included in the internal page using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage among the default read voltages corresponding to the second read operation; wherein the second offset is less than the first offset; wherein the open block includes a plurality of the programming pages; the plurality of programming pages include the edge page and the internal page.

18. The operating method according to claim 17, characterized in that, The operation method includes: The second offset is determined based on the number of programming pages and the second coefficient; the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient. The second offset read voltage is obtained based on the difference between the second read voltage and the second offset.

19. The operating method according to claim 18, characterized in that, The operation method further includes: Based on the first preset interval among multiple preset intervals where the corresponding erase / write cycle number of the block to be read falls, the second coefficient is firstly corrected to determine the second coefficient as a first value. Based on the fact that the number of erase / write cycles of the block to be read falls within a second preset interval that is different from the first preset interval among the plurality of preset intervals, the second coefficient is modified in the second way to determine that the second coefficient is a second value that is different from the first value; Each of the preset intervals includes at least one number of erase / write cycles, and the average value of the preset interval is the average value of the number of erase / write cycles in the preset interval.

20. The operating method according to claim 16 or 19, characterized in that, The operation method further includes: The plurality of preset intervals are defined according to the preset number of erase / write cycles of the memory device, and the plurality of preset intervals are M intervals from the first interval to the Mth interval; wherein, the number of the M intervals is positively correlated with the number of preset erase / write cycles; wherein, M is a positive integer and M≥2.

21. The operating method according to claim 17, characterized in that, The operation method further includes: The first offset or the second offset is determined based on additional information; wherein the additional information includes whether the data stored in the storage unit included in the edge page or the inner page is in a hold-in state or a disturbed state.

22. The operating method according to claim 14, characterized in that, The operation method further includes: Based on the premise that the block to be read among the plurality of storage blocks is a closed block, a third read operation is performed on the storage unit included in a page of the block to be read using a third read voltage; the third read voltage is a read voltage corresponding to the third read operation among the default read voltages; the storage unit included in any page of the closed block has been programmed.

23. A memory system, characterized in that, Includes a memory device and a memory controller coupled to and controlling the memory device; The memory controller is configured to send read commands; The memory device is further configured to: receive the read command and perform a first read operation on the memory cells included in the edge pages of the block to be read in the memory device using a first offset read voltage; the first offset read voltage has a first offset relative to a first read voltage; The first read voltage is a read voltage corresponding to the first read operation from the default read voltages of the block to be read.

24. The memory system according to claim 23, characterized in that, The memory controller is further configured to: send a first instruction; the first instruction instructs to acquire a first offset read voltage; The memory device is further configured to: receive the first instruction and acquire first information characterizing the first offset read voltage; And send the second information, representing the completion of acquiring the first information, to the memory controller; The memory controller is also configured to send the read command based on the second information; The memory device is further configured to: receive the read command, generate the first offset read voltage based on the first information, and control the memory device to perform a first read operation based on the first offset read voltage.

25. The memory system according to claim 24, characterized in that, The memory controller is configured to: send the first instruction; the first instruction includes open block information; the open block information includes information indicating that the block to be read is an open block, information indicating that the page to be read in the block to be read is an edge page, and information indicating that a first offset is associated with the edge page; The memory device is configured to: receive the first instruction and obtain the first information characterizing the first offset read voltage based on the open block information; The second information, representing the completion of acquiring the first information, is then sent to the memory controller.

26. The memory system according to claim 23, characterized in that, The memory controller is further configured to: send the read command; the read command includes a first instruction; the first instruction indicates acquiring a first offset read voltage; The memory device is further configured to: receive the read command and acquire first information characterizing the first offset read voltage; as well as The first offset read voltage is generated based on the first information, and the memory device is controlled to perform a first read operation based on the first offset read voltage.

27. The memory system according to claim 26, characterized in that, The memory controller is configured to: send the read command; the read command includes the first instruction; the first instruction includes open block information; the open block information includes information indicating that the block to be read is an open block, information indicating that the page to be read in the block to be read is an edge page, and information indicating that a first offset is associated with the edge page; The memory device is configured to: receive the read command and obtain the first information representing the first offset read voltage based on the open block information.

28. The memory system according to claim 25 or 27, characterized in that, The open block information also includes information representing the number of programming pages in the block to be read and information representing the first coefficient; the information relating the first offset to the edge page includes information representing that the first offset is positively correlated with the number of programming pages and negatively correlated with the first coefficient; The memory device is configured to: determine information representing the first offset based on information representing the number of programming pages and information representing the first coefficient, as well as information representing the first offset being positively correlated with the number of programming pages and negatively correlated with the first coefficient; Information characterizing the first offset read voltage is obtained based on information characterizing the first read voltage and information characterizing the first offset.

29. The memory system according to claim 28, characterized in that, The open block includes at least one blank page and at least one programmed page; the storage units included in the blank page are not programmed, while the storage units included in the programmed page are programmed; the at least one programmed page includes the edge page, which is adjacent to one of the blank pages in the stacking direction of the block to be read; the open block includes a plurality of the programmed pages; the plurality of programmed pages include the edge page and an inner page; The memory device is also configured to: A second read operation is performed on the memory cells included in the internal page using a second offset read voltage; the second offset read voltage has a second offset relative to a second read voltage; the second read voltage is a read voltage among the default read voltages corresponding to the second read operation; wherein the second offset is less than the first offset.

30. The memory system according to claim 29, characterized in that, The open block information also includes information representing the number of programming pages in the block to be read and information representing the second coefficient; the information relating the second offset to the edge page includes information representing that the second offset is positively correlated with the number of programming pages and negatively correlated with the second coefficient; The memory device is configured to: determine information characterizing the second offset based on information characterizing the number of programming pages and information characterizing the second coefficient, as well as information characterizing the second offset as being positively correlated with the number of programming pages and negatively correlated with the second coefficient; Information representing the second offset read voltage is obtained based on information representing the second read voltage and information representing the second offset; wherein the second offset is less than the first offset.

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