Complementary field effect transistor circuit and its one-time programmable memory cell

Abstract

A complementary field-effect transistor (CFPT) circuit and its one-time programmable memory cell are disclosed. The CFPT circuit includes a first CFPT and a second CFPT. The first CFPT includes a first element and a second element. The second CFPT includes a third element and a fourth element. In the first one-time programmable memory cell, a first drain / source terminal of the second element is electrically connected to a bit line, and a gate terminal of the second element is electrically connected to a word line; a first drain / source terminal of the fourth element is electrically coupled to a second drain / source terminal of the second element, and a gate terminal of the fourth element is electrically connected to an antifuse control line.

Description

Technical Field

[0001] This invention relates to a memory cell for a non-volatile memory, and more particularly to a complementary field-effect transistor circuit and its one-time programmable memory cell. Background Technology

[0002] As is well known, non-volatile memory cells can be classified as: multi-time programmable memory cells (MTP cells), one-time programmable memory (OTP cells), or mask ROM cells.

[0003] Basically, users can program MTP memory cells multiple times and modify the stored data multiple times. Conversely, users can only program OTP memory cells once, and once the OTP memory cell is programmed, its stored data cannot be modified. As for Mask ROM memory cells, all stored data is already recorded in them after they leave the factory; users can only read the stored data in Mask ROM memory cells, but cannot program them.

[0004] For example, an antifuse-type OTP memory cell is in a high-resistance storage state before programming. After programming, it becomes a low-resistance storage state. Once programmed, the stored data in an antifuse-type OTP memory cell cannot be modified. Multiple antifuse-type OTP memory cells can be combined to form a programmable memory. Summary of the Invention

[0005] This invention relates to a complementary field-effect transistor (CFPT) circuit, comprising: a first CFPT including a first element, a second element, and an isolation structure; a second CFPT including a third element, a fourth element, and the isolation structure; wherein a first primary programming memory cell includes the second element and the fourth element; a second primary programming memory cell includes the first element and the third element; wherein the isolation structure extends in an XY plane, the first primary programming memory cell is located on one side of the isolation structure in the Z direction, and the second primary programming memory cell is located on the other side of the isolation structure in the Z direction; wherein in the first primary programming memory cell, a first drain / source terminal of the second element is electrically connected to a first bit line, and a gate terminal of the second element is electrically connected to a first word line; a first drain / source terminal of the fourth element is electrically coupled to a second drain / source terminal of the second element, and a gate terminal of the fourth element is electrically connected to a first antifuse control line.

[0006] This invention relates to a complementary field-effect transistor (CFPT) circuit, comprising: a first complementary field-effect transistor including a first element, a second element, and an isolation structure; wherein a one-time programmable memory cell includes: the first element and the second element; wherein the isolation structure extends in an XY plane, the first element is located on one side of the isolation structure in the Z direction, and the second element is located on the other side of the isolation structure in the Z direction; wherein, in the one-time programmable memory cell, a first drain / source terminal of the second element is electrically connected to a bit line, and a gate terminal of the second element is electrically connected to a word line; a first drain / source terminal of the first element is electrically connected to a second drain / source terminal of the second element, and a gate terminal of the first element is electrically connected to an antifuse control line.

[0007] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description

[0008] Figure 1A A schematic diagram of a P-type element in a CFET transistor;

[0009] Figure 1B This is a schematic diagram of the P-type element and insulating structure in a CFET transistor;

[0010] Figure 1C This is a schematic diagram of a CFET transistor;

[0011] Figure 1D This is a cross-sectional view of the gate structure of a CFET transistor along the dashed line ab.

[0012] Figure 1E This is a schematic diagram of another CFET transistor;

[0013] Figure 1F This is a schematic diagram of another CFET transistor;

[0014] Figure 2A This is the CFET circuit of the first embodiment of the present invention;

[0015] Figure 2B and Figure 2C This is a schematic diagram of the bias voltage and operation of the CFET transistor circuit in the first embodiment of the present invention for programming.

[0016] Figure 2D and Figure 2E This is a schematic diagram of the bias voltage and operation of the CFET transistor circuit in the first embodiment of the present invention for performing a read operation.

[0017] Figure 3 This is the CFET circuit of the second embodiment of the present invention;

[0018] Figure 4A This is the CFET circuit of the third embodiment of the present invention;

[0019] Figure 4B and Figure 4C This is a schematic diagram of the bias voltage and operation of the CFET transistor circuit in the third embodiment of the present invention for programming.

[0020] Figure 4D and Figure 4E This is a schematic diagram of the bias voltage and operation of the CFET transistor circuit for reading operations according to the third embodiment of the present invention.

[0021] Figure 5 This is the CFET circuit of the fourth embodiment of the present invention;

[0022] Figure 6 The CFET circuit of the fifth embodiment of the present invention; and

[0023] Figure 7 This is the CFET circuit of the sixth embodiment of the present invention.

[0024] [Symbol Explanation]

[0025] 200, 300, 400: CFET transistor circuits

[0026] 110, 122, 210, 230, 350, 410, 430, 450, 510, 530, 610, 710: P-type components

[0027] 130, 124, 220, 240, 360, 420, 440, 460, 520, 540, 620, 720: N-type components

[0028] 101, 103, 126, 131, 133, 211, 213, 221, 223, 233, 243, 353, 363, 411, 413, 421, 423, 433, 443, 453, 463, 513, 523, 533, 543, 611, 613, 621, 623, 711, 713, 721, 723: Drain / Source Structure

[0029] 102, 104, 132, 134, 212, 214, 222, 224, 232, 234, 242, 244, 352, 354, 362, 364, 412, 414, 422, 424, 432, 434, 442, 444, 452, 454, 462, 464, 512, 514, 522, 524, 532, 534, 542, 544, 612, 614, 622, 624, 712, 714, 722, 724: Nanosheets

[0030] 106, 108, 136, 138, 216, 218, 226, 228, 236, 238, 246, 248, 356, 358, 366, 368, 416, 418, 426, 428, 436, 438, 446, 448, 456, 458, 466, 468, 516, 518, 526, 528, 536, 538, 546, 548, 616, 618, 626, 628, 716, 718, 726, 728: Gate dielectric layer

[0031] 109, 139, 219, 229, 239, 249, 359, 369, 419, 429, 439, 449, 459, 469, 519, 529, 539, 549, 619, 629, 719, 729: Gate layer

[0032] 120, 290, 490, 690, 790: Isolation structures

[0033] 121, 691, 791: Conductors Detailed Implementation

[0034] This invention relates to a one-time programmable memory cell for non-volatile memory. Furthermore, the term "breakage" described herein may refer to quantum tunneling. Specifically, when the energy accumulated at the gate terminal of a CFET transistor reaches a certain level, quantum tunneling occurs. The energy accumulated at the gate terminal is released through the gate leakage path where quantum tunneling is taking place, thus generating a quantum tunneling current greater than a predetermined threshold. The mechanism of quantum tunneling can be similar to gate oxide breakdown, but is not limited to hard / destructive breakdown. For example, quantum tunneling can be a soft breakdown utilizing trap-assisted tunneling, but this invention is not limited to this. For ease of understanding, a CFET transistor that generates a quantum tunneling current greater than a predetermined threshold can be said to have a "broken" gate dielectric layer, while a CFET transistor that generates a quantum tunneling current less than a predetermined threshold (or does not undergo quantum tunneling) can be said to have a "unbroken" gate dielectric layer.

[0035] A complementary field-effect transistor (CFET) is a novel type of vertical transistor. A CFET consists of an N-type element and a P-type element. The CFET is formed on top of a semiconductor substrate, with the N-type and P-type elements stacked together to reduce the layout area of ​​the IC circuit. For example, the P-type element is located on top of the semiconductor substrate, and the N-type element is located on top of the P-type element. For ease of illustration, the semiconductor substrate is not shown in the following figures.

[0036] Please refer to Figure 1A The diagram shown is a schematic of a P-type element in a CFET transistor. Figure 1B This is a schematic diagram of the P-type element and the isolation structure in a CFET transistor. Figure 1C This is a schematic diagram of a CFET transistor. Figure 1D This is a cross-sectional view of the gate structure of a CFET transistor along the dashed line ab.

[0037] like Figure 1AAs shown, the P-type device 110 includes two drain / source structures 101 and 103, a gate structure, and two nanosheets 102 and 104. The gate structure surrounds the middle region of nanosheets 102 and 104. The middle region of nanosheets 102 and 104 can be regarded as the channel region of the P-type device 110.

[0038] Drain / source structure 101 is electrically connected to the first side region of nanosheets 102 and 104, and drain / source structure 103 is electrically connected to the second side region of nanosheets 102 and 104. That is, the first ends of nanosheets 102 and 104 are electrically connected to drain / source structure 101, and the second ends of nanosheets 102 and 104 are electrically connected to drain / source structure 103.

[0039] like Figure 1A and Figure 1D As shown, the gate structure of the P-type element 110 includes a gate layer 109 and gate dielectric layers 106 and 108. Gate dielectric layers 106 and 108 surround the middle regions of nanosheets 102 and 104, respectively. Furthermore, gate layer 109 surrounds gate dielectric layers 106 and 108, and gate layer 109 is not electrically connected to nanosheets 102 and 104.

[0040] As can be seen from the above description, the gate layer 109 can be used as the gate terminal of the P-type element 110, and the two drain / source structures 101 and 103 can be used as the two drain / source terminals of the P-type element 110.

[0041] Furthermore, the nanosheets 102 and 104 in the P-type element 110 have various doping modes. For example, the first and second side regions of nanosheets 102 and 104 are P-doped regions, and the middle region of nanosheets 102 and 104 is an undoped region. Alternatively, the middle region of nanosheets 102 and 104 is a P-doped region, and the first and second side regions of nanosheets 102 and 104 are undoped regions. Or, all regions of nanosheets 102 and 104 are P-doped regions.

[0042] like Figure 1BAs shown, an insulating structure 120 is located above the P-type element 110. This insulating structure 120 can be used to electrically isolate the P-type element 110 and the N-type element of the CFET transistor. Of course, if multiple CFET transistors are fabricated simultaneously on the semiconductor substrate, this insulating structure 120 can be used to electrically isolate the P-type element and the N-type element of all CFET transistors. In some embodiments, the insulating structure 120 is used to isolate the P-type element 110 and the N-type element in the Z direction, that is, the insulating structure 120 does not contact the semiconductor substrate. The insulating structure 120 extends along the XY plane above the semiconductor substrate, such that the P-type element 110 and the N-type element are located on opposite sides of the insulating structure 120 in the Z direction.

[0043] like Figure 1C As shown, the CFET transistor includes a P-type element 110, an insulating structure 120, and an N-type element 130. The N-type element 130 is located above the insulating structure 120. The N-type element 130 includes two drain / source structures 131 and 133, a gate structure, and two nanosheets 132 and 134. The gate structure surrounds the middle region of nanosheets 132 and 134. The middle region of nanosheets 132 and 134 can be considered as the channel region of the N-type element 130.

[0044] Drain / source structure 131 is electrically connected to the first side region of nanosheets 132 and 134, and drain / source structure 133 is electrically connected to the second side region of nanosheets 132 and 134. That is, the first ends of nanosheets 132 and 134 are electrically connected to drain / source structure 131, and the second ends of nanosheets 132 and 134 are electrically connected to drain / source structure 133.

[0045] like Figure 1C and Figure 1D As shown, the gate structure of the N-type device 130 includes a gate layer 139 and gate dielectric layers 136 and 138. Gate dielectric layers 136 and 138 surround the middle regions of nanosheets 132 and 134, respectively. Furthermore, gate layer 139 surrounds gate dielectric layers 136 and 138, and gate layer 139 does not make electrical contact with nanosheets 132 and 134.

[0046] As can be seen from the above description, the gate layer 139 can be used as the gate terminal of the N-type element 130, and the two drain / source structures 131 and 133 can be used as the two drain / source terminals of the N-type element 130.

[0047] Similarly, the nanosheets 132 and 134 in the N-type device 130 have various doping modes. For example, the first and second side regions of nanosheets 132 and 134 are N-doped regions, and the middle region of nanosheets 132 and 134 is an undoped region. Alternatively, the middle region of nanosheets 132 and 134 is an N-doped region, and the first and second side regions of nanosheets 132 and 134 are undoped regions. Or, all regions of nanosheets 132 and 134 are N-doped regions.

[0048] like Figure 1C As shown, the P-type element 110 and the N-type element 130 are isolated by the insulating structure 120, so the P-type element 110 and the N-type element 130 are not in contact with each other. That is to say, the two drain / source structures 101 and 131 are isolated by the insulating structure 120 and are not in electrical contact, the two drain / source structures 103 and 133 are isolated by the insulating structure 120 and are not in electrical contact, and the two gate structures are isolated by the insulating structure 120 and are not in electrical contact.

[0049] In the above description, the P-type element 110 of the CFET transistor includes two nanosheets 102 and 104, and the N-type element 130 includes two nanosheets 132 and 134. In fact, those skilled in the art can design any number of nanosheets in the P-type element 110 and the N-type element 130, as long as the number of nanosheets is greater than or equal to 1.

[0050] In fact, a CFET transistor is not limited to having one P-type element and one N-type element. That is, a CFET transistor can also be composed of two stacked N-type elements or two stacked P-type elements.

[0051] In addition, in some applications of CFET transistors, the following will be used: Figure 1C The drain / source structure 101 of the P-type element 110 is electrically connected to the drain / source structure 131 of the N-type element 130. That is, one drain / source terminal of the P-type element 110 is electrically connected to one drain / source terminal of the N-type element 130.

[0052] At this time, as Figure 1E Another CFET transistor shown can be designed with a wire 121 electrically connected to the drain / source structure 101 of the P-type element 110 and the drain / source structure 131 of the N-type element 130. Alternatively, as... Figure 1F Another CFET transistor is shown, in which part of the insulating structure 120 is etched away to form a shared drain / source structure 126. That is, the P-type element 122 and the N-type element 124 share the drain / source structure 126, which means that the drain / source structure of the P-type element 122 is electrically connected to the drain / source structure of the N-type element.

[0053] This invention utilizes multiple CFET transistors to form a CFET transistor circuit (hereinafter referred to as a CFET circuit), and the CFET transistor circuit includes at least one OTP memory cell. Furthermore, the OTP memory cell of this invention is an antifuse type OTP memory cell. In the following embodiments, the CFET transistors in the CFET transistor circuit are described as P-type elements with two nanosheets and N-type elements with two nanosheets. Of course, this invention is not limited to this; it is permissible as long as the number of nanosheets in each element is greater than or equal to one.

[0054] Please refer to Figure 2A The diagram illustrates a CFET circuit according to a first embodiment of the present invention. The CFET transistor circuit 200 of the first embodiment includes two CFET transistors. Furthermore, to facilitate understanding of the structure of the CFET transistor circuit 200, only the insulating structure 290 shown by diagonal lines between the two gate structures of each CFET transistor is depicted in the CFET transistor circuit 200; the insulating structure 290 is not shown in other parts. In fact, similar to... Figure 1C The drain / source structure of each CFET transistor is also isolated by the insulating structure 290.

[0055] In the CFET transistor circuit 200, the first CFET transistor includes a P-type element 210 and an N-type element 220. The second CFET transistor includes a P-type element 230 and an N-type element 240. Furthermore, the P-type elements 210 and 230 are located below the isolation structure 290, and the N-type elements 220 and 240 are located above the isolation structure 290. Additionally, the structures of all CFET transistors in the first embodiment of the CFET transistor circuit 200 are similar to... Figure 1C The following only briefly describes the connection relationship of these CFET transistors, without going into detail about their structure.

[0056] According to a first embodiment of the present invention, the CFET transistor circuit 200 includes two OTP memory cells, Cell1 and Cell2. OTP memory cell Cell1 includes N-type elements 220 and 240. OTP memory cell Cell2 includes P-type elements 210 and 230. Each OTP memory cell, Cell1 and Cell2, can store one bit of data. That is, Figure 2A The CFET transistor circuit 200 can store two bits of data.

[0057] In the OTP memory cell Cell1, an N-type element 220 serves as the selection element. The N-type element 220 includes two drain / source structures 221 and 223, a gate structure, and two nanosheets 222 and 224. The gate structure includes a gate layer 229 and gate dielectric layers 226 and 228. The first ends of the nanosheets 222 and 224 are electrically connected to the drain / source structure 221, and the second ends of the nanosheets 222 and 224 are electrically connected to the drain / source structure 223. Furthermore, the gate layer 229 is electrically connected to the word line WL1, and the drain / source structure 221 is electrically connected to the bit line BL1.

[0058] The N-type element 240 serves as an antifuse element. The N-type element 240 includes two drain / source structures 223 and 243, a gate structure, and two nanosheets 242 and 244. The gate structure includes a gate layer 249 and gate dielectric layers 246 and 248. The first ends of the nanosheets 242 and 244 are electrically connected to the drain / source structure 223, and the second ends of the nanosheets 242 and 244 are also electrically connected to the drain / source structure 243. The two N-type elements 220 and 240 share the drain / source structure 223. Furthermore, the gate layer 249 is electrically connected to the antifuse control line (AF1).

[0059] As explained above, in the OTP memory cell Cell1, the first drain / source terminal of the N-type element 220 is electrically connected to the bit line BL1, and the gate terminal of the N-type element 220 is electrically connected to the word line WL1. Furthermore, the first drain / source terminal of the N-type element 240 is electrically coupled to the second drain / source terminal of the N-type element 220, and the gate terminal of the N-type element 240 is electrically connected to the antifuse control line AF1.

[0060] In the OTP memory cell Cell2, a P-type element 210 serves as the selection element. The P-type element 210 includes two drain / source structures 211 and 213, a gate structure, and two nanosheets 212 and 214. The gate structure includes a gate layer 219 and gate dielectric layers 216 and 218. The first ends of the nanosheets 212 and 214 are electrically connected to the drain / source structure 211, and the second ends of the nanosheets 212 and 214 are electrically connected to the drain / source structure 213. Furthermore, the gate layer 219 is electrically connected to the word line WL2, and the drain / source structure 211 is electrically connected to the bit line BL2.

[0061] P-type element 230 serves as an antifuse element. P-type element 230 includes two drain / source structures 213 and 233, a gate structure, and two nanosheets 232 and 234. The gate structure includes a gate layer 239 and gate dielectric layers 236 and 238. The first ends of nanosheets 232 and 234 are electrically connected to the drain / source structure 213, and the second ends of nanosheets 232 and 234 are electrically connected to the drain / source structure 233. The two P-type elements 210 and 230 share the drain / source structure 213. Furthermore, the gate layer 239 is electrically connected to the antifuse control line AF2.

[0062] According to embodiments of the present invention, in an OTP memory cell, when the gate oxide layer of the antifuse element is intact, the internal resistance of the antifuse element is high, and the OTP memory cell is in an intact state. Conversely, when the gate oxide layer of the antifuse element is ruptured, the internal resistance of the antifuse element is low, and the OTP memory cell is in a ruptured state. For example, the ruptured state can be considered as storing logic "1", and the intact state can be considered as storing logic "0".

[0063] Please refer to Figure 2B and Figure 2C The diagram shows the bias voltage and operation of the CFET transistor circuit in the first embodiment of the present invention during programming. Figure 2D and Figure 2E This is a schematic diagram of the bias voltage and operation of the CFET transistor circuit in the first embodiment of the present invention for the read action. Since the operating principles of the two OTP memory cells Cell1 and Cell2 are similar, the programming and read actions of the CFET transistor circuit 200 will be described below using OTP memory cell Cell1 as an example.

[0064] like Figure 2B As shown, during programming, bit line BL1 receives ground voltage (0V), and word line WL1 receives on-voltage (V). ON And the antifuse control line AF1 receives the programming voltage V. PGM For example, the programming voltage V PGM The voltage range is between 3V and 6V, and the turn-on voltage is V. ON The voltage range is between 0.4V and 3V.

[0065] In the OTP memory cell Cell1, when the select element (i.e., N-type element 220) is turned on, the ground voltage (0V) received by the bit line BL1 is transmitted to the nanosheets 242 and 244 of the antifuse element (i.e., N-type element 240), causing the voltage stress on the two gate dielectric layers 246 and 248 of the antifuse element (i.e., N-type element 240) to be equal to the programming voltage V. PGM Therefore, this will cause one of the two gate dielectric layers 246 and 248 to rupture, resulting in a large programming current I. PGM This allows the OTP memory cell Cell1 to be programmed into a broken state. The programming current I0 PGM The flow from the anti-fuse control line AF1 through the anti-fuse element (i.e., N-type element 240) and the selector element (i.e., N-type element 220) to the position line BL1.

[0066] exist Figure 2B During the programming process, the gate dielectric layer 246 cracked, causing the OTP memory cell Cell1 to become cracked. Alternatively, the gate dielectric layer 248 could also crack during the programming process, causing the OTP memory cell Cell1 to become cracked.

[0067] like Figure 2C During programming, bit line BL1 receives ground voltage (0V), and word line WL1 receives off voltage (V). OFF The antifuse control line AF1 receives the programming voltage V. PGM For example, the off voltage V OFF It is 0V.

[0068] In the OTP memory cell Cell1, with the select element (i.e., N-type element 220) off, the ground voltage (0V) received by the bit line BL1 cannot be transmitted to the nanosheets 242 and 244 of the antifuse element (i.e., N-type element 240), thus the two gate dielectric layers 246 and 248 of the antifuse element (i.e., N-type element 240) are not subjected to voltage stress. Therefore, the two gate dielectric layers 246 and 248 will not rupture, and the programming current I... PGM The value is almost zero, which keeps the OTP memory cell Cell1 in an unbroken state.

[0069] Of course, during programming, other bias voltages can be provided to keep the OTP memory cell Cell1 in an unbroken state. For example, during programming, the antifuse control line AF1 and the bit line BL1 receive ground voltage (0V), and the word line WL1 receives the turn-on voltage V. ON This can also keep the OTP memory cell Cell1 in an unbroken state.

[0070] like Figure 2D and 2E As shown in the figure, during the read operation, bit line BL1 receives the ground voltage (0V), and word line WL1 receives the turn-on voltage V. ON The antifuse control line AF1 receives and reads the voltage V. RD For example, reading the voltage V RD The voltage range is between 0.75V and 1.2V.

[0071] like Figure 2D As shown, the selector (i.e., N-type element 220) is turned on, and the antifuse (i.e., N-type element 240) is broken. Therefore, a large read current I is generated in the OTP memory cell Cell1. RD The flow from the anti-fuse control line AF1 through the anti-fuse element (i.e., N-type element 240) and the selection element (i.e., N-type element 220) to the position line BL1.

[0072] like Figure 2E As shown, the selector element (i.e., N-type element 220) is turned on, and the antifuse element (i.e., N-type element 240) is in an unbroken state. Therefore, a small (almost zero) read current I is generated in the OTP memory cell Cell1. RD .

[0073] As explained above, after the programming operation is completed, the reading operation can be performed using the reading current I on bit line BL1. RD The size determines the storage state of the OTP memory cell Cell1. For example, a current comparator is provided to receive the read current I. RD And the reference current Iref. When reading the current I... RD When the current is greater than the reference current Iref, the OTP memory cell Cell1 is considered broken. Conversely, when the read current I... RD When the current is less than the reference current Iref, the OTP memory cell Cell1 is determined to be in an unbroken state.

[0074] In the CFET transistor circuit 200 of the first embodiment, N-type elements 220 and 240 form OTP memory cell Cell1, and P-type elements 210 and 230 form OTP memory cell Cell2. However, the present invention is not limited to this. For example, in the CFET transistor circuit 200 of the first embodiment, all elements 210, 220, 230, and 240 are N-type elements, and both OTP memory cells Cell1 and Cell2 are composed of N-type elements. Alternatively, in the CFET transistor circuit 200 of the first embodiment, all elements 210, 220, 230, and 240 are P-type elements, and both OTP memory cells Cell1 and Cell2 are composed of P-type elements.

[0075] Please refer to Figure 3 The diagram illustrates a CFET circuit according to a second embodiment of the present invention. Compared to the first embodiment, the CFET transistor circuit 300 of the second embodiment adds one more CFET transistor. The newly added CFET transistor includes a P-type element 350 and an N-type element 360. The connection relationship of the newly added CFET transistor will only be described below, and the rest will not be described in detail.

[0076] According to a second embodiment of the present invention, the CFET transistor circuit 300 includes two OTP memory cells, Cell1 and Cell2. OTP memory cell Cell1 includes N-type elements 220, 240, and 360. OTP memory cell Cell2 includes P-type elements 210, 230, and 350. Each OTP memory cell, Cell1 or Cell2, can store one bit of data. That is, Figure 3 The CFET transistor circuit 300 can store two bits of data.

[0077] In the OTP memory cell Cell1, an N-type element 360 serves as the selection element. The N-type element 360 includes two drain / source structures 243 and 363, a gate structure, and two nanosheets 362 and 364. The gate structure includes a gate layer 369 and gate dielectric layers 366 and 368. The first ends of the nanosheets 362 and 364 are electrically connected to the drain / source structure 243, and the second ends of the nanosheets 362 and 364 are electrically connected to the drain / source structure 363. Furthermore, the gate layer 369 is electrically connected to the word line WL1, and the drain / source structure 363 is electrically connected to the bit line BL1. Additionally, the two N-type elements 240 and 360 share the drain / source structure 243.

[0078] In the OTP memory cell Cell2, a P-type element 350 serves as the selection element. The P-type element 350 includes two drain / source structures 233 and 353, a gate structure, and two nanosheets 352 and 354. The gate structure includes a gate layer 359 and gate dielectric layers 356 and 358. The first ends of the nanosheets 352 and 354 are electrically connected to the drain / source structure 233, and the second ends of the nanosheets 352 and 354 are electrically connected to the drain / source structure 353. Furthermore, the gate layer 359 is electrically connected to the word line WL2, and the drain / source structure 353 is electrically connected to the bit line BL2. Additionally, the two P-type elements 230 and 350 share the drain / source structure 233.

[0079] As can be seen from the above description, in the OTP memory cell Cell1, the first drain / source terminal of the N-type element 360 is electrically coupled to the second drain / source terminal of the N-type element 240, the second drain / source terminal of the N-type element 360 is electrically connected to the bit line BL1, and the gate terminal of the N-type element 360 is electrically connected to the word line WL1.

[0080] Furthermore, the bias voltage for programming and reading operations of the CFET transistor circuit 300 in the second embodiment is similar to that of the CFET transistor circuit 200 in the first embodiment, and will not be described again here.

[0081] In the CFET transistor circuit 300 of the second embodiment, OTP memory cell Cell1 is composed of N-type elements 220, 240, and 360, and OTP memory cell Cell2 is composed of P-type elements 210, 230, and 350. However, the invention is not limited to this. For example, in the CFET transistor circuit 300 of the second embodiment, all elements 210, 220, 230, 240, 350, and 360 are N-type elements, and both OTP memory cells Cell1 and Cell2 are composed of N-type elements. Alternatively, in the CFET transistor circuit 300 of the second embodiment, all elements 210, 220, 230, 240, 350, and 360 are P-type elements, and both OTP memory cells Cell1 and Cell2 are composed of P-type elements.

[0082] Please refer to Figure 4A The diagram illustrates a CFET circuit according to a third embodiment of the present invention. The CFET transistor circuit 400 of the third embodiment includes three CFET transistors. Similarly, in the CFET transistor circuit 400, only the insulating structure 490 shown by the diagonal line between the two gate structures of each CFET transistor is drawn; the insulating structure 490 is not shown in other parts.

[0083] In the CFET transistor circuit 400, the first CFET transistor includes a P-type element 410 and an N-type element 420. The second CFET transistor includes a P-type element 430 and an N-type element 440. The third CFET transistor includes a P-type element 450 and an N-type element 460. Furthermore, the P-type elements 410, 430, and 450 are located below the isolation structure 490, and the N-type elements 420, 440, and 460 are located above the isolation structure 490. Additionally, the structure of all CFET transistors in the third embodiment of the CFET transistor circuit 400 is similar to... Figure 1C CFET transistors.

[0084] According to a third embodiment of the present invention, the CFET transistor circuit 400 includes two OTP memory cells. OTP memory cell Cell1 includes N-type elements 420, 440, and 460. OTP memory cell Cell2 includes P-type elements 410, 430, and 450. Each OTP memory cell, Cell1 or Cell2, can store one bit of data. That is, Figure 4A The CFET transistor circuit 400 can store two bits of data.

[0085] In the OTP memory cell Cell1, an N-type element 420 serves as the selection element. The N-type element 420 includes two drain / source structures 421 and 423, a gate structure, and two nanosheets 422 and 424. The gate structure includes a gate layer 429 and gate dielectric layers 426 and 428. Furthermore, the gate layer 429 is electrically connected to the word line WL1, and the drain / source structure 421 is electrically connected to the bit line BL1.

[0086] The N-type element 440 serves as a following element. The N-type element 440 includes two drain / source structures 423 and 443, a gate structure, and two nanosheets 442 and 444. The gate structure includes a gate layer 449 and gate dielectric layers 446 and 448. Furthermore, the gate layer 449 is electrically connected to the following control line (FL1).

[0087] The N-type element 460 serves as an antifuse element. The N-type element 460 includes two drain / source structures 443 and 463, a gate structure, and two nanosheets 462 and 464. The gate structure includes a gate layer 469 and gate dielectric layers 466 and 468. Furthermore, the gate layer 469 is electrically connected to the antifuse control line AF1.

[0088] As explained above, in the OTP memory cell Cell1, the first drain / source terminal of N-type element 420 is electrically connected to BL1, and the gate terminal of N-type element 420 is electrically connected to WL1. The first drain / source terminal of N-type element 460 is electrically coupled to the second drain / source terminal of N-type element 420, and the gate terminal of N-type element 460 is electrically connected to the antifuse control line AF1. Furthermore, the first drain / source terminal of N-type element 460 is electrically coupled to the second drain / source terminal of N-type element 420 via N-type element 440. The first drain / source terminal of N-type element 440 is electrically connected to the second drain / source terminal of N-type element 420, the second drain / source terminal of N-type element 440 is electrically connected to the first drain / source terminal of N-type element 460, and the gate terminal of N-type element 440 is electrically connected to the follower control line FL1.

[0089] In the OTP memory cell Cell2, a P-type element 410 serves as the selection element. The P-type element 410 includes two drain / source structures 411 and 413, a gate structure, and two nanosheets 412 and 414. The gate structure includes a gate layer 419 and gate dielectric layers 416 and 418. Furthermore, the gate layer 419 is electrically connected to the word line WL2, and the drain / source structure 411 is electrically connected to the bit line BL2.

[0090] The P-type element 430 serves as a follower element. The P-type element 430 includes two drain / source structures 413 and 433, a gate structure, and two nanosheets 432 and 434. The gate structure includes a gate layer 439 and gate dielectric layers 436 and 438. Furthermore, the gate layer 439 is electrically connected to the follower control line FL2.

[0091] The P-type element 450 serves as an antifuse element. The P-type element 450 includes two drain / source structures 433 and 453, a gate structure, and two nanosheets 452 and 454. The gate structure includes a gate layer 459 and gate dielectric layers 456 and 458. Furthermore, the gate layer 459 is electrically connected to the antifuse control line AF2.

[0092] Please refer to Figure 4B and Figure 4C The diagram shown is a schematic diagram of the bias voltage and operation of the CFET transistor circuit in the third embodiment of the present invention during programming. Figure 4D and Figure 4E This is a schematic diagram of the bias voltage and operation of the CFET transistor circuit for reading operations according to the third embodiment of the present invention. Since the operating principles of the two OTP memory cells Cell1 and Cell2 are similar, the programming and reading operations of the CFET transistor circuit 400 will be described below using OTP memory cell Cell1 as an example.

[0093] like Figure 4B As shown, during programming, bit line BL1 receives the ground voltage (0V), and word line WL1 receives the turn-on voltage V. ON The control line FL1 receives the conduction voltage (V). CD The antifuse control line AF1 receives the programming voltage V. PGM For example, the programming voltage V PGM The voltage range is between 3V and 6V, and the on-state voltage V CD The voltage range is between 0.4V and 3V, and the turn-on voltage is V. ON The voltage range is between 0.4V and 3V.

[0094] In the OTP memory cell Cell1, the select element (i.e., N-type element 420) is turned on, and the follower element (i.e., N-type element 440) is in the conducting state. The ground voltage (0V) received by the bit line BL1 is transmitted to the nanosheets 462 and 464 of the antifuse element (i.e., N-type element 460), so that the voltage stress on the two gate dielectric layers 466 and 468 of the antifuse element (i.e., N-type element 460) is the programming voltage V. PGM Therefore, this will cause one of the two gate dielectric layers, 466 and 468, to crack, resulting in a large programming current I. PGM This allows the OTP memory cell Cell1 to be programmed into a broken state. The programming current I0 PGM The anti-fuse control line AF1 flows to the position line BL1 via the anti-fuse element (i.e., N-type element 460), the follower element (i.e., N-type element 440), and the selector element (i.e., N-type element 420).

[0095] exist Figure 4B During the programming process, the gate dielectric layer 468 cracked, causing the OTP memory cell Cell1 to become cracked. Alternatively, the gate dielectric layer 466 could also crack during the programming process, causing the OTP memory cell Cell1 to become cracked.

[0096] like Figure 4C During programming, bit line BL1 receives ground voltage (0V), and word line WL1 receives shutdown voltage V. OFF Follow the control line FL1 to receive the turn-on voltage V CD The antifuse control line AF1 receives the programming voltage V. PGM For example, the off voltage V OFF It is 0V.

[0097] In OTP memory cell Cell1, when the select element (i.e., N-type element 420) is off, the ground voltage (0V) received by bit line BL1 cannot be transmitted to the nanosheets 462 and 464 of the antifuse element (i.e., N-type element 460). This means the two gate dielectric layers 466 and 468 of the antifuse element (i.e., N-type element 460) are not subjected to voltage stress, so the two gate dielectric layers 466 and 468 will not crack, and the programming current I... PGM The value is almost zero, which keeps the OTP memory cell Cell1 in an unbroken state.

[0098] Of course, during programming, other bias voltages can be provided to keep the OTP memory cell Cell1 in an unbroken state. For example, during programming, the antifuse control line AF1 and bit line BL1 receive ground voltage (0V), and the follower control line FL1 receives the turn-on voltage V. CD The word line WL1 receives the turn-on voltage V. ON This can also keep the OTP memory cell Cell1 in an unbroken state.

[0099] like Figure 4D and 4E As shown in the figure, during the read operation, bit line BL1 receives the ground voltage (0V), and word line WL1 receives the turn-on voltage V. ON Follow the control line FL1 to receive the turn-on voltage V CD The antifuse control line AF1 receives and reads the voltage V. RD For example, reading the voltage V RD The voltage range is between 0.75V and 1.2V.

[0100] like Figure 4D As shown, the select element (i.e., N-type element 420) is turned on, the follower element (i.e., N-type element 440) is in the on state, and the antifuse element (i.e., N-type element 460) is in the broken state. Therefore, a large read current I is generated in the OTP memory cell Cell1. RD The anti-fuse control line AF1 flows to the position line BL1 via the anti-fuse element (i.e., N-type element 460), the follower element (i.e., N-type element 440), and the selector element (i.e., N-type element 420).

[0101] like Figure 4E As shown, the select element (i.e., N-type element 420) is turned on, the follower element (i.e., N-type element 440) is in the on state, and the antifuse element (i.e., N-type element 460) is in the unbroken state. Therefore, a small (almost zero) read current I is generated in the OTP memory cell Cell1. RD .

[0102] As explained above, after the programming operation is completed, the reading operation can be performed using the reading current I on bit line BL1. RD The size determines the storage state of the OTP memory cell Cell1.

[0103] In the CFET transistor circuit 400 of the third embodiment, OTP memory cell Cell1 is composed of N-type elements 420, 440, and 460, and OTP memory cell Cell2 is composed of P-type elements 410, 430, and 450. However, the present invention is not limited to this. For example, in the CFET transistor circuit 400 of the third embodiment, all elements 410, 420, 430, 440, 450, and 460 are N-type elements, and both OTP memory cells Cell1 and Cell2 are composed of N-type elements. Alternatively, in the CFET transistor circuit 400 of the third embodiment, all elements 410, 420, 430, 440, 450, and 460 are P-type elements, and both OTP memory cells Cell1 and Cell2 are composed of P-type elements.

[0104] Please refer to Figure 5 The diagram illustrates a CFET circuit according to a fourth embodiment of the present invention. Compared to the third embodiment, the CFET transistor circuit 500 of the fourth embodiment adds two CFET transistors. The first newly added CFET transistor includes a P-type element 510 and an N-type element 520; the second newly added CFET transistor includes a P-type element 530 and an N-type element 540. The connection relationship of the newly added CFET transistors will only be described below; other details will not be elaborated further.

[0105] According to a fourth embodiment of the present invention, the CFET transistor circuit 500 includes two OTP memory cells, Cell1 and Cell2. OTP memory cell Cell1 includes N-type elements 420, 440, 460, 520, and 540. OTP memory cell Cell2 includes P-type elements 410, 430, 450, 510, and 530. Each OTP memory cell, Cell1 or Cell2, can store one bit of data. That is, Figure 5 The CFET transistor circuit 500 can store two bits of data.

[0106] In the OTP memory cell Cell1, an N-type element 520 serves as a follower element. The N-type element 520 includes two drain / source structures 463 and 523, a gate structure, and two nanosheets 522 and 524. The gate structure includes a gate layer 529 and gate dielectric layers 526 and 528. The first ends of the nanosheets 522 and 524 are electrically connected to the drain / source structure 463, and the second ends of the nanosheets 522 and 524 are electrically connected to the drain / source structure 523. Furthermore, the gate layer 529 is electrically connected to the follower control line FL1. Additionally, the two N-type elements 520 and 560 share the drain / source structure 463.

[0107] N-type element 540 serves as the selection element. N-type element 540 includes two drain / source structures 523 and 543, a gate structure, and two nanosheets 542 and 544. The gate structure includes a gate layer 549 and gate dielectric layers 546 and 548. The first ends of nanosheets 542 and 544 are electrically connected to the drain / source structure 523, and the second ends of nanosheets 542 and 544 are electrically connected to the drain / source structure 543. Furthermore, the gate layer 549 is electrically connected to word line WL1, and the drain / source structure 543 is electrically connected to bit line BL1. Additionally, the two N-type elements 520 and 540 share the drain / source structure 523.

[0108] In the OTP memory cell Cell2, a P-type element 510 serves as a follower element. The P-type element 510 includes two drain / source structures 453 and 513, a gate structure, and two nanosheets 512 and 514. The gate structure includes a gate layer 519 and gate dielectric layers 516 and 518. The first ends of the nanosheets 512 and 514 are electrically connected to the drain / source structure 453, and the second ends of the nanosheets 512 and 514 are electrically connected to the drain / source structure 513. Furthermore, the gate layer 519 is electrically connected to the follower control line FL2. Additionally, the two P-type elements 510 and 510 share the drain / source structure 453.

[0109] P-type element 530 serves as the selection element. P-type element 530 includes two drain / source structures 513 and 533, a gate structure, and two nanosheets 532 and 534. The gate structure includes a gate layer 539 and gate dielectric layers 536 and 538. The first ends of nanosheets 532 and 534 are electrically connected to the drain / source structure 513, and the second ends of nanosheets 532 and 534 are electrically connected to the drain / source structure 533. Furthermore, the gate layer 539 is electrically connected to word line WL2, and the drain / source structure 533 is electrically connected to bit line BL2. Additionally, the two P-type elements 510 and 530 share the drain / source structure 513.

[0110] As explained above, in the OTP memory cell Cell1, the second drain / source terminal of N-type element 540 is electrically connected to BL1, and the gate terminal of N-type element 540 is electrically connected to WL1. The second drain / source terminal of N-type element 460 is electrically coupled to the first drain / source terminal of N-type element 540. Furthermore, the second drain / source terminal of N-type element 460 is electrically coupled to the first drain / source terminal of N-type element 540 via N-type element 520. The first drain / source terminal of N-type element 520 is electrically connected to the second drain / source terminal of N-type element 460, the second drain / source terminal of N-type element 520 is electrically connected to the first drain / source terminal of N-type element 540, and the gate terminal of N-type element 520 is electrically connected to the follower control line FL1.

[0111] Furthermore, the bias voltage for programming and reading operations of the CFET transistor circuit 500 in the fourth embodiment is similar to that of the CFET transistor circuit 400 in the third embodiment, and will not be described again here.

[0112] In the CFET transistor circuit 500 of the fourth embodiment, OTP memory cell Cell1 is composed of N-type elements 420, 440, 460, 520, and 540, and OTP memory cell Cell2 is composed of P-type elements 410, 430, 450, 510, and 530. However, the present invention is not limited to this. For example, in the CFET transistor circuit 500 of the fourth embodiment, all elements 410, 420, 430, 440, 450, 460, 510, 520, 530, and 540 are N-type elements, and both OTP memory cells Cell1 and Cell2 are composed of N-type elements. Alternatively, in the fourth embodiment, all components 410, 420, 430, 440, 450, 460, 510, 520, 530, and 540 in the CFET transistor circuit 500 are P-type components, and the two OTP memory cells Cell1 and Cell2 are both composed of P-type components.

[0113] Please refer to Figure 6 The diagram illustrates a CFET circuit according to a fifth embodiment of the present invention. The CFET transistor circuit of the fifth embodiment includes only one CFET transistor. The CFET transistor includes a P-type element 610 and an N-type element 620. An insulating structure 690 electrically isolates the P-type element 610 and the N-type element 620. That is, the OTP memory cell includes a P-type element 610 and an N-type element 620, and the OTP memory cell can store one bit of data.

[0114] In the OTP memory cell, an N-type element 620 serves as the selection element. The N-type element 620 includes two drain / source structures 621 and 623, a gate structure, and two nanosheets 622 and 624. The gate structure includes a gate layer 629 and gate dielectric layers 626 and 628. The first ends of the nanosheets 622 and 624 are electrically connected to the drain / source structure 621, and the second ends of the nanosheets 622 and 624 are electrically connected to the drain / source structure 623. Furthermore, the gate layer 629 is electrically connected to the word line WL, and the drain / source structure 621 is electrically connected to the bit line BL.

[0115] The P-type element 610 serves as an antifuse element. The P-type element 610 includes two drain / source structures 611 and 613, a gate structure, and two nanosheets 612 and 614. The gate structure includes a gate layer 619 and gate dielectric layers 616 and 618, with the gate layer 619 electrically connected to the antifuse control line AF. Furthermore, the first ends of the nanosheets 612 and 614 are electrically connected to the drain / source structure 611, and the second ends of the nanosheets 612 and 614 are electrically connected to the drain / source structure 613.

[0116] According to a fifth embodiment of the present invention, in the OTP memory cell, wire 691 is electrically connected to the drain / source structure 613 of the P-type element 610 and the drain / source structure 623 of the N-type element 620. Of course, in other embodiments, the P-type element 610 and the N-type element 620 may also share a drain / source structure.

[0117] As explained above, in the OTP memory cell, the first drain / source terminal of the N-type element 620 is electrically connected to the bit line BL, and the gate terminal of the N-type element 620 is electrically connected to the word line WL. The first drain / source terminal of the P-type element 610 is electrically connected to the second drain / source terminal of the N-type element 620, and the gate terminal of the P-type element 610 is electrically connected to the antifuse control line AF.

[0118] Furthermore, the bias voltage for programming and reading operations of the CFET transistor circuit in the fifth embodiment is similar to that of the CFET transistor circuit 200 in the first embodiment, and will not be described again here.

[0119] In the CFET transistor circuit of the fifth embodiment, the OTP memory cell is composed of N-type elements 620 and P-type elements 610. However, the invention is not limited to this. For example, in the CFET transistor circuit of the fifth embodiment, all elements 610 and 620 are N-type elements, and the OTP memory cell is composed entirely of N-type elements. Alternatively, in the CFET transistor circuit of the fifth embodiment, all elements 610 and 620 are P-type elements, and the OTP memory cell is composed entirely of P-type elements.

[0120] Please refer to Figure 7 The diagram illustrates a CFET circuit according to a sixth embodiment of the present invention. The CFET transistor circuit of the sixth embodiment includes only one CFET transistor. The CFET transistor includes a P-type element 710 and an N-type element 720. An insulating structure 790 electrically isolates the P-type element 710 and the N-type element 720. That is, the OTP memory cell includes a P-type element 710 and an N-type element 720, and the OTP memory cell can store one bit of data.

[0121] In the OTP memory cell, a P-type element 710 serves as the selection element. The P-type element 710 includes two drain / source structures 711 and 713, a gate structure, and two nanosheets 712 and 714. The gate structure includes a gate layer 719 and gate dielectric layers 716 and 718. The first ends of the nanosheets 712 and 714 are electrically connected to the drain / source structure 711, and the second ends of the nanosheets 712 and 714 are electrically connected to the drain / source structure 713. Furthermore, the gate layer 719 is electrically connected to the word line WL, and the drain / source structure 711 is electrically connected to the bit line BL.

[0122] The N-type element 720 serves as an antifuse element. The N-type element 720 includes two drain / source structures 721 and 723, a gate structure, and two nanosheets 722 and 724. The gate structure includes a gate layer 729 and gate dielectric layers 726 and 728, with the gate layer 729 electrically connected to the antifuse control line AF. Furthermore, the first ends of the nanosheets 722 and 724 are electrically connected to the drain / source structure 721, and the second ends of the nanosheets 722 and 724 are electrically connected to the drain / source structure 723.

[0123] According to a sixth embodiment of the present invention, in the OTP memory cell, wires 791 are electrically connected to the drain / source structure 713 of the P-type element 710 and the drain / source structure 723 of the N-type element 720. Of course, in other embodiments, the P-type element 710 and the N-type element 720 may also share a drain / source structure.

[0124] As explained above, in the OTP memory cell, the first drain / source terminal of the P-type element 710 is electrically connected to the bit line BL, and the gate terminal of the P-type element 710 is electrically connected to the word line WL. The first drain / source terminal of the N-type element 720 is electrically connected to the second drain / source terminal of the P-type element 710, and the gate terminal of the N-type element 720 is electrically connected to the antifuse control line AF.

[0125] Furthermore, the bias voltage for programming and reading operations of the CFET transistor circuit in the sixth embodiment is similar to that of the CFET transistor circuit 200 in the first embodiment, and will not be described again here.

[0126] In the CFET transistor circuit of the sixth embodiment, the OTP memory cell is composed of N-type elements 720 and P-type elements 710. However, the invention is not limited to this. For example, in the CFET transistor circuit of the sixth embodiment, all elements 710 and 720 are N-type elements, and the OTP memory cell is composed entirely of N-type elements. Alternatively, in the CFET transistor circuit of the sixth embodiment, all elements 710 and 720 are P-type elements, and the OTP memory cell is composed entirely of P-type elements.

[0127] As described above, this invention proposes a CFET circuit and its OTP memory cell. During programming, an appropriate bias voltage can be provided to control the OTP memory cell to be in a broken or unbroken state. Furthermore, during reading, an appropriate bias voltage can be provided to cause the OTP memory cell to generate a read current I. RD And based on the read current I RD The size of the OTP memory cell determines its storage state.

[0128] Furthermore, in the CFET transistor circuits 200, 300, 400, and 500 of the first to fourth embodiments, insulating structures 290 and 490 are used to isolate the two OTP memory cells Cell1 and Cell2. Those skilled in the art can program only one OTP memory cell without programming the other. For example, in CFET transistor circuit 200, only OTP memory cell Cell1 is programmed, while OTP memory cell Cell2 is not programmed, and OTP memory cell Cell2 is used as a fake OTP cell. This significantly increases the difficulty of cracking the data stored in the non-volatile memory.

[0129] Similarly, dummy OTP memory cells can also be used in the CFET transistor circuits of the fifth to sixth embodiments. For example, multiple memory cells of the fifth embodiment are fabricated on two regions of a semiconductor substrate. During programming, only the OTP memory cells in the first region are programmed, while the OTP memory cells in the second region are not programmed, and the OTP memory cells in the second region are used as dummy memory cells. In this way, the difficulty of cracking the data stored in the non-volatile memory can be significantly increased.

[0130] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.

Claims

1. A complementary field-effect transistor circuit, comprising: The first complementary field-effect transistor includes a first element, a second element, and an isolation structure; The second complementary field-effect transistor includes a third element, a fourth element, and the isolation structure; The first primary programmable memory cell includes the second element and the fourth element; the second primary programmable memory cell includes the first element and the third element. The isolation structure extends in the XY plane, the first primary programming memory cell is located on one side of the isolation structure in the Z direction, and the second primary programming memory cell is located on the other side of the isolation structure in the Z direction. In the first primary programmable memory cell, the first drain / source terminal of the second element is electrically connected to the first bit line, and the gate terminal of the second element is electrically connected to the first word line; the first drain / source terminal of the fourth element is electrically coupled to the second drain / source terminal of the second element, and the gate terminal of the fourth element is electrically connected to the first antifuse control line.

2. The complementary field-effect transistor circuit as claimed in claim 1, wherein the second element is a first selection element, and the fourth element is a first antifuse element; in, The first selection element includes a first drain / source terminal, a second drain / source terminal, a first nanosheet, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds the middle region of the first nanosheet, and the first gate layer surrounds the first gate dielectric layer; the first drain / source terminal is electrically contacted to a first side region of the first nanosheet, and the second drain / source terminal is electrically contacted to a second side region of the first nanosheet; and the first drain / source terminal is electrically connected to the first bit line, and the first gate layer is electrically connected to the first word line; as well as The first antifuse element includes a second drain / source terminal, a third drain / source terminal, a second nanosheet, and a second gate structure; the second gate structure includes a second gate dielectric layer and a second gate layer; the second gate dielectric layer surrounds the middle region of the second nanosheet, and the second gate layer surrounds the second gate dielectric layer; the second drain / source terminal is electrically contacted to a first side region of the second nanosheet, and the third drain / source terminal is electrically contacted to a second side region of the second nanosheet; and the second gate layer is electrically connected to the first antifuse control line.

3. The complementary field-effect transistor circuit as claimed in claim 2, wherein during programming, the first bit line receives a ground voltage, the first word line receives an enable voltage, and the first antifuse control line receives a programming voltage; the first select element is enabled, and the voltage stress on the second gate dielectric layer is the programming voltage; and the second gate dielectric layer breaks, causing the first primary programming memory cell to become broken.

4. The complementary field-effect transistor circuit of claim 1, wherein in the second primary programmable memory cell, the first drain / source terminal of the first element is electrically connected to the second bit line, and the gate terminal of the first element is electrically connected to the second word line; the first drain / source terminal of the third element is electrically coupled to the second drain / source terminal of the first element, and the gate terminal of the third element is electrically connected to the second antifuse control line.

5. The complementary field-effect transistor circuit as described in claim 1, further comprising: A third complementary field-effect transistor includes a fifth element, a sixth element, and the isolation structure; wherein the first primary programming memory cell further includes the sixth element, and the second primary programming memory cell further includes the fifth element; in the first primary programming memory cell, the first drain / source terminal of the sixth element is electrically connected to the second drain / source terminal of the fourth element, the second drain / source terminal of the sixth element is electrically connected to the first bit line, and the gate terminal of the sixth element is electrically connected to the first word line; and in the second primary programming memory cell, the first drain / source terminal of the fifth element is electrically connected to the second drain / source terminal of the third element, the second drain / source terminal of the fifth element is electrically connected to the second bit line, and the gate terminal of the fifth element is electrically connected to the second word line.

6. The complementary field-effect transistor circuit as claimed in claim 5, wherein the second element is a first selection element, the fourth element is a first antifuse element, and the sixth element is a second selection element; in, The first selection element includes a first drain / source terminal, a second drain / source terminal, a first nanosheet, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds the middle region of the first nanosheet, and the first gate layer surrounds the first gate dielectric layer; the first drain / source terminal is electrically contacted to a first side region of the first nanosheet, and the second drain / source terminal is electrically contacted to a second side region of the first nanosheet; and the first drain / source terminal is electrically connected to the first bit line, and the first gate layer is electrically connected to the first word line; The first antifuse element includes a second drain / source terminal, a third drain / source terminal, a second nanosheet, and a second gate structure. The second gate structure includes a second gate dielectric layer and a second gate layer. The second gate dielectric layer surrounds the middle region of the second nanosheet, and the second gate layer surrounds the second gate dielectric layer. The second drain / source terminal is electrically contacted to a first side region of the second nanosheet, and the third drain / source terminal is electrically contacted to a second side region of the second nanosheet. The second gate layer is electrically connected to the first antifuse control line. The second selection element includes a third drain / source terminal, a fourth drain / source terminal, a third nanosheet, and a third gate structure; the third gate structure includes a third gate dielectric layer and a third gate layer; the third gate dielectric layer surrounds the middle region of the third nanosheet, and the third gate layer surrounds the third gate dielectric layer; the third drain / source terminal is electrically contacted to a first side region of the third nanosheet, and the fourth drain / source terminal is electrically contacted to a second side region of the third nanosheet; and the third gate layer is electrically connected to the first word line, and the fourth drain / source terminal is electrically connected to the first bit line.

7. The complementary field-effect transistor circuit as described in claim 1, further comprising: A third complementary field-effect transistor includes a fifth element, a sixth element, and the isolation structure; wherein the first primary programmable memory cell further includes the sixth element, and the second primary programmable memory cell further includes the fifth element; in the first primary programmable memory cell, the first drain / source terminal of the fourth element is electrically coupled to the second drain / source terminal of the second element via the sixth element, and the gate terminal of the sixth element is electrically connected to a first follower control line; and in the second primary programmable memory cell, the first drain / source terminal of the third element is electrically coupled to the second drain / source terminal of the first element via the fifth element, and the gate terminal of the fifth element is electrically connected to a second follower control line.

8. The complementary field-effect transistor circuit of claim 7, wherein the second element is a first selection element, the fourth element is a first antifuse element, and the sixth element is a first follower element; in, The first selection element includes a first drain / source terminal, a second drain / source terminal, a first nanosheet, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds the middle region of the first nanosheet, and the first gate layer surrounds the first gate dielectric layer; the first drain / source terminal is electrically contacted to a first side region of the first nanosheet, and the second drain / source terminal is electrically contacted to a second side region of the first nanosheet; and the first drain / source terminal is electrically connected to the first bit line, and the first gate layer is electrically connected to the first word line; The first follower element includes a second drain / source terminal, a third drain / source terminal, a second nanosheet, and a second gate structure. The second gate structure includes a second gate dielectric layer and a second gate layer. The second gate dielectric layer surrounds the middle region of the second nanosheet, and the second gate layer surrounds the second gate dielectric layer. The second drain / source terminal is electrically contacted to a first side region of the second nanosheet, and the third drain / source terminal is electrically contacted to a second side region of the second nanosheet. The second gate layer is electrically connected to the first follower control line. The first antifuse element includes a third drain / source terminal, a fourth drain / source terminal, a third nanosheet, and a third gate structure; the third gate structure includes a third gate dielectric layer and a third gate layer; the third gate dielectric layer surrounds the middle region of the third nanosheet, and the third gate layer surrounds the third gate dielectric layer; the third drain / source terminal is electrically contacted to a first side region of the third nanosheet, and the fourth drain / source terminal is electrically contacted to a second side region of the third nanosheet; and the third gate layer is electrically connected to the first antifuse control line.

9. The complementary field-effect transistor circuit of claim 8, wherein during programming, the first bit line receives a ground voltage, the first word line receives an enable voltage, the first follower control line receives an enable voltage, and the first antifuse control line receives a programming voltage; the first select element is enabled, the first follower element is in a conducting state, and the voltage stress borne by the third gate dielectric layer is the programming voltage; and the third gate dielectric layer breaks, causing the first primary programming memory cell to become broken.

10. The complementary field-effect transistor circuit of claim 7, further comprising: The fourth complementary field-effect transistor and the fifth complementary field-effect transistor; The fourth complementary field-effect transistor includes a seventh element, an eighth element, and the isolation structure; The fifth complementary field-effect transistor includes a ninth element, a tenth element, and the isolation structure; wherein the first primary programmable memory cell further includes the eighth element and the tenth element, and the second primary programmable memory cell further includes the seventh element and the ninth element; in the first primary programmable memory cell, the first drain / source terminal of the eighth element is electrically connected to the second drain / source terminal of the fourth element, the gate terminal of the eighth element is electrically connected to the first follower control line, the first drain / source terminal of the tenth element is electrically connected to the second drain / source terminal of the eighth element, the gate terminal of the tenth element is electrically connected to the first word line, and the second drain / source terminal of the tenth element is electrically connected to the first bit line; and in the second primary programmable memory cell, the first drain / source terminal of the seventh element is electrically connected to the second drain / source terminal of the third element, the gate terminal of the seventh element is electrically connected to the second follower control line, the first drain / source terminal of the ninth element is electrically connected to the second drain / source terminal of the seventh element, the gate terminal of the ninth element is electrically connected to the second word line, and the second drain / source terminal of the ninth element is electrically connected to the second bit line.

11. The complementary field-effect transistor circuit of claim 10, wherein the second element is a first select element, the fourth element is a first antifuse element, the sixth element is a first follower element, the eighth element is a second follower element, and the tenth element is a second select element; in, The first selection element includes a first drain / source terminal, a second drain / source terminal, a first nanosheet, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds the middle region of the first nanosheet, and the first gate layer surrounds the first gate dielectric layer; the first drain / source terminal is electrically contacted to a first side region of the first nanosheet, and the second drain / source terminal is electrically contacted to a second side region of the first nanosheet; and the first drain / source terminal is electrically connected to the first bit line, and the first gate layer is electrically connected to the first word line; The first follower element includes a second drain / source terminal, a third drain / source terminal, a second nanosheet, and a second gate structure; the second gate structure includes a second gate dielectric layer and a second gate layer; the second gate dielectric layer surrounds the middle region of the second nanosheet, and the second gate layer surrounds the second gate dielectric layer; the second drain / source terminal is electrically contacted to a first side region of the second nanosheet, and the third drain / source terminal is electrically contacted to a second side region of the second nanosheet; and the second gate layer is electrically connected to the first follower control line. The first antifuse element includes a third drain / source terminal, a fourth drain / source terminal, a third nanosheet, and a third gate structure. The third gate structure includes a third gate dielectric layer and a third gate layer. The third gate dielectric layer surrounds the middle region of the third nanosheet, and the third gate layer surrounds the third gate dielectric layer. The third drain / source terminal is electrically contacted to a first side region of the third nanosheet, and the fourth drain / source terminal is electrically contacted to a second side region of the third nanosheet. The third gate layer is electrically connected to the first antifuse control line. The second follower element includes a fourth drain / source terminal, a fifth drain / source terminal, a fourth nanosheet, and a fourth gate structure. The fourth gate structure includes a fourth gate dielectric layer and a fourth gate layer. The fourth gate dielectric layer surrounds the middle region of the fourth nanosheet, and the fourth gate layer surrounds the fourth gate dielectric layer. The fourth drain / source terminal is electrically contacted to a first side region of the fourth nanosheet, and the fifth drain / source terminal is electrically contacted to a second side region of the fourth nanosheet. The fourth gate layer is electrically connected to the first follower control line. The second selection element includes a fifth drain / source terminal, a sixth drain / source terminal, a fifth nanosheet, and a fifth gate structure; the fifth gate structure includes a fifth gate dielectric layer and a fifth gate layer; the fifth gate dielectric layer surrounds the middle region of the fifth nanosheet, and the fifth gate layer surrounds the fifth gate dielectric layer; the fifth drain / source terminal is electrically contacted to the first side region of the fifth nanosheet, and the sixth drain / source terminal is electrically contacted to the second side region of the fifth nanosheet; and the sixth drain / source terminal is electrically connected to the first word line, and the fifth gate layer is electrically connected to the first word line.

12. A complementary field-effect transistor circuit, comprising: The first complementary field-effect transistor includes a first element, a second element, and an isolation structure; The single-programmable memory cell includes: the first element and the second element; The isolation structure extends in the XY plane, the first element is located on one side of the isolation structure in the Z direction, and the second element is located on the other side of the isolation structure in the Z direction. In this primary programmable memory cell, the first drain / source terminal of the second element is electrically connected to the bit line, and the gate terminal of the second element is electrically connected to the word line; the first drain / source terminal of the first element is electrically connected to the second drain / source terminal of the second element, and the gate terminal of the first element is electrically connected to the antifuse control line.

13. The complementary field-effect transistor circuit of claim 12, wherein the second element is a selection element and the first element is an antifuse element; in, The selection element includes a first drain / source terminal, a second drain / source terminal, a first nanosheet, and a first gate structure; the first gate structure includes a first gate dielectric layer and a first gate layer; the first gate dielectric layer surrounds the middle region of the first nanosheet, and the first gate layer surrounds the first gate dielectric layer; the first drain / source terminal is electrically contacted to a first side region of the first nanosheet, and the second drain / source terminal is electrically contacted to a second side region of the first nanosheet; and the first drain / source terminal is electrically connected to the bit line, and the first gate layer is electrically connected to the word line; as well as The antifuse element includes a third drain / source terminal, a fourth drain / source terminal, a second nanosheet, and a second gate structure. The second gate structure includes a second gate dielectric layer and a second gate layer. The second gate dielectric layer surrounds the middle region of the second nanosheet, and the second gate layer surrounds the second gate dielectric layer. The third drain / source terminal is electrically contacted to a first side region of the second nanosheet, and the fourth drain / source terminal is electrically contacted to a second side region of the second nanosheet. The second gate layer is electrically connected to the antifuse control line, and the second drain / source terminal is electrically connected to the third drain / source terminal.

14. The complementary field-effect transistor circuit of claim 13, wherein during programming, the bit line receives a ground voltage, the word line receives an enable voltage, and the antifuse control line receives a programming voltage; the select element is enabled, and the voltage stress on the second gate dielectric layer is the programming voltage; and the second gate dielectric layer breaks, causing the primary programming memory cell to become fractured.

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