Computing chips and semiconductor packages

Abstract

This invention discloses a computing chip and semiconductor package, wherein the computing chip includes a high-bandwidth memory (HBM) interface subsystem. The HBM interface subsystem includes an HBM controller circuit and an HBM physical layer (PHY) circuit. The HBM controller circuit is used to control access to at least one HBM. The HBM PHY circuit is used to communicate with the at least one HBM. The HBM interface subsystem is designed to tolerate the failure of at least one HBM channel through channel redundancy.

Description

Technical Field

[0001] This invention relates to integrated circuit (IC) design, and more particularly to a compute die and related semiconductor package capable of tolerating failure of at least one high bandwidth memory (HBM) channel. Background Technology

[0002] HBM systems are typically used in application-specific integrated circuit (ASIC) chip designs that employ dedicated processors, such as artificial intelligence (AI) accelerators, graphics processing units (GPUs), central processing units (CPUs), or other datacenter processors. The amount of HBM on ASIC chips has increased dramatically. Consequently, the area of ​​the HBM controller circuitry and HBM physical layer (PHY) circuitry on the computing chips included in ASIC chips (such as XPU chips) has increased significantly. If the HBM controller circuitry and HBM PHY circuitry fail or experience yield issues, the entire die complex must be discarded after assembly and packaging. Summary of the Invention

[0003] One of the objectives of this invention is to provide a computing chip and related semiconductor packaging capable of tolerating failure of at least one HBM channel.

[0004] According to a first aspect of the present invention, an exemplary computing chip is disclosed. The exemplary computing chip includes a high-bandwidth memory (HBM) interface subsystem. The HBM interface subsystem includes an HBM controller circuit and an HBM physical layer (PHY) circuit. The HBM controller circuit is used to control access to at least one HBM. The HBM PHY circuit is used to communicate with the at least one HBM. The HBM interface subsystem is used to tolerate the failure of at least one HBM channel through channel redundancy.

[0005] According to a second aspect of the present invention, an exemplary semiconductor package is disclosed. The exemplary semiconductor package includes at least one high-bandwidth memory (HBM) and a computing chip. The computing chip includes an HBM interface subsystem. The HBM interface subsystem includes an HBM controller circuit and an HBM physical layer (PHY) circuit. The HBM controller circuit is used to control access to at least one HBM. The HBM PHY circuit is used to communicate with the at least one HBM. The HBM interface subsystem is used to tolerate failure of at least one HBM channel through channel redundancy.

[0006] These and other objectives of the present invention will undoubtedly become apparent to those skilled in the art upon reading the following detailed description of the preferred embodiments shown in conjunction with the figures and drawings. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the structure of a semiconductor package according to an embodiment of the present invention.

[0008] Figure 2 This is a block diagram of a computing chip with HBM channel fault tolerance according to an embodiment of the present invention.

[0009] Figure 3 This is a schematic diagram of a first ASIC chip design according to an embodiment of the present invention.

[0010] Figure 4 This is a schematic diagram of a second ASIC chip design according to an embodiment of the present invention.

[0011] The reference numerals in the attached figures are explained as follows: 100, 300, 400: Semiconductor packaging 101: Packaging substrate 102: Computing chips (GPU / CPU / SoC chips) 104, 306, 308, 310, 312, 314, 316, 318, 320, 322, 324, 326, 328, 404, 406, 408, 410, 412, 414: HBM 106: Intermediary Layer 108: Logic Chip 110: HBMDRAM chip 112: Through-silicon via 114, 116, 208: HBMPHY circuit 118: HBM controller circuit 200, 302, 304, 402: Computing chips 202_1, 202_M: Processor cores 204: HBM Interface Subsystem 206: HBM controller circuit 210: HBM Interface 330, 332, 416, 418: IO chips Detailed Implementation

[0012] Certain terms are used in the specification and claims to refer to specific elements. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same element. This specification and claims do not distinguish elements based on differences in name, but rather on differences in function. The terms "comprising" and "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the terms "coupled" or "coupled" herein include any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices and connection means.

[0013] Figure 1 This is a schematic diagram of a semiconductor package structure according to an embodiment of the present invention. The semiconductor package 100 can be an ASIC chip. Figure 1As shown, the semiconductor package 100 includes a package substrate 101, a compute die 102, a high bandwidth memory (HBM) 104, and an interposer 106. The compute die 102 and HBM 104 are both mounted on the interposer 105 and connected through it. In this embodiment, the compute die 102 and HBM 104 are placed side-by-side on the interposer 105. The HBM 104 is implemented using a three-dimensional (3D) stacking method, by vertically stacking multiple HBM dynamic random access memory (DRAM) chips 110 on a logic die (also called a basedie) 108. Each HBM DRAM chip 110 is electrically connected to the logic die 108 through a through-silicon via (TSV) 112. Logic chip 108 is the basic non-memory layer at the bottom of the 3D memory stack and provides an interface to computing chips (e.g., GPU / CPU / SoC chips) 102. Specifically, logic chip 108 has an HBM PHY circuit (labeled "PHY" in the figure) 114, which is electrically connected to an HBM PHY circuit (labeled "PHY" in the figure) 116 on computing chip 102. HBM PHY circuits 114 / 116 include multiple physical channels, each of which is divided into multiple pseudo channels. For example, for a 3D memory stack of HBM 104, a 64-bit physical channel can be divided into two 32-bit pseudo channels. In this embodiment, both HBM PHY circuits 114 and 116 support channel redundancy. Specifically, both HBM PHY circuits 114 and 116 support one or more redundant HBM channels (e.g., redundant physical channels or redundant pseudo channels). Therefore, when an HBM channel (e.g., a physical channel or a pseudo channel) fails to function properly, a redundant HBM channel (e.g., a redundant physical channel or a redundant pseudo channel) can be selected as a replacement for the defective HBM channel (e.g., a physical channel or a pseudo channel), and the HBM controller circuit (labeled "MC" in the figure) 118 can control access (read / write) of HBM 104 through the redundant HBM channel (e.g., a redundant physical channel or a redundant pseudo channel).

[0014] It is important to note that Figure 1The packaging structure shown is for illustrative purposes only and is not intended to limit the invention. In practical applications, the present invention does not limit the packaging technology used for assembling and packaging the computing chip 102 and HBM 104. Furthermore, the number of computing chips and the number of HBMs can be adjusted according to actual application requirements. In some embodiments of the present invention, the semiconductor package 100 may be an ASIC chip having multiple computing chips 102 and / or multiple HBMs 104. These alternative designs are all within the scope of the present invention.

[0015] Figure 2 This is a block diagram of a computing chip with HBM channel fault tolerance according to an embodiment of the present invention. Figure 1 The computing chip 102 shown can be used Figure 2 The computing chip 200 shown is implemented in this embodiment. In this embodiment, the computing chip 200 may be an XPU chip, including processor cores 202_1 to 202_M. The HBM interface subsystem 204, along with other circuitry (not shown), includes an HBM controller circuit 206 and an HBM PHY circuit 208. The HBM controller circuit 206 controls HBM access (read / write). The HBM PHY circuit 208 communicates with the HBM. For example, the computing chip 200 and the HBM are placed side-by-side on an interposer layer. The HBM PHY circuit 208 includes one or more HBM interfaces (labeled "IF") 210, each HBM interface being a PHY interface between the HBM and the computing chip 200. The difference between conventional computing chips and the computing chip 200 proposed in this invention is that the HBM interface subsystem 204 of the computing chip 200 is used to tolerate the failure of at least one HBM channel through channel redundancy. For example, the HBM interface subsystem 204 of the computing chip 200 can only tolerate the failure of one HBM channel (e.g., one physical channel or one pseudo channel). In the HBM interface subsystem 204 of the computing chip 200, tolerating a single dummy channel failure can achieve a 1.6x yield improvement. Another example is that the HBM interface subsystem 204 of the computing chip 200 can tolerate failures of multiple HBM channels (e.g., two physical channels or two dummy channels). In the HBM interface subsystem 204 of the computing chip 200, tolerating two dummy channel failures can achieve a 1.8x yield improvement.

[0016] In some embodiments of the present invention, the number of defective HBM channels (e.g., physical channels or pseudo channels) that can be tolerated on the computing chip 200 may depend on the area contribution of the HBM interface subsystem 204 to the computing chip 200. For example, when the HBM interface subsystem 204 occupies X% of the chip area of ​​the computing chip 200, the HBM interface subsystem 204 of the computing chip 200 is designed to tolerate the failure of only one HBM channel (e.g., one physical channel or one pseudo channel). Another example is that when the HBM interface subsystem 204 occupies Y% of the chip area of ​​the computing chip 200, the HBM interface subsystem 204 of the computing chip 200 is designed to tolerate the failure of multiple HBM channels (e.g., two physical channels or two pseudo channels), where Y > X. However, these are for illustrative purposes only and are not intended to limit the invention. In practical applications, any ASIC chip employing the computing chip with HBM channel failure tolerance capabilities proposed in this invention to improve yield falls within the scope of this invention.

[0017] In some embodiments of the present invention, the HBM interface subsystem 204 of the computing chip 200 can be designed to tolerate the failure of one HBM channel (e.g., a physical channel or a pseudo channel) among N HBM interfaces, wherein .

[0018] Figure 3 This is a schematic diagram of a first ASIC chip design according to an embodiment of the present invention. The semiconductor package 300 includes multiple computing chips 302 and 304, multiple HBMs 306-328, and multiple input / output (IO) chiplets 330 and 332. Each computing chip in computing chips 302 and 304 can be implemented using the computing chip 200 with HBM channel fault tolerance proposed in this invention. Therefore, a shoreline of computing chip 302 has an HBM interface (e.g., ...). Figure 2 The HBM interface 210 shown is electrically connected to HBM 306, 308, and 310 respectively. Another chip has an HBM interface (e.g., Figure 2 The HBM interface 210 shown is electrically connected to HBMs 312, 314, and 316 respectively; one chip of the computing chip 304 has an HBM interface (e.g., Figure 2 The HBM interface 210 shown is electrically connected to HBM 318, 320, and 322 respectively. Another chip edge has an HBM interface (e.g., Figure 2The HBM interface 210 shown is electrically connected to HBMs 324, 326, and 328, respectively. In an exemplary HBM channel failure-tolerant design, computing chips 302 / 304 can tolerate the failure of one HBM channel (e.g., one physical channel or one pseudo channel) among three HBM interfaces arranged along a chip edge. In another exemplary HBM channel failure-tolerant design, computing chips 302 / 304 can tolerate the failure of one HBM channel (e.g., one physical channel or one pseudo channel) in each HBM interface.

[0019] Figure 4 This is a schematic diagram of a second ASIC chip design according to an embodiment of the present invention. The semiconductor package 400 includes a single computing chip 402, multiple HBMs 404-414, and multiple I / O chips 416, 418. The computing chip 402 can be implemented using the proposed computing chip 200 with HBM channel fault tolerance. Therefore, one chip edge of the computing chip 402 has an HBM interface (e.g., ...). Figure 2 The HBM interface 210 shown is electrically connected to HBM 404, 406, and 408 respectively. Another chip edge has an HBM interface (e.g., Figure 2 The HBM interface 210 shown is electrically connected to HBMs 410, 412, and 414, respectively. In one exemplary HBM channel failure-tolerant design, the computing chip 402 can tolerate the failure of one HBM channel (e.g., one physical channel or one pseudo channel) among three HBM interfaces arranged along a chip edge. In another exemplary HBM channel failure-tolerant design, the computing chip 402 can tolerate the failure of one HBM channel (e.g., one physical channel or one pseudo channel) in each HBM interface.

[0020] When there are K HBM channel failures ( When the HBM channel fault tolerance capability proposed in this invention is tolerating the faults of K HBM channels through channel redundancy, the computing chip can be used to tolerate the faults of K HBM channels. This ensures the overall system functions correctly. In this way, yield can be significantly improved. Specifically, the failure rate of K HBM channels ( This may originate from packaging defects. For example, the computing chip with HBM channel fault tolerance proposed in this invention can solve the attachment yield loss caused by the HBM PHY region. The yield loss during chip bonding can be reduced by about 18 times, which will bring significant cost savings.

[0021] The computing chip with HBM channel fault tolerance proposed in this invention can tolerate the faults of K HBM channels through channel redundancy. In some embodiments of the invention, the failure of K HBM channels ( This could stem from runtime failures caused by aging and degradation. If a runtime failure occurs in an HBM channel (e.g., a physical channel or a pseudo channel), redundant HBM channels (e.g., redundant physical channels or redundant pseudo channels) can be made available, allowing the overall system to function normally by replacing the defective HBM channel with a redundant channel that is free from runtime failures.

[0022] The foregoing has outlined the features of several embodiments, enabling those skilled in the art to fully understand various aspects of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or substantially the same results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A computing chip, characterized in that, include: The HBM interface subsystem includes: HBM controller circuitry for controlling access to at least one HBM; and HBM PHY circuitry for communicating with at least one HBM; The HBM interface subsystem is used to tolerate the failure of at least one HBM channel through channel redundancy.

2. The computing chip as described in claim 1, characterized in that, The at least one HBM channel consists of only a single channel.

3. The computing chip as described in claim 2, characterized in that, This single channel is a pseudo channel.

4. The computing chip as described in claim 1, characterized in that, The at least one HBM channel includes multiple channels.

5. The computing chip as described in claim 4, characterized in that, Each of these multiple channels is a pseudo channel.

6. The computing chip as described in claim 1, characterized in that, The HBM PHY circuit includes: Multiple HBM interfaces are used to communicate with multiple HBMs respectively; The HBM interface subsystem is designed to tolerate the failure of one HBM channel of each of the multiple HBM interfaces.

7. The computing chip as described in claim 1, characterized in that, The HBM PHY circuit includes: Multiple HBM interfaces are used to communicate with multiple HBMs respectively; The HBM interface subsystem is designed to tolerate failures in one of the multiple HBM channels within the multiple HBM interfaces.

8. The computing chip as described in claim 1, characterized in that, The number of at least one HBM channel depends on the area contribution of the HBM interface subsystem to the computing chip.

9. The computing chip as described in claim 1, characterized in that, The failure of at least one HBM channel was caused by a packaging defect.

10. The computing chip as described in claim 1, characterized in that, The failure of at least one HBM channel is due to a runtime fault.

11. A semiconductor package, characterized in that, include: At least one HBM; as well as Computing chips, including: The HBM interface subsystem includes: HBM controller circuitry for controlling access to at least one HBM; and HBM PHY circuitry for communicating with at least one HBM; The HBM interface subsystem is used to tolerate the failure of at least one HBM channel through channel redundancy.

12. The semiconductor package as claimed in claim 11, characterized in that, The at least one HBM channel consists of only a single channel.

13. The semiconductor package as described in claim 12, characterized in that, This single channel is a pseudo channel.

14. The semiconductor package as claimed in claim 11, characterized in that, The at least one HBM channel includes multiple channels.

15. The semiconductor package as claimed in claim 14, characterized in that, Each of these multiple channels is a pseudo channel.

16. The semiconductor package as claimed in claim 11, characterized in that, The semiconductor package includes multiple HBMs, and the HBM PHY circuit includes: Multiple HBM interfaces are used to communicate with each of the multiple HBMs separately; The HBM interface subsystem is designed to tolerate the failure of one HBM channel of each of the multiple HBM interfaces.

17. The semiconductor package as claimed in claim 11, characterized in that, The semiconductor package includes multiple HBMs, and the HBM PHY circuit includes: Multiple HBM interfaces are used to communicate with each of the multiple HBMs separately; The HBM interface subsystem is used to tolerate the failure of one HBM channel of the multiple HBM interfaces contained in the multiple HBM interfaces.

18. The semiconductor package as claimed in claim 11, characterized in that, The number of at least one HBM channel depends on the area contribution of the HBM interface subsystem to the computing chip.

19. The semiconductor package as claimed in claim 11, characterized in that, The failure of at least one HBM channel was caused by a packaging defect.

20. The semiconductor package as claimed in claim 11, characterized in that, The failure of at least one HBM channel is due to a runtime fault.

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