Non-arcing three-leg on-load tap changer and control method thereof

Abstract

This invention discloses an arc-free three-branch on-load tap changer and its control method. The method includes: an arc-free three-branch on-load tap changer comprising: a main circuit branch serving as a low-resistance mechanical contact path; a thyristor bypass branch serving as a bidirectional arc-free switching path; and an intelligent trigger branch serving as a dynamic control signal path, used to detect the current direction and amplitude of the main circuit branch and generate trigger pulses to control the conduction of the thyristor. The main circuit branch and the thyristor bypass branch are respectively connected to an FPGA controller in the intelligent trigger branch.

Description

Technical Field

[0001] This invention relates to the field of power system technology, and more specifically, to an arc-free three-branch on-load tap changer and its control method. Background Technology

[0002] As a core component of power transformer voltage regulation, the on-load tap changer (OLTC) directly affects the equipment's lifespan and the reliability of the power grid. With the development of power grids towards higher voltage, larger capacity, and higher dynamic response, traditional arc-extinguishing technologies face the following challenges: Mechanical arc extinguishing relies on oil or a vacuum interrupter, which carries the risk of arcing due to medium aging (oil carbonization, vacuum reduction). Furthermore, the fixed-sequence switching process is susceptible to load current fluctuations, leading to variations in contact arcing time. Even though new arc-free on-load tap changers have been proposed in recent years, their excessive number of branches and insufficient intelligent control remain significant challenges.

[0003] Therefore, there is an urgent need to develop a new technology for an arc-free on-load tap changer that is highly adaptive and has more intelligent control. Summary of the Invention

[0004] To address the shortcomings of existing technologies, this invention provides an arc-free three-branch on-load tap changer and its control method.

[0005] According to one aspect of the present invention, an arc-free three-branch on-load tap changer is provided, comprising: Main circuit branch, used as a low-resistance mechanical contact path; Thyristor bypass branch, used as a bidirectional arc-free switching path; The intelligent trigger branch serves as a dynamic control signal path, used to detect the current direction and amplitude in the main circuit branch and generate trigger pulses to control the conduction of the thyristor. The main circuit branch and the thyristor bypass branch are respectively connected to the FPGA controller in the intelligent triggering branch.

[0006] Optionally, the main circuit branch includes stationary contact A, stationary contact D, and moving contact K, which are respectively connected between power supply M and load N. The first end of stationary contact A is directly connected to power supply M, and the second end is in movable contact with one end of moving contact K. The other end of moving contact K is in movable contact with the first end of stationary contact D. The second end of stationary contact D is directly connected to load N.

[0007] Optionally, the thyristor bypass branch includes a first thyristor SCR1 and a second thyristor SCR2, which are connected in reverse parallel structure between the power supply M and the load N. The anode of the first thyristor SCR1 is directly connected to the power supply M, and its cathode is connected to the cathode of the second thyristor SCR2. The anode of the second thyristor SCR2 is directly connected to the load N. The thyristor bypass branch is turned on and off by an FPGA controller.

[0008] Optionally, the intelligent triggering branch includes Hall sensor H1 and Hall sensor H2, as well as an FPGA controller and an isolation drive circuit; Hall sensor H1 surrounds the input wire of the main circuit branch, and Hall sensor H2 surrounds the output wire of the main circuit branch, used to detect the direction and amplitude of the current. The FPGA controller receives the Hall sensor signal and the displacement state signal of the moving contact K after the signal conditioning circuit is processed, and generates two trigger pulse signals to trigger the first thyristor SCR1 and the second thyristor SCR2 respectively. The signal conditioning circuit is connected to the Hall sensor H1 and the Hall sensor H2.

[0009] Optionally, the isolation drive circuit includes an optocoupler isolator, which includes optocoupler 1 and optocoupler 2. The input terminal of optocoupler 1 is connected to the PWM_OUT1 output terminal of the FPGA controller, and the input terminal of optocoupler 2 is connected to the PWM_OUT2 output terminal of the FPGA controller.

[0010] Optionally, the arc-free three-branch on-load tap changer also includes: an optical encoder, used to detect the displacement of the moving contact K in the main circuit branch and transmit the displacement signal to the FPGA controller in real time.

[0011] Optionally, the arc-free three-branch on-load tap changer also includes: a backup circuit breaker, which triggers the backup circuit breaker to forcibly disconnect the main circuit branch when the conduction time of any thyristor in the thyristor bypass exceeds a preset maximum value.

[0012] Optionally, the FPGA controller employs a finite state machine to manage the switching process, including initialization, steady-state monitoring, contact displacement detection, current direction determination, trigger pulse generation, conduction verification, natural turn-off, and abnormal handling states.

[0013] Optionally, the isolation drive circuit adopts a three-stage cascaded amplification structure, including: a signal isolation stage composed of high-speed optocouplers; a current amplification stage composed of bipolar transistors; and a power output stage composed of MOSFETs.

[0014] According to another aspect of the present invention, a control method for a three-branch on-load tap changer without arcing is provided, comprising: Contact action trigger detection steps: The displacement of the moving contact K is detected by the photoelectric encoder. When the displacement exceeds the preset threshold, the switching process is triggered. Hall sensors H1 and H2 are used to detect the direction and amplitude of the main circuit current. The FPGA controller determines the current direction through dual-channel signals and calculates the trigger advance time. Based on the current direction, the FPGA controller generates a corresponding trigger pulse, which drives the first thyristor SCR1 or the second thyristor SCR2 to conduct through different optocouplers and gate current limiting resistors. After the first thyristor SCR1 or the second thyristor SCR2 is turned on, the main circuit current is transferred to the bypass. The FPGA controller verifies the conduction status of the first thyristor SCR1 or the second thyristor SCR2 through voltage or current sensors. The trigger advance time is dynamically adjusted according to the load current amplitude. If the circuit breaker is not turned off within the time limit, the backup circuit breaker is triggered and the fault code is recorded.

[0015] Optionally, the displacement of the moving contact K is transmitted to the FPGA controller in real time via a photoelectric encoder, and a switching process is triggered when the displacement exceeds 0.1mm.

[0016] Optionally, Hall sensors H1 and H2 are used to detect the direction and amplitude of the main circuit current. The FPGA controller determines the current direction through dual-channel signals, including: The FPGA controller identifies the zero-crossing point of the current through a digital comparator and determines the direction of the current by combining the output signals of Hall sensors H1 and H2.

[0017] Optionally, depending on the current direction, the FPGA controller generates a corresponding trigger pulse to drive the first thyristor SCR1 or the second thyristor SCR2 to conduct through different optocouplers and gate current limiting resistors, including: When there is a forward current, the FPGA controller generates a PWM_OUT1 pulse to drive the first thyristor SCR1 to turn on; when there is a reverse current, the FPGA controller generates a PWM_OUT2 pulse to drive the second thyristor SCR2 to turn on.

[0018] Optionally, the FPGA controller verifies the conduction state of the first thyristor SCR1 or the second thyristor SCR2 using a voltage or current sensor, including: The FPGA controller determines the conduction status by monitoring the anode-cathode voltage drop VAK of the first thyristor SCR1 or the second thyristor SCR2. If VAK is less than 1V, the conduction is considered successful.

[0019] Optionally, the trigger advance time is dynamically adjusted according to the load current amplitude. If the circuit breaker is not turned off within the time limit, the standby circuit breaker is triggered, including: The FPGA controller dynamically adjusts the trigger advance time based on the real-time current amplitude to ensure that the thyristor turns on before the current crosses zero; if the thyristor conduction time exceeds 12ms, the FPGA controller triggers the backup circuit breaker to forcibly disconnect the main circuit branch.

[0020] Optionally, it also includes: when the current crosses zero, the thyristor automatically turns off, and after the FPGA controller confirms that the moving contact K is completely open, it turns off the PWM output and resets the relevant timers.

[0021] Optionally, it also includes: if a fault is detected, the FPGA controller triggers the backup circuit breaker to forcibly shut down the main circuit, records the fault code, and alarms via LED or communication interface.

[0022] Optionally, it also includes: after the exception handling is completed or after natural shutdown, the FPGA controller resets all status registers and timers, the moving contact K returns to the closed position, and re-enters the steady-state monitoring state.

[0023] Optionally, the FPGA controller employs a finite state machine to manage the switching process, including initialization, steady-state monitoring, contact displacement detection, current direction determination, trigger pulse generation, conduction verification, natural turn-off, exception handling, and system reset state.

[0024] Therefore, this invention employs a three-branch collaborative architecture (main circuit branch, thyristor bypass branch, and intelligent triggering branch) to achieve a highly adaptive and intelligently controlled arc-free on-load tap changer. Furthermore, the FPGA utilizes an innovative finite state machine (FSM) to manage the switching process, strictly constraining logic jump conditions. In addition, it is understood that for the technical problem this invention aims to solve, while a two-branch architecture has fewer branches, its reliability is relatively low. The three-branch collaborative architecture of this invention achieves a balance between technical effectiveness and the number of branches as much as possible. Attached Figure Description

[0025] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures: Figure 1 This is a schematic diagram of the structure of a three-branch on-load tap changer without arcing provided in an exemplary embodiment of the present invention; Figure 2 This is a simulation diagram of the application of the three-branch on-load tap changer in a system with a photovoltaic feeder provided by an exemplary embodiment of the present invention. Figure 3 This is a schematic diagram of the timing change curve of the tap position of a tap changer provided in an exemplary embodiment of the present invention; Figure 4 This is a schematic diagram of the voltage timing variation curves at each node of a power distribution feeder, provided by an exemplary embodiment of the present invention. Figure 5 This is a schematic flowchart of a control method for a three-branch on-load tap changer without arcing, provided in an exemplary embodiment of the present invention. Detailed Implementation

[0026] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0027] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0028] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of the present invention are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0029] It should also be understood that in the embodiments of the present invention, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0030] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more unless explicitly defined or given contrary instructions in the context.

[0031] Furthermore, the term "and / or" in this invention is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this invention generally indicates that the preceding and following related objects have an "or" relationship.

[0032] It should also be understood that the description of the various embodiments in this invention emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0033] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0034] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0035] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0036] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0037] Figure 1 This is a schematic diagram of the structure of an arc-free three-branch on-load tap changer provided in an exemplary embodiment of the present invention. The arc-free three-branch on-load tap changer includes: Main circuit branch, used as a low-resistance mechanical contact path; Thyristor bypass branch, used as a bidirectional arc-free switching path; The intelligent trigger branch serves as a dynamic control signal path, used to detect the current direction and amplitude in the main circuit branch and generate trigger pulses to control the conduction of the thyristor. The main circuit branch and the thyristor bypass branch are respectively connected to the FPGA controller in the intelligent triggering branch.

[0038] Specifically, refer to Figure 1 As shown, this invention discloses a three-branch on-load tap changer with no arcing, comprising: The main circuit branch, used as a low-resistance mechanical contact path, includes stationary contact A, stationary contact D and moving contact K, which are respectively connected between the power supply M and the load N; The thyristor bypass branch is used as a bidirectional arc-free switching path, including the first thyristor SCR1 and the second thyristor SCR2, which are connected between the power supply M and the load N in an anti-parallel structure, and their conduction and turn-off are controlled by the FPGA controller. The intelligent trigger branch, used as a dynamic control signal path, includes Hall sensors H1 and H2, an FPGA controller, and an isolation drive circuit. It is used to detect the direction and amplitude of the main circuit current and generate trigger pulses to control the conduction of the thyristors.

[0039] In another embodiment, The first end of the stationary contact A in the main circuit branch is directly connected to the power supply M, and the second end is in movable contact with one end of the moving contact K; the other end of the moving contact K is in movable contact with the first end of the stationary contact D; the second end of the stationary contact D is directly connected to the load N.

[0040] In another embodiment, The anode of the first thyristor SCR1 in the thyristor bypass branch is directly connected to the power supply M, and its cathode is shared with the cathode of the second thyristor SCR2; the anode of the second thyristor SCR2 is directly connected to the load N.

[0041] In another embodiment, Hall sensor H1 of the intelligent trigger branch surrounds the main circuit input wire (M side), and Hall sensor H2 surrounds the main circuit output wire (N side) to detect the current direction and amplitude.

[0042] In another embodiment, The FPGA controller receives the Hall sensor signal and the displacement state signal of the moving contact K after the signal conditioning circuit is processed, and generates two trigger pulse signals to trigger the first thyristor SCR1 and the second thyristor SCR2 respectively.

[0043] In another embodiment, The isolation drive circuit is used to convert the FPGA output signal into voltage and current waveforms that meet the driving requirements of the first thyristor SCR1 or the second thyristor SCR2.

[0044] In another embodiment, The isolation drive circuit includes an optocoupler isolator, a level shifting circuit, and a gate current limiting resistor.

[0045] In another embodiment, The level conversion circuit includes a boost DC-DC module and a driver chip. Suitable models of boost converters available on the market can be used.

[0046] In another embodiment, The intelligent triggering branch also includes a power supply to power the FPGA, level conversion circuit, Hall sensor, etc. Preferably, since the Hall sensor is installed on the power side, it uses a separate isolated power supply to avoid common-mode interference.

[0047] In another embodiment, The optocoupler includes optocoupler 1 and optocoupler 2. The input terminal of optocoupler 1 is connected to the PWM_OUT1 output terminal of the FPGA, and the output terminal is connected to the gate of the first thyristor SCR1 via the gate current limiting resistor R_g1. The input terminal of optocoupler 2 is connected to the PWM_OUT2 output terminal of the FPGA, and the output terminal is connected to the gate of the second thyristor SCR2 via the gate current limiting resistor R_g2.

[0048] In another embodiment, It also includes an optical encoder, which is used to detect the displacement of the moving contact K and transmit the displacement signal to the FPGA in real time.

[0049] In another embodiment, The FPGA controller uses a finite state machine (FSM) to manage the switching process, including initialization, steady-state monitoring, contact displacement detection, current direction determination, trigger pulse generation, conduction verification, natural turn-off, and exception handling.

[0050] In another embodiment, It also includes a backup circuit breaker. When the conduction time of any thyristor in the thyristor bypass branch exceeds the preset maximum value, the FPGA triggers the backup circuit breaker to forcibly disconnect the main circuit.

[0051] In another embodiment, The FPGA controller is also used to record fault codes and issue alarms via LEDs or a communication interface.

[0052] In another embodiment, the present invention discloses an arc-free three-branch on-load tap changer, wherein the component connection relationship of each branch in the three-branch design (intelligent timing control scheme) is defined by dividing the branches and clarifying the connection method of each port: 1. Main circuit branch (used as a path for low-resistance mechanical contacts) This branch road includes: Stationary contact A: Fixedly installed at the input end of the main circuit (near the power supply side M).

[0053] Stationary contact D: Fixedly installed at the output end of the main circuit (near the load side N).

[0054] Moving contact K: A movable conductive piece that connects stationary contacts A and D.

[0055] Connection relationships: Stationary contact A: First terminal (input terminal): Directly connected to power supply M.

[0056] The second end (output end) is in active contact with one end of the moving contact K.

[0057] Moving contact K: First end: in active contact with the second end of stationary contact A.

[0058] The second end is in active contact with the first end of the stationary contact D.

[0059] Static contact D: The first end (input end) is in active contact with the second end of the moving contact K.

[0060] The second terminal (output terminal) is directly connected to the load N.

[0061] For this main circuit branch, the current path under steady-state conduction is as follows: Power supply M → stationary contact A (first terminal → second terminal) → moving contact K (first terminal → second terminal) → stationary contact D (first terminal → second terminal) → load N; 2. Thyristor bypass branch (used as a bidirectional arc-free switching path) This branch road includes: First thyristor SCR1: Forward conducting device in the reverse parallel structure.

[0062] Second thyristor SCR2: Reverse conduction device in reverse parallel structure.

[0063] Connection relationships: SCR1: Anode (A): Directly connected to power supply M.

[0064] Cathode (K): The cathode (K) connected to the SCR2.

[0065] Gate (G): Connected to the trigger signal output of the FPGA via an isolation drive circuit.

[0066] SCR2: Anode (A): Directly connected to load N.

[0067] Cathode (K): The cathode (K) connected to SCR1.

[0068] Gate (G): Connected to another trigger signal output terminal of the FPGA via an isolation drive circuit.

[0069] For example, the isolation drive circuit includes a gate current-limiting resistor and an optocoupler (also called an optocoupler isolator). Therefore, further: SCR1: Anode (A) is connected to M, cathode (K) is connected to the same cathode as SCR2, and gate (G) is connected to the output terminal of optocoupler 1 via R_g1.

[0070] SCR2: Anode (A) is connected to N, cathode (K) is connected to the same cathode as SCR1, and gate (G) is connected to the output terminal of optocoupler 2 via R_g2.

[0071] For this thyristor bypass branch The current path under forward conduction is: Power supply M → SCR1 (anode → cathode) → SCR2 (cathode → anode) → Load N; The current path under reverse conduction is: Load N → SCR2 (anode → cathode) → SCR1 (cathode → anode) → Power supply M; 3. Intelligent trigger branch (used as a dynamic control signal path) This branch road includes: Hall sensor H1: detects the direction and amplitude of the current at the input terminal (M side) of the main circuit.

[0072] Hall sensor H2: detects the direction and amplitude of the current at the output terminal (N side) of the main circuit.

[0073] FPGA controller: processes sensor signals and generates trigger pulses.

[0074] Optocoupler isolator: transmits trigger signals to the gate of the thyristor.

[0075] Gate current limiting resistors (R_g1 / R_g2): protect the gate of the thyristor.

[0076] Connection relationships: Hall sensor H1: Input terminal: The wire surrounding the input terminal of the main circuit (M side) induces the magnetic field of the current.

[0077] Output terminal (signal line): Connected to the input terminal of the signal conditioning circuit.

[0078] Hall sensor H2: Input terminal: The wire surrounding the output terminal of the main circuit (N side) induces a current magnetic field.

[0079] Output terminal (signal line): Connected to the input terminal of the signal conditioning circuit.

[0080] Signal conditioning circuit: Input terminal: Receives analog signals from H1 / H2.

[0081] Output: After filtering and ADC conversion, the digital signal is output to the FPGA.

[0082] FPGA controller: Input port: Receives the conditioned digital current signal and the displacement status signal of contact K.

[0083] Output port: Generates two trigger pulse signals (corresponding to SCR1 and SCR2).

[0084] Optical isolators 1 and 2: Input terminal (LED side): Connects to the trigger pulse output terminal of the FPGA.

[0085] Output terminal (transistor side): connected to the gate current limiting resistor (R_g1 / R_g2).

[0086] Gate current limiting resistance: R_g1: One end is connected to the output of the optocoupler, and the other end is connected to the gate (G) of SCR1.

[0087] R_g2: One end is connected to the output of the optocoupler, and the other end is connected to the gate (G) of SCR2.

[0088] For this branch road Taking SCR1 triggering as an example, the signal transmission path is as follows: Hall sensor H1 detects current direction → signal conditioning circuit → FPGA → optocoupler 1 → R_g1 → SCR1 gate; Taking SCR2 triggering as an example, the signal transmission path is as follows: Hall sensor H2 → Signal conditioning circuit → FPGA → Optocoupler 2 → R_g2 → SCR2 gate.

[0089] In another embodiment, for the three branches mentioned above, the key nodes for cross-connection between the branches involve: (1) Parallel connection between the main circuit and the thyristor branch: Power supply side (M): The first end (M) of the stationary contact A of the main circuit branch is connected to the anode (A) of SCR1 of the thyristor branch.

[0090] Load side (N): The second terminal (N) of the stationary contact D of the main circuit branch is connected to the anode (A) of SCR2 in the thyristor branch.

[0091] (2) Control connection between the trigger branch and the thyristor branch: The gate (G) of SCR1 / SCR2 is bound to the output of the FPGA through the corresponding optocoupler isolator 1 or 2 to form an independent control loop.

[0092] In another embodiment, Hall sensor H1 detects the current at the main circuit input terminal (M side), and H2 detects the current at the output terminal (N side). The current direction (M→N or N→M) is determined based on the H1 / H2 signals.

[0093] When the current reverses (N→M), H2 detects a negative signal, and the voltage of H1 is below the threshold. The sensitive direction of H1 is positively correlated with the current from M to N, and it outputs a positive voltage; the sensitive direction of H2 is positively correlated with the current from N to M, and it outputs a positive voltage.

[0094] When the current reverses (N→M), H1 outputs a negative voltage and H2 outputs a positive voltage. The FPGA determines the current direction by the sign.

[0095] The gates of SCR1 and SCR2 are connected to the FPGA via independent optocouplers (optocoupler 1 / optocoupler 2) and resistors (R_g1 / R_g2). The FPGA generates two independent pulses to trigger SCR1 and SCR2 respectively.

[0096] The input of optocoupler 1 is connected to PWM_OUT1 of the FPGA, and its output is connected to the gate (G) and cathode (K) of SCR1 via R_g1. The input of optocoupler 2 is connected to PWM_OUT2 of the FPGA, and its output is connected to the gate (G) and cathode (K) of SCR2 via R_g2.

[0097] The displacement of the moving contact K is detected by a photoelectric encoder; the output interface of the photoelectric encoder (such as SPI or GPIO) is directly connected to the digital input port of the FPGA to transmit the displacement of contact K in real time. The contact displacement signal needs to be input into the FPGA to initiate the arc switching process.

[0098] SCR1 anode is connected to M, SCR2 anode is connected to N, and both cathodes are connected together. When the main circuit is disconnected, the current bypasses through SCR1 or SCR2. The common cathode connection point of SCR1 and SCR2 is designed to float, and is connected to the main circuit only through M and N to avoid potential conflicts.

[0099] Hall sensor H1: Surrounds the M-side wire, and the output is connected to signal conditioning channel 1.

[0100] Hall sensor H2: Surrounds the N-side wire, and the output is connected to signal conditioning channel 2.

[0101] Signal conditioning circuit: Two channels independently perform filtering and ADC conversion, both output to FPGA.

[0102] FPGA: Input: Conditioned current signal, contact K displacement signal (SPI interface).

[0103] Outputs: PWM_OUT1 (driving SCR1 via optocoupler 1), PWM_OUT2 (driving SCR2 via optocoupler 2).

[0104] Optical isolator: Optocoupler 1: The input terminal is connected to PWM_OUT1, and the output terminal is connected to the gate of R_g1→SCR1.

[0105] Optocoupler 2: The input terminal is connected to PWM_OUT2, and the output terminal is connected to the gate of R_g2→SCR2.

[0106] See Figures 2-4 In another embodiment, For systems with photovoltaic feeders, simulations show that in forward power flow, the on-load tap changer (OLTC) disclosed in this invention can operate on the heavily loaded line with the largest voltage difference to solve the low voltage problem; while in reverse power flow, the on-load tap changer disclosed in this invention only operates on the line connected to the photovoltaic to solve the overvoltage problem; and there is no arcing.

[0107] Figure 5 This is a flowchart illustrating a control method for a three-branch on-load tap changer without arcing, provided in an exemplary embodiment of the present invention. Figure 5 As shown, the control method 500 for a three-branch on-load tap changer without arcing includes: Step 501: Contact action trigger detection step: The displacement of the moving contact K is detected by the photoelectric encoder. When the displacement exceeds the preset threshold, the switching process is triggered. Step 502: Use Hall sensor H1 and Hall sensor H2 to detect the direction and amplitude of the main circuit current. The FPGA controller determines the current direction through dual-channel signals and calculates the trigger advance time. Step 503: According to the current direction, the FPGA controller generates a corresponding trigger pulse, which drives the first thyristor SCR1 or the second thyristor SCR2 to conduct through different optocoupler isolators and gate current limiting resistors. Step 504: After the first thyristor SCR1 or the second thyristor SCR2 is turned on, the main circuit current is transferred to the bypass. The FPGA controller verifies the conduction status of the first thyristor SCR1 or the second thyristor SCR2 through voltage or current sensors. Step 505: Dynamically adjust the trigger advance time according to the load current amplitude. If the circuit breaker is not turned off within the time limit, trigger the backup circuit breaker and record the fault code.

[0108] Specifically, the present invention also discloses a method for a three-branch on-load tap changer based on arc-free operation, comprising the following steps: The switching process is triggered by detecting the contact movement using a photoelectric encoder. The current direction and phase are determined through different channels, and the trigger advance time is further calculated; Depending on the direction of the current, the trigger path is executed independently through different channels to drive either of the two thyristors to conduct; After the thyristor is turned on, current switching and verification are performed; Based on the load current amplitude, adaptive protection is implemented, and fault codes are recorded.

[0109] Preferred, In the contact action trigger detection step, the displacement of the moving contact K is transmitted to the FPGA in real time through a photoelectric encoder.

[0110] Preferred, In the process of determining the direction and phase of the current, the FPGA identifies the zero-crossing point of the current through a digital comparator.

[0111] Preferred, In the step of independent trigger path execution, the FPGA generates PWM_OUT1 or PWM_OUT2 pulses according to the current direction, and drives the gate of the first thyristor SCR1 or the second thyristor SCR2 to turn on respectively through the optocoupler isolator.

[0112] Preferred, In the current switching and verification steps, the FPGA determines the conduction state by monitoring the thyristor anode-cathode voltage drop VAK.

[0113] Preferred, In the adaptive and protection steps, the FPGA dynamically adjusts the trigger advance time based on the real-time current amplitude to ensure that the thyristor turns on before the current crosses zero.

[0114] Preferred, It also includes natural turn-off and contact complete disconnection steps: when the current crosses zero, the thyristor automatically turns off, and after the FPGA confirms that contact K is completely disconnected, the PWM output is turned off and the relevant timers are reset.

[0115] Preferred, During the fault handling process, if a fault is detected, the FPGA triggers the backup circuit breaker to forcibly shut down the main circuit and records the fault code, triggering an alarm via LED or communication interface.

[0116] Preferred, The method also includes system reset and preparation for the next switchover: after the exception handling is completed or after natural shutdown, the FPGA resets all status registers and timers, the moving contact K returns to the closed position, and re-enters the steady-state monitoring state.

[0117] Preferred, The FPGA uses a finite state machine (FSM) to manage the entire switching process, ensuring strict logic self-consistency, including initialization, steady-state monitoring, contact displacement detection, current direction determination, trigger pulse generation, conduction verification, natural turn-off, exception handling, and system reset.

[0118] In summary, the method of the present invention mainly includes: Contact movement trigger detection: The displacement of the moving contact K is transmitted to the FPGA via a photoelectric encoder, triggering the switching process.

[0119] Current direction and phase determination: H1 / H2 detects the current polarity, and the FPGA determines the direction through dual-channel signals and calculates the trigger advance time.

[0120] Independent trigger path execution: Forward current (M→N) → FPGA generates PWM_OUT1 → Optocoupler 1 → R_g1 → SCR1 gate turns on.

[0121] Reverse current (N→M) → FPGA generates PWM_OUT2 → optocoupler 2 → R_g2 → SCR2 gate turns on.

[0122] Current switching and verification: After the thyristor is turned on, the main circuit current is transferred to the bypass, and the FPGA verifies the conduction status through voltage drop or current sensor.

[0123] Adaptation and Protection: In case of overload, the trigger advance time is dynamically shortened; if the circuit breaker is not triggered before the timeout, the fault code is recorded.

[0124] For example, the method includes the following steps: Step 1: System Initialization and Parameter Loading Power-on self-test: The main circuit mechanical contacts (A / D) remain closed, and the thyristors (SCR1 / SCR2) are in the off state.

[0125] The FPGA is loaded with preset parameters (trigger advance angle θ=5°, pulse width 50μs, maximum conduction time 12ms).

[0126] Hall sensors (H1 / H2) perform zero-point calibration to eliminate interference from ambient magnetic fields.

[0127] Preparation for steady-state monitoring: The signal conditioning circuit is activated, and the ADC module acquires the current signal at a sampling rate of 1MHz.

[0128] The photoelectric encoder is initialized, and the displacement status of the moving contact K is monitored in real time.

[0129] Step 2: Moving contact displacement detection and switching triggering Displacement threshold determination: When the displacement of the moving contact K exceeds 0.1mm, the photoelectric encoder outputs a digital signal to the FPGA.

[0130] Set the FPGA switching flag (Flag_Switch=1) to start the switching process.

[0131] Synchronization of mechanical movements: As contact K continues to move, the resistance of the main circuit gradually increases, and the current begins to shift to the thyristor branch.

[0132] Step 3: Current signal acquisition and direction determination Simultaneous sampling by dual sensors: Hall sensor H1 detects the current direction on the power supply side (M), and H2 detects the current direction on the load side (N).

[0133] The signal conditioning circuit filters (cutoff frequency 1kHz) and amplifies the original signal.

[0134] Zero-crossing detection: The FPGA uses a digital comparator to identify the zero-crossing point (ZCP) of the current.

[0135] Calculate the current frequency f; Directional logic determination: Forward current (M→N): H1 outputs a positive voltage, and the voltage of H2 is below the threshold.

[0136] Reverse current (N→M): H2 outputs a positive voltage, and the voltage of H1 is below the threshold.

[0137] Step 4: Trigger Pulse Generation and Gate Drive Trigger advance time calculation: Calculate the trigger advance time based on the preset θ (e.g., 5°) and the real-time frequency f; Dynamic load adaptation: If the detected current amplitude is greater than the rated current, the trigger advance time will be shortened proportionally. Pulse generation and isolation drive: Forward current: The FPGA generates a PWM_OUT1 pulse (50μs width, 5V amplitude) before the current crosses zero. Its path is: FPGA → Optocoupler 1 → R_g1 (50Ω) → SCR1 gate (G).

[0138] Reverse current: The FPGA generates the PWM_OUT2 pulse, the path is: FPGA → optocoupler 2 → R_g2 (50Ω) → SCR2 gate (G).

[0139] Step 5: Verification of thyristor conduction and current switching Conductivity monitoring: The FPGA detects the anode-cathode voltage drop VAK of the thyristor using a voltage sensor.

[0140] Successful conduction: VAK < 1V (SCR is in a low-resistance state).

[0141] Trigger failure: If VAK>1V, the FPGA will initiate a re-trigger (up to 3 times) or a protection mechanism.

[0142] Current path switching: Forward conduction: The current switches from the main circuit to the path M→SCR1→SCR2→N.

[0143] Reverse conduction: Current switches to path N→SCR2→SCR1→M.

[0144] Step 6: Natural shutdown and complete disconnection of contacts Current zero-crossing turn-off: When the current crosses zero, the thyristor automatically turns off, and the main circuit current drops to zero.

[0145] The mechanical contact has completed its movement: Contact K continues to move to the fully disconnected position (mechanical delay of approximately 10ms) to ensure that no residual current flows through the contact.

[0146] Step 7: Exception Handling and Protection Mechanism Timeout protection: If the thyristor conduction time (t_on) > 12ms, the FPGA triggers the backup circuit breaker (such as the IGBT module) to forcibly disconnect the main circuit.

[0147] Fault logging and alarms: The FPGA records fault codes (such as "trigger timeout" or "sensor failure") and sends alarms via LEDs or communication interfaces.

[0148] Step 8: System Reset and Preparation for Next Switchover Contact reset: When contact K returns to the closed position, the FPGA clears the switching flag (Flag_Switch=0).

[0149] Re-entering steady-state monitoring: The Hall sensor resumes real-time sampling and awaits the next switching command.

[0150] It should be noted that the key nodes are connected as follows: From step 2 to step 3: The contact displacement trigger signal (Flag_Switch=1) directly starts the current signal acquisition and direction determination to ensure timing synchronization.

[0151] From step 4 to step 5: After the trigger pulse is generated, conduction verification is initiated immediately to form closed-loop control.

[0152] From step 7 to step 8: After the fault is handled, the system is forcibly reset to prevent the accumulation of faults.

[0153] Furthermore, in another embodiment, the processing method executed by the FPGA uses a state machine to manage the switching process, with each state corresponding to a specific timing action. For example: A finite state machine (FSM) is used to manage the transition process, defining seven core states. Each state corresponds to a clear sequence of actions and transition conditions, ensuring strict logical self-consistency. Specifically: State 1: Initialization (INIT) Entry condition: FPGA power-on or hard reset signal trigger.

[0154] Perform the following actions: Load preset parameters: trigger advance angle θ, pulse width t pulse, maximum conduction time t max.

[0155] Self-testing sensors (Hall H1 / H2, photoelectric encoder) and communication interfaces (SPI / GPIO).

[0156] Initialize the PWM output port (PWM_OUT1 / 2) to low level.

[0157] Clear the fault flag register.

[0158] Exit condition: Self-test passes and parameters are loaded, then jump to steady-state monitoring state.

[0159] State 2: Steady-state monitoring (MONITOR) Entry condition: Initialization completed or system reset.

[0160] Perform the following actions: The current signals of Hall sensors H1 / H2 are acquired in real time, and the frequency and amplitude are calculated.

[0161] Monitor the displacement of the moving contact K (photoelectric encoder signal).

[0162] Check the fault flag register. If there is an unhandled fault, jump to the exception handling state.

[0163] Exit conditions: Normal switching: When the contact displacement exceeds the threshold (0.1mm), the system switches to contact displacement detection mode.

[0164] Abnormal Trigger: If a sudden current change or sensor failure is detected, the system will switch to the abnormal handling state.

[0165] State 3: Contact Displacement Detection (DETECT_DISPLACEMENT) Entry condition: The contact displacement exceeds the limit during steady-state monitoring.

[0166] Perform the following actions: Lock the current current direction and phase (to avoid signal fluctuation interference during switching).

[0167] Start timer T1 to record the displacement speed of contact K.

[0168] Predict the time t_disconnect when the contact is completely disconnected and match it with the preset timing.

[0169] Exit conditions: Allow triggering: t disconnect matches the current zero-crossing point and jumps to the current direction determination state.

[0170] Timing conflict: If the prediction time deviation is >10%, jump to the anomaly handling state.

[0171] State 4: Current direction determination (CHECK_DIRECTION) Entry condition: Contact displacement detection passed.

[0172] Perform the following actions: Read the polarity signals of H1 / H2, and determine the direction by combining the current zero-crossing point: Forward (M→N): H1 is positive voltage, H2 is low level.

[0173] Reverse (N→M): H2 is positive voltage, H1 is low level.

[0174] The trigger advance time tpre is dynamically calculated and adaptively corrected based on the load current amplitude.

[0175] Exit condition: Direction determination complete, jump to trigger pulse generation state.

[0176] State 5: Trigger pulse generation (GEN_PULSE) Entry condition: Current direction determination completed.

[0177] Perform the following actions: Forward current: Configure PWM_OUT1 parameters (t pre, t pulse) and start timer T2.

[0178] Reverse current: Configure PWM_OUT2 parameters and start timer T2.

[0179] At the moment tpre before the current crosses zero, a trigger pulse (50μs high level) is output.

[0180] Exit conditions: Pulse transmission complete: Jump to conduction verification state.

[0181] Timeout failed to trigger: Timer T2 overflowed, jump to exception handling state.

[0182] State 6: Continuity Verification (VERIFY_CONDUCTION) Entry condition: Trigger pulse has been sent.

[0183] Perform the following actions: Read the thyristor anode-cathode voltage drop VAK.

[0184] Determine the conduction status: Successful conduction: VAK < 1V, jump to natural shutdown state.

[0185] Connection failed: If VAK > 1V, retry triggering (maximum 3 times).

[0186] Exit conditions: Verification successful: Jump to natural shutdown state.

[0187] Retry exceeded: Jump to exception handling status.

[0188] State 7: Natural_OFF Entry condition: The thyristor is successfully turned on.

[0189] Perform the following actions: Monitor the current as it crosses zero and wait for the thyristor to turn off naturally.

[0190] Confirm that contact K is completely disconnected (displacement reaches maximum value).

[0191] Turn off PWM output and reset timers T1 / T2.

[0192] Exit condition: The contact has been disconnected and the system will jump to the reset state.

[0193] State 8: Exception Handling (ERROR_HANDLE) Entry condition: A fault is detected in any state (timeout, sensor failure, etc.).

[0194] Perform the following actions: The standby circuit breaker is triggered to forcibly shut down the main circuit.

[0195] Record the fault code (error type, timestamp).

[0196] Alarms are triggered via LEDs or communication interfaces.

[0197] Exit condition: Fault clearing or manual reset signal, jump to system reset state.

[0198] Status 9: System Reset (SYSTEM_RESET) Entry conditions: Natural shutdown completed or abnormal handling ended.

[0199] Perform the following actions: Reset all status registers and timers.

[0200] The moving contact K returns to the closed position.

[0201] Re-enable steady-state monitoring function.

[0202] Exit condition: Reset complete, jump to steady-state monitoring state.

[0203] In another embodiment, the present invention discloses a method for a three-branch on-load tap changer based on arc-free operation, comprising the following steps: The switching process is triggered by detecting the contact movement using a photoelectric encoder. The current direction and phase are determined through different channels, and the trigger advance time is further calculated; Depending on the direction of the current, the trigger path is executed independently through different channels to drive either of the two thyristors to conduct; After the thyristor is turned on, current switching and verification are performed; Based on the load current amplitude, adaptive protection is implemented, and fault codes are recorded.

[0204] In another embodiment, a method for a three-branch on-load tap changer based on arc-free operation includes the following steps: Contact movement trigger detection: The displacement of the moving contact K is detected by a photoelectric encoder. When the displacement exceeds a preset threshold, the switching process is triggered. Current direction and phase determination: Hall sensors H1 and H2 are used to detect the direction and amplitude of the main circuit current. The FPGA determines the current direction through dual-channel signals and calculates the trigger advance time. Independent trigger path execution: Based on the current direction, the FPGA generates a corresponding trigger pulse, which drives the thyristor SCR1 or SCR2 to conduct through different optocoupler isolators and gate current limiting resistors; Current switching and verification: After the thyristor is turned on, the main circuit current is transferred to the bypass. The FPGA verifies the conduction state of the thyristor through voltage or current sensors. Adaptive and protective: The trigger advance time is dynamically adjusted according to the load current amplitude. If the circuit breaker is not turned off within the time limit, the backup circuit breaker is triggered and the fault code is recorded.

[0205] In another embodiment, to avoid trigger failure due to insufficient current when the FPGA directly drives the thyristor, the isolation drive circuit for the FPGA-driven thyristor adopts a three-stage cascaded amplification structure, including: The signal isolation stage, composed of high-speed optocouplers, achieves electrical isolation between the FPGA and the power circuit. The current amplification stage, composed of bipolar junction transistors (BJTs), provides primary current amplification; The power output stage, composed of MOSFETs, provides sufficient gate drive current.

[0206] Specifically, the following components are used to achieve this: The high-speed optocoupler HCPL-3120 has its input terminal connected to the PWM output port of the FPGA, with an isolation voltage ≥3500V; The NPN transistor 2N3904 has its base connected to the optocoupler output terminal and its collector connected to the +15V power supply through a pull-up resistor. The N-channel MOSFET IRF540N has its gate connected to the emitter of the transistor 2N3904, its drain connected to a +15V power supply, and its source connected to the thyristor gate through a gate current limit resistor. The gate current limiting resistor R_g has a resistance of 50Ω. One end is connected to the source of the MOSFET, and the other end is connected to the gate of the thyristor. The gate protection circuit includes a 100nF ceramic capacitor and an 18V Zener diode connected in parallel between the gate and cathode of the thyristor. The anode of the optocoupler HCPL-3120 is connected to the PWM output of the FPGA through a current-limiting resistor (330Ω), and the cathode is grounded. The output collector of the optocoupler HCPL-3120 is connected to a +15V power supply via a pull-up resistor (1kΩ), and the emitter is grounded. The base of the transistor 2N3904 is connected to the output of the optocoupler, the emitter is grounded, and the collector is connected to the +15V power supply through a 1kΩ resistor. The gate of the MOSFET IRF540N is connected to the collector of the transistor 2N3904, the drain is connected to the +15V power supply, and the source is connected to the gate current limiting resistor R_g. The other end of the gate current limiting resistor R_g is connected to the thyristor gate; A 100nF capacitor and an 18V Zener diode are connected in parallel between the gate and cathode of the thyristor. 1) When the FPGA outputs a high level, the internal LED of the optocoupler is turned on, which turns on the output transistor of the optocoupler, pulling the base of the NPN transistor 2N3904 low; When the NPN transistor 2N3904 is turned on, the gate voltage of the MOSFET IRF540N drops, and the MOSFET turns on. After the MOSFET IRF540N is turned on, the +15V power supply provides drive current to the thyristor gate through the gate current limiting resistor; The gate protection circuit ensures that the thyristor gate voltage does not exceed 18V to prevent overvoltage damage. 2) When the FPGA outputs a low level, the internal LED of the optocoupler is turned off, the entire circuit returns to its initial state, and there is no drive signal at the gate of the thyristor.

[0207] Since the HCPL-3120 can provide an isolation voltage of ≥3500V, this invention can effectively prevent power system interference from affecting the FPGA. In addition, the three-stage cascaded amplification structure can provide an instantaneous drive current of >200mA, far exceeding the gate trigger current requirement of the thyristor. The performance of the devices used ensures that the overall circuit response time is <1μs, thus meeting the requirements of high-frequency switching. Furthermore, the gate protection circuit can prevent overvoltage and voltage oscillation, extending the thyristor life. For thyristors of different specifications, only the appropriate gate current limiting resistor value needs to be adjusted or selected.

[0208] In the three-branch on-load tap changer disclosed in this invention, the isolation drive circuit can be implemented as two identical drive circuits, respectively applied to the gate drive of thyristors SCR1 and SCR2, wherein: The first set of driver circuits connects the PWM_OUT1 output terminal of the FPGA to the gate of SCR1. The second set of driving circuits connects the PWM_OUT2 output terminal of the FPGA to the gate of SCR2.

[0209] Therefore, this drive circuit works in conjunction with the finite state machine (FSM) controlled by the FPGA to ensure that the FPGA can trigger the corresponding thyristors as needed, achieving true arc-free switching. Actual tests show that after adopting this drive circuit, the thyristor triggering success rate increased from 92% to 99.8%. Especially under high load conditions, the triggering reliability is significantly improved, effectively solving the problem that the FPGA may fail to trigger the thyristors without the drive circuit.

[0210] Preferred, In the contact action trigger detection step, the displacement of the moving contact K is transmitted to the FPGA in real time through the photoelectric encoder. When the displacement exceeds 0.1mm, the switching process is triggered.

[0211] In another embodiment, in the current direction and phase determination step, the FPGA identifies the current zero-crossing point through a digital comparator and determines the current direction by combining the output signals of Hall sensors H1 and H2.

[0212] In another embodiment, in the independent trigger path execution step, the FPGA generates PWM_OUT1 or PWM_OUT2 pulses according to the current direction, and drives the gate of the first thyristor SCR1 or the second thyristor SCR2 to turn on respectively through an optocoupler isolator.

[0213] In another embodiment, during the current switching and verification step, the FPGA determines the conduction state by monitoring the thyristor anode-cathode voltage drop VAK. If VAK is less than 1V, the conduction is considered successful.

[0214] In another embodiment, in the adaptive and protection step, the FPGA dynamically adjusts the trigger advance time based on the real-time current amplitude to ensure that the thyristor turns on before the current crosses zero.

[0215] In another embodiment, a natural turn-off and contact complete disconnection step is also included: when the current crosses zero, the thyristor automatically turns off, and after the FPGA confirms that contact K is completely disconnected, the PWM output is turned off and the relevant timer is reset.

[0216] In another embodiment, during the fault handling step, if a fault is detected, the FPGA triggers the backup circuit breaker to forcibly shut down the main circuit and records the fault code, triggering an alarm via LED or communication interface.

[0217] In another embodiment, the method further includes a system reset and preparation for the next switchover step: after the exception handling is completed or after natural shutdown, the FPGA resets all status registers and timers, the moving contact K returns to the closed position, and re-enters the steady-state monitoring state.

[0218] In another embodiment, the FPGA employs a finite state machine (FSM) to manage the entire switching process, ensuring strict logical self-consistency, including initialization, steady-state monitoring, contact displacement detection, current direction determination, trigger pulse generation, conduction verification, natural shutdown, exception handling, and system reset.

[0219] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the invention to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A three-branch on-load tap changer with no arcing, characterized in that, include: Main circuit branch, used as a low-resistance mechanical contact path; Thyristor bypass branch, used as a bidirectional arc-free switching path; The intelligent trigger branch serves as a dynamic control signal path, used to detect the current direction and amplitude of the main circuit branch and generate trigger pulses to control the conduction of the thyristor. The main circuit branch and the thyristor bypass branch are respectively connected to the FPGA controller in the intelligent trigger branch.

2. The arc-free three-branch on-load tap changer according to claim 1, characterized in that, The main circuit branch includes stationary contact A, stationary contact D, and moving contact K, which are respectively connected between power supply M and load N. The first end of stationary contact A is directly connected to power supply M, and the second end is in movable contact with one end of moving contact K. The other end of moving contact K is in movable contact with the first end of stationary contact D. The second end of stationary contact D is directly connected to load N.

3. The arc-free three-branch on-load tap changer according to claim 1, characterized in that, The thyristor bypass branch includes a first thyristor SCR1 and a second thyristor SCR2, which are connected in reverse parallel between the power supply M and the load N. The anode of the first thyristor SCR1 is directly connected to the power supply M, and its cathode is shared with the cathode of the second thyristor SCR2. The anode of the second thyristor SCR2 is directly connected to the load N. The FPGA controller controls the conduction and cutoff of the thyristor bypass branch.

4. The arc-free three-branch on-load tap changer according to claim 3, characterized in that, The intelligent triggering branch includes Hall sensor H1 and Hall sensor H2, as well as an FPGA controller and an isolation drive circuit. The Hall sensor H1 surrounds the input wire of the main circuit branch, and the Hall sensor H2 surrounds the output wire of the main circuit branch, and is used to detect the direction and amplitude of the current. The FPGA controller receives the Hall sensor signal processed by the signal conditioning circuit and the displacement state signal of the moving contact K, and generates two trigger pulse signals to trigger the first thyristor SCR1 and the second thyristor SCR2 respectively. The signal conditioning circuit is connected to the Hall sensor H1 and the Hall sensor H2.

5. The arc-free three-branch on-load tap changer according to claim 4, characterized in that, The isolation drive circuit includes an optocoupler isolator, which includes optocoupler 1 and optocoupler 2. The input terminal of optocoupler 1 is connected to the PWM_OUT1 output terminal of the FPGA controller, and the input terminal of optocoupler 2 is connected to the PWM_OUT2 output terminal of the FPGA controller.

6. The arc-free three-branch on-load tap changer according to claim 1, characterized in that, Also includes: The photoelectric encoder is used to detect the displacement of the moving contact K in the main circuit branch and transmit the displacement signal to the FPGA controller in real time.

7. The arc-free three-branch on-load tap changer according to claim 1, characterized in that, Also includes: The backup circuit breaker is triggered by the FPGA controller to forcibly disconnect the main circuit branch when the conduction time of any thyristor in the thyristor bypass exceeds a preset maximum value.

8. The arc-free three-branch on-load tap changer according to claim 4, characterized in that, The FPGA controller uses a finite state machine to manage the switching process, including initialization, steady-state monitoring, contact displacement detection, current direction determination, trigger pulse generation, conduction verification, natural shutdown, and abnormal handling.

9. The arc-free three-branch on-load tap changer according to claim 1, characterized in that, The isolation drive circuit adopts a three-stage cascaded amplification structure, including: a signal isolation stage composed of high-speed optocouplers; a current amplification stage composed of bipolar transistors; and a power output stage composed of MOSFETs.

10. A control method for a three-branch on-load tap changer without arcing as described in any one of claims 1 to 9, characterized in that, include: Contact action trigger detection steps: The displacement of the moving contact K is detected by the photoelectric encoder. When the displacement exceeds the preset threshold, the switching process is triggered. Hall sensors H1 and H2 are used to detect the direction and amplitude of the main circuit current. The FPGA controller determines the current direction through dual-channel signals and calculates the trigger advance time. According to the current direction, the FPGA controller generates a corresponding trigger pulse, which drives the first thyristor SCR1 or the second thyristor SCR2 to conduct through different optocouplers and gate current limiting resistors. After the first thyristor SCR1 or the second thyristor SCR2 is turned on, the main circuit current is transferred to the bypass. The FPGA controller verifies the conduction status of the first thyristor SCR1 or the second thyristor SCR2 through voltage or current sensors. The trigger advance time is dynamically adjusted according to the load current amplitude. If the circuit breaker is not turned off within the time limit, the backup circuit breaker is triggered and the fault code is recorded.

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