A hardware logic-based battery-powered low-voltage power supply control system

Abstract

This application relates to a hardware logic-based battery-powered low-voltage power supply control system. The system includes: an external power input unit for receiving external power and outputting an input bus voltage; a battery management unit connected to the external power input unit for managing battery charging using the input bus voltage and providing a battery output terminal; a power management unit connected to the battery output terminal, including a button-locking circuit and a hysteresis low-voltage detection circuit; the button-locking circuit responds to button operations and controls the connection / disconnection between the battery output terminal and the system bus; and a buck-boost microstepping power supply unit that uses the system bus as input and transforms and outputs at least one supply voltage. This application completely abandons the traditional power control method that relies on microcontrollers and software code, and constructs a highly reliable pure hardware cascade protection mechanism.

Description

Technical Field

[0001] This application relates to the field of battery power technology, and in particular to a battery-powered low-voltage power supply control system based on hardware logic. Background Technology

[0002] In the field of portable electronic devices, battery-powered systems typically need to implement functions such as charge and discharge management, power on / off control, and multiple power source conversion.

[0003] In existing technologies, the aforementioned functions generally rely on a microcontroller (MCU) and its accompanying software program for coordination and control. The microcontroller acquires the battery voltage through an analog-to-digital converter (ADC), processes it through software algorithms, and outputs control signals to implement undervoltage protection and power-on / off logic. However, microcontroller-based control schemes have several inherent drawbacks: First, the system is highly susceptible to battery damage due to software malfunctions. Under harsh conditions such as extreme temperatures, strong electromagnetic interference, or code defects, the microcontroller is prone to malfunctions or crashes. Once a crash occurs, the low-battery shutdown logic fails, causing the battery to be continuously drained until it is deeply over-discharged and completely damaged.

[0004] Secondly, there is a risk of repeated restarts and oscillations due to voltage rebound. Batteries have internal resistance, and their terminal voltage is pulled down when discharging under load. When the software triggers a low-power shutdown to remove the load, the battery terminal voltage rebounds instantly. Existing single-threshold or software hysteresis solutions are highly susceptible to this rebound voltage during system anomalies, causing the system to immediately meet the power-on conditions immediately after shutdown. This results in the device oscillating at the critical voltage point through high-frequency cycles of power-on, drop-down shutdown, rebound, and then power-on again, which can easily burn out downstream hardware.

[0005] Finally, traditional shutdown methods are incomplete and have high standby power consumption. Existing control logic typically only disconnects downstream loads or puts the MCU into sleep mode when shutting down, leaving the system main bus energized. The static operating current of the microcontroller and power chip will still slowly deplete the battery during long-term storage.

[0006] Based on the above, how to achieve true physical-level cutoff protection through pure hardware logic circuits without relying on microcontrollers and software programs, effectively solve the system oscillation problem caused by battery voltage rebound, and ensure extremely low standby power consumption of the entire system after shutdown is a problem that urgently needs to be solved in this technical field. Summary of the Invention

[0007] In view of the above-mentioned defects or improvement needs of the prior art, this application provides a battery-powered low-voltage power supply control system based on hardware logic, which completely abandons the traditional power control method that relies on microcontrollers and software code, and constructs a highly reliable pure hardware cascade protection mechanism.

[0008] The embodiments of this application adopt the following technical solutions: This application provides a hardware logic-based battery-powered low-voltage power supply control system, including: External power input unit, used to receive external power and output input bus voltage; The battery management unit is connected to the external power input unit and is used to manage the charging of the battery using the input bus voltage, and to provide a battery output terminal. The power management unit is connected to the battery output terminal and includes a button self-locking circuit and a hysteresis low-voltage detection circuit; the button self-locking circuit responds to button operation and controls the connection and disconnection between the battery output terminal and the system bus. The step-up / step-down subdivision power supply unit takes the system bus as input and transforms the output voltage of at least one power supply line. The button self-locking circuit includes a self-locking feedback path, which feeds back the output voltage of the buck-boost subdivision power supply unit to the control terminal of the button self-locking circuit to maintain the conduction state of the system bus after the button is released. The hysteresis low-voltage detection circuit includes a hysteresis comparator. The input of the hysteresis comparator is connected to the system bus, and the output of the hysteresis comparator is connected to the enable terminal of the buck-boost subdivision power supply unit. The hysteresis comparator is powered by an independent reference power supply, which is directly powered by the battery output and is independent of the system bus. When the voltage of the system bus is lower than the shutdown threshold, the hysteresis comparator shuts down the buck-boost subdivision power supply unit. The self-locking feedback path releases the conduction state of the system bus due to the loss of feedback voltage, forming a cascaded shutdown. The recovery threshold of the hysteresis comparator is higher than the shutdown threshold.

[0009] Through the above technical solution, this application completely abandons the traditional power control method that relies on microcontrollers and software code, and constructs a highly reliable pure hardware cascade protection mechanism. Specifically: Cascaded shutdown prevents deep discharge: When the battery voltage is too low, the hysteresis comparator first shuts down the enable terminal of the buck-boost subdivision power supply unit, causing its output voltage to drop; the self-locking feedback path automatically releases the self-locking switch due to the loss of this output voltage, thereby disconnecting the system bus. This hardware cascaded shutdown, which involves low voltage detection -> power-off of the subsequent stage -> disconnection of the preceding stage bus, completely cuts off the power consumption path of the entire system (including the main control circuit and branch power supplies), achieving true zero-power physical-level shutdown and greatly protecting the battery from deep over-discharge damage.

[0010] Independent power supply ensures uninterrupted monitoring: The hysteresis comparator is powered by an independent reference power source directly drawn from the battery, independent of the controlled system bus. This ensures that even after the system bus is completely powered off, the low-voltage detection loop can continue to monitor the battery voltage continuously and accurately with extremely low power consumption.

[0011] Hysteresis characteristics solve the pain point of oscillation and crashes: The hardware-set recovery threshold is higher than the shutdown threshold, perfectly solving the industry pain point of repeated automatic start-stop and crashes at the critical point caused by voltage rebound after the battery disconnects from a high-current load. The overall solution has significant advantages such as nanosecond-level response speed, resistance to software crash interference, and ultra-low standby power consumption.

[0012] In some embodiments, the button self-locking circuit further includes an RC delay network and a self-locking switch; The input of the RC delay network is connected to an external button, and the output is connected to the control terminal of the self-locking switch. The self-locking switch includes two MOS transistors connected back to back. The gates of the two MOS transistors together serve as the control terminal of the self-locking switch, and the drains of the two MOS transistors are respectively connected to the battery output terminal and the system bus. The self-locking feedback path includes an isolation diode and a pull-up resistor. The output voltage of the buck-boost subdivision power supply unit is connected to the gates of the two MOS transistors via the isolation diode and the pull-up resistor.

[0013] Through the above technical solutions, the RC delay network realizes pure hardware button debounce and long press power-on delay; the back-to-back MOSFET structure realizes bidirectional isolation switch between the system bus and the battery output terminal, avoiding the load current on the system bus from being reverse-flowed into the battery through the body diode; the isolation diode prevents the self-locking feedback voltage from being pulled down by the subsequent circuit during the power-off process, ensuring unidirectional triggering and high reliability of the cascaded power-off process.

[0014] In some embodiments, the button self-locking circuit further includes a power-off control branch; The shutdown control branch includes a shutdown trigger terminal and a shutdown switch transistor; the shutdown trigger terminal is used to receive an external shutdown signal, the gate of the shutdown switch transistor is connected to the shutdown trigger terminal, the drain of the shutdown switch transistor is connected to the control terminal of the self-locking switch, and the source is grounded; a holding capacitor is connected between the gate of the shutdown switch transistor and ground. When the power-off trigger terminal receives the external power-off signal, the power-off switch transistor is turned on and pulls the control terminal of the self-locking switch low. The holding capacitor maintains the on-time of the power-off switch transistor to ensure that the feedback voltage of the self-locking feedback path is completely discharged, thereby causing the self-locking switch to be completely turned off.

[0015] Through the above technical solution, the shutdown control branch ensures that the conduction time of the shutdown switch tube can cover the complete discharge process of the self-locking feedback voltage by maintaining the capacitor, thus avoiding shutdown failure and system crash restart due to the self-locking circuit not being completely released because the transient shutdown signal is too short; at the same time, the shutdown trigger terminal is compatible with external button and wired control level signals, which expands the flexibility of the system shutdown method.

[0016] In some implementations, the independent reference power supply is a low-dropout linear regulator, the input of which is directly connected to the battery output, and the output of which outputs a fixed reference voltage to the hysteresis comparator. The non-inverting input of the hysteresis comparator is connected to the system bus through a first voltage divider network, and the inverting input of the hysteresis comparator is connected to the reference voltage. A positive feedback resistor is connected between the output of the hysteresis comparator and the non-inverting input to enable the hysteresis comparator to exhibit hysteresis characteristics.

[0017] Through the above technical solution, the independent reference power supply is directly powered by the battery and does not pass through the controlled system bus, so that after the system is powered off, the hysteresis comparator can continue to monitor the changes in battery voltage with ultra-low power consumption at the microampere level, ensuring that it can accurately determine whether the battery voltage has reached the recovery threshold during the charging recovery process; the hardware hysteresis window formed by the positive feedback resistor avoids the comparator from oscillating and flipping near the critical point of battery voltage.

[0018] In some implementations, the battery voltage range corresponding to the turn-off threshold of the hysteresis comparator is 3.40V to 3.50V, and the battery voltage range corresponding to the recovery threshold of the hysteresis comparator is 3.50V to 3.60V.

[0019] Through the above technical solution, a hardware hysteresis window of approximately 100mV is formed between the shutdown threshold and the recovery threshold. The shutdown threshold corresponds to the critical region of deep battery discharge, which can effectively avoid battery over-discharge damage; the recovery threshold ensures that the battery has sufficient capacity margin before re-energizing the system, preventing the system from repeatedly starting and stopping in the extremely unstable range when the battery power is insufficient.

[0020] In some embodiments, the battery management unit includes a charging rate control circuit; The charging rate control circuit includes an input voltage divider network and a rail-to-rail comparator; the input voltage divider network is connected to the output terminal of the external power input unit, the non-inverting input terminal of the rail-to-rail comparator is connected to the voltage divider output terminal of the input voltage divider network, and the inverting input terminal of the rail-to-rail comparator is connected to a fixed reference voltage; The output of the rail-to-rail comparator is connected to a resistor divider network of the charging current setting terminal of the charging management chip, so that the output level of the rail-to-rail comparator can switch the equivalent resistance value of the resistor divider network, thereby changing the charging current limit value of the charging management chip through hardware.

[0021] The above technical solution utilizes a purely analog rail-to-rail comparator to perform hardware threshold discrimination of the external input voltage. Based on the discrimination result, the equivalent voltage division ratio of the charging current setting terminal is automatically switched to achieve automatic switching between high-current fast charging and low-current slow charging. This completely eliminates the need for microcontroller ADC sampling and software code judgment, achieving a response speed at the nanosecond level and extremely high system robustness.

[0022] In some implementations, the voltage division ratio of the input voltage divider network is configured such that when the input bus voltage of the external power supply input unit is 6.6V, the voltage at the voltage divider output terminal is equal to the fixed reference voltage. When the input bus voltage is greater than 6.6V, the rail-to-rail comparator outputs a high level, and the charging current limit is configured as a first current value; when the input bus voltage is less than or equal to 6.6V, the rail-to-rail comparator outputs a low level, and the charging current limit is configured as a second current value; the first current value is greater than the second current value.

[0023] Through the above technical solution, the threshold for hardware charging rate switching is cleverly set to 6.6V (higher than the standard USB 5V power supply voltage and lower than the 9V / 12V output voltage commonly used in PD fast charging protocols). This enables automatic current limiting for slow charging when connected to standard USB (5V) to protect the adapter from overload, and automatic unlocking of high-current fast charging when connected to PD fast charging (9V / 12V), greatly improving charging efficiency and compatibility.

[0024] In some embodiments, the battery management unit further includes a time-sharing voltage acquisition circuit; The time-division voltage acquisition circuit includes a sampling voltage divider resistor pair and a cascaded MOSFET switch; one end of the sampling voltage divider resistor pair is connected to the battery output terminal, and the other end is grounded through the cascaded MOSFET switch; The cascaded MOS transistor switch includes a PMOS transistor connected in series in the grounding loop and an NMOS transistor driving the PMOS transistor; the gate of the NMOS transistor is connected to an external acquisition control signal terminal, and the drain is connected to the gate of the PMOS transistor; the source of the PMOS transistor is connected to the battery output terminal. When the external acquisition control signal terminal is high, the NMOS transistor is turned on and pulls down the gate voltage of the PMOS transistor, thus turning on the PMOS transistor. The sampling voltage divider resistor pair forms a voltage divider circuit and outputs a sampling voltage. When the external acquisition control signal terminal is low or floating, both the NMOS transistor and the PMOS transistor are turned off, and the sampling voltage divider resistor pair has no static power consumption current.

[0025] The above technical solution employs a cascaded switching structure where a low-voltage NMOS drives a high-side PMOS, enabling external (e.g., from the motherboard) 1.8V or 3.3V acquisition control signals to effectively control the on / off state of the grounding loop without reaching the battery's high level, thus eliminating the level mismatch problem. The time-division control method ensures that the voltage divider resistor is completely disconnected from ground during non-acquisition periods, eliminating the continuous leakage current of the voltage divider resistor network and significantly reducing the battery's standby power consumption.

[0026] In some implementations, the external power input unit includes a DC input interface and a USB interface; The DC input interface allows an input voltage range of 5V to 28V; the USB interface is equipped with a PD fast charging protocol chip, which requests a preset fast charging voltage from the power supply end only through the level configuration of its own hardware pins. A hardware priority selection circuit is provided between the DC input interface and the output terminal of the USB interface. The hardware priority selection circuit includes an isolation PMOS transistor. When the input voltage of the DC input interface is higher than the output voltage of the USB interface, the isolation PMOS transistor is biased and cut off to cut off the output path of the USB interface.

[0027] Through the above technical solutions, the dual input interfaces can automatically and seamlessly switch through a pure hardware priority selection circuit, avoiding the risk of current backflow and high voltage breakdown caused by powering the downstream stage when two external power supplies are connected at the same time; the PD fast charging protocol chip can directly handshake the fast charging voltage through fixed hardware pin configuration, without the participation of any software protocol stack, thus maintaining the original design intention of zero code and pure hardware of the entire power control system and its extremely high reliability.

[0028] In some embodiments, the buck-boost subdivision power supply unit includes a boost regulator sub-circuit and a multi-channel subdivision sub-circuit; The boost regulator sub-circuit takes the system bus as input and boosts and regulates it to a standard 5V voltage. The multi-channel sub-circuit uses the 5V standard voltage as a common input reference and transforms the output to a 12V drive power rail, a 3.3V digital power rail, and multiple low-voltage analog power rails through independent DC-DC step-down circuits and LDO linear regulator circuits; each power rail output is equipped with an independent LC filter network.

[0029] The above technical solution utilizes a boost sub-circuit to uniformly boost and stabilize the fluctuating system bus (battery voltage) to a standard 5V voltage. Then, a secondary step-down subdivision is performed based on this voltage, effectively isolating the front-end fluctuations caused by the decrease in battery voltage. Each sub-power rail is electrically isolated through independent conversion circuits and LC filter networks, avoiding interference from digital circuit switching noise on analog sensitive circuits. This provides an extremely clean and stable multi-channel power supply guarantee for various complex load devices in the downstream stage.

[0030] In summary, this application includes at least the following beneficial technical effects: 1. Achieving highly reliable pure hardware cascaded power-off protection completely eliminates the risk of software crashes. This application ingeniously constructs a hardware cascaded shutdown logic: hysteresis comparator disconnects the subsequent microstepping power supply -> no output in the subsequent stage leads to the disappearance of feedback -> the front-end button self-locking circuit automatically unlocks -> the system bus is physically powered off. No microcontroller intervention is required throughout the process, making it immune to any software crashes or malfunctions; when the battery is low, it can completely cut off the system bus, achieving physical-level zero-power shutdown and providing ultimate protection against deep over-discharge damage.

[0031] 2. The hardware hysteresis characteristic completely eliminates system oscillations and crashes caused by battery voltage rebound. This application introduces a hardware comparator with hysteresis characteristics into the low-battery detection circuit and sets the recovery threshold to be significantly higher than the shutdown threshold. This ensures that after the system shuts down due to low battery, the load is removed, and the battery voltage rebounds, the rebound voltage remains within the hysteresis window and cannot trigger a restart. Enable is only restored when the battery is effectively charged and crosses the higher recovery threshold. This mechanism completely eliminates the potential for repeated automatic start-stop cycles near critical battery levels from the underlying hardware logic, greatly improving system stability and hardware lifespan.

[0032] 3. An independent reference power supply architecture enables uninterrupted ultra-low power monitoring after power failure. The hysteresis low-voltage detection loop in this application uses an ultra-low power reference power supply (directly powered by the battery) independent of the system bus. This architecture ensures that even when the system bus is completely powered off, the comparator can still continuously and accurately monitor the battery voltage at ultra-low power consumption in the microamp or even nanoamp range. This ensures that the recovery threshold can be accurately determined when the device is plugged in for charging, perfectly balancing ultra-long standby time during shutdown and real-time status monitoring.

[0033] 4. The end-to-end pure hardware adaptive control significantly reduces system complexity and cost. In addition to basic power-on / off and protection, this application further implements automatic switching of charging rates (adapting to standard USB and fast charging) through rail-to-rail comparators, time-sharing low-power voltage acquisition through cascaded MOSFETs, and multi-input reverse-current protection switching through hardware priority circuits. The entire system constructs a complete and self-consistent zero-code hardware power management ecosystem, eliminating the development, debugging, and maintenance costs of microcontrollers and software programs, greatly shortening the product development cycle, and improving overall robustness under complex operating conditions. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments of this application will be briefly described below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 A block diagram of the overall architecture of a battery-powered low-voltage power supply control system based on hardware logic, provided for embodiments of this application; Figure 2 The schematic diagram of the external USB+DC input hardware circuit provided in the embodiments of this application; Figure 3 A charging management circuit diagram provided for an embodiment of this application; Figure 4 A schematic diagram of the hardware charging rate control circuit provided in the embodiments of this application; Figure 5 This is a circuit diagram for battery voltage acquisition provided in an embodiment of this application; Figure 6 This application provides a circuit diagram for a button delay + power self-locking power on / off control circuit. Figure 7 This is a schematic diagram of a power-on self-locking MOS switch provided in an embodiment of this application; Figure 8 A 5V system DC-DC regulator circuit diagram provided in the embodiments of this application; Figure 9 This is a circuit diagram of a multi-channel buck-boost microstepping power supply provided in an embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. Furthermore, the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other.

[0037] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0038] Example 1: This embodiment describes the overall architecture of a battery-powered low-voltage power supply control system based on hardware logic.

[0039] It should be noted that existing battery-powered systems rely on microcontrollers and software programs to achieve charge and discharge management and power control, which has problems such as the risk of software crashes, high development and maintenance costs, and the non-negligible power consumption of the microcontroller itself.

[0040] To address the aforementioned issues, this application constructs a four-level hardware link architecture consisting of an external power input unit, a battery management unit, a power management unit, and a buck-boost subdivision power supply unit connected sequentially. All control logic is implemented using analog hardware devices. This approach eliminates the risk of software failures, reduces system cost and complexity, and improves the reliability of the power system under extreme operating conditions.

[0041] refer to Figure 1 As shown, this embodiment provides a battery-powered low-voltage power supply control system based on hardware logic, including an external power input unit, a battery management unit, a power management unit, and a buck-boost microstepping power supply unit connected in sequence. All control logic of the system, including charge / discharge management, power-on / off control, and charging current level switching, is implemented using analog hardware circuits, including comparators, MOSFETs, RC voltage divider networks, switching power supply chips, protection diodes, and other analog hardware devices, eliminating the need for a microcontroller and accompanying software programs.

[0042] Specifically, the external power input unit receives external power, and after hardware protection and priority selection, outputs a unified input bus voltage VDD_INPUT to the battery management unit. The battery management unit uses VDD_INPUT to manage battery charging and provides time-sharing low-power acquisition of battery voltage. The power management unit obtains power from the battery output, controls the on / off state of the system bus VCC_SYS through a button self-locking circuit, and boosts VCC_SYS to a 5V standard voltage VCC_5V_STD through a boost regulator circuit. The buck-boost microstepping power supply unit uses VCC_5V_STD as input and converts and outputs multiple microstepped power rails such as 12V and 3.3V to power various downstream load devices.

[0043] The entire system forms a closed-loop control of hardware logic throughout the entire process, from external power input to multiple power outputs, without relying on any microcontroller, firmware program, or software algorithm.

[0044] Example 2: This embodiment further explains the external power input unit.

[0045] It should be noted that portable devices must be compatible with multiple external power supply methods, and current backflow and voltage conflict between different power sources must be prevented. At the same time, the input terminal must have surge and electrostatic protection capabilities.

[0046] To address the aforementioned issues, this application embodiment features dual input channels: a DC input interface and a USB interface. It incorporates a PD fast charging protocol chip and a hardware priority selection circuit, and integrates ESD / TVS protection devices, a resettable fuse, and a filter capacitor in the input circuit. This approach enables automatic switching and mutual isolation between the wide-voltage DC input and the USB PD fast charging input, protecting downstream circuitry from surge and electrostatic interference.

[0047] refer to Figure 2 As shown, the external power input unit includes two input channels: a DC input interface and a USB interface. The DC input interface supports a wide voltage input range of 5V to 28V, adapting to various external DC adapters. The input circuit is equipped with a series current-limiting resistor, a Schottky protection diode, and a multi-layer ceramic filter capacitor and a high-voltage current-resistant RC network to provide hardware protection against input surges, reverse voltage, and electrostatic interference.

[0048] The USB interface supports the PD fast charging protocol and is equipped with a CH224Q PD fast charging protocol chip. This chip integrates a CC identification pin, allowing for a default 12V fast charging voltage request via hardware configuration, eliminating the need for a software protocol stack. The USB interface has reserved DP / DM data pins for direct connection if a downstream device requires USB functionality. The USB interface also features ESD / TVS protection and a resettable fuse.

[0049] A priority selection circuit is provided between the DC input interface and the output of the USB interface. This circuit includes a PMOS transistor. When the input voltage of the DC input interface is present and higher than the output voltage of the USB interface, the PMOS transistor is turned off due to the gate-source voltage relationship, isolating the USB interface output, and the system is powered by the DC input interface. When there is no input to the DC input interface or its voltage is lower than the USB interface output voltage, the PMOS transistor is turned on, and the USB interface supplies power to the subsequent stage. After priority selection, both inputs output a unified input bus voltage VDD_INPUT to supply the battery management unit.

[0050] Example 3: This embodiment further describes the battery management unit, which includes a charging management circuit, a charging rate control circuit, and a time-sharing voltage acquisition circuit.

[0051] It should be noted that the power supply capabilities of different external power sources vary significantly (e.g., the output power of a standard USB 5V is limited, while PD fast charging can provide higher power). The charging current needs to be automatically adjusted according to the actual input voltage, and this adjustment process should avoid relying on software sampling and judgment logic.

[0052] To address the aforementioned issues, this application employs a charging management chip in conjunction with a rail-to-rail comparator and a resistor divider network. External input voltage is determined via a hardware threshold, and the equivalent voltage division ratio at the charging current setting terminal is automatically switched. This method achieves adaptive control, automatically switching to high-current fast charging when the input voltage is above 6.6V and automatically limiting current for slow charging when it is below 6.6V, with a response speed reaching the nanosecond level, requiring no software intervention.

[0053] refer to Figure 3 As shown, the charging management circuit uses the BQ24610RGE charging management chip as its core, adapting to single or multiple parallel lithium batteries. The charging management chip limits the battery charging cutoff voltage to 4.20V via hardware resistor configuration. The circuit integrates a battery temperature voltage divider detection loop, a charging enable control pin (hardware-enabled by default), a charging current sampling resistor SRP, and a battery voltage feedback loop. The charging management chip, paired with a power MOSFET CSD17318Q2, forms the charging power path, and a hardware RC network ensures charging loop stability. The circuit features an independent ground plane BGND to isolate power ground from signal ground, reducing charging noise interference. The charging management chip also includes an indicator light circuit shared by the charging and system to indicate the charging status.

[0054] refer to Figure 4 As shown, the charging rate control circuit includes an input voltage divider network and a rail-to-rail comparator U19 (LMV321IDBVR). The input voltage divider network consists of resistors R135 and R144 connected in series. Resistor R135 has a resistance of 300KΩ, and resistor R144 has a resistance of 100KΩ. One end of resistor R135 is connected to the output bus VDD_INPUT, and one end of resistor R144 is grounded. The connection point of resistors R135 and R144 serves as the voltage divider output terminal, which is connected to the non-inverting input terminal of the rail-to-rail comparator U19. The voltage division ratio of the input voltage divider network is R144 / (R135+R144)=100KΩ / (300KΩ+100KΩ)=1 / 4, meaning the voltage at the voltage divider output terminal is one-quarter of VDD_INPUT.

[0055] The inverting input of the rail-to-rail comparator U19 is set with a fixed reference voltage via a voltage divider using resistors R145 and R138. Resistor R145 has a resistance of 100KΩ and is connected at one end to the reference voltage VREF_3V3 (3.3V); resistor R138 also has a resistance of 100KΩ and is connected at one end to ground. After the voltage divider, the voltage at the inverting input is half of VREF_3V3, i.e., 3.3V × 100KΩ / (100KΩ + 100KΩ) = 1.65V. The power supply of the rail-to-rail comparator U19 is connected to VREF_3V3 and decoupled using a filter capacitor C91 (100nF).

[0056] Since the voltage at the non-inverting input terminal is one-quarter of VDD_INPUT, and the fixed reference voltage at the inverting input terminal is 1.65V, when VDD_INPUT = 1.65V × 4 = 6.6V, the voltage at the non-inverting input terminal is exactly equal to the voltage at the inverting input terminal. 6.6V is the hardware recognition threshold for charging rate switching.

[0057] The output of the rail-to-rail comparator U19 is connected to the charging current setting terminal ISET1 of the charging management chip via resistors R139 (300K) and R143 (100K). A pull-down resistor R107 (24K) is connected between the charging current setting terminal ISET1 and BGND. A filter capacitor C87 (100nF / 50V) is connected in parallel to the charging current setting terminal ISET1 and then connected to BGND to eliminate false triggering caused by input voltage fluctuations.

[0058] Fast charging mode: When the external input voltage is greater than 6.6V (typical scenario is PD fast charging 12V input), the rail-to-rail comparator U19 outputs a high level, and the output voltage VCC is 3.3V. At this time, the charging current setting terminal ISET1 receives a voltage divider formed by the pull-up resistor R_UP (equivalent resistance 300K×100K / (300K+100K)=75K) formed by the parallel connection of resistors R139 (300K) and R143 (100K), and the pull-down resistor R_DOWN, i.e., R107 (24K). Let the comparator output voltage be VCC, the equivalent pull-up resistor be R_UP, the equivalent parallel resistor at the output terminal be R_OUT (i.e., the parallel value of R139 and R143), and the pull-down resistor be R_DOWN, then the voltage at the ISET1 terminal is:

[0059] According to the parameters of the BQ2461x series charging management chip, the charging current is determined by the ISET1 terminal voltage and the charging current sampling resistor R_SR. The hardware configuration charging current limit (first current value) is as follows:

[0060] Normal slow charging mode: When the external input voltage is less than or equal to 6.6V (typically a standard USB 5V input), the rail-to-rail comparator U19 outputs a low level of 0V, causing a change in the resistor divider network. At this time, the comparator output no longer provides a pull-up voltage, and the voltage at ISET1 is obtained from the reference voltage VREF_3V3 (3.3V) through a resistor divider network. Let the pull-down resistor R_DOWN be R107 (24K), the pull-up resistor R_UP be R139 (300K), and the comparator output resistor R_OUT be R143 (100K). Then the voltage at ISET1 is:

[0061] According to the parameters of the BQ2461x series charging management chip, the hardware configuration charging current (second current value) is limited as follows:

[0062] The entire charging rate control process described above is completed by a pure hardware circuit. The rail-to-rail comparator automatically switches the output level according to the relationship between the input voltage and the 6.6V threshold, changing the equivalent voltage division ratio at the ISET1 terminal to achieve adaptive switching between 4A (first current value) fast charging and 1A (second current value) slow charging. No microcontroller sampling or software judgment is required, and the response speed reaches the nanosecond level.

[0063] It should be noted that battery voltage monitoring typically uses a resistor divider method. However, the divider resistors create a continuous static current leakage path in the battery power supply system, increasing standby power consumption and shortening the device's battery life. Furthermore, the signal voltage controlling the on / off state of the divider circuit may be lower than the battery voltage, making conventional single-MOSFET switches unsuitable for control requirements.

[0064] Based on this, this embodiment connects a cascaded MOS switch, consisting of an NMOS transistor driving a PMOS transistor, in series in the grounding loop of the sampling voltage divider resistor pair. Time-division switching control is achieved through external acquisition control signals. In this way, the voltage divider resistor pair is completely de-energized during non-acquisition periods, eliminating the continuous static power consumption of the voltage divider resistor; the cascaded structure of the NMOS transistor driving the PMOS transistor reduces the requirements for the control signal voltage level.

[0065] refer to Figure 5 As shown, the time-division voltage acquisition circuit includes a sampling voltage divider resistor pair and a cascaded MOSFET switch.

[0066] The sampling voltage divider resistor pair consists of two 10K resistors. One end is connected to the battery output terminal VBAT, and the other end is grounded through a cascaded switch of a MOSFET. The voltage divider node of the two 10K resistors outputs a sampling voltage SEN_BAT, which is used by the subsequent detection circuit.

[0067] The cascaded MOSFET switch consists of a PMOS transistor CJMP2011 and an NMOS transistor CSD17318Q2. The PMOS transistor is connected in series in the ground loop of the sampling voltage divider resistor pair, and its source is connected to the battery output terminal VBAT. The gate of the NMOS transistor is connected to the external acquisition control signal terminal CTR_SEN_BAT, its drain is connected to the gate of the PMOS transistor, and its source is grounded.

[0068] When the external acquisition control signal terminal CTR_SEN_BAT is high, the NMOS transistor is turned on, pulling the gate voltage of the PMOS transistor down to near ground potential. Since the source of the PMOS transistor is the battery voltage VBAT (approximately 3.4V~4.2V), the gate-source voltage meets the conduction condition of the PMOS transistor after the gate is pulled low, and the PMOS transistor turns on. The sampling voltage divider resistors form a complete voltage divider circuit, and half of the battery voltage output at the voltage divider node is used as the sampling voltage SEN_BAT.

[0069] When the external acquisition control signal terminal CTR_SEN_BAT is low, or the signal is absent, or the external detection line is interrupted or disconnected, the NMOS transistor is turned off, and the gate of the PMOS transistor is pulled high to the VBAT potential through the pull-up resistor, causing the PMOS transistor to turn off. At this time, there is no current path through the sampling voltage divider resistor, and the static current is zero, significantly reducing the battery standby power consumption.

[0070] By using a cascaded control method of NMOS transistors driving PMOS transistors, the voltage of the externally acquired control signal only needs to meet the gate threshold voltage of the NMOS transistor (usually 1V~2V) to achieve the on / off control of the voltage divider circuit. There is no need for the control signal voltage to reach the battery voltage level, which effectively reduces the requirements for the voltage level of the external control signal.

[0071] Example 4: This embodiment further describes the power management unit, which includes a button self-locking circuit, a hysteresis low voltage detection circuit, and a 5V system boost regulator circuit.

[0072] It should be noted that portable battery-powered devices need to implement functions such as powering on by pressing and holding, continuous power supply after releasing the button, and powering off by pressing a button or external signal. These timing control logics need to be implemented by pure hardware circuits without a microcontroller.

[0073] To address the aforementioned issues, this embodiment generates a power-on delay signal using a resistor-capacitor delay network. Back-to-back MOSFETs form a self-locking switch. The boost-regulated output is fed back to the self-locking switch control terminal via an isolation diode and a pull-up resistor, forming a self-lock. The power-off control branch achieves reliable shutdown through a power-off switch transistor and a holding capacitor. This approach achieves a complete power-on / off logic: a hardware delay of 8-10 seconds for power-on, self-locking to maintain power supply after release, and power-off via an external signal, eliminating the need for software timing and state management.

[0074] The button self-locking circuit includes an RC delay network, a self-locking switch, a self-locking feedback path, and a power-off control branch. (Reference) Figure 6 As shown, the input of the RC delay network is connected to button KEY_P. When button KEY_P is pressed, the delayed signal VEN is charged through the RC delay network consisting of a resistor and a 100nF delay capacitor. The delay time is determined by the RC time constant, and the hardware-set delay is approximately 8-10 seconds (the specific delay time depends on the accuracy of the components). After the delay is completed, the VEN voltage rises above the threshold, and the enable signal 5V_EN is output.

[0075] refer to Figure 7 As shown, the self-locking switch includes two MOSFETs connected back-to-back. The gates of both MOSFETs are connected to the enable signal 5V_EN, and their drains are connected to the VSYS node on the VBAT side of the battery output and the system bus VCC_SYS, respectively. When the 5V_EN signal is established, the back-to-back MOSFETs turn on. The battery voltage at the VSYS node forms the system bus voltage VCC_SYS through the turned-on MOSFETs, thereby starting the subsequent 5V system boost regulator circuit and generating the VCC_5V_STD bus voltage. The back-to-back connection structure ensures that the body diodes of the two MOSFETs are in opposite directions, preventing the load current on the system bus from flowing back into the battery output through the body diodes.

[0076] The self-locking feedback path includes an isolation diode B5819WS and a pull-up resistor. When the KEY_P button is released, the RC delay network no longer maintains the VEN voltage, and the delay signal VEN drops. However, VCC_5V_STD has already been established. VCC_5V_STD reapplies voltage to the 5V_EN enable signal through the isolation diode B5819WS and the pull-up resistor, maintaining 5V_EN at a high level, thus maintaining the conduction state of the back-to-back MOSFETs and forming a hardware self-locking loop. The self-locking path continuously keeps the power on, and the user does not need to continuously press and hold the button. The isolation diode prevents the pull-down action of 5V_EN during the shutdown process from affecting VCC_5V_STD in reverse.

[0077] refer to Figure 6As shown, the shutdown control branch includes a shutdown trigger terminal (SHUTDOWN) and a shutdown switch transistor. The shutdown trigger terminal (SHUTDOWN) receives an external shutdown signal, which can be provided by a dry contact button composed of an external button and any power supply combination, or it can be connected to an external controller via a wired control device. The shutdown switch transistor is an NMOS transistor, with its gate connected to the shutdown trigger terminal (SHUTDOWN) and its drain connected to the enable signal 5V_EN. A sustaining capacitor is connected between the gate of the shutdown switch transistor and ground.

[0078] When the shutdown trigger terminal SHUTDOWN receives any pull-up action exceeding 1V and lasts for more than 10ms, the NMOS transistor of the shutdown switch turns on. The holding capacitor maintains charge on the gate of the NMOS transistor, keeping the NMOS transistor on for more than 100ms. During this period, the turned-on NMOS transistor pulls the 5V_EN enable signal down to 0V, completely dissipating the feedback voltage of the self-locking feedback path. The back-to-back MOS transistors turn off, the system bus VCC_SYS is de-energized, the boost regulator circuit stops outputting VCC_5V_STD, and the self-locking loop is completely released, achieving hardware self-locking shutdown.

[0079] The circuit uses a Schottky diode B5819WS for reverse isolation, and a high-voltage pull-up resistor to suppress leakage current, thereby improving the reliability and anti-interference of the circuit.

[0080] It should be noted that the battery voltage cannot provide a stable current output during deep discharge. If the system is still running at this time, it may lead to problems such as unstable output voltage and abnormal device operation. It is necessary to forcibly shut down the system when the battery voltage drops to the critical region and prevent the system from turning on until the battery is charged back to a sufficient voltage. This protection logic must be implemented entirely in hardware.

[0081] To address the aforementioned issues, this application employs an independent reference power supply and a hysteresis comparator to construct a hysteresis low-voltage detection circuit. This circuit, along with a button self-locking circuit, forms a cascaded linkage with the output of the step-up / step-down subdivision power supply unit and the system bus, achieving hardware cascaded shutdown and startup isolation. In this manner, the system cascades shuts down when the battery voltage falls below the shutdown threshold, and the system cannot start until the battery is charged above the recovery threshold. This avoids repeated start-stop cycles in unstable voltage ranges, protecting the overall system's power stability.

[0082] refer to Figure 8 As shown, the 5V system boost regulator circuit uses the TPS61089RNRR DC-DC boost chip as its core. It boosts the system bus voltage VCC_SYS (3.4V~4.2V) to generate a stable 5V main power supply VCC_5V_STD, which serves as the unified input power for the subsequent boost-buck subdivision power supply units. The DC-DC boost chip is controlled by the DC-DC_EN enable signal.

[0083] The independent reference power supply is provided by the ultra-low power low-dropout linear regulator ME6214C33M5G. The input of this low-dropout linear regulator is directly connected to the battery output VBAT, directly converting the battery voltage to a 3.3V reference voltage VRTC without passing through the system bus VCC_SYS and the latching switch. Since no control loop is added, VRTC remains active as long as the battery has power. This low-dropout linear regulator consumes only 0.7μA of quiescent current, equivalent to approximately 6.132mAh of power per year, with a negligible impact on battery life. VRTC also serves as the power supply for the ultra-low power RTC clock and the hysteresis comparator.

[0084] The hysteresis low-voltage detection circuit includes a hysteresis comparator. The non-inverting input of the hysteresis comparator is connected to the system bus VCC_SYS via a first voltage divider network, and the inverting input is connected to the reference voltage VRTC (3.3V). A positive feedback resistor R_FEED is connected between the output and the non-inverting input of the hysteresis comparator to create the hysteresis characteristic. The first voltage divider network consists of an upper voltage divider resistor R_UP (15K) and a lower voltage divider resistor R_DOWN (330K). The DCDC_EN enable signal is provided by the output of the hysteresis comparator, which is initially high and has the same voltage as VCC_SYS. The positive feedback resistor R_FEED has a resistance of 499K.

[0085] Shutdown Process: When the battery power is consumed during system operation, causing the VCC_SYS voltage to drop from high to low, the voltage V_P at the non-inverting input of the hysteresis comparator decreases accordingly. Since the comparator output is high (DCDC_EN is equivalent to VCC_SYS), the positive feedback resistor R_FEED (499K) feeds the high level of the comparator output back to the non-inverting input. At this time, the voltage V_P at the non-inverting input is determined by VCC_SYS through the first voltage divider network and the positive feedback resistor, calculated as follows:

[0086] The comparator reaches its dropout threshold when V_P falls to the inverting input reference voltage VRTC (3.3V). That is:

[0087] Therefore, when the VCC_SYS voltage drops to approximately 3.446V, the hysteresis comparator output jumps to a low level of 0V, DCDC_EN goes low, shutting down the DCDC boost chip, and VCC_5V_STD stops outputting, thus achieving low-power shutdown.

[0088] Because the self-locking feedback path of the button self-locking circuit relies on VCC_5V_STD to be fed back to the self-locking switch control terminal through an isolation diode to maintain the self-locking state, the disappearance of VCC_5V_STD causes the self-locking feedback voltage to be lost, the enable signal 5V_EN drops, the self-locking switch composed of back-to-back MOSFETs turns off, and the system bus VCC_SYS is de-energized. This forms a hardware cascaded shutdown link from low voltage detection → DC-DC shutdown → self-lock release → system bus de-energization, and the entire process is completed automatically by the hardware circuit.

[0089] Recovery Process: After system shutdown, if the user connects an external power source to charge the battery, the battery voltage gradually rises from low to high, meaning the battery begins charging from a low-battery shutdown state. Since the independent reference power supply is directly powered by the battery without passing through the latching switch and the system bus, the hysteresis comparator is still powered (by VRTC) after system shutdown, continuously monitoring battery voltage changes. Although the system bus VCC_SYS has been disconnected by the latching switch, the non-inverting input of the hysteresis comparator is connected to the VSYS node through the first voltage divider network. The VSYS node is directly connected to the battery, and after the latching switch is turned off, the VSYS node voltage remains equal to the battery voltage VBAT. Therefore, the hysteresis comparator can still indirectly monitor the battery voltage.

[0090] At this time, the comparator output is low (0V), and the positive feedback resistor R_FEED feeds the low level back to the non-inverting input, making the recovery threshold higher than the turn-off threshold. When VCC_SYS changes from low to high, the voltage V_P at the non-inverting input is calculated as follows:

[0091] The comparator output can only switch to a high level when V_P rises to the reference voltage VRTC (3.3V) at the inverting input. That is:

[0092] Therefore, when the battery voltage recovers to approximately 3.548V, the hysteresis comparator output jumps to a high level, and DCDC_EN is enabled again.

[0093] However, even if DCDC_EN returns to a high level, the self-locking switch of the button self-locking circuit remains off (no one presses the button to trigger the RC delay network), the system bus VCC_SYS is not established, the DC-DC boost chip has no input voltage, and VCC_5V_STD will not output. This ensures that the charging recovery process will not cause the system to automatically power on. The user must actively press the button KEY_P, and the RC delay network will re-trigger the self-locking switch before the system can start normally.

[0094] If the battery voltage has not yet recovered to the recovery threshold (approximately 3.548V), even if the user presses the button, the RC delay network can normally generate a 5V_EN signal and turn on the self-locking switch, establishing VCC_SYS. However, DCDC_EN remains low (because the hysteresis comparator output is still low), the DCDC boost chip will not start, VCC_5V_STD will not output, and the self-locking feedback path cannot obtain feedback voltage. When the user releases the button, 5V_EN drops, and the self-locking switch turns off again. This creates a startup isolation effect: hardware-level prevention of power-on in the low-charge, unstable range.

[0095] The significance of the hysteresis low-power shutdown circuit lies in the fact that when the battery voltage drops to approximately 3.45V, the battery charge is already at a very low level, typically insufficient to maintain sufficient current output. At this point, the power supply to all downstream devices is forcibly shut down, and the devices are not allowed to power on until the battery voltage is charged to approximately 3.55V. This ensures that the devices do not operate within the unstable battery voltage range, thereby improving the overall system power stability. The approximately 100mV hysteresis window between the shutdown threshold of approximately 3.446V and the recovery threshold of approximately 3.548V is determined by the resistance value of the positive feedback resistor R_FEED, preventing repeated system start-ups and shutdowns caused by battery voltage fluctuations near the critical point.

[0096] Example 5: This embodiment further explains the buck-boost microstepping power supply unit.

[0097] It should be noted that the downstream load equipment requires multiple power supplies of different voltage levels (such as 12V, 3.3V, 1.8V, 2.8V, etc.), and multiple conversions should be performed using a unified reference voltage as input. Furthermore, each power supply must be isolated from the others to avoid load interference.

[0098] To address the aforementioned issues, this embodiment uses a standard 5V main power supply (VCC_5V_STD) as a unified input. Independent boost and buck circuits are used to transform the output power rails separately, and each power rail is equipped with an independent LC filter network and decoupling capacitor. This approach provides multiple isolated and stable power supplies to downstream devices, with each power rail independently filtered and decoupled, avoiding crosstalk between different loads.

[0099] refer to Figure 9 As shown, the step-up / step-down power supply unit takes the 5V standard voltage VCC_5V_STD output from the power management unit as input. An independent boost circuit converts the 5V to a 12V high-voltage power rail, and an independent buck circuit converts the 5V to a 3.3V standard low-voltage power rail. Depending on the requirements of downstream equipment, it can further convert the output to other voltage levels such as 1.8V and 2.8V.

[0100] Each power rail is equipped with an independent LC filter network (a low-pass filter composed of inductors and capacitors) and RC decoupling capacitors to suppress voltage fluctuations caused by switching power supply ripple and load transient response. Each power conversion circuit is independent of the others, achieving electrical isolation through independent power paths and filter networks to prevent current changes in one load from affecting the stability of other power rails through common impedance coupling. Each power rail is also equipped with current-limiting protection hardware loops to prevent damage to the conversion circuitry from load short circuits or overloads.

[0101] The step-up / step-down subdivision power supply unit provides multiple isolated and stable power supplies for the motherboard, charging control circuit, peripheral interfaces, etc., meeting the different power voltage levels and power quality requirements of different functional modules in portable electronic devices.

[0102] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A battery-powered low-voltage power supply control system based on hardware logic, characterized in that, include: External power input unit, used to receive external power and output input bus voltage; The battery management unit is connected to the external power input unit and is used to manage the charging of the battery using the input bus voltage, and to provide a battery output terminal. The power management unit is connected to the battery output terminal and includes a button self-locking circuit and a hysteresis low-voltage detection circuit; the button self-locking circuit responds to button operation and controls the connection and disconnection between the battery output terminal and the system bus. The step-up / step-down subdivision power supply unit takes the system bus as input and transforms the output voltage of at least one power supply line. The button self-locking circuit includes a self-locking feedback path, which feeds back the output voltage of the buck-boost subdivision power supply unit to the control terminal of the button self-locking circuit to maintain the conduction state of the system bus after the button is released. The hysteresis low-voltage detection circuit includes a hysteresis comparator. The input of the hysteresis comparator is connected to the system bus, and the output of the hysteresis comparator is connected to the enable terminal of the buck-boost subdivision power supply unit. The hysteresis comparator is powered by an independent reference power supply, which is directly powered by the battery output and is independent of the system bus. When the voltage of the system bus is lower than the shutdown threshold, the hysteresis comparator shuts down the buck-boost subdivision power supply unit. The self-locking feedback path releases the conduction state of the system bus due to the loss of feedback voltage, forming a cascaded shutdown. The recovery threshold of the hysteresis comparator is higher than the shutdown threshold.

2. The battery-powered low-voltage power supply control system based on hardware logic according to claim 1, characterized in that, The button self-locking circuit also includes an RC delay network and a self-locking switch; The input of the RC delay network is connected to an external button, and the output is connected to the control terminal of the self-locking switch. The self-locking switch includes two MOS transistors connected back to back. The gates of the two MOS transistors together serve as the control terminal of the self-locking switch, and the drains of the two MOS transistors are respectively connected to the battery output terminal and the system bus. The self-locking feedback path includes an isolation diode and a pull-up resistor. The output voltage of the buck-boost subdivision power supply unit is connected to the gates of the two MOS transistors via the isolation diode and the pull-up resistor.

3. The battery-powered low-voltage power supply control system based on hardware logic according to claim 2, characterized in that, The button self-locking circuit also includes a power-off control branch; The shutdown control branch includes a shutdown trigger terminal and a shutdown switch transistor; the shutdown trigger terminal is used to receive an external shutdown signal, the gate of the shutdown switch transistor is connected to the shutdown trigger terminal, the drain of the shutdown switch transistor is connected to the control terminal of the self-locking switch, and the source is grounded; a holding capacitor is connected between the gate of the shutdown switch transistor and ground. When the power-off trigger terminal receives the external power-off signal, the power-off switch transistor is turned on and pulls the control terminal of the self-locking switch low. The holding capacitor maintains the on-time of the power-off switch transistor to ensure that the feedback voltage of the self-locking feedback path is completely discharged, thereby causing the self-locking switch to be completely turned off.

4. The battery-powered low-voltage power supply control system based on hardware logic according to claim 1, characterized in that, The independent reference power supply is a low-dropout linear regulator. The input terminal of the low-dropout linear regulator is directly connected to the output terminal of the battery, and the output terminal outputs a fixed reference voltage to the hysteresis comparator. The non-inverting input of the hysteresis comparator is connected to the system bus through a first voltage divider network, and the inverting input of the hysteresis comparator is connected to the reference voltage. A positive feedback resistor is connected between the output of the hysteresis comparator and the non-inverting input to enable the hysteresis comparator to exhibit hysteresis characteristics.

5. The battery-powered low-voltage power supply control system based on hardware logic according to claim 4, characterized in that, The battery voltage range corresponding to the turn-off threshold of the hysteresis comparator is 3.40V to 3.50V, and the battery voltage range corresponding to the recovery threshold of the hysteresis comparator is 3.50V to 3.60V.

6. The battery-powered low-voltage power supply control system based on hardware logic according to claim 1, characterized in that, The battery management unit includes a charging rate control circuit. The charging rate control circuit includes an input voltage divider network and a rail-to-rail comparator; the input voltage divider network is connected to the output terminal of the external power input unit, the non-inverting input terminal of the rail-to-rail comparator is connected to the voltage divider output terminal of the input voltage divider network, and the inverting input terminal of the rail-to-rail comparator is connected to a fixed reference voltage; The output of the rail-to-rail comparator is connected to a resistor divider network of the charging current setting terminal of the charging management chip, so that the output level of the rail-to-rail comparator can switch the equivalent resistance value of the resistor divider network, thereby changing the charging current limit value of the charging management chip through hardware.

7. The battery-powered low-voltage power supply control system based on hardware logic according to claim 6, characterized in that, The voltage division ratio of the input voltage divider network is configured such that when the input bus voltage of the external power input unit is 6.6V, the voltage at the voltage divider output terminal is equal to the fixed reference voltage. When the input bus voltage is greater than 6.6V, the rail-to-rail comparator outputs a high level, and the charging current limit is configured as a first current value; when the input bus voltage is less than or equal to 6.6V, the rail-to-rail comparator outputs a low level, and the charging current limit is configured as a second current value; the first current value is greater than the second current value.

8. The battery-powered low-voltage power supply control system based on hardware logic according to claim 1, characterized in that, The battery management unit also includes a time-sharing voltage acquisition circuit; The time-division voltage acquisition circuit includes a sampling voltage divider resistor pair and a cascaded MOSFET switch; one end of the sampling voltage divider resistor pair is connected to the battery output terminal, and the other end is grounded through the cascaded MOSFET switch; The cascaded MOS transistor switch includes a PMOS transistor connected in series in the grounding loop and an NMOS transistor driving the PMOS transistor; the gate of the NMOS transistor is connected to an external acquisition control signal terminal, and the drain is connected to the gate of the PMOS transistor; the source of the PMOS transistor is connected to the battery output terminal. When the external acquisition control signal terminal is high, the NMOS transistor is turned on and pulls down the gate voltage of the PMOS transistor, thus turning on the PMOS transistor. The sampling voltage divider resistor pair forms a voltage divider circuit and outputs a sampling voltage. When the external acquisition control signal terminal is low or floating, both the NMOS transistor and the PMOS transistor are turned off, and the sampling voltage divider resistor pair has no static power consumption current.

9. The battery-powered low-voltage power supply control system based on hardware logic according to claim 1, characterized in that, The external power input unit includes a DC input interface and a USB interface; The DC input interface allows an input voltage range of 5V to 28V; the USB interface is equipped with a PD fast charging protocol chip, which requests a preset fast charging voltage from the power supply end only through the level configuration of its own hardware pins. A hardware priority selection circuit is provided between the DC input interface and the output terminal of the USB interface. The hardware priority selection circuit includes an isolation PMOS transistor. When the input voltage of the DC input interface is higher than the output voltage of the USB interface, the isolation PMOS transistor is biased and cut off to cut off the output path of the USB interface.

10. The battery-powered low-voltage power supply control system based on hardware logic according to claim 1, characterized in that, The buck-boost subdivision power supply unit includes a boost regulator sub-circuit and a multi-channel subdivision sub-circuit; The boost regulator sub-circuit takes the system bus as input and boosts and regulates it to a standard 5V voltage. The multi-channel sub-circuit uses the 5V standard voltage as a common input reference and transforms the output to a 12V drive power rail, a 3.3V digital power rail, and multiple low-voltage analog power rails through independent DC-DC step-down circuits and LDO linear regulator circuits; each power rail output is equipped with an independent LC filter network.

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