Peak current mode control circuit and control method for dc-dc circuit

Abstract

This disclosure provides a peak current mode control circuit and control method for a DC-DC converter, relating to the power supply field. The control circuit includes a voltage error amplifier, a voltage-to-current module, an analog calculator, and a current comparator. The voltage-to-current module converts the control voltage signal output by the voltage error amplifier into a peak current control signal. The analog calculator generates a peak current compensation signal based on the input voltage signal at the input voltage terminal and the output voltage signal at the output voltage terminal. The positive input terminal of the current comparator is coupled to the output terminal of the voltage-to-current module and the output terminal of the analog calculator. The output terminal of the current comparator is coupled to the control terminals of the first, second, third, and fourth switching transistors. The current comparator controls the conduction and cutoff of the first to fourth switching transistors based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal, thereby reducing the ripple generated at the output voltage terminal.

Description

Technical Field

[0001] This disclosure relates to the field of power supply technology, specifically to a peak current mode control circuit and control method for a DC-DC circuit. Background Technology

[0002] In DC-DC converter circuits (where DC stands for Direct Current), a fixed clock duty cycle, clk_max, is used as the criterion for switching between different modes. However, in actual operation, the input voltage VIN can change abruptly, causing the relationship between the input voltage VIN and the output voltage VOUT to change rapidly within a short period. At this time, the source used to adjust the duty cycle in the circuit is the error amplifier (EA) in the voltage loop of the peak current control mode. This voltage loop response is very slow and cannot change with the actual input voltage VIN and output voltage VOUT. Even during a slow scan of the input voltage VIN, an error will exist, causing corresponding ripple in the output. Summary of the Invention

[0003] The main objective of this disclosure is to provide a peak current mode control circuit and control method for a DC-DC circuit. By performing feedforward compensation during the peak current regulation stage, the peak current value changes with the actual input voltage VIN and output voltage VOUT, which helps to reduce the ripple generated at the output voltage terminal.

[0004] To achieve the above objectives, a first aspect of this disclosure provides a peak current mode control circuit for a DC-DC converter. The DC-DC converter includes: an input voltage terminal, an output voltage terminal, an inductor, a first switch, a second switch, a third switch, and a fourth switch. The first terminal of the first switch is coupled to the input voltage terminal, the second terminal of the first switch is coupled to the first terminal of the second switch and the first terminal of the inductor, the second terminal of the second switch is coupled to a ground terminal, the first terminal of the fourth switch is coupled to the second terminal of the inductor and the first terminal of the third switch, the second terminal of the fourth switch is coupled to the output voltage terminal, and the second terminal of the third switch is coupled to a ground terminal. The peak current mode control circuit includes: a voltage error amplifier, a voltage-to-current converter, an analog calculator, and a current comparator. The positive input of the voltage error amplifier is coupled to a reference voltage signal, and the inverting input is coupled to a feedback voltage signal acquired based on the output voltage. The input of the voltage-to-current converter is coupled to the output of the voltage error amplifier, and the voltage-to-current converter converts the control voltage signal output by the voltage error amplifier into a peak current control signal. The analog calculator is configured to generate a peak current compensation signal based on the input voltage signal at the input voltage terminal and the output voltage signal at the output voltage terminal. The positive input of the current comparator is coupled to the output of the voltage-to-current converter and the output of the analog calculator, and the negative input is coupled to the inductor current sampling signal of the inductor. The output of the current comparator is coupled to the control terminals of the first, second, third, and fourth switches. The current comparator controls the on / off state of the first to fourth switches based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal.

[0005] In some embodiments of this disclosure, the analog calculator generates a peak current compensation signal based on the input voltage signal at the input voltage terminal and the output voltage signal at the output voltage terminal. This includes: when the DCDC circuit switches from a first mode to a second mode, based on the principle that the load current at the output voltage terminal remains constant and that the inductor's starting current in the first mode is equal to the inductor's starting current in the second mode, determining the required second peak current control signal in the second mode according to the first peak current control signal in the first mode; wherein the first mode and the second mode are any two of buck mode, boost mode, and buck-boost mode; the difference between the first peak current control signal and the second peak current control signal is used as the peak current compensation signal; a current comparator controls the conduction and cutoff of the first to fourth switches based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal, including: after the DCDC circuit switches from the first mode to the second mode, the current comparator controls the conduction and cutoff of the first to fourth switches based on the first peak current control signal, the peak current compensation signal, and the inductor current sampling signal.

[0006] In some embodiments of this disclosure, one of the first mode and the second mode is a buck mode and the other is a buck-boost mode; or, one of the first mode and the second mode is a boost mode and the other is a buck-boost mode.

[0007] In some embodiments of this disclosure, the first mode is a buck mode and the second mode is a buck-boost mode. The first mode includes a first stage in which the inductor current rises from the initial current to the first peak current control signal, and a second stage in which the inductor current falls from the first peak current control signal to the initial current. The second mode includes a third stage in which the inductor current rises from the initial current to the second peak current control signal, a fourth stage in which the inductor current rises from the second peak current control signal to the third peak current control signal, and a fifth stage in which the third peak current control signal falls to the initial current. The current comparator controls the conduction and cutoff of the first to fourth switches based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal. The mode also includes controlling the fourth duration of the fourth stage to be equal to the second duration of the second stage after the DC-DC circuit switches from the first mode to the second mode. The calculation principle also includes that the fourth duration of the fourth stage is equal to the second duration of the second stage.

[0008] In some embodiments of this disclosure, in the first stage, the first and fourth switches are turned on, and the second and third switches are turned off; in the second stage, the second and fourth switches are turned on, and the first and third switches are turned off; in the third stage, the first and third switches are turned on, and the second and fourth switches are turned off; in the fourth stage, the first and fourth switches are turned on, and the second and third switches are turned off; and in the fifth stage, the second and fourth switches are turned on, and the first and third switches are turned off.

[0009] In some embodiments of this disclosure, the peak current compensation signal I_COMP is calculated using the following formula: I_COMP=

[0010] Where VIN represents the input voltage value at the input voltage terminal, VOUT represents the output voltage value at the output voltage terminal, L represents the inductance value of the inductor, and TS represents the duty cycle of the second mode.

[0011] In some embodiments of this disclosure, when the DC-DC circuit switches from the first mode to the second mode, the current comparator controls the conduction and cutoff of the first to the fourth switching transistors based on the first peak current control signal, the peak current compensation signal, and the inductor current sampling signal. This includes: when the DC-DC circuit switches from the first mode to the second mode, the current comparator controls the switch from the third stage to the fourth stage based on the relationship between the sum of the first peak current control signal and the peak current compensation signal and the inductor current sampling signal.

[0012] In some embodiments of this disclosure, based on calculation principles, a second peak current control signal and a peak current compensation signal are determined in the second mode according to the first peak current control signal in the first mode. This includes: determining the load current at the output voltage terminal based on the peak current control signal, the second duration of the second stage, and the second inductor current slope of the inductor current in the second stage; determining the total charge in the second mode based on the load current at the output voltage terminal and the duty cycle of the second mode; and determining the total charge in the second mode based on the second peak current control signal, the fourth duration of the fourth stage, and the fourth inductor current slope of the inductor current in the fourth stage. The third peak current control signal; based on the second peak current control signal and the third duration of the third stage, the third charge quantity of the third stage is determined; based on the second peak current control signal, the third peak current control signal, and the fourth duration of the fourth stage, the fourth charge quantity of the fourth stage is determined; based on the third peak current control signal and the fifth duration of the fifth stage, the fifth charge quantity of the fifth stage is determined; based on the relationship that the sum of the third charge quantity, the fourth charge quantity, and the fifth charge quantity equals the total charge quantity of the second mode, the relationship between the second peak current control signal and the first peak current control signal is determined, and the peak current compensation signal is determined.

[0013] In some embodiments of this disclosure, the second terminal of the first switching transistor is coupled to the negative input terminal of the current comparator through a current sampling circuit. The current sampling circuit is used to sample the inductor current of the inductor to obtain the inductor current sampling signal.

[0014] The second aspect of this disclosure provides a peak current mode control method for a DC-DC circuit. This method is based on the peak current mode control circuit for the DC-DC circuit provided in the first aspect of this disclosure. The method includes: when the DC-DC circuit switches from a first mode to a second mode, based on the principle that the load current at the output voltage terminal remains constant and that the inductor's starting current in the first mode is equal to the inductor's starting current in the second mode, determining a second peak current control signal required in the second mode according to a first peak current control signal in the first mode; wherein the first mode and the second mode are any two modes selected from buck mode, boost mode, and buck-boost mode; the difference between the first peak current control signal and the second peak current control signal is used as a peak current compensation signal; after the DC-DC circuit switches from the first mode to the second mode, the conduction and turn-off of the first to fourth switching transistors are controlled based on the first peak current control signal, the peak current compensation signal, and the inductor current sampling signal.

[0015] A third aspect of this disclosure provides a chip that includes a peak current mode control circuit for any of the DC-DC circuits provided in the first aspect of this disclosure.

[0016] A fourth aspect of this disclosure provides an electronic device that includes the chip provided in the third aspect of this disclosure.

[0017] The peak current mode control circuit and method for the DC-DC circuit provided in this disclosure adds an analog calculator. The analog calculator generates a peak current compensation signal based on the input voltage signal at the input voltage terminal and the output voltage signal at the output voltage terminal. The positive input terminal of the current comparator is coupled to the output terminal of the voltage-to-current module and the output terminal of the analog calculator, thereby controlling the on and off of the first to fourth switching transistors based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal. During the peak current adjustment stage, the peak current control signal is feedforward compensated by the peak current compensation signal, which allows the actual peak current value based on the positive input terminal of the current comparator to change with the actual input voltage signal VIN and the output voltage signal VOUT, thus facilitating the reduction of ripple generated at the output voltage terminal. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1This is a schematic diagram of a DC-DC circuit provided in an embodiment of the present disclosure; Figure 2 A schematic circuit diagram of a peak current mode control circuit for a DC-DC circuit provided in an embodiment of this disclosure; Figure 3 A waveform diagram illustrating the change of inductor current over time during switching from a first mode to a second mode, according to an embodiment of this disclosure; Figure 4 This is a schematic flowchart of a peak current mode control method for a DC-DC circuit provided in an embodiment of the present disclosure.

[0020] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] In this disclosure, the terms "upper," "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily used to better describe this disclosure and its embodiments, and are not intended to limit the indicated devices, elements, or components to having a particular orientation, or to be constructed and operated in a particular orientation.

[0024] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of this specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement “connected” or “coupled” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components. As used herein, one electrode of the source and drain of a switching transistor such as a MOSFET or power transistor is defined as the first electrode, the other electrode as the second electrode, and the gate as the control electrode.

[0025] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0026] Example 1 To address the aforementioned issues, this disclosure provides a peak current mode control circuit for a DC-DC converter. The aim is to reduce the ripple generated at the output voltage terminal by performing feedforward compensation during the peak current regulation stage, so that the peak current value changes with the actual input voltage signal VIN and the output voltage signal VOUT. Figure 1 A DC-DC circuit according to an embodiment of the present disclosure is shown. Figure 2 A schematic circuit diagram of a peak current mode control circuit for a DC-DC circuit according to an embodiment of the present disclosure is shown.

[0027] like Figure 1 As shown, the DC-DC circuit includes: an input voltage terminal VIN, an output voltage terminal VOUT, an inductor IND, a first switch Q1, a second switch Q2, a third switch Q3, and a fourth switch Q4; the first terminal of the first switch Q1 is coupled to the input voltage terminal VIN, the second terminal of the first switch Q1 is coupled to the first terminal of the second switch Q2 and the first terminal of the inductor IND, the second terminal of the second switch Q2 is coupled to the ground terminal GND, the first terminal of the fourth switch Q4 is coupled to the second terminal of the inductor IND and the first terminal of the third switch Q3, the second terminal of the fourth switch Q4 is coupled to the output voltage terminal VOUT, and the second terminal of the third switch Q3 is coupled to the ground terminal GND.

[0028] like Figure 2As shown, the peak current mode control circuit includes: a voltage error amplifier EA, a voltage-to-current module V2I, an analog calculator CAU (Calculator, abbreviated as CAU), and a current comparator COMP. The positive input terminal of the voltage error amplifier EA is coupled to the reference voltage signal REF, and the inverting input terminal of the voltage error amplifier EA is coupled to the feedback voltage signal FB acquired based on the output voltage terminal VOUT. This allows the voltage error amplifier EA to generate a corresponding control voltage signal based on the difference between the reference voltage signal REF and the feedback voltage signal FB.

[0029] refer to Figure 1 and Figure 2 The input terminal of the voltage-to-current module V2I is coupled to the output terminal of the voltage error amplifier EA. The voltage-to-current module V2I is used to convert the control voltage signal output by the voltage error amplifier EA into a peak current control signal, and then output the converted peak current control signal from the output terminal of the voltage-to-current module V2I.

[0030] refer to Figure 1 and Figure 2 The analog calculator CAU is configured to generate a peak current compensation signal I_COMP based on the input voltage signal VIN and the output voltage signal VOUT. This means the peak current compensation signal I_COMP changes according to variations in the input and output voltage signals. During the peak current regulation phase, I_COMP provides feedforward compensation to the peak current control signal, ensuring that the actual peak current input to the positive input of the current comparator COMP is the sum of the peak current control signal and the peak current compensation signal I_COMP. As the input voltage signal VIN and / or the output voltage signal VOUT change, the peak current compensation signal I_COMP dynamically changes in real time, ensuring that the sum of the peak current control signal and the peak current compensation signal I_COMP, representing the actual peak current value, changes with the actual input voltage signal VIN and the output voltage signal VOUT.

[0031] refer to Figure 1 and Figure 2The positive input of the current comparator COMP is coupled to the output of the voltage-to-current module V2I and the output of the analog calculator CAU. The negative input of the current comparator COMP is coupled to the inductor current sampling signal SNS of the inductor IND. Therefore, when comparing the inductor current sampling signal SNS with the peak current value at the positive input, the current comparator COMP is actually comparing the sum of the inductor current sampling signal SNS and the peak current control signal and peak current compensation signal I_COMP, which represent the actual peak current value. The output of the current comparator COMP is coupled to the control terminals of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4.

[0032] refer to Figure 1 and Figure 2 The current comparator COMP controls the on / off state of the first to fourth switches Q1 through Q4 based on the peak current control signal, the peak current compensation signal I_COMP, and the inductor current sampling signal SNS. During the peak current regulation phase, the peak current control signal is feedforward compensated by the peak current compensation signal I_COMP. This allows the actual peak current value at the positive input of the current comparator COMP to change with the actual input voltage signal VIN and the output voltage signal VOUT, thus reducing the ripple generated at the output voltage VOUT.

[0033] It should be noted that the peak current mode control circuit shown in this embodiment is applicable to control strategies based on peak current control mode, for compensating and adjusting the peak current during the energy storage stage of the inductor IND. The peak current compensation signal I_COMP, generated by a fast channel composed of an analog calculator CAU, adjusts the peak current control signal at the positive input of the current comparator COMP to obtain the actual peak current value. Because the input voltage signal VIN and the output voltage signal VOUT are directly acquired, the analog calculator CAU and the peak current mode control circuit in this embodiment can directly convert between different input voltage signals VIN and output voltage signals VOUT.

[0034] The following combination Figures 1 to 3 A detailed description of the peak current mode control circuit for a DC-DC converter is provided. It should be understood that... (The rest of the text is missing.) Figures 1 to 3 This description is only intended for the peak current mode control circuit of a DC-DC converter and is not intended to limit the protection range of the peak current mode control circuit of a DC-DC converter.

[0035] The analog calculator CAU can generate the peak current compensation signal I_COMP based on the input voltage signal at the input voltage terminal VIN and the output voltage signal at the output voltage terminal VOUT in various ways. Some of these methods are illustrated below.

[0036] For example, refer to Figure 1 , Figure 2 and Figure 3 The analog calculator CAU generates a peak current compensation signal I_COMP based on the input voltage signal at the input voltage terminal VIN and the output voltage signal at the output voltage terminal VOUT, which may include the following steps: When the DC-DC circuit switches from the first mode to the second mode, based on the principle that the load current IO at the output voltage terminal VOUT remains unchanged and the calculation principle that the starting current IA of the inductor IND in the first mode is equal to the starting current IA of the inductor IND in the second mode, the second peak current control signal IB2 required in the second mode is determined according to the first peak current control signal IB1 in the first mode; wherein, the first mode and the second mode are any two modes among buck mode, boost mode and buck-boost mode. The difference between the first peak current control signal IB1 and the second peak current control signal IB2 is used as the peak current compensation signal I_COMP. At this time, refer to Figure 1 , Figure 2 and Figure 3 The current comparator COMP controls the on and off of the first switch Q1 to the fourth switch Q4 based on the peak current control signal, the peak current compensation signal I_COMP, and the inductor current sampling signal SNS. This includes: when the DC-DC circuit switches from the first mode to the second mode, the current comparator COMP controls the on and off of the first switch Q1 to the fourth switch Q4 based on the first peak current control signal IB1, the peak current compensation signal I_COMP, and the inductor current sampling signal SNS.

[0037] Specifically, the calculation principles include the following objectives and assumptions: During the transition from the first mode to the second mode of the DC-DC circuit, the load current IO at the output voltage terminal VOUT remains constant; and the starting current IA of the inductor IND in the first mode is equal to the starting current IA of the inductor IND in the second mode. It should be noted that the aforementioned starting current IA refers to the inductor current of the inductor IND when entering this mode.

[0038] The first mode and the second mode mentioned above are any two different modes among buck mode, boost mode, and buck-boost mode. Specifically, the first mode can be buck mode, and the second mode can be boost mode or buck-boost mode; the first mode can be boost mode, and the second mode can be buck mode or buck-boost mode; the first mode can be buck-boost mode, and the second mode can be buck mode or boost mode.

[0039] The first peak current control signal IB1 mentioned above refers to the actual peak current of the DCDC circuit when it operates in the first mode. The second peak current control signal IB2 mentioned above refers to the actual peak current or target peak current required to ensure that the voltage output meets the above calculation principles when the DCDC circuit operates in the second mode. Since the first mode has already been completed during the switch from the first mode to the second mode, the actual peak current in the first mode is known and fixed. However, the switch from the first mode to the second mode is relatively rapid. At this time, the voltage loop composed of the voltage error amplifier EA has not yet adjusted the voltage control signal in time. Therefore, the voltage control signal output by the voltage error amplifier EA is still the voltage control signal corresponding to the first peak current control signal IB1. That is, the peak current control signal output by the voltage-to-current module V2I is still the first peak current control signal IB1. Obviously, the first peak current control signal IB1 cannot be adapted to the control of the second mode, which will cause corresponding ripple in the output.

[0040] In this embodiment, after switching to the second mode, the current comparator COMP controls the on / off state of the first switch Q1 to the fourth switch Q4 based on the first peak current control signal IB1, the peak current compensation signal I_COMP, and the inductor current sampling signal SNS. Since the difference between the first peak current control signal IB1 and the second peak current control signal IB2 equals the peak current compensation signal I_COMP, the current comparator COMP controls the on / off state of the first switch Q1 to the fourth switch Q4 based on the second peak current control signal IB2 obtained from the sum of the first peak current control signal IB1 and the peak current compensation signal I_COMP, and the inductor current sampling signal SNS. That is, compared to related technologies, the first peak current control signal IB1 has been compensated and corrected to keep the load current IO at the output voltage terminal VOUT constant, and the starting current IA of the inductor IND in the first mode equal to the starting current IA of the inductor IND in the second mode, reducing the corresponding ripple generated at the output. The peak current compensation signal I_COMP obtained above is quickly inserted into the positive input terminal of the current comparator COMP by the analog calculator CAU, so that the peak current actually input to the positive input terminal of the comparator is equal to the sum of the peak current control signal and the peak current compensation signal I_COMP, and then compared with the inductor current sampling signal SNS at the negative input terminal of the comparator. This can ensure the energy transfer error caused by mode switching.

[0041] Specifically, in related circuits, the source used to adjust the duty cycle is the error amplifier in the voltage loop of the peak current control mode. This voltage loop response is slow and cannot promptly follow changes in the input voltage signal VIN to eliminate the ripple generated during mode switching. However, this disclosure provides a fast path that uses the difference between the peak current control signals of the inductor IND (the difference obtained by subtracting the second peak current control signal IB2 from the first peak current control signal IB1) ​​between different modes as the peak current compensation signal I_COMP for fast feedforward. This reduces ripple during system mode switching and improves product competitiveness.

[0042] Since related technologies lack an analog calculator (CAU) to provide an additional peak current compensation signal I_COMP, when mode switching occurs, the duty cycle of the voltage error amplifier EA output changes due to the difference between the first and second modes. Because the voltage error amplifier EA output has capacitance, the response is relatively slow. This embodiment provides an additional peak current compensation signal I_COMP to compensate for the changes at the voltage error amplifier EA output, thereby improving the response speed. This allows the peak current mode control circuit to be applicable to switching between different modes. It only needs to calculate the difference between the corresponding first peak current control signal IB1 and the second peak current control signal IB2 according to the above method, use this difference as the peak current compensation signal I_COMP, and perform feedforward compensation during the peak current adjustment phase, thus improving the response speed.

[0043] For example, refer to Figure 1 , Figure 2 and Figure 3 In this configuration, one of the first and second modes is buck mode, and the other is buck-boost mode. For example, the first mode is buck mode and the second mode is buck-boost mode; or the first mode is buck-boost mode and the second mode is buck mode. This improves the output ripple at the output voltage terminal VOUT when switching between buck and buck-boost modes.

[0044] For example, refer to Figure 1 , Figure 2 and Figure 3 In this configuration, one of the first and second modes is boost mode, and the other is buck-boost mode. For example, the first mode is boost mode, and the second mode is buck-boost mode; or, the first mode is buck-boost mode, and the second mode is boost mode. This improves the output ripple at the output voltage terminal VOUT when switching between boost mode and buck-boost mode.

[0045] The following is Figure 3 The first mode shown is a buck mode, and the second mode is a buck-boost mode, which will be described in detail below. It should be understood that when the first mode and the second mode are other combinations of modes, the following embodiments can be adapted to obtain the desired results, and these are all within the protection scope of the embodiments disclosed herein.

[0046] For example, refer to Figure 1 , Figure 2 and Figure 3The first mode is a buck mode, which includes a first stage where the inductor current of inductor IND rises from the initial current IA to the first peak current control signal IB1, and a second stage where the inductor current falls from the first peak current control signal IB1 back to the initial current IA. The second mode is a buck-boost mode, which includes a third stage where the inductor current of inductor IND rises from the initial current IA to the second peak current control signal IB2, a fourth stage where the inductor current rises from the second peak current control signal IB2 to the third peak current control signal IC, and a fifth stage where the inductor current falls from the third peak current control signal IC back to the initial current IA. In this mode, the current comparator COMP controls the on / off state of the first to fourth switches Q1 to Q4 based on the peak current control signal, the peak current compensation signal I_COMP, and the inductor current sampling signal SNS. It may also include: when the DC-DC circuit switches from the first mode to the second mode, controlling the fourth duration T4 of the fourth stage to be equal to the second duration T2 of the second stage. The calculation principle at this time may also include that the fourth duration T4 of the fourth stage is equal to the second duration T2 of the second stage. By making the fourth duration T4 of the fourth stage equal to the second duration T2 of the second stage, it is convenient to accurately calculate and predict the second peak current control signal IB2 and the peak current compensation signal I_COMP based on the calculation principles of "energy conservation" or "charge balance".

[0047] For example, refer to Figure 1 and Figure 3In the first stage, the first switch Q1 and the fourth switch Q4 are turned on, while the second switch Q2 and the third switch Q3 are turned off. For example, the inductor current slope of the inductor IND in the first stage can be defined as the first inductor current slope S1. In the second stage, the second switch Q2 and the fourth switch Q4 are turned on, while the first switch Q1 and the third switch Q3 are turned off. For example, the inductor current slope of the inductor IND in the second stage can be defined as the second inductor current slope S2. In the third stage, the first switch Q1 and the third switch Q3 are turned on, while the second switch Q2 and the fourth switch Q4 are turned off. For example, the inductor current slope of the inductor IND in the third stage can be defined as the fourth inductor current slope S4. In the fourth stage, the first switch Q1 and the fourth switch Q4 are turned on, while the second switch Q2 and the third switch Q3 are turned off. For example, the inductor current slope of the inductor IND in the fourth stage can be defined as the fourth inductor current slope S4. In the fifth stage, the second switch Q2 and the fourth switch Q4 are turned on, while the first switch Q1 and the third switch Q3 are turned off. For example, the inductor current slope of the inductor IND in the fifth stage can be defined as the fifth inductor current slope S5. That is, in each of the above stages, the operating states of the first switch Q1 to the fourth switch Q4 are different, thus allowing for direct switching of the corresponding switch state when the peak current switching conditions for different stages are met.

[0048] For example, the peak current compensation signal I_COMP can be calculated using the following formula: I_COMP=

[0049] Where VIN represents the input voltage value at the input voltage terminal VIN, VOUT represents the output voltage value at the output voltage terminal VOUT, L represents the inductance value of the inductor IND, and TS represents the duty cycle of the second mode. The above method also references the duty cycle TS of the second mode and the inductance value of the inductor IND, and calculates the peak current compensation signal I_COMP quantitatively. This not only simplifies the calculation of the peak current compensation signal I_COMP but also improves its accuracy.

[0050] For example, refer to Figure 1 , Figure 2 and Figure 3When the DC-DC circuit switches from the first mode to the second mode, the current comparator COMP controls the on / off state of the first switch Q1 to the fourth switch Q4 based on the first peak current control signal IB1, the peak current compensation signal I_COMP, and the inductor current sampling signal SNS. It may also include: when the DC-DC circuit switches from the first mode to the second mode, the current comparator COMP controls the switch from the third stage to the fourth stage based on the relationship between the sum of the first peak current control signal IB1 and the peak current compensation signal I_COMP and the inductor current sampling signal SNS. That is, after entering the second mode, the condition for determining whether the operating state of the first switch Q1 to the fourth switch Q4 switches from the third stage to the fourth stage is the relationship between the sum of the first peak current control signal IB1 and the peak current compensation signal I_COMP and the inductor current sampling signal SNS. For example, when the inductor current sampling signal SNS is less than the sum of the first peak current control signal IB1 and the peak current compensation signal I_COMP, the operating state of the first switch Q1 to the fourth switch Q4 is kept in the third stage; while when the inductor current sampling signal SNS is equal to the sum of the first peak current control signal IB1 and the peak current compensation signal I_COMP, the operating state of the first switch Q1 to the fourth switch Q4 is switched from the third stage to the fourth stage to reduce the output ripple at the output voltage terminal VOUT.

[0051] Based on the calculation principle, the second peak current control signal IB2 and the peak current compensation signal I_COMP in the second mode can be determined in various ways according to the first peak current control signal IB1 in the first mode. Some methods are exemplified below.

[0052] For example, refer to Figure 1 , Figure 2 and Figure 3 Based on calculation principles, and according to the first peak current control signal IB1 in the first mode, the second peak current control signal IB2 and the peak current compensation signal I_COMP in the second mode are determined, which may include the following calculation steps: Based on the peak current control signal, the second duration T2 of the second stage, and the second inductor current slope S2 of the inductor IND in the second stage, the load current IO of the output voltage terminal VOUT is determined. The total charge in the second mode is determined based on the load current IO at the output voltage terminal VOUT and the duty cycle TS of the second mode. Based on the second peak current control signal IB2, the fourth duration T4 of the fourth stage, and the fourth inductor current slope S4 of the inductor IND current in the fourth stage, the third peak current control signal IC is determined. Based on the second peak current control signal IB2 and the third duration T3 of the third stage, the third charge amount of the third stage is determined. Based on the second peak current control signal IB2, the third peak current control signal IC, and the fourth duration T4 of the fourth stage, the fourth charge quantity of the fourth stage is determined. Based on the third peak current control signal IC and the fifth duration T5 of the fifth stage, the fifth charge quantity of the fifth stage is determined. Based on the relationship that the sum of the third, fourth, and fifth charges equals the total charge of the second mode, the relationship between the second peak current control signal IB2 and the first peak current control signal IB1 is determined, and the peak current compensation signal I_COMP is determined.

[0053] The following is an example of a basic calculation principle based on calculation principles. By default, only the input voltage signal VIN at the input voltage terminal VIN changes, while the load current IO at the output voltage terminal VOUT remains unchanged. The starting current IA of the inductor IND in the first mode is the same as that in the second mode. For peak current mode control, the difference between the first mode and the second mode is only the change between the first peak current control signal IB1 and the actual second peak current control signal IB2 in the first mode.

[0054] refer to Figure 1 , Figure 2 and Figure 3 Because for the second mode of buck-boost, given a fixed duty cycle TS and operating frequency, the fourth duration T4 of the fourth stage and the fifth duration T5 of the fifth stage can both be calculated using volt-second balance. Furthermore, to better implement the cot (constant off time, in Buck-Boost circuits, the constant off time control strategy refers to constant control of the off time of the first switch Q1) architecture, it is necessary to keep the fourth duration T4 of the fourth stage consistent with the second duration T2 of the second stage. This can be achieved through load consistency, where Sx represents the slope of the inductor current IND in the corresponding stage.

[0055] refer to Figure 1 , Figure 2 and Figure 3 For the first stage (the duration of the first stage is defined as the first duration T1) and the second stage in the first mode of buck conversion, the load current... The slope of the second inductor current Therefore, based on the peak current control signal, the second duration T2 of the second stage, and the second inductor current slope S2 of the inductor IND in the second stage, the load current IO of the output voltage terminal VOUT can satisfy the following relationship:

[0056] For the third, fourth, and fifth stages in the second mode, which is a buck-boost mode, the slope of the third inductor current... The slope of the fourth inductor current The absolute value of the slope S5 of the fifth inductor current .

[0057] Therefore, based on the second peak current control signal IB2, the fourth duration T4 of the fourth stage, and the fourth inductor current slope S4 of the inductor IND current in the fourth stage, the third peak current control signal IC is determined as follows:

[0058] In the second mode, the starting current IA of the inductor IND is as follows:

[0059] Based on the load current IO at the output voltage terminal VOUT and the duty cycle TS of the second mode, the total charge in the second mode is determined as follows: Based on the second peak current control signal IB2 and the third duration T3 of the third stage, the third charge quantity of the third stage is determined as follows: Based on the second peak current control signal IB2, the third peak current control signal IC, and the fourth duration T4 of the fourth stage, the fourth charge quantity of the fourth stage is determined as follows: Based on the third peak current control signal IC and the fifth duration T5 of the fifth stage, the fifth charge quantity of the fifth stage is determined as follows: The sum of the third, fourth, and fifth charges equals The second phase, second duration. Equal to the fourth duration of the fourth stage .

[0060] The relationship between the sum of the third, fourth, and fifth charges and the total charge of the second mode is as follows:

[0061] T3+T4+T5=TS, where TS is the entire working cycle TS when working in the second mode, and TS depends on the specific working frequency in the actual application.

[0062] refer to Figure 1 , Figure 2 and Figure 3 After integrating the previous formulas, we can obtain the second peak current control signal IB2 required in the second mode. At this point, we obtain the difference between the first peak current control signal IB1 in the first mode and the second peak current control signal IB2 in the second mode. The difference in peak current between the two (peak current compensation signal I_COMP) is equal to:

[0063] Therefore, in the second mode, during the boost energy storage stage (third stage), the peak current compensation signal I_COMP is inserted into the peak current at the positive input of the comparator current transformer to combine the first peak current control signal IB1 and the peak current compensation signal. By comparing the signal with the inductor current sampling signal SNS, the switching condition from the third stage to the fourth stage can be set to the required second peak current control signal IB2.

[0064] It should be noted that SNS in the diagram represents the inductor current sampling signal, which is the real-time inductor current on the inductor IND obtained by sampling the current of the inductor IND. This inductor current sampling signal SNS is sent to the positive input of the current comparator COMP to control the operating state of the first switch Q1 to the fourth switch Q4. IND stands for Inductor. RON represents the on-resistance of the first switch Q1.

[0065] For example, refer to Figure 2 The second terminal of the first switching transistor Q1 is coupled to the negative input terminal of the current comparator COMP through the current sampling circuit SENSE. The current sampling circuit SENSE is used to sample the inductor current to obtain the inductor current sampling signal SNS. By setting the current sampling circuit SENSE, it is convenient to obtain the inductor current sampling signal SNS in real time and accurately.

[0066] It should be understood that the peak current mode control circuit of the DC-DC circuit disclosed herein may include other components in addition to the components shown above, and these components are all within the protection scope of the peak current mode control circuit of the DC-DC circuit disclosed herein.

[0067] Example 2 This disclosure provides a peak current mode control method for a DC-DC circuit. This method is based on the peak current mode control circuit for the DC-DC circuit provided in the first aspect of this disclosure, with reference to... Figure 4 The sampling method mainly includes the following steps: In step S401, during the process of the DC-DC circuit switching from the first mode to the second mode, based on the principle that the load current IO of the output voltage terminal VOUT remains unchanged and the calculation principle that the starting current IA of the inductor IND in the first mode is equal to the starting current IA of the inductor IND in the second mode, the second peak current control signal IB2 required in the second mode is determined according to the first peak current control signal IB1 in the first mode; wherein, the first mode and the second mode are any two modes among buck mode, boost mode and buck-boost mode; In step S402, the difference between the first peak current control signal IB1 and the second peak current control signal IB2 is used as the peak current compensation signal I_COMP. In step S403, after the DC-DC circuit switches from the first mode to the second mode, the first switch Q1 to the fourth switch Q4 are controlled to turn on and off based on the first peak current control signal IB1, the peak current compensation signal I_COMP and the inductor current sampling signal SNS.

[0068] It should be noted that, in addition to the method steps shown above, the peak current mode control method for the DCDC circuit provided in this disclosure embodiment may also include the relevant steps shown in Embodiment 1, all of which are within the protection scope of the peak current mode control method for the DCDC circuit provided in this disclosure embodiment.

[0069] Example 3 This disclosure provides a chip that includes a peak current mode control circuit for any of the DC-DC circuits provided in Embodiment 1 of this disclosure.

[0070] Example 4 This disclosure provides an electronic device, which includes the chip provided in Embodiment 3 of this disclosure.

[0071] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0072] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this disclosure may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0073] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims. Although embodiments of this disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this disclosure, and all such modifications and variations fall within the scope defined by the appended claims.

Claims

1. A peak current mode control circuit for a DC-DC converter, wherein, The DC-DC circuit includes: an input voltage terminal, an output voltage terminal, an inductor, a first switching transistor, a second switching transistor, a third switching transistor, and a fourth switching transistor; the first terminal of the first switching transistor is coupled to the input voltage terminal, the second terminal of the first switching transistor is coupled to the first terminal of the second switching transistor and the first terminal of the inductor, the second terminal of the second switching transistor is coupled to ground, the first terminal of the fourth switching transistor is coupled to the second terminal of the inductor and the first terminal of the third switching transistor, the second terminal of the fourth switching transistor is coupled to the output voltage terminal, and the second terminal of the third switching transistor is coupled to ground; characterized in that the peak current mode control circuit includes: A voltage error amplifier, wherein the positive input terminal of the voltage error amplifier is coupled to a reference voltage signal, and the inverting input terminal of the voltage error amplifier is coupled to a feedback voltage signal acquired based on the output voltage terminal; A voltage-to-current module, wherein the input terminal of the voltage-to-current module is coupled to the output terminal of the voltage error amplifier, and the voltage-to-current module is used to convert the control voltage signal output by the voltage error amplifier into a peak current control signal; An analog calculator configured to generate a peak current compensation signal based on the input voltage signal at the input voltage terminal and the output voltage signal at the output voltage terminal; A current comparator is provided, wherein its positive input is coupled to the output of the voltage-to-current module and the output of the analog calculator, its negative input is coupled to the inductor current sampling signal, and its output is coupled to the control terminals of the first, second, third, and fourth switches. The current comparator controls the on / off state of the first to fourth switches based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal.

2. The peak current mode control circuit as described in claim 1, characterized in that, The analog calculator generates a peak current compensation signal based on the input voltage signal at the input voltage terminal and the output voltage signal at the output voltage terminal, including: When the DC-DC circuit switches from the first mode to the second mode, based on the principle that the load current at the output voltage terminal remains unchanged and that the starting current of the inductor in the first mode is equal to the starting current of the inductor in the second mode, the second peak current control signal required in the second mode is determined according to the first peak current control signal in the first mode; wherein, the first mode and the second mode are any two modes among buck mode, boost mode and buck-boost mode; The difference between the first peak current control signal and the second peak current control signal is used as the peak current compensation signal. The current comparator controls the on and off of the first switch to the fourth switch based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal, including: when the DC-DC circuit switches from the first mode to the second mode, the current comparator controls the on and off of the first switch to the fourth switch based on the first peak current control signal, the peak current compensation signal, and the inductor current sampling signal.

3. The peak current mode control circuit as described in claim 2, characterized in that, One of the first mode and the second mode is a buck mode, and the other is a buck-boost mode; or, One of the first mode and the second mode is a boost mode, and the other mode is a buck-boost mode.

4. The peak current mode control circuit as described in claim 3, characterized in that, The first mode is a buck mode, and the second mode is a buck-boost mode; The first mode includes a first stage in which the inductor current rises from the starting current to the first peak current control signal, and a second stage in which the inductor current falls from the first peak current control signal back to the starting current; The second mode includes a third stage in which the inductor current rises from the starting current to the second peak current control signal, a fourth stage in which the inductor current rises from the second peak current control signal to the third peak current control signal, and a fifth stage in which the inductor current falls from the third peak current control signal to the starting current. The current comparator controls the on and off of the first to the fourth switching transistors based on the peak current control signal, the peak current compensation signal, and the inductor current sampling signal. It also includes controlling the fourth duration of the fourth stage to be equal to the second duration of the second stage after the DC-DC circuit switches from the first mode to the second mode. The calculation principle also includes that the fourth duration of the fourth stage is equal to the second duration of the second stage.

5. The peak current mode control circuit as described in claim 4, characterized in that, During the first stage, the first switch and the fourth switch are turned on, while the second switch and the third switch are turned off. During the second stage, the second switch and the fourth switch are turned on, while the first switch and the third switch are turned off. In the third stage, the first and third switches are turned on, while the second and fourth switches are turned off. In the fourth stage, the first and fourth switches are turned on, while the second and third switches are turned off. In the fifth stage, the second and fourth switches are turned on, while the first and third switches are turned off.

6. The peak current mode control circuit as described in claim 4, characterized in that, The peak current compensation signal I_COMP is calculated using the following formula: I_COMP= in, This indicates the input voltage value at the input voltage terminal. This indicates the output voltage value at the output voltage terminal. This indicates the inductance value of the inductor. This indicates the working cycle of the second mode.

7. The peak current mode control circuit as described in claim 4, characterized in that, When the DC-DC circuit switches from the first mode to the second mode, the current comparator controls the on / off state of the first to the fourth switching transistors based on the first peak current control signal, the peak current compensation signal, and the inductor current sampling signal, including: When the DC-DC circuit switches from the first mode to the second mode, the current comparator controls the switch from the third stage to the fourth stage based on the relationship between the sum of the first peak current control signal and the peak current compensation signal and the inductor current sampling signal.

8. The peak current mode control circuit as described in claim 4, characterized in that, Based on the aforementioned calculation principle, and according to the first peak current control signal in the first mode, the second peak current control signal and the peak current compensation signal in the second mode are determined, including: Based on the peak current control signal, the second duration of the second stage, and the second inductor current slope of the inductor current in the second stage, the load current at the output voltage terminal is determined. Based on the load current at the output voltage terminal and the operating cycle of the second mode, the total charge of the second mode is determined; The third peak current control signal is determined based on the second peak current control signal, the fourth duration of the fourth stage, and the fourth inductor current slope of the inductor current in the fourth stage. Based on the second peak current control signal and the third duration of the third stage, the third charge amount of the third stage is determined; Based on the second peak current control signal, the third peak current control signal, and the fourth duration of the fourth stage, the fourth charge quantity of the fourth stage is determined; Based on the third peak current control signal and the fifth duration of the fifth stage, the fifth charge quantity of the fifth stage is determined; Based on the relationship that the sum of the third charge, the fourth charge, and the fifth charge equals the total charge of the second mode, the relationship between the second peak current control signal and the first peak current control signal is determined, and the peak current compensation signal is determined.

9. The peak current mode control circuit as described in claim 1, characterized in that, The second terminal of the first switching transistor is coupled to the negative input terminal of the current comparator through a current sampling circuit. The current sampling circuit is used to sample the inductor current of the inductor to obtain the inductor current sampling signal.

10. A peak current-mode control method for a DC-DC circuit, characterized in that, The method is based on the peak current mode control circuit of the DCDC circuit as described in any one of claims 2 to 9, and the method includes: When the DC-DC circuit switches from the first mode to the second mode, based on the principle that the load current at the output voltage terminal remains unchanged and that the starting current of the inductor in the first mode is equal to the starting current of the inductor in the second mode, the second peak current control signal required in the second mode is determined according to the first peak current control signal in the first mode; wherein, the first mode and the second mode are any two modes among buck mode, boost mode and buck-boost mode; The difference between the first peak current control signal and the second peak current control signal is used as the peak current compensation signal. When the DC-DC circuit switches from the first mode to the second mode, it controls the conduction and turn-off of the first switch to the fourth switch based on the first peak current control signal, the peak current compensation signal and the inductor current sampling signal.

11. A chip, characterized in that, The chip includes a peak current mode control circuit for the DC-DC circuit as described in any one of claims 1 to 9.

12. An electronic device, characterized in that, The electronic device includes the chip as described in claim 11.

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