Circuit for controlling the rate of fall of an output node in a high performance voltage converter

Abstract

This invention discloses a circuit for controlling the output node descent rate in a high-performance voltage converter, belonging to the field of voltage converter technology. It includes an SW node descent rate detection module, an SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit. The detection module collects the switching node signal and sends it to the control module, outputting two control signals. PM3 and NM3 form a push-pull structure for lower transistor drive. The substrate switching unit is controlled by the two signals, selecting two power supplies with different potentials to be connected to the substrate of PM3. The driving capability is adjusted by utilizing the body effect to realize the regulation of the switching node descent rate.

Description

Technical Field

[0001] This invention belongs to the field of voltage converter and semiconductor display technology, specifically relating to a circuit for controlling the descent rate of the output node in a high-performance voltage converter. Background Technology

[0002] In synchronous DC-DC (Direct Current to Direct Current) converters, such as BUCK (buck converter circuits), controlling the descent rate of the SW (Switch) node in the DC-DC converter is essentially about finding an optimal balance between efficiency and electromagnetic compatibility (EMI) / stress. Too fast a rate will produce severe voltage spikes (overshoot) and high-frequency oscillations (ringing); too slow a rate, while optimizing noise, will increase switching losses and reduce conversion efficiency.

[0003] The commonly used methods for controlling the descent rate include the following: 1. Optimize the PCB (Printed Circuit Board) layout. As the most fundamental solution, the core of layout optimization is to reduce the area of ​​the power loop, thereby reducing the parasitic inductance Lp and reducing the energy of LC (inductor-capacitor) resonance from the root. Specific measures include placing power devices such as input capacitors and high- and low-side MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) close together; widening and shortening the traces of the SW node and other related traces; and avoiding long parallel traces below the SW node to reduce capacitive coupling.

[0004] 2. Increase the gate drive resistor. By increasing the resistance in the MOSFET gate drive circuit, the turn-on or turn-off rate can be directly limited. As one of the most direct and effective methods to achieve "slowing down the fall rate", increasing the gate resistance of the upper MOSFET can control the rising edge of the SW node, while the gate resistance of the lower MOSFET controls the falling edge. Increasing the resistance value can slow down the switching waveform to suppress spikes and ringing, but it will increase switching losses, prolong dead time, and may lead to excessively slow switching speed.

[0005] 3. Dead-time control, as the most core and fundamental method, involves artificially inserting a delay between the switching signals of the upper and lower transistors, during which both transistors are turned off. This can be implemented via chip integration (fixed / adjustable) using MCU (Micro Controller Unit), DSP (Digital Signal Processor), or FPGA (Field-Programmable Gate Array). It is simple to implement and serves as the first line of defense against shoot-through. Efficiency trade-offs: a too-long dead time results in high conduction losses in the body diode, reducing efficiency; a too-short dead time increases the risk of shoot-through. Limitations: a fixed dead time must be set based on worst-case scenarios and is usually too long; the accuracy of the MCU's dead-time unit may be insufficient.

[0006] In addition, Chinese patent application CN105024529A, published on November 4, 2015, disclosed an adaptive dead time generation circuit for intelligent power modules. Although the circuit effectively avoids the simultaneous operation of high-side MOSFETs and low-side MOSFETs in the intelligent power module, ensuring the stability of each module in the applied intelligent power module, the implementation scheme is relatively complex and the area and power consumption are not optimal.

[0007] Against the backdrop of rapid development in semiconductor display technology, GaN (gallium nitride)-based Micro-LEDs (micro-light-emitting diodes) have attracted widespread attention as a next-generation display technology. Micro-LEDs offer advantages such as high brightness, fast response speed, and low power consumption, making them an ideal choice for augmented reality (AR) displays and microdisplays. As Micro-LEDs evolve towards higher resolution and higher refresh rates, pixel arrays place higher demands on the transient stability and power consumption control of the driving power supply. However, existing DC-DC voltage converters for Micro-LED drivers still have significant technical shortcomings: existing driver converters generally lack a precise control mechanism for the descent rate of the switching nodes, easily generating large transient voltage spikes and high-frequency oscillations during rapid switching of the switching transistors. This exacerbates electromagnetic interference and causes fluctuations in pixel driving current, directly leading to image quality issues such as uneven brightness and flickering. Furthermore, existing solutions that adjust the switching rate through series current-limiting devices in the main path introduce additional conduction losses, making it difficult to simultaneously meet the dual requirements of high image quality and low power consumption in AR displays and other scenarios, thus hindering the performance improvement and commercialization of GaN-based Micro-LED display driver systems. Summary of the Invention

[0008] The purpose of this invention is to overcome the problem of the inability to balance efficiency and electromagnetic compatibility in DC-DC converters, and to propose a circuit for controlling the descent rate of the output node in a high-performance voltage converter.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a circuit for controlling the output node descent rate in a high-performance voltage converter, including an SW node descent rate detection module, an SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit. The input terminal of the SW node descent rate detection module is connected to the switching node SW of the voltage converter, and the output terminal of the SW node descent rate detection module is connected to the input terminal of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and used to receive the lower transistor drive control signal VCN; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and used to connect to the gate of the lower switching transistor NM1 of the voltage converter. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, and the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. The first control terminal of the substrate potential switching unit receives a first control signal Vctrl1, which is used to control the connection and disconnection between the first power supply terminal and the output terminal; the second control terminal of the substrate potential switching unit receives a second control signal Vctrl2, which is used to control the connection and disconnection between the second power supply terminal and the output terminal.

[0010] Furthermore, the SW node descent rate detection module includes a second capacitor C2, a third resistor R3, a fourth resistor R4, and a buffer. One end of the second capacitor C2 is the input terminal of the SW node descent rate detection module, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 respectively to form a voltage divider node SW2. The other end of the third resistor R3 is connected to the first power supply potential VDD, and the other end of the fourth resistor R4 is grounded. The resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal. The voltage divider node SW2 is connected to the input of the buffer, and the output of the buffer is the output of the SW node descent rate detection module, which outputs the signal of the second switch node SW3.

[0011] Furthermore, the SW node descent rate control module includes a D flip-flop DFF1, a first inverter INV1, and a timing detection module; The data input terminal D of the D flip-flop DFF1 is connected to a high potential. The clock terminal Clk of the D flip-flop DFF1 is the input terminal of the SW node descent rate control module. The reset terminal Reset of the D flip-flop DFF1 is connected to the output terminal of the timing detection module and receives the reset signal Rst. The positive output terminal Q of D flip-flop DFF1 outputs the first control signal Vctrl1. The positive output terminal Q of D flip-flop DFF1 is connected to the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 outputs the second control signal Vctrl2. The input of the timing detection module is connected to the output of the descent rate detection module of the SW node; The timing detection module includes a clock source, a timing circuit, a decision module, a monostable multivibrator, and an output module; The clock source outputs a clock signal CLKOUT and connects to the input of the timing circuit. The first output of the timing circuit is connected to the control terminal of the decision module, and the second output of the timing circuit is connected to the input of the monostable multivibrator. The input terminal of the decision module is the input terminal of the timing detection module, and the output terminal of the decision module is connected to the input terminal of the output module; The output of the monostable multivibrator is connected to the control terminal of the output module, and the output of the output module is the output of the timing detection module, which outputs a reset signal Rst.

[0012] Furthermore, the clock source is a ring oscillator, including a second inverter INV11, a third inverter INV12, a fourth inverter INV13, a fifth inverter INV14, a third capacitor C11, a fourth capacitor C12, and a fifth capacitor C13. The second inverter INV11, the third inverter INV12, and the fourth inverter INV13 are connected in series to form a closed loop circuit; The output of the second inverter INV11 is connected to one end of the third capacitor C11, the output of the third inverter INV12 is connected to one end of the fourth capacitor C12, and the output of the fourth inverter INV13 is connected to one end of the fifth capacitor C13. The other ends of the third capacitor C11, the fourth capacitor C12, and the fifth capacitor C13 are all grounded; The output of the fourth inverter INV13 is connected to the input of the fifth inverter INV14, and the output of the fifth inverter INV14 is the output of the clock source.

[0013] Furthermore, the substrate potential switching unit includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5; The source of the fourth PMOS transistor PM4 is the first power supply terminal, and the source of the fifth PMOS transistor PM5 is the second power supply terminal. The drain of the fourth PMOS transistor PM4 is connected to the drain of the fifth PMOS transistor PM5 and serves as the output terminal. The gate of the fourth PMOS transistor PM4 is the first control terminal, and the gate of the fifth PMOS transistor PM5 is the second control terminal.

[0014] In a second aspect, the present invention provides a control method for a circuit that controls the descent rate of an output node in a high-performance voltage converter. The method, using the circuit that controls the descent rate of an output node in a high-performance voltage converter, includes the following steps: The voltage signal of the switching node SW of the voltage converter is acquired to generate a rate detection signal; Based on the rate detection signal, output the first control signal Vctrl1 and the second control signal Vctrl2; The first control signal Vctrl1 and the second control signal Vctrl2 are used to select the first power supply potential VDD or the second power supply potential VDD2 to be connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. By changing the substrate potential of the third PMOS transistor PM3, the driving capability of the third PMOS transistor PM3 is adjusted, the conduction speed of the switching transistor NM1 under the voltage converter is controlled, and the descent rate of the switching node SW is adjusted.

[0015] Thirdly, the present invention provides a DC-DC converter, including a DC-DC chip, an inductor L0, an output capacitor C0, a first voltage divider resistor R1 and a second voltage divider resistor R2. The DCDC chip integrates an upper switch PM1, a lower switch NM1, a logic control module, an upper switch driver circuit, a lower switch driver circuit, and a circuit that controls the descent rate of the output node in the high-performance voltage converter. The drain of the upper switch PM1 is connected to the input voltage Vin, and the source of the upper switch PM1 and the drain of the lower switch NM1 are connected together to form a switching node SW; the source of the lower switch NM1 is grounded. The switching node SW is connected to one end of the inductor L0, and the other end of the inductor L0 is the output terminal Vout; the output capacitor C0 is connected between the output terminal Vout and ground; the first voltage divider resistor R1 and the second voltage divider resistor R2 are connected in series between the output terminal Vout and ground, and the voltage divider node outputs a feedback voltage Vfb and is connected to the feedback input terminal of the DC-DC chip; The logic control module is connected to the gate of the upper switching transistor PM1 via the upper transistor drive circuit, and the logic control module is connected to the gate of the lower switching transistor NM1 via the lower transistor drive circuit. The lower transistor drive circuit includes a third PMOS transistor PM3 and a third NMOS transistor NM3; the source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and connected to the lower transistor drive control signal VCN output by the logic control module; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and connected to the gate of the lower switching transistor NM1. The input of the SW node descent rate detection module is connected to the switch node SW, and the output of the SW node descent rate detection module is connected to the input of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, and the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. The first control terminal of the substrate potential switching unit receives a first control signal Vctrl1, which is used to control the connection and disconnection between the first power supply terminal and the output terminal; the second control terminal of the substrate potential switching unit receives a second control signal Vctrl2, which is used to control the connection and disconnection between the second power supply terminal and the output terminal.

[0016] Furthermore, the DC-DC chip also integrates an error amplifier EA, a comparator COMP, a soft-start module, and a clock. The non-inverting input of error amplifier EA is connected to the reference voltage Vref, the inverting input of error amplifier EA is connected to the feedback voltage Vfb, and the output of error amplifier EA is connected to the inverting input of comparator COMP. The non-inverting input of comparator COMP is connected to the ramp signal Ramp, and the inverting input of comparator COMP is connected to the output of the soft-start module; the output of comparator COMP is connected to the input of the logic control module; the clock output is connected to the clock input of the logic control module. The first output terminal of the logic control module outputs the upper transistor drive control signal VCP and connects to the input terminal of the upper transistor drive circuit. The output terminal of the upper transistor drive circuit is connected to the gate of the upper switching transistor PM1. The second output terminal of the logic control module outputs the lower transistor drive control signal VCN and connects to the input terminal of the lower transistor drive circuit. The upper transistor driving circuit includes a second PMOS transistor PM2 and a second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the first power supply potential VDD, and the source of the second NMOS transistor NM2 is grounded; the gate of the second PMOS transistor PM2 and the gate of the second NMOS transistor NM2 are connected together and serve as the input terminal of the upper transistor driving circuit; the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2 are connected together and serve as the output terminal of the upper transistor driving circuit.

[0017] Furthermore, the SW node descent rate detection module includes a second capacitor C2, a third resistor R3, a fourth resistor R4, and a buffer. One end of the second capacitor C2 is the input terminal of the SW node descent rate detection module, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 respectively to form a voltage divider node SW2. The other end of the third resistor R3 is connected to the first power supply potential VDD, and the other end of the fourth resistor R4 is grounded; the voltage divider node SW2 is connected to the input of the buffer, and the output of the buffer is the output of the SW node descent rate detection module; The substrate potential switching unit includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5; the source of the fourth PMOS transistor PM4 is the first power supply terminal, and the source of the fifth PMOS transistor PM5 is the second power supply terminal; the drain of the fourth PMOS transistor PM4 and the drain of the fifth PMOS transistor PM5 are connected together and serve as the output terminal; the gate of the fourth PMOS transistor PM4 is the first control terminal, and the gate of the fifth PMOS transistor PM5 is the second control terminal.

[0018] Fourthly, the present invention provides a GaN-based Micro-LED display driving system, including a DC-DC chip and a GaN-based Micro-LED array, wherein the output terminal of the DC-DC chip is connected to the power supply terminal of the GaN-based Micro-LED array; The DCDC chip internally includes a lower switching transistor NM1, a SW node descent rate detection module, a SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit. The input of the SW node descent rate detection module is connected to the switching node SW of the DC-DC chip, and the output of the SW node descent rate detection module is connected to the input of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and connected to the lower transistor drive control signal VCN; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and connected to the gate of the lower switching transistor NM1. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, and the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3; the first control terminal of the substrate potential switching unit receives the first control signal Vctrl1, and the second control terminal of the substrate potential switching unit receives the second control signal Vctrl2.

[0019] Compared with the prior art, the present invention has the following beneficial technical effects: This invention proposes a circuit for controlling the fall rate of the output node in a high-performance voltage converter. Through simplified design, it controls the fall rate of the SW node in a DC-DC converter, enabling the DC-DC converter to achieve both high conversion efficiency and excellent electromagnetic compatibility (EMC). This circuit achieves adaptive regulation of the switch node fall rate, effectively balancing the conversion efficiency and EMC of the voltage converter. The SW node fall rate detection module collects the voltage change status of the switch node in real time, quickly identifying falling edge overshoot and ringing phenomena, providing accurate data for rate regulation. By relying on the substrate potential switching unit to change the substrate bias of the driving PMOS transistor, the driving capability is adjusted using the PMOS body effect: when the switch node fall rate is too fast, the substrate potential is raised to weaken the driving strength, suppressing voltage spikes and high-frequency oscillations, and reducing electromagnetic interference; when the fall rate is within a reasonable range, a strong driving state with a low substrate potential is maintained to reduce switching losses and ensure conversion efficiency. This circuit can adaptively match different input voltages and load conditions without external configuration parameters. Its overall architecture is simple and easy to integrate on-chip, achieving synergistic optimization of efficiency and electromagnetic performance without significantly increasing chip area and power consumption.

[0020] The control method for controlling the output node descent rate in a high-performance voltage converter proposed in this invention achieves precise control of the switching node descent rate by real-time acquisition of the voltage state of the switching node, adaptively adjusting the substrate potential of the lower-side drive transistor, and dynamically adjusting the drive capability using the PMOS body effect. This method requires no additional external components or manual parameter configuration, automatically matches the optimal operating state under different input voltages and load conditions, effectively suppresses voltage overshoot and high-frequency oscillations, and avoids unnecessary switching losses, achieving synergistic optimization of conversion efficiency and electromagnetic compatibility performance.

[0021] This invention proposes a DC-DC converter that, through an on-chip integrated switching node fall rate detection and control architecture, can adaptively adjust the fall rate of the switching node, effectively balancing buck conversion efficiency and electromagnetic compatibility performance. The SW node fall rate detection module collects the voltage change status of the switching node in real time, accurately identifying fall-edge overshoot and ringing phenomena. The control module drives the substrate potential switching unit, utilizing the PMOS body effect to adjust the driving capability of the lower transistor driving the upper transistor: when the switching node fall rate is too fast, the substrate potential of the driving transistor is raised to weaken the driving strength, suppressing voltage spikes and high-frequency oscillations, and reducing electromagnetic interference; when the fall rate is within a reasonable range, a strong driving state with a low substrate potential is maintained to reduce switching losses and ensure conversion efficiency. The entire control circuit is integrated inside the chip, requiring no additional external components or parameter configurations, simplifying application circuitry and PCB layout. It can adapt to a wide range of input voltages and load conditions, improving overall electromagnetic reliability while maintaining high-efficiency power supply performance.

[0022] This invention proposes a GaN (Gallium Nitride)-based Micro-LED display driving system. By integrating a SW node fall rate detection module, a SW node fall rate control module, and a substrate potential switching unit within a DC-DC chip, adaptive adjustment of the switching node fall rate can be achieved. The system eliminates the need for a current-limiting device in series in the main driving path; the driving strength can be changed simply by dynamically adjusting the substrate potential of the third PMOS transistor. This effectively suppresses transient voltage and current spikes during switching, reduces high-frequency oscillations and electromagnetic interference, and avoids additional conduction losses, balancing driving stability and conversion efficiency. In Micro-LED (Micro Light Emitting Diode) display applications, stable driving voltage and current ensure consistent pixel array driving at high refresh rates, improve brightness uniformity and flicker, and enhance display stability and image quality uniformity. Optimized switching loss characteristics reduce overall driving power consumption, making it suitable for power-sensitive and image-quality-critical micro-display scenarios such as augmented reality, thus improving the system's overall performance and scenario adaptability. Attached Figure Description

[0023] The accompanying drawings are provided to further understand the invention and constitute a part of this invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0024] Figure 1 This is a schematic diagram of the system architecture of a traditional DC-DC converter.

[0025] Figure 2 This is a schematic diagram of the system architecture of a DC-DC converter provided in an embodiment of the present invention.

[0026] Figure 3 This is a block diagram illustrating the principle of the descent rate control circuit in an embodiment of the present invention.

[0027] Figure 4 This is a detailed circuit diagram of the descent rate control circuit in an embodiment of the present invention.

[0028] Figure 5 This is the working waveform of the present invention.

[0029] Figure 6 This is a waveform diagram of the key node in the SW node descent rate control process in an embodiment of the present invention.

[0030] Figure 7 This is a circuit diagram of the SW node descent rate control module in an embodiment of the present invention.

[0031] Figure 8 This is a circuit diagram of the timing detection module in an embodiment of the present invention.

[0032] Figure 9 This is a circuit diagram of the clock source module in an embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0034] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only embodiments.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that the terms "first," "second," etc., in the specification and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0037] Example 1 See Figure 3 and Figure 4 The circuit for controlling the output node descent rate in a high-performance voltage converter includes an SW node descent rate detection module, an SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit. The input terminal of the SW node descent rate detection module is connected to the switching node SW of the voltage converter, and the output terminal of the SW node descent rate detection module is connected to the input terminal of the SW node descent rate control module. The SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The SW node descent rate detection module includes a second capacitor C2, a third resistor R3, a fourth resistor R4, and a buffer. One end of the second capacitor C2 is the input terminal of the SW node descent rate detection module, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 to form a voltage divider node SW2. The other end of the third resistor R3 is connected to the first power supply potential VDD, and the other end of the fourth resistor R4 is grounded. The resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal. The voltage divider node SW2 is connected to the input terminal of the buffer, and the output terminal of the buffer is the output terminal of the SW node descent rate detection module, which outputs the second switching node SW3 signal.

[0038] The second capacitor C2 couples the voltage jump signal of the acquisition switch node SW. After being divided by the third resistor R3 and the fourth resistor R4, the voltage level change corresponding to the falling edge pulse is formed at the voltage divider node SW2. The two resistors are set to be equal to statically bias the voltage divider node SW2 at 1 / 2 of the first power supply potential VDD, ensuring that the buffer can stably identify the falling edge pulse. After being shaped, the buffer outputs the signal of the second switch node SW3, completing the detection and conversion of the rate signal.

[0039] See Figure 7 The SW node descent rate control module includes a D flip-flop DFF1, a first inverter INV1, and a timing detection module. The data input D of the D flip-flop DFF1 is connected to a high potential. The clock input Clk of the D flip-flop DFF1 is the input of the SW node descent rate control module. The reset input Reset of the D flip-flop DFF1 is connected to the output of the timing detection module and receives the reset signal Rst. The positive output Q of the D flip-flop DFF1 outputs a first control signal Vctrl1. The positive output Q of the D flip-flop DFF1 is connected to the input of the first inverter INV1. The output of the first inverter INV1 outputs a second control signal Vctrl2. The input of the timing detection module is connected to the output of the SW node descent rate detection module. Figure 7 In It is the inverted output of the D flip-flop DFF1.

[0040] The second switch node SW3 inputs the clock input Clk to the D flip-flop DFF1, triggering the D flip-flop DFF1 to latch up. The positive output terminal Q outputs the first control signal Vctrl1, and the positive output terminal outputs the second control signal Vctrl2 via the first inverter INV1. The timing detection module counts the duration of the control: the clock source outputs the clock signal CLKOUT to provide a timing reference for the timing circuit. After the set duration is reached, the decision module, the monostable multivibrator, and the output module generate a reset signal Rst to reset the D flip-flop DFF1 and end the control state.

[0041] See Figure 8 The timing detection module includes a clock source, a timing circuit, a decision module, a monostable multivibrator, and an output module. The clock source outputs a clock signal CLKOUT and connects to the input of the timing circuit. The first output of the timing circuit is connected to the control terminal of the decision module, and the second output of the timing circuit is connected to the input of the monostable multivibrator. The input of the decision module is the input of the timing detection module, and the output of the decision module is connected to the input of the output module. The output of the monostable multivibrator is connected to the control terminal of the output module, and the output of the output module is the output of the timing detection module, outputting a reset signal Rst.

[0042] See Figure 9The clock source is a ring oscillator, including a second inverter INV11, a third inverter INV12, a fourth inverter INV13, a fifth inverter INV14, a third capacitor C11, a fourth capacitor C12, and a fifth capacitor C13. The second inverter INV11, the third inverter INV12, and the fourth inverter INV13 are connected in series to form a closed loop. The output of the second inverter INV11 is connected to one end of the third capacitor C11, the output of the third inverter INV12 is connected to one end of the fourth capacitor C12, and the output of the fourth inverter INV13 is connected to one end of the fifth capacitor C13. The other ends of the third capacitor C11, the fourth capacitor C12, and the fifth capacitor C13 are all grounded. The output of the fourth inverter INV13 is connected to the input of the fifth inverter INV14, and the output of the fifth inverter INV14 is the output of the clock source.

[0043] See Figure 4 The source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and used to receive the lower transistor drive control signal VCN; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and used to connect to the gate of the lower switching transistor NM1 of the voltage converter. See Figure 4 The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, and the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. The first control terminal of the substrate potential switching unit receives a first control signal Vctrl1 to control the on / off state between the first power supply terminal and the output terminal. The second control terminal of the substrate potential switching unit receives a second control signal Vctrl2 to control the on / off state between the second power supply terminal and the output terminal.

[0044] See Figure 4 The third PMOS transistor PM3 and the third NMOS transistor NM3 form a push-pull drive structure, which jointly receive the lower switch drive control signal VCN and drive the lower switch transistor NM1. When the substrate end sub of the third PMOS transistor PM3 switches to the higher second power supply potential VDD2, its conduction drive capability is weakened, which slows down the conduction speed of the lower switch transistor NM1, thereby reducing the descent rate of the switching node SW and suppressing overshoot and oscillation. When the substrate is connected back to the first power supply potential VDD, the strong drive state is restored to ensure switching efficiency.

[0045] See Figure 4The substrate potential switching unit includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5; the source of the fourth PMOS transistor PM4 is the first power supply terminal, and the source of the fifth PMOS transistor PM5 is the second power supply terminal; the drain of the fourth PMOS transistor PM4 and the drain of the fifth PMOS transistor PM5 are connected together and serve as the output terminal; the gate of the fourth PMOS transistor PM4 is the first control terminal, and the gate of the fifth PMOS transistor PM5 is the second control terminal.

[0046] See Figure 4 The fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 correspond to the first power supply potential VDD and the second power supply potential VDD2, respectively. The first control signal Vctrl1 controls the on / off state of the fourth PMOS transistor PM4, and the second control signal Vctrl2 controls the on / off state of the fifth PMOS transistor PM5. The two signals complement each other and output the corresponding power supply potential to the substrate terminal sub of the third PMOS transistor PM3 to realize the switching of the substrate potential level.

[0047] This invention addresses the challenge of balancing conversion efficiency and electromagnetic compatibility in DC-DC converters by addressing the difficulty of achieving optimal switching node descent rates. It employs a fully integrated architecture with on-chip passive detection, digital logic latching, and substrate bias control. The passive detection structure utilizes capacitive coupling and equal-resistance voltage divider to directly extract the switching node's transition edge signal. A static bias of half the power supply potential ensures reliable pulse recognition by the buffer, eliminating the need for active sampling circuits. This results in fast response and no interference with the main power circuit. Overshoot detection results are latched by a D flip-flop, and a complementary control signal is output to drive potential switching. Combined with a timed reset circuit, the system automatically restores a strong drive state when no abnormalities occur. This eliminates the need for complex algorithms and external configurations, allowing for easy on-chip integration of the digital logic and strong anti-interference capabilities. Utilizing the PMOS body effect principle, the substrate potential of the pull-up transistor is switched via a dual-selector transistor. This dynamically adjusts the drive current capability without changing the drive signal level or increasing the drive path impedance, resulting in lower additional losses and smoother control compared to traditional series current limiting schemes. The entire rate control circuit is fully integrated inside the chip, and is naturally compatible with traditional Buck-type control loops. No additional external components or debugging parameters are required. It can adapt to a wide range of input voltages and load conditions, minimizing efficiency loss while suppressing voltage spikes and improving electromagnetic performance.

[0048] Example 2 A control method for the circuit controlling the descent rate of the output node in a high-performance voltage converter, using the circuit for controlling the descent rate of the output node in the high-performance voltage converter in this embodiment, includes the following steps: The voltage signal of the switching node SW of the voltage converter is acquired to generate a rate detection signal; Based on the rate detection signal, output the first control signal Vctrl1 and the second control signal Vctrl2; The first control signal Vctrl1 and the second control signal Vctrl2 are used to select the first power supply potential VDD or the second power supply potential VDD2 to be connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. By changing the substrate potential of the third PMOS transistor PM3, the driving capability of the third PMOS transistor PM3 is adjusted, the conduction speed of the switching transistor NM1 under the voltage converter is controlled, and the descent rate of the switching node SW is adjusted.

[0049] Example 3 See Figure 2A DC-DC converter includes a DC-DC chip, an inductor L0, an output capacitor C0, a first voltage divider resistor R1, and a second voltage divider resistor R2. The DC-DC chip integrates an upper switching transistor PM1, a lower switching transistor NM1, a logic control module, an upper transistor drive circuit, a lower transistor drive circuit, and the circuit for controlling the output node descent rate in the high-performance voltage converter described in Embodiment 1. The drain of the upper switching transistor PM1 is connected to the input voltage Vin, and the source of the upper switching transistor PM1 and the drain of the lower switching transistor NM1 are connected together to form a switching node SW. The source of the lower switching transistor NM1 is grounded. The switching node SW is connected to one side of the inductor L0. One end of the inductor L0 is the output terminal Vout; the output capacitor C0 is connected between the output terminal Vout and ground; the first voltage divider resistor R1 and the second voltage divider resistor R2 are connected in series between the output terminal Vout and ground, and the voltage divider node outputs a feedback voltage Vfb which is connected to the feedback input terminal of the DC-DC chip; the logic control module is connected to the gate of the upper switching transistor PM1 via the upper transistor drive circuit, and the logic control module is connected to the gate of the lower switching transistor NM1 via the lower transistor drive circuit; the lower transistor drive circuit includes a third PMOS transistor PM3 and a third NMOS transistor NM3; the source of the third PMOS transistor PM3 is connected to the first power supply potential VDD. The source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 is connected to the gate of the third NMOS transistor NM3 and is connected to the lower transistor drive control signal VCN output by the logic control module; the drain of the third PMOS transistor PM3 is connected to the drain of the third NMOS transistor NM3 and is connected to the gate of the lower switching transistor NM1; the input of the SW node descent rate detection module is connected to the switching node SW, and the output of the SW node descent rate detection module is connected to the input of the SW node descent rate control module; the SW node descent rate control module outputs the first control signal Vctrl1 and the second control signal Vc. trl2; The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, and the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. The first control terminal of the substrate potential switching unit receives the first control signal Vctrl1, which is used to control the on / off connection between the first power supply terminal and the output terminal. The second control terminal of the substrate potential switching unit receives the second control signal Vctrl2, which is used to control the on / off connection between the second power supply terminal and the output terminal.

[0050] The DC-DC chip also integrates an error amplifier EA, a comparator COMP, a soft-start module, and a clock. The non-inverting input of the error amplifier EA is connected to a reference voltage Vref, and the inverting input is connected to a feedback voltage Vfb. The output of the error amplifier EA is connected to the inverting input of the comparator COMP. The non-inverting input of the comparator COMP is connected to a ramp signal Ramp, and the inverting input is connected to the output of the soft-start module. The output of the comparator COMP is connected to the input of the logic control module. The output of the clock is connected to the clock input of the logic control module. The first output of the logic control module outputs the upper transistor drive control signal VCP. The upper transistor drive circuit is connected to the input terminal of the upper transistor drive circuit, and the output terminal of the upper transistor drive circuit is connected to the gate of the upper switching transistor PM1. The second output terminal of the logic control module outputs the lower transistor drive control signal VCN and is connected to the input terminal of the lower transistor drive circuit. The upper transistor drive circuit includes a second PMOS transistor PM2 and a second NMOS transistor NM2. The source of the second PMOS transistor PM2 is connected to the first power supply potential VDD, and the source of the second NMOS transistor NM2 is grounded. The gates of the second PMOS transistor PM2 and the second NMOS transistor NM2 are connected together and serve as the input terminal of the upper transistor drive circuit. The drains of the second PMOS transistor PM2 and the second NMOS transistor NM2 are connected together and serve as the output terminal of the upper transistor drive circuit.

[0051] The SW node descent rate detection module includes a second capacitor C2, a third resistor R3, a fourth resistor R4, and a buffer. One end of the second capacitor C2 is the input terminal of the SW node descent rate detection module, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 to form a voltage divider node SW2. The other end of the third resistor R3 is connected to the first power supply potential VDD, and the other end of the fourth resistor R4 is grounded. The voltage divider node SW2 is connected to the input terminal of the buffer, and the output terminal of the buffer is the output terminal of the SW node descent rate detection module. The substrate potential switching unit includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5. The source of the fourth PMOS transistor PM4 is the first power supply terminal, and the source of the fifth PMOS transistor PM5 is the second power supply terminal. The drains of the fourth PMOS transistor PM4 and the fifth PMOS transistor PM5 are connected together and serve as the output terminal. The gate of the fourth PMOS transistor PM4 is the first control terminal, and the gate of the fifth PMOS transistor PM5 is the second control terminal.

[0052] The present invention will be further explained and described below with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a traditional DC-DC system. Figure 2This is a system schematic diagram of a DC-DC converter according to the present invention. The present invention uses a switching node SW descent rate detection and control module to detect the switching node SW signal in real time, and outputs a signal to control the NMOS (N-Metal-Oxide-Semiconductor) driver transistor according to the detection result, thereby optimizing the descent rate of the SW node. Figure 2 In this diagram, L0 is the inductor, Iind is the inductor current, C0 is the output capacitor, Vout is the output terminal, R1 is the first voltage divider resistor, R2 is the second voltage divider resistor, Vfb is the feedback voltage, Iload is the load current, Vin is the input voltage, PM1 is the upper switching transistor, NM1 is the lower switching transistor, SW is the switching node, PG is the upper transistor gate drive signal, NG is the lower transistor gate drive signal, Hdrv is the upper transistor drive circuit, Ldrv is the lower transistor drive circuit, COMP is the comparator, Ramp is the ramp signal, Vea_out is the error amplifier output voltage, Vref is the reference voltage, and EA is the error amplifier.

[0053] Figure 3 This is a simplified block diagram of the circuit controlling the output node descent rate in the high-performance voltage converter of this invention, comprising two main modules: SW node descent rate detection module: Real-time detection of the SW signal at the switching node, and feedback of the detection results to the SW node descent rate control module.

[0054] SW node descent rate control module: Based on the detection results output by the SW node descent rate detection module: first output signal Vctrl1 and second output signal Vctrl2, the SW node descent rate is controlled.

[0055] See Figure 4 The present invention provides a circuit diagram of a circuit that controls the descent rate of the output node in a high-performance voltage converter. Figure 4 In this circuit, SW is the switching node, PM1 is the upper switching transistor, NM1 is the lower switching transistor, L1 is the first inductor, and C1 is the first capacitor; PM2 is the second PMOS transistor, NM2 is the second NMOS transistor, VCP is the upper transistor drive control signal, and PM2 and NM2 are used to drive PM1; PM3 is the third PMOS transistor, PM4 is the fourth PMOS transistor, PM5 is the fifth PMOS transistor, VCN is the lower transistor drive control signal, and PM3, PM4, and PM5 are used to drive NM1; Vctrl1 is the first control signal, and Vctrl2 is the second control signal; C2 is the second capacitor, R3 is the third resistor, R4 is the fourth resistor, SW2 is the voltage divider node, Buffer is the buffer, and SW3 is the second switching node; VDD is the first power supply potential, and VDD2 is the second power supply potential. The working principle of the circuit controlling the output node descent rate in the high-performance voltage converter of this invention is as follows: One end of the second capacitor C2 is connected to the switch node SW, and the other end is connected to the third resistor R3, the fourth resistor R4, and the input terminal of the buffer. The second capacitor C2 performs high-pass filtering on the SW signal, and its filtering calculation formula is as follows:

[0056] in, R3 is the cutoff frequency, R3 is the resistance value of the third resistor, and C2 is the capacitance value of the second capacitor. The third resistor R3 and the fourth resistor R4 (where R3=R4) mainly generate an intermediate potential (1 / 2VDD) through resistor voltage division, which makes it easier for the voltage divider node SW2 signal to be recognized by the subsequent buffer.

[0057] The Buffer mainly shapes the signal of SW2 and outputs the signal of the second switching node SW3 to the SW node descent rate control module.

[0058] If SW3 does not generate a low pulse, the first output signal Vctrl1:0 controls the fourth PMOS transistor PM4 to turn on; the second output signal Vctrl2:1 controls the fifth PMOS transistor PM5 to turn off; the sub (substrate) terminal of the third PMOS transistor PM3 is connected to the first power supply potential VDD and works normally.

[0059] If SW3 generates a low pulse, the first output signal Vctrl1:1 controls the fourth PMOS transistor PM4 to turn off; the second output signal Vctrl2:0 controls the fifth PMOS transistor PM5 to turn on; the sub terminal of the third PMOS transistor PM3 is connected to the second power supply potential VDD2. The potential of the second power supply potential VDD2 is higher than that of the first power supply potential VDD, which increases its turn-on threshold and limits its driving capability.

[0060] The principle of the influence of the substrate potential of a PMOS (P-channel Metal-Oxide-Semiconductor) transistor on the threshold voltage Vth is analyzed as follows: General formula for PMOS threshold voltage: ) in, Zero shim bias Intrinsic threshold, The source-substrate voltage difference Substrate voltage, Source voltage, The body effect coefficient (positive number). For Fermi potential, This is the threshold voltage of the PMOS. Therefore, when When (substrate = source), there is no bulk effect. Initial threshold. When As the substrate voltage increases (higher than the source voltage), the absolute value of the PMOS threshold voltage increases, making it more difficult for the transistor to conduct, thus raising the conduction threshold.

[0061] Figure 5 This is the working waveform of the present invention. The vertical axis V represents voltage, and the horizontal axis Time represents time.

[0062] Figure 6 This is a comparison between the SW waveform of the DC-DC converter of this invention and the SW waveform of the conventional DC-DC converter. The top one is the conventional SW waveform without the improvement of this invention, and the bottom one is the SW waveform of the DC-DC converter using the improvement of this invention. The vertical axis V represents voltage, and the horizontal axis Time represents time.

[0063] See Figure 7 The SW node descent rate control module circuit of the present invention Figure 7 In the diagram, Reset is the reset pin, D is the data input pin, Clk is the clock input pin, and Q is the data output pin. This is the inverted code output terminal, INV1 is the first inverter, and Rst is the reset signal. The working principle of the SW node descent rate control module circuit of this invention is as follows: The second switch node SW3 signal is detected in real time by the timing detection module, and the SW3 signal enters the clock input terminal Clk of the D flip-flop DFF1. When the reset signal Rst=0, the D flip-flop DFF1 is reset, the first output signal Vctrl1=0, and the second output signal Vctrl2=1; When the reset signal Rst=1, the D flip-flop DFF1 can work normally. When the second switch node SW3 has a low pulse, the first output signal Vctrl1=D=1 and the second output signal Vctrl2=0. If the timing detection module detects the second switch node SW3 signal and finds that SW3=1 for a long time (100ms in this example) (SW has no overshoot), it releases the pulse of the reset signal RST=0 to reset the D flip-flop DFF1. Then the first output signal Vctrl1=0 and the second output signal Vctrl2=1.

[0064] Figure 8 This is the timing detection module circuit of the present invention. Figure 8In this circuit, CLKOUT is the clock signal and Rst is the reset signal. The working principle of the timing detection module circuit of this invention is as follows: The clock source generates a clock signal to set the timing circuit, and the timing circuit outputs a timing control signal to the decision module and the monostable multivibrator; the decision module performs real-time judgment on the input SW3: whether SW3=1 for a long time (100ms) (SW has no overshoot), and outputs the judgment result to the output module; the output module is controlled by the monostable multivibrator and outputs the decision module at regular intervals.

[0065] Figure 9 This is the clock source module circuit of the present invention. In the figure, INV11 is the second inverter, INV12 is the third inverter, INV13 is the fourth inverter, INV14 is the fifth inverter, C11 is the third capacitor, C12 is the fourth capacitor, C13 is the fifth capacitor, and CLKOUT is the clock signal. The clock source module circuit used in the present invention has a traditional ring oscillator architecture. The third capacitor C11, the fourth capacitor C12, and the fifth capacitor C13 are mainly used to generate delay.

[0066] The novel structure adopted in this invention is simple, significantly reduces chip area and power consumption, is easy to implement, and improves detection reliability.

[0067] Example 4 A GaN-based Micro-LED display driving system includes a DC-DC chip and a GaN-based Micro-LED array, wherein the output terminal of the DC-DC chip is connected to the power supply terminal of the GaN-based Micro-LED array; The DCDC chip internally includes a lower switching transistor NM1, a SW node descent rate detection module, a SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit. The input of the SW node descent rate detection module is connected to the switching node SW of the DC-DC chip, and the output of the SW node descent rate detection module is connected to the input of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and connected to the lower transistor drive control signal VCN; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and connected to the gate of the lower switching transistor NM1. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, and the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3; the first control terminal of the substrate potential switching unit receives the first control signal Vctrl1, and the second control terminal of the substrate potential switching unit receives the second control signal Vctrl2.

[0068] Specifically, this embodiment uses a DC-DC converter from Embodiment 3 to provide stable driving voltage and current for the Micro-LED pixel array.

[0069] To address the stringent requirements of high refresh rate driving for Micro-LEDs in terms of power supply transient stability, this embodiment integrates a DC-DC chip that controls the output node descent rate of a high-performance voltage converter with an InGaN (indium gallium nitride) based Micro-LED array with a main wavelength above 560nm. This integration is achieved through a W2W (wafer-to-wafer) eutectic metal bonding process, resulting in a wafer-level heterogeneous integration and forming an integrated display driving system. The Micro-LED array is fabricated using mature processes such as epitaxial growth, wafer bonding, epitaxial layer lift-off, pixel etching, and sidewall passivation.

[0070] When the system is working, the DC-DC chip provides a precise driving voltage for the Micro-LED array and controls the output node fall rate circuit in the high-performance voltage converter to operate synchronously: the SW node fall rate detection module collects the voltage change rate of the switching node SW in real time, and the SW node fall rate control module outputs the first control signal Vctrl1 and the second control signal Vctrl2 according to the detection results, driving the substrate potential switching unit to dynamically adjust the substrate potential of the third PMOS transistor PM3, and control the conduction speed of the lower switching transistor NM1 to achieve adaptive adjustment of the switching node fall rate.

[0071] Synchronous operation of the circuit controlling the output node drop rate in the high-performance voltage converter can effectively suppress transient current spikes during the rapid switching process of Micro-LED pixels, reduce the impact of electromagnetic interference on the stability of the drive current, maintain the consistency of the drive voltage at high refresh rates above 1000Hz, and improve uneven screen brightness and flickering. At the same time, the optimized switching rate can reduce drive losses, adapt to power-sensitive scenarios such as AR (Augmented Reality) displays, and meet the drive requirements of different brightness levels.

[0072] The above content provides a further detailed description of the present invention. It should not be construed that the specific embodiments of the present invention are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered as falling within the protection scope of the present invention as determined by the submitted content.

Claims

1. A circuit for controlling the descent rate of the output node in a high-performance voltage converter, characterized in that, It includes a SW node descent rate detection module, a SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit; The input terminal of the SW node descent rate detection module is connected to the switching node SW of the voltage converter, and the output terminal of the SW node descent rate detection module is connected to the input terminal of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and used to receive the lower transistor drive control signal VCN; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and used to connect to the gate of the lower switching transistor NM1 of the voltage converter. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3, and the second power supply potential VDD2 is higher than the first power supply potential VDD. The first control terminal of the substrate potential switching unit receives the first control signal Vctrl1 and is used to control the connection and disconnection between the first power supply terminal and the output terminal. The second control terminal of the substrate potential switching unit receives the second control signal Vctrl2 and is used to control the connection and disconnection between the second power supply terminal and the output terminal.

2. The circuit for controlling the descent rate of the output node in a high-performance voltage converter according to claim 1, characterized in that, The SW node descent rate detection module includes a second capacitor C2, a third resistor R3, a fourth resistor R4, and a buffer. One end of the second capacitor C2 is the input terminal of the SW node descent rate detection module, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 respectively to form a voltage divider node SW2; The other end of the third resistor R3 is connected to the first power supply potential VDD, and the other end of the fourth resistor R4 is grounded. The resistance values ​​of the third resistor R3 and the fourth resistor R4 are equal. The voltage divider node SW2 is connected to the input terminal of the buffer, and the output terminal of the buffer is the output terminal of the SW node descent rate detection module, which outputs the second switch node SW3 signal.

3. The circuit for controlling the descent rate of the output node in a high-performance voltage converter according to claim 1, characterized in that, The SW node descent rate control module includes a D flip-flop DFF1, a first inverter INV1, and a timing detection module. The data input terminal D of the D flip-flop DFF1 is connected to a high potential. The clock terminal Clk of the D flip-flop DFF1 is the input terminal of the SW node descent rate control module. The reset terminal Reset of the D flip-flop DFF1 is connected to the output terminal of the timing detection module and receives the reset signal Rst. The positive output terminal Q of the D flip-flop DFF1 outputs the first control signal Vctrl1. The positive output terminal Q of the D flip-flop DFF1 is connected to the input terminal of the first inverter INV1. The output terminal of the first inverter INV1 outputs the second control signal Vctrl2. The input of the timing detection module is connected to the output of the SW node descent rate detection module; The timing detection module includes a clock source, a timing circuit, a decision module, a monostable multivibrator, and an output module; The clock source outputs a clock signal CLKOUT and connects to the input of the timing circuit. The first output of the timing circuit is connected to the control terminal of the decision module, and the second output of the timing circuit is connected to the input of the monostable multivibrator. The input terminal of the decision module is the input terminal of the timing detection module, and the output terminal of the decision module is connected to the input terminal of the output module. The output terminal of the monostable multivibrator is connected to the control terminal of the output module, and the output terminal of the output module is the output terminal of the timing detection module, which outputs the reset signal Rst.

4. The circuit for controlling the descent rate of the output node in a high-performance voltage converter according to claim 3, characterized in that, The clock source is a ring oscillator, including a second inverter INV11, a third inverter INV12, a fourth inverter INV13, a fifth inverter INV14, a third capacitor C11, a fourth capacitor C12, and a fifth capacitor C13. The second inverter INV11, the third inverter INV12, and the fourth inverter INV13 are connected in series to form a closed loop. The output terminal of the second inverter INV11 is connected to one end of the third capacitor C11, the output terminal of the third inverter INV12 is connected to one end of the fourth capacitor C12, and the output terminal of the fourth inverter INV13 is connected to one end of the fifth capacitor C13. The other ends of the third capacitor C11, the fourth capacitor C12, and the fifth capacitor C13 are all grounded; The output of the fourth inverter INV13 is connected to the input of the fifth inverter INV14, and the output of the fifth inverter INV14 is the output of the clock source.

5. The circuit for controlling the descent rate of the output node in a high-performance voltage converter according to claim 1, characterized in that, The substrate potential switching unit includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5; The source of the fourth PMOS transistor PM4 is the first power supply terminal, and the source of the fifth PMOS transistor PM5 is the second power supply terminal. The drain of the fourth PMOS transistor PM4 is connected to the drain of the fifth PMOS transistor PM5 and serves as the output terminal. The gate of the fourth PMOS transistor PM4 is the first control terminal, and the gate of the fifth PMOS transistor PM5 is the second control terminal.

6. A control method for a circuit controlling the descent rate of an output node in a high-performance voltage converter, using the circuit for controlling the descent rate of an output node in a high-performance voltage converter as described in any one of claims 1-5, characterized in that, Includes the following steps: The voltage signal of the switching node SW of the voltage converter is acquired to generate a rate detection signal; Based on the rate detection signal, output the first control signal Vctrl1 and the second control signal Vctrl2; The first control signal Vctrl1 and the second control signal Vctrl2 are used to select the first power supply potential VDD or the second power supply potential VDD2 to be connected to the substrate terminal sub of the third PMOS transistor PM3. The second power supply potential VDD2 is higher than the first power supply potential VDD. By changing the substrate potential of the third PMOS transistor PM3, the driving capability of the third PMOS transistor PM3 is adjusted, the conduction speed of the switching transistor NM1 under the voltage converter is controlled, and the descent rate of the switching node SW is adjusted.

7. A DC-DC converter, characterized in that, Includes a DC-DC chip, inductor L0, output capacitor C0, first voltage divider resistor R1, and second voltage divider resistor R2; The DC-DC chip integrates an upper switch PM1, a lower switch NM1, a logic control module, an upper switch driver circuit, a lower switch driver circuit, and the circuit for controlling the descent rate of the output node in the high-performance voltage converter as described in any one of claims 1-5. The drain of the upper switch PM1 is connected to the input voltage Vin, and the source of the upper switch PM1 and the drain of the lower switch NM1 are connected together to form a switching node SW; the source of the lower switch NM1 is grounded. The switching node SW is connected to one end of the inductor L0, and the other end of the inductor L0 is the output terminal Vout; the output capacitor C0 is connected between the output terminal Vout and ground; the first voltage divider resistor R1 and the second voltage divider resistor R2 are connected in series between the output terminal Vout and ground, and the voltage divider node outputs a feedback voltage Vfb and is connected to the feedback input terminal of the DC-DC chip; The logic control module is connected to the gate of the upper switching transistor PM1 via the upper transistor driving circuit, and the logic control module is connected to the gate of the lower switching transistor NM1 via the lower transistor driving circuit. The lower transistor drive circuit includes a third PMOS transistor PM3 and a third NMOS transistor NM3; the source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and connected to the lower transistor drive control signal VCN output by the logic control module; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and connected to the gate of the lower switching transistor NM1; The input terminal of the SW node descent rate detection module is connected to the switch node SW, and the output terminal of the SW node descent rate detection module is connected to the input terminal of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3, and the second power supply potential VDD2 is higher than the first power supply potential VDD. The first control terminal of the substrate potential switching unit receives the first control signal Vctrl1 and is used to control the connection and disconnection between the first power supply terminal and the output terminal. The second control terminal of the substrate potential switching unit receives the second control signal Vctrl2 and is used to control the connection and disconnection between the second power supply terminal and the output terminal.

8. A DC-DC converter according to claim 7, characterized in that, The DC-DC chip also integrates an error amplifier EA, a comparator COMP, a soft-start module, and a clock. The non-inverting input of the error amplifier EA is connected to the reference voltage Vref, the inverting input of the error amplifier EA is connected to the feedback voltage Vfb, and the output of the error amplifier EA is connected to the inverting input of the comparator COMP. The non-inverting input of the comparator COMP is connected to the ramp signal Ramp, and the inverting input of the comparator COMP is connected to the output of the soft-start module; the output of the comparator COMP is connected to the input of the logic control module; the output of the clock is connected to the clock input of the logic control module. The first output terminal of the logic control module outputs the upper transistor drive control signal VCP and is connected to the input terminal of the upper transistor drive circuit. The output terminal of the upper transistor drive circuit is connected to the gate of the upper switching transistor PM1. The second output terminal of the logic control module outputs the lower transistor drive control signal VCN and is connected to the input terminal of the lower transistor drive circuit. The upper transistor driving circuit includes a second PMOS transistor PM2 and a second NMOS transistor NM2; the source of the second PMOS transistor PM2 is connected to the first power supply potential VDD, and the source of the second NMOS transistor NM2 is grounded; the gate of the second PMOS transistor PM2 and the gate of the second NMOS transistor NM2 are connected together and serve as the input terminal of the upper transistor driving circuit; the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2 are connected together and serve as the output terminal of the upper transistor driving circuit.

9. A DC-DC converter according to claim 7, characterized in that, The SW node descent rate detection module includes a second capacitor C2, a third resistor R3, a fourth resistor R4, and a buffer. One end of the second capacitor C2 is the input terminal of the SW node descent rate detection module, and the other end of the second capacitor C2 is connected to one end of the third resistor R3 and one end of the fourth resistor R4 respectively to form a voltage divider node SW2; The other end of the third resistor R3 is connected to the first power supply potential VDD, and the other end of the fourth resistor R4 is grounded; the voltage divider node SW2 is connected to the input terminal of the buffer, and the output terminal of the buffer is the output terminal of the SW node descent rate detection module; The substrate potential switching unit includes a fourth PMOS transistor PM4 and a fifth PMOS transistor PM5; the source of the fourth PMOS transistor PM4 is the first power supply terminal, and the source of the fifth PMOS transistor PM5 is the second power supply terminal; the drain of the fourth PMOS transistor PM4 and the drain of the fifth PMOS transistor PM5 are connected together and serve as the output terminal; the gate of the fourth PMOS transistor PM4 is the first control terminal, and the gate of the fifth PMOS transistor PM5 is the second control terminal.

10. A GaN-based Micro-LED display driving system, characterized in that, It includes a DC-DC chip and a GaN-based Micro-LED array, wherein the output terminal of the DC-DC chip is connected to the power supply terminal of the GaN-based Micro-LED array; The DC-DC chip internally includes a lower switching transistor NM1, a SW node descent rate detection module, a SW node descent rate control module, a third PMOS transistor PM3, a third NMOS transistor NM3, and a substrate potential switching unit. The input terminal of the SW node descent rate detection module is connected to the switching node SW of the DC-DC chip, and the output terminal of the SW node descent rate detection module is connected to the input terminal of the SW node descent rate control module; the SW node descent rate control module outputs a first control signal Vctrl1 and a second control signal Vctrl2. The source of the third PMOS transistor PM3 is connected to the first power supply potential VDD, and the source of the third NMOS transistor NM3 is grounded; the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are connected together and connected to the lower transistor drive control signal VCN; the drain of the third PMOS transistor PM3 and the drain of the third NMOS transistor NM3 are connected together and connected to the gate of the lower switching transistor NM1. The first power supply terminal of the substrate potential switching unit is connected to the first power supply potential VDD, the second power supply terminal of the substrate potential switching unit is connected to the second power supply potential VDD2, the output terminal of the substrate potential switching unit is connected to the substrate terminal sub of the third PMOS transistor PM3, and the second power supply potential VDD2 is higher than the first power supply potential VDD; the first control terminal of the substrate potential switching unit receives the first control signal Vctrl1, and the second control terminal of the substrate potential switching unit receives the second control signal Vctrl2.

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