A driving chip power supply circuit

Abstract

This invention provides a power supply circuit for a driver chip, including a first power transistor, a control chip, and a gate driver chip. The gate driver chip includes a second power transistor, the drain of which is connected to the source of the first power transistor. A driver circuit receives a control signal output by the control chip and converts it into a drive signal, which is output to the gate of the second power transistor to control the on / off state of the second power transistor, thereby controlling the on / off state of the first power transistor. A current sampling circuit is used to output a sampling signal corresponding to the operating current of the first power transistor during the conduction period of the second power transistor. A power management circuit has a first input terminal connected to the source of the first power transistor, a second input terminal connected to the control chip, and a third input terminal optionally connected to an external power supply port. It is used to select one of the source voltage, the voltage of the control signal, and the external power supply voltage as the input voltage of the power management circuit based on the voltage states of the first input terminal, the second input terminal, and the third input terminal, and output the operating voltage.

Description

Technical Field

[0001] This invention relates to the field of power control technology, and in particular to a power supply circuit for a driver chip. Background Technology

[0002] Switching power supplies are widely used in electronic devices such as power adapters, chargers, and industrial power supplies. Their control chips control the switching on and off of power transistors and perform functions such as drive control and current detection. To ensure stable operation of the control chip, existing switching power supplies typically provide it with a dedicated power supply pin, along with auxiliary windings, high-voltage start-up circuits, and other external power supply circuits. While this power supply method meets the control chip's power requirements, it increases the number of chip pins and external power supply circuits, raising chip packaging costs and circuit design complexity, and limiting the miniaturization and high integration of the control chip.

[0003] Furthermore, for switching power supplies using depletion-mode power transistors (DMPTs), during the DMPT's conduction period, its source potential decreases, and the control chip can no longer obtain a stable power supply through the DMPT's source. However, the internal drive circuitry, current sampling circuitry, and other functional circuits of the control chip still need to operate continuously to complete drive control and current detection. Existing technologies typically use dedicated power supply pins to maintain the normal operation of the control chip. While this ensures continuous power supply to the control chip, it further increases the number of chip pins and the complexity of peripheral circuits, making it difficult to simultaneously meet the requirements of power supply continuity, integration, and low-cost design for the control chip. Summary of the Invention

[0004] The purpose of this invention is to provide a power supply circuit for a driver chip, so as to solve the technical problem that the driver chip relies on independent power supply pins to achieve continuous power supply in the prior art, which leads to reduced chip integration and increased complexity of peripheral circuits.

[0005] According to one aspect of the present invention, a power supply circuit for a driver chip is provided, comprising a first power transistor M1, a control chip, and a gate driver chip. The control chip is used to output a control signal PWM. The drain of the first power transistor M1 is connected to an input power supply, its gate is grounded, and its source is connected to the gate driver chip. The gate driver chip comprises: The drain of the second power transistor M2 is connected to the source of the first power transistor M1, and the source is grounded. The driving circuit has its input terminal connected to the control chip and its output terminal connected to the gate of the second power transistor M2. It is used to receive the control signal PWM output by the control chip and convert it into a driving signal to be output to the gate of the second power transistor M2, so as to control the on and off of the second power transistor M2, thereby controlling the on and off of the first power transistor M1. A current sampling circuit has its first input terminal connected to the source of the first power transistor M1, its control terminal connected to the output terminal of the drive circuit, and its output terminal connected to the control chip. It is used to output a sampling signal corresponding to the operating current of the first power transistor M1 during the conduction period of the second power transistor M2. The power management circuit has a first input terminal connected to the source of the first power transistor M1 to receive the source voltage VS, a second input terminal connected to the control chip to receive the control signal PWM, and a third input terminal optionally connected to an external power supply port to receive the external power supply voltage VCC. The power management circuit is used to select one of the source voltage VS, the voltage of the control signal PWM, and the external power supply voltage VCC as the input voltage of the power management circuit according to the voltage state of the first input terminal, the second input terminal, and the third input terminal, and outputs the operating voltage VDD.

[0006] Optionally, the first power transistor M1 is a depletion-mode power transistor, the second power transistor M2 is an NMOS power transistor, the first power transistor M1 and the second power transistor M2 are cascaded, and the second power transistor M2 is integrated inside the gate driver chip.

[0007] Optionally, the power management circuit includes a power switching module and a voltage regulator module; The power supply switching module includes a first diode D1 and a second diode D2. The input terminal of the first diode D1 is connected to the source of the first power transistor M1, and the input terminal of the second diode D2 is connected to the output terminal of the control chip. The output terminals of both the first diode D1 and the second diode D2 are connected to the voltage regulator module. The voltage regulator module is used to regulate the voltage output by the power supply switching module and output a stable working power supply to the drive circuit and the current sampling circuit.

[0008] Optionally, the voltage regulator module includes a first resistor R1, a third diode D3, and a third power transistor M3; The drain of the third power transistor M3 is connected to the output terminals of both the first diode D1 and the second diode D2. The gate is connected to the drain of the third power transistor M3 through the first resistor R1. The source outputs the operating voltage VDD. The first terminal of the third diode D3 is connected to the gate of the third power transistor M3, and the second terminal is grounded.

[0009] Optionally, the driving circuit includes a comparison module and a driving output module; The input terminal of the comparison module is connected to the output terminal of the control chip, and the output terminal of the comparison module is connected to the first input terminal of the drive output module. The second input terminal of the drive output module is connected to the output terminal of the power management circuit, and the output terminal of the drive output module is connected to the gate of the second power transistor M2.

[0010] Optionally, the current sampling circuit includes a fourth power transistor M4 and a sampling module; The first input terminal of the sampling module serves as the first input terminal of the current sampling circuit and is connected to the source of the first power transistor M1. The gate of the fourth power transistor M4 serves as the control terminal of the current sampling circuit and is connected to the output terminal of the drive output module. The drain of the fourth power transistor M4 is connected to the second input terminal of the sampling module, and the source is grounded.

[0011] Optionally, the sampling module includes a follower unit and a mirror unit; The follower unit includes a first comparator AMP1 and a fifth power transistor M5. The first input terminal of the first comparator AMP1 is connected to the source of the first power transistor M1, the second input terminal is connected to the drain of the fourth power transistor M4, and the output terminal is connected to the gate of the fifth power transistor M5. The source of the fifth power transistor M5 is connected to the drain of the fourth power transistor M4, and the drain of the fifth power transistor M5 is connected to the mirror unit.

[0012] Optionally, the mirror unit includes a sixth power transistor M6 and a seventh power transistor M7; The sources of the sixth power transistor M6 and the seventh power transistor M7 are both connected to the output terminal of the power management circuit. The gates of the sixth power transistor M6 and the seventh power transistor M7 are connected and jointly connected to the drain of the fifth power transistor M5. The drain of the sixth power transistor M6 is connected to the drain of the fifth power transistor M5. The drain of the seventh power transistor M7 serves as the output terminal of the current sampling circuit, outputting the sampling signal CS.

[0013] Optionally, the power supply switching module further includes: The fourth diode D4 has its input terminal connected to the external power supply voltage VCC and its output terminal connected to the drain of the third power transistor M3.

[0014] Optionally, the gate driver chip further includes: The first capacitor C1 has its first end connected to the output terminal of the power management circuit and its second end grounded.

[0015] According to the present invention, by setting up a power management circuit, the power management circuit switches between power supply to the source of the first power transistor and power supply to the control chip according to the conduction state of the first power transistor, so as to provide working power to the drive circuit and the current sampling circuit. This enables the drive chip to maintain a stable power supply during the conduction and turn-off of the first power transistor, avoiding power interruption of the drive chip due to changes in the source voltage of the first power transistor. This ensures the continuous and stable operation of the drive circuit and the current sampling circuit, improves the continuity and reliability of the drive control process, and eliminates the need for an additional independent power supply pin, reducing the complexity of chip design and improving chip integration.

[0016] Furthermore, by setting up a power supply switching module and a voltage regulation module, smooth switching between different power supply paths is achieved, and the operating power supply is regulated to ensure the power supply stability of the drive circuit and the current sampling circuit. Simultaneously, by using the drive circuit in conjunction with the current sampling circuit, a current mirror sampling structure is established using a follower unit and a mirror unit. This allows the sampling branch to output a sampling signal corresponding to the operating current of the first power transistor while maintaining its operating state. This provides the control chip with accurate current detection data, thereby achieving precise control of the operating current of the first power transistor, improving drive control accuracy, system stability, and overall operational reliability.

[0017] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, the preferred embodiments of the present invention are described in detail below. Attached Figure Description

[0018] Figure 1 A circuit topology diagram of a driver chip power supply circuit according to an embodiment of the present invention is shown; Figure 2 A circuit topology diagram of a gate driver chip according to an embodiment of the present invention is shown; Figure 3 A circuit topology diagram of a power management circuit according to an embodiment of the present invention is shown; Figure 4 A circuit topology diagram of a driving circuit according to an embodiment of the present invention is shown; Figure 5 A circuit topology diagram of a sampling module according to an embodiment of the present invention is shown. Detailed Implementation

[0019] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0020] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0021] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0022] Figure 1 A circuit topology diagram of a driver chip power supply circuit according to an embodiment of the present invention is shown. Figure 1 As shown, the power supply circuit of the driver chip includes a first power transistor M1, a control chip 10, a gate driver chip 20, and a transformer. The control chip 10 is interconnected with the gate driver chip 20. The control chip 10 outputs a control signal PWM to the gate driver chip 20 and simultaneously receives the sampling signal CS output by the gate driver chip 20 to control the operating state of the first power transistor M1 and detect its current. The control chip 10 is also connected to a feedback signal VFB input terminal, an external power supply voltage VCC input terminal, and a ground terminal. The gate driver chip 20 has a ground terminal and is connected to the first power transistor M1. The drain of the first power transistor M1 is connected to the primary winding of the transformer, the gate is grounded, and the source is connected to the gate driver chip 20. The voltage node corresponding to this source is denoted as the source voltage VS. The primary winding of the transformer is connected to the input power supply VIN. When the first power transistor M1 is turned on, the input power supply VIN provides electrical energy to the primary winding of the transformer and forms a working current in the primary winding. When the first power transistor M1 is turned off, the energy stored in the primary winding is released to the secondary side to realize the conversion of electrical energy.

[0023] Figure 2A circuit topology diagram of a gate driver chip 20 according to an embodiment of the present invention is shown. Figure 2 As shown, the gate driver chip 20 includes a second power transistor M2, a driver circuit 21, a current sampling circuit 22, and a power management circuit 23. The drain of the second power transistor M2 is connected to the source of the first power transistor M1, and the source is grounded. The input terminal of the driver circuit 21 is connected to the control chip 10, and the output terminal is connected to the gate of the second power transistor M2. It receives the control signal PWM output by the control chip 10 and converts it into a drive signal, which is then output to the gate of the second power transistor M2 to control the on / off state of the second power transistor M2, thereby controlling the on / off state of the first power transistor M1. The first input terminal of the current sampling circuit 22 is connected to the source of the first power transistor M1, the second input terminal is connected to the output terminal of the driver circuit 21, and the output terminal is connected to the control chip 10. It outputs a sampling signal corresponding to the operating current of the first power transistor M1 during the conduction period of the second power transistor M2. The first input terminal of the power management circuit 23 is connected to the source of the first power transistor M1 to receive the source voltage VS. The second input terminal is connected to the control chip 10 to receive the voltage of the control signal PWM. The third input terminal is optionally connected to the external power supply port to receive the external power supply voltage VCC. The power management circuit 23 outputs the operating voltage VDD. The power management circuit 23 selects one of the source voltage VS, the voltage of the control signal PWM, and the external power supply voltage VCC as the input voltage of the power management circuit 23 according to the voltage state of the first input terminal, the second input terminal, and the third input terminal, and outputs a stable operating voltage VDD.

[0024] In this embodiment, the first power transistor M1 is a depletion-mode power transistor, and the second power transistor M2 is an NMOS power transistor. The first power transistor M1 and the second power transistor M2 are cascaded, with the second power transistor M2 integrated within the gate driver chip 20. The operating state of the first power transistor M1 is controlled by controlling the on / off state of the second power transistor M2. Specifically, the control chip 10 outputs a control signal PWM to the gate driver chip 20. The drive circuit 21 within the gate driver chip 20 receives the control signal PWM and converts it into a drive signal GATE, which is then output to the gate of the second power transistor M2. When the control signal PWM is high, the second power transistor M2 is turned on, and the first power transistor M1 is simultaneously turned on; when the control signal PWM is low, the second power transistor M2 is turned off, and the first power transistor M1 is simultaneously turned off, thereby controlling the on / off state of the first power transistor M1.

[0025] Meanwhile, the current sampling circuit 22 monitors the operating state of the first power transistor M1 in real time. When the second power transistor M2 is turned on, the operating current flowing through the first power transistor M1 is replicated by the current sampling circuit 22, and a corresponding sampling signal CS is generated according to a preset ratio and output to the control chip 10. The control chip 10 obtains the operating current information of the first power transistor M1 based on the sampling signal CS for current detection and subsequent control, thereby realizing closed-loop control of the operating process of the first power transistor M1.

[0026] In addition, the power management circuit 23 in the gate driver chip 20 is connected to the source voltage VS, the voltage of the control signal PWM and the external power supply voltage VCC respectively. According to the voltage state of the three, one of them is selected as the input voltage of the power management circuit 23 and outputs a stable operating voltage VDD to provide the operating voltage VDD to the drive circuit 21 and the current sampling circuit 22.

[0027] It should be noted that the third input terminal in this invention is an optional external power supply port for connecting to an external independent power supply. When the third input terminal is connected to an external power supply, the power management circuit preferentially selects the external power supply voltage VCC as the working power input and outputs the working voltage VDD because the external power supply voltage VCC has high stability. When the third input terminal is not connected to an external power supply, the power management circuit selects one of the source voltage VS and the control signal PWM voltage as the working power input based on the voltage state of the source voltage VS and the control signal PWM voltage, and outputs the working voltage VDD. Specifically, when the first power transistor M1 is in different conduction states, the potential of the voltage node VS changes accordingly. The power management circuit 23 switches between the source voltage VS power supply and the control signal PWM voltage power supply according to the power supply state of the source of the first power transistor M1, so that the drive circuit 21 and the current sampling circuit 22 can obtain a stable working power supply throughout the entire operation, thereby ensuring that drive control and current sampling can continue without the need for additional independent power supply pins.

[0028] According to the above embodiment, by setting up a power management circuit 23, and by switching between power supply to the source of the first power transistor and power supply to the control chip 10 according to the conduction state of the first power transistor, the power management circuit 23 provides working power to the drive circuit 21 and the current sampling circuit 22, so that the drive chip can maintain a stable power supply during the conduction and turn-off of the first power transistor, avoiding power interruption of the drive chip due to changes in the source voltage of the first power transistor, thereby ensuring the continuous and stable operation of the drive circuit 21 and the current sampling circuit 22, improving the continuity and reliability of the drive control process, and eliminating the need to add an independent power supply pin, reducing the complexity of chip design and improving chip integration.

[0029] In one embodiment, reference Figure 1 The power supply circuit for the driver chip also includes a second resistor R2. The first end of the second resistor R2 is connected to the output of the current sampling circuit 22, and the second end is grounded.

[0030] In this embodiment, the sampling current output by the current sampling circuit 22 flows through the second resistor R2, forming a sampling voltage corresponding to the sampling current across the second resistor R2, and is output to the control chip 10 for current detection. By setting the second resistor R2, the sampling current output by the current sampling circuit 22 can be converted into a voltage signal that is easy for the control chip 10 to detect, thereby providing a detection basis for the control chip 10 to realize closed-loop control of the operating current of the first power transistor, while ensuring the stability and detection accuracy of the sampling process.

[0031] Figure 3 A circuit topology diagram of a power management circuit 23 according to an embodiment of the present invention is shown. Figure 3 As shown, the power management circuit 23 includes a power switching module 231 and a voltage regulator module 232. The power switching module 231 includes a first diode D1 and a second diode D2. The input terminal of the first diode D1 is connected to the source of the first power transistor M1, and the input terminal of the second diode D2 is connected to the output terminal of the control chip 10. The output terminals of both the first diode D1 and the second diode D2 are connected to the voltage regulator module 232. The voltage regulator module 232 is used to regulate the voltage output by the power switching module 231 and output a stable operating power supply to the drive circuit 21 and the current sampling circuit 22.

[0032] In this embodiment, during the turn-on and turn-off process of the first power transistor M1, its source voltage changes with the operating state, so the power supply provided by the source is not always stable. The power supply switching module 231 uses the first diode D1 and the second diode D2 to correspond to the power supply path of the source of the first power transistor M1 and the power supply path of the control chip 10, respectively, to automatically establish corresponding power supply paths at different operating stages. This allows the power supply to switch continuously according to the power supply state without the need for additional control circuitry to participate in the switching process. This avoids mutual interference between different power supply paths and ensures the reliability of the power supply switching process. After the power supply switching is completed, the voltage regulator module 232 further regulates and buffers the input voltage to reduce voltage fluctuations generated during the power supply switching process, keeping the operating voltage VDD stable and continuously providing a stable operating power supply for the drive circuit 21 and the current sampling circuit 22. Since the drive circuit 21 and the current sampling circuit 22 always operate in a stable power supply environment, they can maintain normal operation throughout the entire process of the first power transistor M1 being turned on and off. This ensures that the drive circuit 21 can continuously output the drive signal and the current sampling circuit 22 can continuously output the sampling signal CS, thus realizing continuous drive control and current sampling throughout the entire working process of the first power transistor M1.

[0033] In one embodiment, reference Figure 3 The power supply switching module 231 also includes a fourth diode D4. The input terminal of the fourth diode D4 is connected to the external power supply voltage VCC, and the output terminal is connected to the drain of the third power transistor M3.

[0034] In this embodiment, the external power supply voltage VCC is an optional external power supply terminal. When an external power supply voltage is connected, the fourth diode D4 is used to establish a power supply path from the external power supply to the voltage regulator module 232, enabling the voltage regulator module 232 to obtain operating power through the external power supply. When the external power supply voltage VCC is not set, the driver chip power supply circuit can still achieve normal power supply through the first diode D1 and the second diode D2, without affecting the normal operation of the circuit. Therefore, by setting the fourth diode D4, the connection of external power supply can be flexibly selected according to different application scenarios, improving the applicability and compatibility of the driver chip power supply circuit.

[0035] In one embodiment, reference Figure 3 The voltage regulator module 232 includes a first resistor R1, a third diode D3, and a third power transistor M3. The drain of the third power transistor M3 is connected to the output terminals of both the first diode D1 and the second diode D2, and its gate is connected to the drain of the third power transistor M3 through the first resistor R1. The source outputs the operating voltage VDD. The first terminal of the third diode D3 is connected to the gate of the third power transistor M3, and the second terminal is grounded.

[0036] In this embodiment, the third power transistor M3 serves as the output regulating device of the voltage regulator module 232. Under the bias of the first resistor R1, it establishes a stable conduction state, allowing the voltage output by the power supply switching module 231 to form the operating voltage VDD after being regulated by the third power transistor M3. When the input voltage changes, the third power transistor M3 can automatically adjust its conduction level according to the gate bias state, keeping the operating voltage VDD relatively stable and reducing the impact of input voltage changes on the drive circuit 21 and the current sampling circuit 22. The third diode D3 is a Zener diode, connected between the gate of the third power transistor M3 and ground, used to limit the range of gate potential changes of the third power transistor M3. When overvoltage or voltage fluctuation occurs at the input terminal, the third diode D3 can clamp the gate voltage to prevent the third power transistor M3 from bearing excessive gate-source voltage, improve the anti-interference capability and operational reliability of the voltage regulator module 232, and ensure that the operating voltage VDD remains stable during power supply switching and voltage fluctuations.

[0037] In one embodiment, reference Figure 2 The gate driver chip 20 also includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the output terminal of the power management circuit 23, and the second terminal is grounded.

[0038] In this embodiment, the first capacitor C1 is used to store and filter the working voltage VDD output by the power management circuit 23. During the power supply switching process, the stored electrical energy is released to maintain the stability of the working voltage VDD, reduce the impact of voltage fluctuations on the drive circuit 21 and the current sampling circuit 22, and thus ensure that the gate drive chip 20 continues to work stably during the first power transistor's turn-on and turn-off processes.

[0039] Figure 4 A circuit topology diagram of a drive circuit 21 according to an embodiment of the present invention is shown. Figure 4 As shown, the driving circuit 21 includes a comparison module 211 and a driving output module 212. The input terminal of the comparison module 211 is connected to the output terminal of the control chip 10, and the output terminal of the comparison module 211 is connected to the first input terminal of the driving output module 212. The second input terminal of the driving output module 212 is connected to the output terminal of the power management circuit 23, and the output terminal of the driving output module 212 is connected to the gate of the second power transistor M2.

[0040] In this embodiment, the comparison module 211 is used to perform level detection on the control signal PWM output by the control chip 10. When the control signal PWM reaches a preset turn-on threshold, the comparison module 211 outputs a turn-on signal; when the control signal is lower than a preset turn-off threshold, the comparison module 211 outputs a turn-off signal. Under the power supply of the operating voltage VDD, the drive output module 212 outputs a corresponding drive level to the gate of the second power transistor M2 according to the turn-on or turn-off signal output by the comparison module 211. When the drive output module 212 outputs a high level, the second power transistor M2 turns on, thereby turning on the first power transistor M1; when the drive output module 212 outputs a low level, the second power transistor M2 turns off, and the first power transistor M1 turns off accordingly. Since the drive output module 212 is directly powered by the operating voltage VDD output by the power management circuit 23, the drive output module 212 can always obtain a stable operating power supply during the turn-on and turn-off process of the first power transistor M1, thereby continuously providing a reliable gate drive signal to the second power transistor M2, ensuring that the turn-on and turn-off states of the first power transistor M1 can be switched stably.

[0041] In some embodiments, the comparison module 211 can be implemented using a comparator, a Schmitt trigger, a level detection circuit, or other circuits with level decision function, for detecting the level of the control signal output by the control chip 10. The drive output module 212 can be implemented using a push-pull drive circuit 21, a gate driver, a buffer drive circuit 21, or other circuits with drive output function, for outputting a corresponding drive level to the second power transistor M2 based on the output result of the comparison module 211. The above circuits are all commonly used circuit structures in the art, and those skilled in the art can select or make equivalent substitutions according to actual application requirements, which will not be described in detail here.

[0042] In one embodiment, reference Figure 2 The current sampling circuit 22 includes a fourth power transistor M4 and a sampling module 221. The first input terminal of the sampling module 221 serves as the first input terminal of the current sampling circuit 22 and is connected to the source of the first power transistor M1. The gate of the fourth power transistor M4 serves as the control terminal of the current sampling circuit 22 and is connected to the output terminal of the drive output module 212. The drain of the fourth power transistor M4 is connected to the second input terminal of the sampling module 221, and the voltage node corresponding to this drain is denoted as DRAIN. The source of the fourth power transistor M4 is grounded.

[0043] In this embodiment, the fourth power transistor M4 is an NMOS power transistor, and its gate is connected to the output terminal of the drive output module 212. Therefore, the fourth power transistor M4 and the second power transistor M2 receive the same drive signal and are synchronously turned on or off under the control of the drive output module 212. When the second power transistor M2 is turned on and the first power transistor M1 enters the on state, the fourth power transistor M4 is synchronously turned on, and a sampling path corresponding to the working state of the first power transistor M1 is established in the sampling module 221, enabling the sampling module 221 to detect the working current of the first power transistor M1. When the second power transistor M2 is turned off, the fourth power transistor M4 is synchronously turned off, and the sampling path is disconnected, thereby avoiding invalid sampling during the non-conducting period of the first power transistor M1. Since the fourth power transistor M4 and the first power transistor M1 always work synchronously, the sampling module 221 only performs current sampling during the actual conduction period of the first power transistor M1, so that the sampling timing is consistent with the conduction state of the first power transistor M1. This provides a working basis for the subsequent sampling module 221 to accurately generate the sampling signal CS, while reducing false sampling in non-working state and improving the accuracy and reliability of current detection.

[0044] Figure 5 A circuit topology diagram of a sampling module 221 according to an embodiment of the present invention is shown. Figure 5 As shown, the sampling module 221 includes a follower unit 2211 and a mirror unit 2212. The follower unit 2211 includes a first comparator AMP1 and a fifth power transistor M5. The first input terminal of the first comparator AMP1 is connected to the source of the first power transistor M1, the second input terminal is connected to the drain of the fourth power transistor M4, and the output terminal is connected to the gate of the fifth power transistor M5. The source of the fifth power transistor M5 is connected to the drain of the fourth power transistor M4, and the drain of the fifth power transistor M5 is connected to the mirror unit 2212.

[0045] In this embodiment, the first comparator AMP1 and the fifth power transistor M5 together constitute the voltage follower unit 2211. The first comparator AMP1 detects the potential difference between the source voltage of the first power transistor M1 and the drain voltage of the fourth power transistor M4 in real time, and continuously adjusts the conduction degree of the fifth power transistor M5 according to the difference, so that the drain voltage of the fourth power transistor M4 gradually approaches the source voltage of the first power transistor M1, thereby establishing a stable voltage follower relationship. Since the fourth power transistor M4 and the first power transistor M1 operate under similar drain-source voltage conditions, their conduction state can more accurately correspond to the actual operating state of the first power transistor M1, providing consistent operating conditions for the subsequent current replication by the mirror unit 2212. By adopting the voltage follower method to eliminate the influence of different node voltages on sampling accuracy, the sampling error caused by changes in operating state can be effectively reduced, so that the subsequent output sampling signal CS can more accurately reflect the operating current of the first power transistor M1, improving the accuracy and stability of current detection.

[0046] In one embodiment, reference Figure 5 The mirror unit 2212 includes a sixth power transistor M6 and a seventh power transistor M7. The sources of both the sixth power transistor M6 and the seventh power transistor M7 are connected to the output terminal of the power management circuit 23. The gates of the sixth power transistor M6 and the seventh power transistor M7 are connected and jointly connected to the drain of the fifth power transistor M5. The drain of the sixth power transistor M6 is connected to the drain of the fifth power transistor M5. The drain of the seventh power transistor M7 serves as the output terminal of the current sampling circuit 22, outputting the sampling signal CS.

[0047] In this embodiment, the sixth power transistor M6 and the seventh power transistor M7 together form a current mirror structure. Since the gates of the sixth power transistor M6 and the seventh power transistor M7 are connected and operate under the same gate-source voltage conditions, the operating current in the sixth power transistor M6 can be replicated to the seventh power transistor M7 according to a preset ratio, thereby forming a sampling signal CS at the output of the current sampling circuit 22 that corresponds to the operating current of the first power transistor M1. The mirror ratio can be set according to the device dimensions or parameters of the sixth power transistor M6 and the seventh power transistor M7, so that the output sampling signal CS maintains its correspondence with the operating current of the first power transistor M1 while meeting the detection range and input requirements of the control chip 10. Since the sampling signal CS is directly output by the mirror unit 2212, current detection can be achieved without connecting an additional sampling resistor in series in the main power circuit of the first power transistor M1. This reduces the main power circuit loss and minimizes the impact of the sampling circuit on the normal operation of the first power transistor M1, providing a stable and accurate sampling signal for the control chip 10 to achieve current closed-loop control.

[0048] Based on the above embodiments, analyzing only the case where no external power supply voltage VCC is set, the working principle of the power supply circuit of the driver chip of the present invention is as follows: The control chip 10 first outputs a control signal according to the working state of the switching power supply and sends the control signal to the gate driver chip 20. The gate driver chip 20 performs level detection on the control signal and generates a corresponding drive signal, which is output to the gate of the second power transistor M2. When the drive signal is an on signal, the second power transistor M2 is turned on, thereby driving the first power transistor M1 to turn on, and the primary winding of the transformer stores energy; when the drive signal becomes an off signal, the second power transistor M2 is turned off, and the first power transistor M1 is turned off accordingly, and the energy stored in the primary winding is released to the secondary side to realize the conversion of electrical energy. Since the source voltage VS of the first power transistor M1 changes during the turn-on and turn-off process, the power management circuit 23 automatically switches the power supply source between the source power supply path of the first power transistor M1 and the power supply path of the control chip 10 according to the change of the source voltage of the first power transistor M1, and outputs a stable operating voltage VDD to continuously provide operating power to the drive circuit 21 and the current sampling circuit 22, so that the gate drive chip 20 always maintains normal operation throughout the entire operation process.

[0049] Specifically, when the first power transistor M1 is turned on, its source voltage VS is pulled down to ground by the second power transistor M2. At this time, the control signal PWM is high, and the source voltage VS is less than the control signal PWM voltage, causing the second diode D2 to turn on and the first diode D1 to turn off. The power management circuit 23 selects the control signal PWM voltage output by the control chip 10 as the power supply voltage and outputs a stable operating voltage VDD. When the first power transistor M1 is turned off, the source voltage VS is the cutoff voltage of the first power transistor M1. At this time, the control signal PWM is low, and the source voltage VS is greater than the control signal PWM voltage, causing the first diode D1 to turn on and the second diode D2 to turn off. The power management circuit 23 selects the source voltage VS of the first power transistor M1 as the power supply voltage and outputs a stable operating voltage VDD.

[0050] Meanwhile, while driving the second power transistor M2 to turn on and off, the drive output module 212 also synchronously controls the fourth power transistor M4 to turn on and off, ensuring that the current sampling circuit 22 establishes a sampling path only during the period when the first power transistor M1 is on. After the sampling path is established, the follower unit 2211 adjusts the operating state of the fourth power transistor M4 in real time to maintain the same operating conditions as the first power transistor M1. The mirror unit 2212 further replicates the corresponding operating current according to a preset ratio and outputs a sampling signal CS to the control chip 10. The control chip 10 obtains the operating current information of the first power transistor M1 based on the sampling signal CS and adjusts the control signal output in the next cycle accordingly, realizing closed-loop control of the operating current of the first power transistor M1. Throughout the entire operation, the drive circuit 21, the current sampling circuit 22, and the power management circuit 23 cooperate with each other to achieve coordinated operation of drive control, power management, and current sampling without the need for additional power supply pins. This ensures that the drive chip continuously receives a stable power supply throughout the entire operating cycle of the first power transistor M1 and maintains the continuity of drive control and current detection.

[0051] According to the above embodiments, by setting up a power supply switching module 231 and a voltage regulator module 232, smooth switching between different power supply paths is achieved, and the working power supply is regulated to ensure the power supply stability of the drive circuit 21 and the current sampling circuit 22. Simultaneously, by using the drive circuit 21 in conjunction with the current sampling circuit 22, a current mirror sampling structure is established using the follower unit 2211 and the mirror unit 2212. This allows the sampling branch to output a sampling signal corresponding to the operating current of the first power transistor while maintaining its operating state. This provides accurate current detection data for the control chip 10, thereby achieving precise control of the operating current of the first power transistor and improving drive control accuracy, system stability, and overall operational reliability.

[0052] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A power supply circuit for a driver chip, characterized in that, The system includes a first power transistor M1, a control chip, and a gate driver chip. The control chip outputs a control signal PWM. The drain of the first power transistor M1 is connected to the input power supply, its gate is grounded, and its source is connected to the gate driver chip. The gate driver chip includes: The drain of the second power transistor M2 is connected to the source of the first power transistor M1, and the source is grounded. The driving circuit has its input terminal connected to the control chip and its output terminal connected to the gate of the second power transistor M2. It is used to receive the control signal PWM output by the control chip and convert it into a driving signal to be output to the gate of the second power transistor M2, so as to control the on and off of the second power transistor M2, thereby controlling the on and off of the first power transistor M1. A current sampling circuit has its first input terminal connected to the source of the first power transistor M1, its control terminal connected to the output terminal of the drive circuit, and its output terminal connected to the control chip. It is used to output a sampling signal corresponding to the operating current of the first power transistor M1 during the conduction period of the second power transistor M2. The power management circuit has a first input terminal connected to the source of the first power transistor M1 to receive the source voltage VS, a second input terminal connected to the control chip to receive the control signal PWM, and a third input terminal optionally connected to an external power supply port to receive the external power supply voltage VCC. The power management circuit is used to select one of the source voltage VS, the voltage of the control signal PWM, and the external power supply voltage VCC as the input voltage of the power management circuit according to the voltage state of the first input terminal, the second input terminal, and the third input terminal, and outputs the operating voltage VDD.

2. The power supply circuit for the driver chip according to claim 1, characterized in that, The first power transistor M1 is a depletion-mode power transistor, and the second power transistor M2 is an NMOS power transistor. The first power transistor M1 and the second power transistor M2 are cascaded together, and the second power transistor M2 is integrated inside the gate driver chip.

3. The power supply circuit for the driver chip according to claim 1, characterized in that, The power management circuit includes a power switching module and a voltage regulator module; The power supply switching module includes a first diode D1 and a second diode D2. The input terminal of the first diode D1 is connected to the source of the first power transistor M1, and the input terminal of the second diode D2 is connected to the output terminal of the control chip. The output terminals of both the first diode D1 and the second diode D2 are connected to the voltage regulator module. The voltage regulator module is used to regulate the voltage output by the power supply switching module and output a stable working power supply to the drive circuit and the current sampling circuit.

4. The power supply circuit for the driver chip according to claim 3, characterized in that, The voltage regulator module includes a first resistor R1, a third diode D3, and a third power transistor M3; The drain of the third power transistor M3 is connected to the output terminals of both the first diode D1 and the second diode D2. The gate is connected to the drain of the third power transistor M3 through the first resistor R1. The source outputs the operating voltage VDD. The first terminal of the third diode D3 is connected to the gate of the third power transistor M3, and the second terminal is grounded.

5. The power supply circuit for the driver chip according to claim 1, characterized in that, The driving circuit includes a comparison module and a driving output module; The input terminal of the comparison module is connected to the output terminal of the control chip, and the output terminal of the comparison module is connected to the first input terminal of the drive output module. The second input terminal of the drive output module is connected to the output terminal of the power management circuit, and the output terminal of the drive output module is connected to the gate of the second power transistor M2.

6. The power supply circuit for the driver chip according to claim 5, characterized in that, The current sampling circuit includes a fourth power transistor M4 and a sampling module; The first input terminal of the sampling module serves as the first input terminal of the current sampling circuit and is connected to the source of the first power transistor M1. The gate of the fourth power transistor M4 serves as the control terminal of the current sampling circuit and is connected to the output terminal of the drive output module. The drain of the fourth power transistor M4 is connected to the second input terminal of the sampling module, and the source is grounded.

7. The power supply circuit for the driver chip according to claim 6, characterized in that, The sampling module includes a follower unit and a mirror unit; The follower unit includes a first comparator AMP1 and a fifth power transistor M5. The first input terminal of the first comparator AMP1 is connected to the source of the first power transistor M1, the second input terminal is connected to the drain of the fourth power transistor M4, and the output terminal is connected to the gate of the fifth power transistor M5. The source of the fifth power transistor M5 is connected to the drain of the fourth power transistor M4, and the drain of the fifth power transistor M5 is connected to the mirror unit.

8. The power supply circuit for the driver chip according to claim 7, characterized in that, The mirror unit includes a sixth power transistor M6 and a seventh power transistor M7; The sources of the sixth power transistor M6 and the seventh power transistor M7 are both connected to the output terminal of the power management circuit. The gates of the sixth power transistor M6 and the seventh power transistor M7 are connected and jointly connected to the drain of the fifth power transistor M5. The drain of the sixth power transistor M6 is connected to the drain of the fifth power transistor M5. The drain of the seventh power transistor M7 serves as the output terminal of the current sampling circuit, outputting the sampling signal CS.

9. The power supply circuit for the driver chip according to claim 4, characterized in that, The power supply switching module also includes: The fourth diode D4 has its input terminal connected to the external power supply voltage VCC and its output terminal connected to the drain of the third power transistor M3.

10. The power supply circuit for the driver chip according to claim 1, characterized in that, The gate driving chip further includes: The first capacitor C1 has its first end connected to the output terminal of the power management circuit and its second end grounded.

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