Three-level inverter and current limiting protection method for three-level inverter

Abstract

This application provides a three-level inverter and a current-limiting protection method for the three-level inverter. The three-level inverter includes a controller and at least one bridge arm. Each bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the series connection terminals of the first and fourth switches and the neutral point of the three-level inverter. Alternatively, each bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series. The controller can control the main switch and the auxiliary switch to turn off when an overcurrent signal is detected to be active within a first time period, and control the auxiliary switch to turn on when the overcurrent signal fails. The controller can also maintain the state of the auxiliary switch on and the main switch off for a second time period if the overcurrent signal remains unchanged after the first time period. If the overcurrent signal remains unchanged after the second time period, the controller controls the main switch to turn on after the second time period ends.

Description

Technical Field

[0001] This application relates to the field of electronic power technology, and in particular to a three-level inverter and a current limiting protection method for a three-level inverter. Background Technology

[0002] Three-level inverters, as a crucial component of energy conversion, are widely used in power electronics applications. In practical applications, the output current of a three-level inverter can surge instantaneously due to overload (i.e., the output load exceeds its capacity), short circuit (such as phase-to-phase short circuit), or the moment the rectifier load closes. This surge can potentially burn out the switching transistors, or cause damage due to overheating or excessively high reverse peak voltage during shutdown. Therefore, current limiting is necessary for three-level inverters. In existing current limiting schemes, when the current exceeds the limit, the driving signal pulse for the switching transistor is pulled low, forcibly blocking the currently conducting transistor and putting the inverter into freewheeling mode, thus reducing the current. When the current drops below the limit, the driving signal pulse resumes operation, controlling the inverter to function normally. If the current of the three-level inverter exceeds the maximum set value again, the currently conducting switch will be blocked again. This process is repeated to reduce the current of the three-level inverter and protect it. However, repeatedly blocking the switch causes severe distortion of the output voltage and current of the three-level inverter and greatly increases the switching losses of the switch. Summary of the Invention

[0003] This application provides a three-level inverter and a current limiting protection method for the three-level inverter, which can improve the effective value of the output current of the bridge arm to a certain extent and reduce the speed of the bus voltage surge, thus solving the problem of inverter shutdown caused by DC bus overvoltage.

[0004] Firstly, this application provides a three-level inverter, which includes a controller and at least one bridge arm. Each of the at least one bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the series connection terminals of the first and fourth switches and the neutral point of the three-level inverter. Here, the series connection terminal of the first and fourth switches is the midpoint of the bridge arm, i.e., the output terminal of the bridge arm. The midpoint of each bridge arm can be connected to the neutral point of the inverter via a second and third switch connected in reverse series, i.e., the series connection terminals of the first and fourth switches are connected to the neutral point of the inverter via a second and third switch connected in reverse series. Here, the reverse series connection of the second and third switches can be achieved by having diodes connected in parallel on the second and third switches with opposite directions; in other words, the current conduction directions of the diodes connected in parallel on the second and third switches are opposite. The diodes connected in parallel on the second and third switches can be reverse diodes included in the second and third switches. For example, a diode connected in parallel with the second switch can conduct current flowing from the neutral point of the inverter to the midpoint of the bridge arm, while a diode connected in parallel with the third switch can conduct current flowing from the midpoint of the bridge arm to the neutral point of the inverter. The aforementioned reverse-connected second and third switches can be either connected to the neutral point of the inverter or the second switch can be connected to the neutral point of the inverter; this is not limited. Alternatively, each of at least one bridge arm includes a first, second, third, and fourth switch connected in series. Here, the series connection point of the second and third switches is the midpoint of the bridge arm, i.e., the output terminal of the bridge arm. The first and fourth switches are the main switches, and the second and third switches are the auxiliary switches. When the controller detects an overcurrent signal within a first time period, it can control the main and auxiliary switches to turn off sequentially to control the output current of the bridge arm to decrease. When the overcurrent signal fails, it can control the auxiliary switches to turn on to control the output current of the bridge arm to remain decreasing or constant. Specifically, the overcurrent signal activates when the output current of the bridge arm rises to a level greater than or equal to the current-limiting protection threshold, and deactivates when the output current of the bridge arm falls below the current-limiting protection threshold. When the overcurrent signal is active, the current-limiting blockade of the three-level inverter is initiated. The controller can sequentially turn off the main and auxiliary switches to control the decrease in the output current of the bridge arm, effectively reducing the possibility of overheating and damage to the switches due to overcurrent. When the controller detects that the overcurrent signal has deactivated, it turns on the auxiliary switch and keeps the main switch off, preventing a surge in the bridge arm's output voltage when all four switches are off. This addresses the issue of easy overvoltage causing the three-level inverter to shut down and improves the waveform of the bridge arm's output voltage to some extent.Meanwhile, keeping the main switch off prevents the bridge arm's output current from rising again within the first time period, thus avoiding the overcurrent signal re-activating and the current-limiting blockade of the three-level inverter restarting. This effectively reduces device switching losses. Furthermore, if the controller detects that the overcurrent signal remains invalid within the first time period, it can maintain the auxiliary switch on and the main switch off for a second time period after the first time period. If the overcurrent signal remains invalid within the second time period, it can control the main switch to turn on after the second time period ends to stop the bridge arm's output current from decreasing. The second time period is greater than or equal to the first time period. In this application, if no overcurrent signal is detected to be active again within the first time period (i.e., only one overcurrent signal is active within the first time period), the controller can maintain the auxiliary switch on and the main switch off for the second time period after the first time period. This controls the output current of the bridge arm to remain decreasing or constant, preventing the output current of the bridge arm from increasing again in the second time period and causing the overcurrent signal to be active again. This reduces the possibility of the switch being damaged by overheating due to overcurrent, thus improving the reliability of the three-level inverter to a certain extent. Furthermore, maintaining the switch state in the bridge arm unchanged during the second time period (i.e., no switch is turned on or off during the second time period) effectively reduces switching losses.

[0005] In one possible implementation, the first duration is one switching cycle, which is the duration between two valid edges of the first drive signal, or the duration between two valid edges of the second drive signal. Here, the first drive signal and the second drive signal can be two complementary drive signals with dead time. The first drive signal can control the on and off of the main switch, and the second drive signal can control the on and off of the auxiliary switch.

[0006] In one possible implementation, the controller can control the auxiliary switch to turn off when it detects the overcurrent signal re-activating within the first time period, maintaining the auxiliary switch off until the overcurrent signal fails. Then, within the second time period, the controller sequentially turns on the auxiliary switch and the main switch to stop the output current of the bridge arm from decreasing. In this embodiment, when the controller detects the overcurrent signal failure within the first time period and only turns on the auxiliary switch, the output current of the bridge arm is freewheeling and theoretically will not increase. However, in the actual operation of the three-level inverter, the output current of the bridge arm may continuously increase, causing the overcurrent signal to re-activate. At this time, the controller needs to control the auxiliary switch to turn off again. It can be seen that when the auxiliary switch is on, the overcurrent signal may activate and fail multiple times within the first time period, causing the controller to control the auxiliary switch to turn on or off multiple times within the first time period, leading to a sharp increase in switching losses. Therefore, when the controller detects the overcurrent signal re-activating within the first time period, it can control the auxiliary switch to turn off and maintain the auxiliary switch off within the first time period. In this way, regardless of whether the overcurrent signal fails, the switching transistor will not be controlled to operate within the first time period. This can avoid the overcurrent signal from being activated repeatedly within the first time period, and can also avoid controlling the switching transistor to operate multiple times to control the output current of the bridge arm, thereby reducing the switching losses of the device.

[0007] In one possible implementation, if the controller detects at least two overcurrent signals occurring within at least two consecutive first time periods, it controls the auxiliary switch to turn off and maintains the auxiliary switch off until the overcurrent signal fails. Then, during a second time period, it controls the auxiliary switch to turn on and keeps the main switch off to control the output current of the bridge arm to decrease or remain constant. Furthermore, if the controller detects that the overcurrent signal has failed within a second time period after at least two first time periods, it maintains the auxiliary switch on and the main switch off until the second time period ends, then controls the main switch to turn on to stop the decrease in the output current of the bridge arm.

[0008] In this embodiment, if the controller detects at least two overcurrent signals within at least two consecutive first time periods (i.e., when the output current of the bridge arm frequently exceeds the current limiting protection threshold), the controller needs to repeatedly turn the auxiliary switch on and off. The auxiliary switch is easily damaged due to overheating or excessively high reverse peak voltage during shutdown. Therefore, when the controller detects a second overcurrent signal, it can control the auxiliary switch to turn off and maintain this off state. Then, regardless of whether the overcurrent signal fails, the switch will no longer be controlled. This avoids repeated switching actions, allowing for more effective control of the switch frequency, thereby reducing device switching losses and improving the reliability of the three-level inverter. Simultaneously, during the second time period, not all switches in the bridge arm are turned off, effectively reducing the speed of bus voltage spikes and solving the problem of DC bus overvoltage causing three-level inverter shutdown.

[0009] Secondly, this application provides a current limiting protection method for a three-level inverter. This method is applicable to the three-level inverter provided in the first aspect above. The three-level inverter includes a controller and at least one bridge arm. Each of the at least one bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the series connection terminals of the first and fourth switches and the neutral point of the three-level inverter. Alternatively, each of the at least one bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series. Here, the series connection terminal of the second and third switches is the midpoint of the bridge arm, i.e., the output terminal of the bridge arm. The first and fourth switches are main switches, and the second and third switches are auxiliary switches. When the controller detects an overcurrent signal within a first time period, it controls the main switches and auxiliary switches to turn off sequentially to control the output current of the bridge arm to decrease. When the overcurrent signal fails, it controls the auxiliary switches to turn on to control the output current of the bridge arm to remain decreasing or unchanged. Specifically, when the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, the overcurrent signal takes effect; when the output current of the bridge arm decreases to a level less than the current limiting protection threshold, the overcurrent signal fails. Further, if the controller detects that the overcurrent signal remains failed within a first duration, it can maintain the auxiliary switch on and the main switch off for a second duration after the first duration. If the overcurrent signal remains failed within the second duration, after the second duration ends, it controls the main switch to turn on to stop the decrease in the bridge arm's output current. The second duration is greater than or equal to the first duration. In this application, when the controller detects that the overcurrent signal is effective within the first duration, it controls the output current of the bridge arm to decrease by sequentially turning off the main switch and the auxiliary switch. When the controller detects that the overcurrent signal has failed, it immediately controls the auxiliary switch to turn on and the main switch to remain off to control the output current of the bridge arm to continue decreasing or remain unchanged. Specifically, immediately turning on the auxiliary switch when the overcurrent signal fails shortens the turn-off time of all four switches, preventing a surge in the bridge arm output voltage when all four switches are off. This addresses the issue of overvoltage causing the three-level inverter to shut down and improves the waveform of the bridge arm output voltage to some extent. Simultaneously, keeping the main switch off prevents the bridge arm output current from rising again to above or equal to the current-limiting protection threshold within the first time period, thus avoiding re-activation of the three-level inverter's current-limiting blockade and increasing switching losses. Furthermore, if the overcurrent signal remains invalid throughout the first time period, the controller can also disable the main switch for a second time period, preventing the bridge arm output current from rising again to above or equal to the current-limiting protection threshold within the second time period. This reduces the likelihood of the switch overheating and being damaged due to overcurrent, improving the reliability of the three-level inverter.

[0010] In one possible implementation, the first duration is one switching cycle, which is the duration between two valid edges of the first drive signal, or the duration between two valid edges of the second drive signal. Here, the first drive signal and the second drive signal can be two complementary drive signals with dead time. The first drive signal can control the on and off of the main switch, and the second drive signal can control the on and off of the auxiliary switch.

[0011] In one possible implementation, the controller can control the auxiliary switch to turn off when it detects the overcurrent signal re-emerging within the first time period, maintaining the auxiliary switch off until the overcurrent signal fails. Then, within the second time period, it controls the auxiliary switch and the main switch to turn on sequentially to stop the output current of the bridge arm from decreasing. In this application, when the controller detects the overcurrent signal re-emerging within the first time period, it can control the auxiliary switch to turn off and not conduct again within the first time period. This avoids the overcurrent signal repeatedly emerging and failing within the first time period, eliminating the need to control the auxiliary switch to operate multiple times within the first time period, effectively reducing device losses.

[0012] In one possible implementation, the controller can, if at least two overcurrent signals are detected within at least two consecutive first time periods, control the auxiliary switch to turn off and maintain the auxiliary switch off until the overcurrent signal fails. Then, for a second time period, the controller controls the auxiliary switch to turn on and maintains the main switch off to control the output current of the bridge arm to decrease or remain constant. Further, if the overcurrent signal fails within a second time period after at least two first time periods, the controller can maintain the auxiliary switch on and the main switch off until the second time period ends, then control the main switch to turn on to stop the decrease in the output current of the bridge arm. In this application, the controller can control the auxiliary switch to turn off and maintain the auxiliary switch off if at least two overcurrent signals are detected within at least two consecutive first time periods. This avoids repeatedly turning the auxiliary switch on and off, reduces the possibility of damage to the auxiliary switch due to overheating or excessively high reverse peak voltage during shutdown, and improves the reliability of the three-level inverter. In addition, during the second time period following at least two consecutive first time periods, only the auxiliary switch is turned on while the main switch is turned off. This can reduce the growth rate of the output current of the bridge arm to a certain extent, so that the overcurrent signal will not take effect during the second time period. It also shortens the time when the switch in the bridge arm is completely turned off to a certain extent, reduces the speed of the surge bus voltage, and solves the problem of the DC bus being prone to overvoltage causing the three-level inverter to shut down.

[0013] Thirdly, this application provides a photovoltaic power generation system, which includes a photovoltaic unit and a three-level inverter as provided in the first aspect, wherein the photovoltaic unit is used to convert light energy into direct current and transmit the direct current to the three-level inverter.

[0014] Fourthly, this application provides an uninterruptible power supply (UPS) comprising a rectifier, a DC-DC converter, and at least one three-level inverter as provided in the first aspect. The input terminal of the rectifier is connected to an AC power grid, and the output terminal of the rectifier is connected to the input terminal of the DC-DC converter and the output terminal of the three-level inverter. The output terminal of the DC-DC converter is connected to a DC power source. The rectifier converts AC power received from the AC power grid into DC power and transmits the DC power to the DC-DC converter and the three-level inverter. The DC-DC converter performs voltage conversion on the DC power to charge the DC power source. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of an application scenario for the three-level inverter provided in this application;

[0016] Figure 2 This is a schematic diagram of another application scenario of the three-level inverter provided in this application;

[0017] Figure 3 This is a schematic diagram of another application scenario of the three-level inverter provided in this application;

[0018] Figure 4 This is a schematic diagram of a Type I three-level inverter;

[0019] Figure 5 This is a waveform diagram of the three-level inverter provided in this application;

[0020] Figure 6 This is a schematic diagram of the three-level inverter provided in this application;

[0021] Figure 7 This is another structural schematic diagram of the three-level inverter provided in this application;

[0022] Figure 8 This is another structural schematic diagram of the three-level inverter provided in this application;

[0023] Figure 9 This is another waveform diagram of the three-level inverter provided in this application;

[0024] Figure 10 This is another waveform diagram of the three-level inverter provided in this application;

[0025] Figure 11 This is another waveform diagram of the three-level inverter provided in this application;

[0026] Figure 12 This is a schematic diagram of the current flow direction of the output current of the bridge arm provided in this application;

[0027] Figure 13 This is another waveform diagram of the three-level inverter provided in this application;

[0028] Figure 14 This is another waveform diagram of the three-level inverter provided in this application;

[0029] Figure 15 This is another structural schematic diagram of the three-level inverter provided in this application;

[0030] Figure 16 This is another structural schematic diagram of the three-level inverter provided in this application;

[0031] Figure 17 This is a flowchart illustrating the current limiting protection method for the three-level inverter provided in this application;

[0032] Figure 18 This is another flowchart illustrating the current limiting protection method for the three-level inverter provided in this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0034] Three-level inverters, as a crucial component of energy conversion, are widely used in power electronics applications such as photovoltaic power generation systems, uninterruptible power supplies (UPS), new energy power generation, and active power filtering. (See also...) Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of the three-level inverter provided in this application. The photovoltaic power generation system provided in this application may include photovoltaic units and at least one power converter. Here, the power converter may be a three-level inverter, and the outputs of the three-level inverters are connected in parallel. The photovoltaic units may be photovoltaic modules. Taking a photovoltaic power generation system including multiple three-level inverters as an example, the DC terminals of the three-level inverters are used to connect to the photovoltaic units, and the AC terminals of the three-level inverters are connected in parallel to connect to the power grid or load. The photovoltaic units can convert light energy into DC power and transmit the DC power to the three-level inverters. The three-level inverters can invert and convert the DC power provided by the photovoltaic units, and output the converted AC power to the power grid or load.

[0035] See Figure 2, Figure 2 This is a schematic diagram illustrating another application scenario of the three-level inverter provided in this application. For example... Figure 2 As shown, a UPS (Uninterruptible Power Supply) is a power supply containing an energy storage device, primarily used to provide uninterrupted power to equipment with high power stability requirements. A UPS may include a rectifier, a DC-DC converter, and an inverter. The rectifier's input is connected to the AC power grid, and its output is connected to the input of the DC-DC converter and the output of a three-level inverter. The DC-DC converter's output is connected to a DC power source. In some feasible implementations, the UPS may also include a static bypass, a maintenance bypass, a first switch, and a second switch. Here, the inverter can be a three-level inverter, and the AC power grid can be mains power. When the mains power is normal, the main circuit branch operates normally; that is, the UPS receives AC power from the mains input through the mains input. The rectifier in the UPS converts this AC power into stable DC power, and the inverter converts this DC power into AC power required by downstream circuits (such as loads). The UPS then supplies power to these downstream circuits through its output. Simultaneously, the DC-DC converter in the UPS performs voltage conversion on the DC power to charge the DC power source. When a UPS malfunctions, such as a rectifier failure, inverter failure, or overload, the UPS can receive mains power through the bypass input. The static bypass is used to filter and regulate this mains power. The second switch is used to connect the bypass branch, i.e., connecting the bypass input, static bypass, and output. The UPS then outputs AC power to supply downstream circuits. It's understood that the main input and bypass input can be from the same AC grid or different AC grids, depending on the specific application scenario; no restrictions are placed here. When the UPS requires maintenance, the maintenance personnel can manually activate the first switch. The UPS can then receive mains power through the bypass input. The maintenance bypass is used to transmit mains power to the UPS output, which outputs AC voltage. This ensures that the UPS maintenance bypass is isolated from the power supply circuits of other branches while maintaining normal power supply to the bypass branch. This maintains normal power supply while ensuring the safety of maintenance personnel.

[0036] See Figure 3 , Figure 3 This is a schematic diagram illustrating another application scenario of the three-level inverter provided in this application. For example... Figure 3 As shown, using multiple UPS units operating in parallel ensures continuous power supply even if one UPS fails, effectively improving power reliability and capacity. The structure of each UPS can be found here. Figure 3It is understandable that, in the case of multiple UPS operating in parallel, the main input terminal and the bypass input terminal can be the same AC power grid or different AC power grids, depending on the actual application scenario, and are not restricted here. Optionally, the bypass input terminal of each UPS can be the same AC power grid, while the main input terminal of each UPS can be the same AC power grid or different AC power grids. The main input terminal and the bypass input terminal can be the same AC power grid or different AC power grids, depending on the actual application scenario, and are not restricted here. Optionally, the DC-DC converter in each UPS can be connected to the same DC power supply or to different DC power supplies, depending on the actual application scenario, and are not restricted here.

[0037] in, Figures 1 to 3 The inverter shown can be a three-level inverter; the structure of a three-level inverter can be found in [reference needed]. Figure 4 The bridge arms of a three-level inverter include a first switch Q11, a second switch Q12, a third switch Q13, and a fourth switch Q14 connected in series. These switches can be controlled to switch between on and off states to enable the three-level inverter to operate. The waveforms of the three-level inverter during operation can be found in [reference needed]. Figure 5 , Figure 5 This is a waveform diagram of the three-level inverter provided in this application. Figure 5 As shown, the enable signal (EN) can be used to control the output voltage of the bridge arm to be in the positive or negative half-cycle. When EN is high, the output voltage of the bridge arm is in the positive half-cycle; when EN is low, the output voltage of the bridge arm is in the negative half-cycle. PWM1 and PWM2 are two complementary drive signals with dead time. PWM1 and PWM2 can be used to generate four drive signals that change according to certain logic. These four drive signals are used to drive the four switches Q11, Q12, Q13, and Q14 in the bridge arm to operate according to switching logic. Specifically, PWM1 can generate drive signals to control the on and off of Q11 and Q14, i.e., PWM_Q11 and PWM_Q14; PWM2 can generate drive signals to control the on and off of Q12 and Q13, i.e., PWM_Q12 and PWM_Q13.

[0038] like Figure 5As shown, when EN is high, the bridge arm's output voltage is in the positive half-cycle, meaning the output voltage is positive. At this time, Q12 is normally on, Q14 is normally off, and Q11 and Q13 generate complementary waveforms. Here, complementary waveform generation can be considered as Q11 and Q13 conducting complementaryly, and the time when both Q11 and Q13 are off is the dead time. Within one switching cycle, the complementary conduction of Q11 and Q13 and the dead time should be included. Taking PWM_Q11 as an example, when PWM_Q11 has a rising edge, Q11 turns on when it changes from low to high, and turns off when it has a falling edge. When EN is low, the bridge arm's output voltage is in the negative half-cycle, meaning the output voltage is negative. Q13 is normally on, Q11 is normally off, and Q12 and Q14 generate complementary waveforms. Here, complementary wave generation can be considered as Q12 and Q14 being complementary in conduction, and the time when both Q12 and Q14 are turned off is the dead time.

[0039] For example, when the output voltage of the bridge arm is positive, Q12 is normally on, Q14 is normally closed, and Q11 and Q13 generate complementary waveforms. When the main switch is on and the auxiliary switch is off, i.e., Q11 is on and Q13 is off, the output current of the bridge arm increases. At this time, the output voltage of the bridge arm is the positive bus voltage +Vbus, and the output current flows out of the bridge arm from the positive DC bus through Q11 and Q12. If the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, the current limiting blockade of the three-level inverter is activated. The main switch will be turned off first, and after the main switch is reliably turned off, the auxiliary switch will be turned off. In other words, when the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, Q11 and Q14 will be turned off first, and after Q11 and Q14 are reliably turned off, Q12 and Q13 will be turned off. After the auxiliary switch is completely turned off, the output current of the bridge arm will freewheel through the negative DC bus and the freewheeling diodes of Q14 and Q13, charging the negative DC bus. At this time, the output voltage of the bridge arm is the negative bus voltage -Vbus. Since all four switches are off, the output current of the bridge arm drops significantly. When the output current of the bridge arm drops below the current limiting protection threshold, the current limiting lockout logic is entered, that is, the auxiliary switch is turned on first and then the main switch. Specifically, when the lockout logic adopts a non-wave-by-wave current limiting method, the auxiliary switch is turned on first and then the main switch when the output current of the bridge arm drops below the current limiting protection threshold. However, after the main switch is turned on, the output current of the bridge arm will rise again, which may cause the output current of the bridge arm to rise again to be greater than or equal to the current limiting protection threshold. At this time, the current limiting lockout of the three-level inverter may be activated multiple times within a switching cycle. Repeatedly locking the switches will cause severe distortion of the output voltage and current of the three-level inverter and will also greatly increase the switching losses of the switches. When the deblocking logic uses wave-by-wave current limiting, the auxiliary switch needs to be turned on first, followed by the main switch, when the next valid edge of the PWM arrives. Here, the valid edge of the PWM can be the rising edge of the PWM. For example, when EN is high, Q12 is normally on, Q14 is normally off, and Q11 and Q13 generate complementary waveforms. At this time, when the pulse of PWM1 is a rising edge and the pulse of PWM2 is low, that is, PWM_Q11, which controls Q11, is high and PWM_Q13, which controls Q13, is low, Q11 is turned on and Q13 is turned off. Since the deblocking logic for exiting the current limiting block is to turn on the auxiliary switch first and then the main switch, Q12 and Q13 are turned on first, followed by Q11, when the valid edge of PWM1 arrives. It should be understood that since PWM_Q13, which controls Q13, is low, Q13 is briefly turned on and then turned off. However, in the above-mentioned unblocking logic for exiting the current limiting block, the four switching transistors in the bridge arm are always turned off before the next valid edge of the PWM arrives. This will charge the DC bus, causing the bus voltage to rise rapidly. Excessive voltage will cause the insulation of electrical equipment to break down, leading to equipment failure and endangering equipment safety.

[0040] See Figure 6 , Figure 6 This is a structural schematic diagram of the three-level inverter provided in this application. Figure 6 As shown, a three-level inverter includes a controller and at least one bridge arm. Optionally, the three-level inverter may also include a first capacitor C1, a second capacitor C2, BUS+, and BUS-. C1 and C2 are connected in series between BUS+ and BUS-, and the bridge arm is connected between BUS+ and BUS-. The series connection terminal of C1 and C2 can be connected to the bridge arm. Here, one end of C1 is connected to BUS+, the other end of C1 is connected to one end of C2, and the other end of C2 is connected to BUS-. The connection terminal where the other end of C1 is connected to one end of C2 is the series connection terminal of C1 and C2. The series connection of C1 and C2 can divide the voltage between the DC buses into three levels: the positive bus voltage, the negative bus voltage, and the voltage at the series connection terminal of C1 and C2. When the capacitance values ​​of C1 and C2 are equal, the voltage at the series connection terminal of C1 and C2 is zero voltage, and the series connection terminal of C1 and C2 can be denoted as the neutral point N. The bridge arm structure in a three-level inverter can adopt a T-type three-level topology or an I-type three-level topology.

[0041] See Figure 7 , Figure 7 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 7As shown, the bridge arms in a three-level inverter may include Q11 and Q14. The series connection terminals of Q11 and Q14 are connected in series with Q12 and Q13 between them and the neutral point N of the three-level inverter. Q11 and Q14 are the main switches, and Q12 and Q13 are auxiliary switches. Here, the series connection terminal of Q11 and Q14 is the midpoint of the bridge arm (denoted as O1), which is the output terminal of the bridge arm. Optionally, the three-level inverter may also include C1, C2, BUS+, and BUS-. At least one bridge arm is connected between BUS+ and BUS-, and C1 and C2 are connected in series between BUS+ and BUS-. The series connection terminals of C1 and C2 can be connected to N. Here, one end of C1 is connected to BUS+, the other end of C1 is connected to one end of C2, and the other end of C2 is connected to BUS-. The connection point where the other end of C1 connects to one end of C2 is the series connection point of C1 and C2. The series connection of C1 and C2 divides the voltage between the DC bus into three levels: the positive bus voltage, the negative bus voltage, and the voltage at the series connection point of C1 and C2. When the capacitance values ​​of C1 and C2 are equal, the voltage at the series connection point of C1 and C2 is zero. This series connection point can be denoted as neutral point N. It should be understood that the series connection point of C1 and C2 and N can be the same. It is also understood that O1 can be connected to N through reverse-connected Q12 and Q13. The reverse-connected series connection of Q12 and Q13 can mean that the diodes connected in parallel on Q12 and Q13 have opposite directions of current conduction. In other words, the diodes connected in parallel on Q12 and Q13 have opposite current conduction directions. These diodes can be reverse-connected diodes included in Q12 and Q13. For example, the diode connected in parallel with Q12 can conduct current flowing from the connection terminals of C1 and C2 to the connection terminals of Q11 and Q14, while the diode connected in parallel with Q13 can conduct current flowing from the connection terminals of Q11 and Q14 to the connection terminals of C1 and C2. Here, in the above-mentioned reverse series connection of Q12 and Q13, Q13 can be connected to the connection terminals of C1 and C2, or Q12 can be connected to the connection terminals of C1 and C2. This embodiment of the application takes the connection terminals of Q12 and C1 and C2 as an example, which will not be elaborated further below. Among them, the switching transistors in the three-level inverter can be insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), gate-turn-off thyristors (GTOs), integrated gate-commutated thyristors (IGCTs), etc.

[0042] In some other feasible implementations, the output terminal O1 of the three-level inverter can be grounded through a filter inductor and a filter capacitor. In this case, the output circuit of the three-level inverter carries a resistive load, and the output current of the bridge arm is the inductor current. It should be understood that connecting the output terminal of the three-level inverter can filter out high-frequency noise, smooth the current waveform, and suppress high-frequency noise.

[0043] In some feasible implementations, the structure of the bridge arm can be seen in [reference needed]. Figure 8 , Figure 8 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 8 As shown, each arm of at least one bridge arm in a three-level inverter may include Q11, Q12, Q13, and Q14 connected in series. Here, the series connection terminal of Q12 and Q13 is O1. Optionally, the three-level inverter may also include a first diode D11 and a second diode D21, with the anode of D11 connected to the cathode of D21 and the series connection terminal of C1 and C2, the cathode of D11 connected to the series connection terminal of Q11 and Q12, and the anode of D21 connected to the series connection terminal of Q13 and Q14. See also Figure 7 and Figure 8 , Figure 7 The bridge arm shown adopts a T-type three-level topology. Figure 8 The bridge arm structure shown adopts a Type I three-level topology. When the power factor of the three-level inverter is high (e.g., close to 1), the frequency of the switching transistors in the bridge arm increases (e.g., switching frequency > 16kHz). In this case, the Type I three-level topology (600V) has lower losses and higher efficiency than the Type T three-level topology. Conversely, when the frequency of the switching transistors in the bridge arm decreases (e.g., switching frequency < 16kHz), the Type T three-level topology (1200V) has lower losses and higher efficiency than the Type I three-level topology. Therefore, when designing an inverter system, a high-efficiency topology can be selected based on different switching frequencies. For ease of description, the following will use... Figure 7 The T-type three-level topology shown is used as an example for detailed description.

[0044] In some feasible implementations, the controller can, upon detecting an overcurrent (OC) signal within a first duration, sequentially turn off the main switch and the auxiliary switch to control the output current of the bridge arm to decrease. Conversely, upon detecting an OC failure, the controller can turn on the auxiliary switch to control the output current of the bridge arm to remain decreasing or constant. In some feasible implementations, the first duration can be one switching cycle, which can be the duration between two valid edges of the first drive signal, or the duration between two valid edges of the second drive signal. Here, the first and second drive signals can be two complementary drive signals with dead time. The first drive signal (e.g., PWM1) can control the on and off of the main switch, and the second drive signal (e.g., PWM2) can control the on and off of the auxiliary switch. For example, as shown... Figure 5 As shown, the first driving signal changes from low to high at times t1 and t2, therefore, the period from t1 to t2 can be considered one switching cycle. Alternatively, the second driving signal changes from low to high at times t3 and t7, therefore, the period from t3 to t7 can also be considered one switching cycle. Optionally, a switching cycle can also be the duration between two falling edges of the first driving signal, such as t2 and t6, or the duration between two falling edges of the second driving signal, such as t4 and t8.

[0045] In some feasible implementations, the controller can acquire the drive signals of each switch in the bridge arm, determine the operating state of each switch based on the analysis of its drive signals, and also collect the output current of the bridge arm and compare it with the current limiting protection threshold. When the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, the overcurrent protection (OC) is determined to be active; when the output current of the bridge arm falls to a level less than the current limiting protection threshold, the OC is determined to be inactive. Optionally, the OC is determined to be active when the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, i.e., when the OC changes from a low level to a high level. The OC is determined to be inactive when the output current of the bridge arm falls to a level less than the current limiting protection threshold, i.e., when the OC changes from a high level to a low level. It should be understood that the controller can determine the OC to be active when it detects that the output current of the bridge arm changes from less than the current limiting protection threshold to greater than or equal to the current limiting protection threshold, or when it detects that the OC level changes from a low level to a high level. Similarly, the controller can determine that an overcurrent (OC) circuit has failed when it detects that the output current of the bridge arm changes from being greater than or equal to the current limiting protection threshold to being less than the current limiting protection threshold, or when it detects that the OC level changes from high to low. The current limiting protection threshold can be preset by a technician. Here, the controller can be various hardware chips with processing capabilities, including but not limited to central processing units (CPUs), microcontroller units (MCUs), digital signal processing (DSP) chips, field-programmable gate array (FPGA) chips, microcontrollers, and combinations of various control chips, etc., without specific limitations here.

[0046] Specifically, when overcurrent protection (OC) is active, the current limiting blockade of the three-level inverter is activated. The controller controls Q11 and Q14 in the bridge arm to turn off first, followed by Q12 and Q13, to control the output current of the bridge arm to drop below the current limiting protection threshold. This reduces the possibility of the switching transistors overheating and being damaged due to overcurrent. After the overcurrent fails, the controller can control the auxiliary switch to turn on. At this time, the output current of the bridge arm remains decreasing or unchanged. However, under actual load conditions, such as when there are other active machines at the inverter output, when the UPS is mistakenly turned on during maintenance bypass, causing the output waveform phase to differ from the AC grid phase, or when there are different voltage and current polarities (such as the II / IV quadrants of inductive and capacitive loads), the output current of the bridge arm may rise again, causing OC to activate again within the first duration. Therefore, after the auxiliary switch turns on within the first duration, it is necessary to detect whether OC has activated again within the first duration, and then different current limiting methods can be adopted according to the number of times OC activates within the first duration. In other words, after the OC fails, different current limiting methods can be adopted depending on the number of times the OC is activated within the first time period, when only the auxiliary switch is turned on.

[0047] Furthermore, if the controller detects that the OC remains in failure within the first duration, it can maintain the auxiliary switch on and the main switch off for a second duration following the first duration. If the controller detects that the overcurrent signal remains in failure within the second duration, it can control the main switch to turn on after the second duration ends to stop the decrease in the bridge arm's output current. The second duration is greater than or equal to the first duration. For example, when the first duration is one switching cycle, the second duration is greater than or equal to one switching cycle; for ease of description, the following will use the example of the second duration being equal to the first duration for detailed explanation. Specifically, the OC only experiences one activation and deactivation within the first duration, and the auxiliary switch remains on and the main switch remains off throughout the second duration following the first duration. Furthermore, if the controller detects that the OC remains in failure throughout the second duration, it can control the main switch to turn on after the second duration ends. For example, if the controller does not detect the OC activation within the second duration, it controls the main switch to turn on when the next valid edge of PWM1 arrives after the second duration ends. In other words, after the second duration ends, the current limiting blockade of the three-level inverter is lifted, and the controller can control each switching transistor to continue working according to the drive signals (such as PWM1 and PWM2).

[0048] It is understandable that in the wave-by-wave current limiting method, when an OC failure is detected and the next valid edge of PWM1 or PWM2 arrives, the output current of the bridge arm is controlled to rise by sequentially turning on the auxiliary and main switches. That is, before the next valid edge of PWM1 or PWM2 arrives, the output current of the bridge arm will be significantly reduced due to the complete shutdown of the switches. In this embodiment, by controlling the auxiliary switch to turn on after an OC failure, the duration of the complete shutdown of all four switches can be shortened, avoiding a surge in the output voltage of the bridge arm when all four switches are off, thus solving the problem of DC bus overvoltage causing the three-level inverter to shut down. At the same time, controlling the auxiliary switch to turn on after an OC failure can control the output current of the bridge arm to remain decreasing or unchanged, which can reduce the rate of decrease of the output current of the bridge arm to a certain extent, so that the output current of the bridge arm is both less than the current limiting protection threshold and still maintained at a relatively high current level. Therefore, in such Figure 1 In the parallel output configuration of multiple three-level inverters shown, when a short circuit occurs in one of the three-level inverters, detecting an over-current (OC) failure within the first time interval can, to some extent, increase the sum of the output currents of the bridge arms of the other normal three-level inverters, thereby increasing the current flowing through the faulty three-level inverter. Specifically, the current flowing through the faulty three-level inverter is the sum of the output currents of the bridge arms of the other normal three-level inverters. It is evident that, compared to the wave-by-wave current limiting method, the output currents of the bridge arms of the other normal three-level inverters remain at a higher value, ensuring that the sum of the output currents of the bridge arms of the other normal three-level inverters also remains at a higher value. This, in turn, increases the current flowing through the faulty three-level inverter, improving the ability to break the fuse of the faulty three-level inverter and, to some extent, increasing the possibility of isolating the faulty three-level inverter from other normal three-level inverters, thus achieving fault clearance. Similarly, in... Figure 3 In the case of multiple UPSs connected in parallel, when a short circuit occurs in the three-level inverter of a certain UPS, the auxiliary switch is turned on when the OC failure is detected within the first time period. This can increase the sum of the output current of the bridge arms of the three-level inverters in other normal UPSs to a certain extent, thereby increasing the current value flowing through the three-level inverter in the faulty UPS. This can improve the ability to blow the fuse of the faulty UPS and, to a certain extent, increase the possibility of isolating the faulty UPS from other normal UPSs, so as to achieve fault isolation.

[0049] In the specific implementation, see Figure 7 and Figure 9 , Figure 9 This is another waveform diagram of the three-level inverter provided in this application. For ease of description, a detailed description is given using the example of the bridge arm's output voltage being in the positive half-cycle (i.e., EN being high). Figure 9As shown, Q12 is normally on, Q14 is normally closed, and Q11 and Q13 provide complementary waveform generation. When PWM_Q11 and PWM_Q12 are high, and PWM_Q13 and PWM_Q14 are low (i.e., Q11 and Q12 are on, and Q13 and Q14 are off), the output current of the bridge arm flows from the DC bus to the output terminal O1 of the bridge arm. At this time, the output current of the bridge arm increases, and the output voltage of the bridge arm is +Vbus. The output current path of the bridge arm can be found in [reference needed]. Figure 12 The solid line, in which, Figure 12 This is a schematic diagram of the output current flow of the bridge arm provided in this application. When PWM_Q11 and PWM_Q14 are low, and PWM_Q12 and PWM_Q13 are high, i.e., Q12 and Q13 are on and Q11 and Q14 are off, the output current of the bridge arm freewheels through Q12 and Q13, and the output voltage of the bridge arm is 0. The output current path of the bridge arm can be found in [reference needed]. Figure 12 The dashed line indicates that when Q11 to Q14 are all off, the output current of the bridge arm freewheels through the reverse diode of Q14, charging BUS-, and the output voltage of the bridge arm is -Vbus. It can be seen that when all the switching transistors are off, the DC bus is charged, causing the bus voltage to rise, which may lead to overvoltage and shutdown of the three-level inverter. Therefore, the speed at which the bus voltage rises can be reduced by shortening the full turn-off time of the switching transistors.

[0050] Specifically, such as Figure 9 As shown, the first duration can be the switching cycle from time t1 to time t9. At time t1, Q11 and Q12 are turned on, while Q13 and Q14 are turned off, and the output current of the bridge arm increases. When the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold at time t2, the OC (Open Current Control) kicks in, i.e., OC becomes high. At this time, the controller can control the main switch and the auxiliary switch to turn off sequentially, i.e., the controller controls Q11 to turn off at time t2. Here, Q14 remains off, so there is no need to operate Q14 again. After Q11 is reliably turned off, the controller controls Q12 to turn off at time t3 to reduce the output current of the bridge arm. When the OC fails, if the OC becomes low at time t4, the controller can control the auxiliary switch to turn on and the main switch to remain off, i.e., the controller controls Q12 and Q13 to turn on, while Q11 and Q14 remain off.

[0051] It should be understood that when the controller detects an over-current (OC) failure, it can directly control Q12 and Q13 to turn on without waiting for the next effective edge of PWM1 or PWM2. In this case, after Q12 and Q13 turn on, the output current of the bridge arm freewheels through Q12 and Q13, without charging a single-sided bus. The output voltage of the bridge arm is 0, which is higher than the output voltage of the bridge arm when Q11 to Q14 are all off (when Q11 to Q14 are all off, the output voltage of the bridge arm is -Vbus). Optionally, when a filter inductor is connected to O1, the voltage drop of the filter inductor is small, the voltage sag is less, and the quality of the output voltage waveform is much better. Optionally, when the controller detects an OC failure, it can control Q12 and Q13 to turn on only after a target duration. Optionally, the target duration can be a preset time, such as 2 microseconds, or it can be a dead time, such as the time when Q11 and Q13 are both off when Q12 is normally on, Q14 is normally off, and Q11 and Q13 are generating complementary waveforms. It can be understood that the first duration can be considered as composed of multiple consecutive target durations. The controller can detect whether the OC is active or inactive within each target duration. When the controller detects that the OC is active within any one of the target durations in the first duration, it can be determined that the OC is active within the first duration. Therefore, by detecting whether the OC is active or inactive within the target duration, the false detection rate can be reduced and the reliability of the detection can be improved. Furthermore, within the target duration, the heat distribution between the reverse diodes of the main switches Q1 and Q4 and the reverse diodes of the auxiliary switches Q2 and Q3 can be adjusted, thereby averaging the temperature of the main and auxiliary switches. For example, when the controller detects that the OC is inactive at time t4, the controller can control Q12 and Q13 to conduct at time t5. It should be understood that at time t5, PWM1 is at a high level and PWM2 is at a low level, meaning that PWM_Q11, which controls Q11, is at a high level and PWM_Q13, which controls Q13, is at a low level. Therefore, the controller can control Q12 to turn on and control Q13 to turn off briefly, i.e., control Q13 to turn off at time t6. At this time, only Q12 is on, and all other switches are off.

[0052] Furthermore, in such Figure 9During the switching cycle from time t1 to t9, if the controller detects that the OC remains in a state of failure, it can keep the auxiliary switch on and the main switch off for the second duration (e.g., during the switching cycle from time t9 to t13). If the controller detects that the OC remains in a state of failure during the second duration, it can control the main switch to turn on after the second duration ends. Here, during the switching cycle from time t9 to t13, since the OC remains in a state of failure, no switch operates in the bridge arm during the second duration. After the second duration ends, the current limiting blockade of the three-level inverter can be released, and the operation of each switch in the bridge arm can be determined according to PWM1 and PWM2. For example, at time t13, when the second duration ends and PWM1 becomes valid, the controller can control Q11 to turn on according to PWM1, release the current limiting blockade of the three-level inverter, and the switches in the bridge arm continue to operate according to PWM1 and PWM2.

[0053] Understandably, when only the auxiliary switch is turned on, the output current of the bridge arm flows from the neutral point through the reverse diodes Q12 and Q13 out of the output terminal O1 of the bridge arm, and the output current of the bridge arm decreases slowly or remains constant. In other words, the rate of decrease of the output current of the bridge arm when only the auxiliary switch is turned on is less than the rate of decrease of the output current of the bridge arm when the switch is fully turned off, which can reduce the speed of the bus voltage surge and solve the problem of DC bus overvoltage causing the three-level inverter to shut down. Meanwhile, in situations such as... Figure 1 In the case of multiple three-level inverters connected in parallel as shown, or in the case of... Figure 3 In the parallel operation mode of multiple UPSs shown, when a short circuit occurs in one of the three-level inverters or at the output of one of the UPSs, the current limiting protection of the other normal three-level inverters can be activated. After the overcurrent protection fails, the output current of the control arm is kept decreasing or remaining constant, so that the output current of the control arm is kept at a higher effective value. This increases the current value flowing through the faulty three-level inverter, thereby increasing the probability of blowing the fuse of the faulty three-level inverter and isolating the faulty three-level inverter from other normal three-level inverters to achieve fault isolation.

[0054] It should be noted that in the actual operation of a three-level inverter, even if an over-current (OC) event occurs only once within the first duration, various complex operating conditions may still cause issues, such as... Figure 2 or Figure 3 In the application scenario shown, a UPS may experience a mis-activation of the maintenance bypass during normal operation, potentially causing a phase difference between the voltage waveform output from the main branch and the voltage waveform output from the maintenance bypass. This could lead to an overcurrent (OC) detection within the second time period. In other words, the output current of the bridge arm might rise to a level greater than or equal to the current-limiting protection threshold even when the auxiliary switch is on and the main switch is off. Figure 9The OC (Over-Conversion) occurs during the switching cycle from time t9 to time t13, as shown. Therefore, in actual operation, the controller also needs to detect whether the OC is active during the second time period.

[0055] In some feasible implementations, when the controller detects an OC (overcurrent) effect within the second time period, it controls the auxiliary switch to turn off and maintains the off state until an OC failure is detected. Then, within the third time period, it controls the auxiliary switch and the main switch to turn on sequentially to control the output current of the bridge arm to decrease. The third time period can be equal to the second time period. For example, when the second time period equals the first time period, the first, second, and third time periods are all one switching cycle. It can be understood that the second time period can be considered as composed of multiple consecutive target time periods. Detecting an OC effect within the second time period can be considered as detecting an OC effect within any one of the target time periods within the second time period. The same applies to the third time period, which will not be elaborated further here. It should be understood that an OC failure may occur within the second time period or within the third time period. Therefore, regardless of whether the controller detects an OC failure within the second or third time period, the controller can control the auxiliary switch and the main switch to turn on sequentially according to PWM1 and PWM2 within the third time period to exit the current limiting blockade of the three-level inverter. At this point, the current limiting and blocking logic of the three-level inverter in the third time period can be referred to the current limiting and blocking logic of the three-level inverter in the first time period, which will not be elaborated on here.

[0056] In the specific implementation, see Figure 10 , Figure 10 This is another waveform diagram of the three-level inverter provided in this application. For example... Figure 10 As shown, the embodiments corresponding to times t1 to t9 can be found in [reference needed]. Figure 9The corresponding implementation will not be elaborated further here. When the controller detects an OC failure in the second time period (e.g., during the switching cycle from t9 to t12), such as when the OC failure is detected at t10, the controller can control the auxiliary switch Q12 to turn off and not turn it on again during the second time period. At this time, the output current of the bridge arm drops significantly due to the complete shutdown of the switch. Thus, regardless of whether the output current of the bridge arm drops below the current limiting protection threshold during the second time period, the switch will no longer be controlled, which can more effectively control the switching frequency of the switch and reduce switching losses. Furthermore, when the controller detects an OC failure, it can control the auxiliary switch and the main switch to turn on sequentially during the third time period (e.g., during the switching cycle from t12 to t14), thus exiting the current limiting blockade of the three-level inverter. For example, if the controller detects an OC failure and PWM1 is active at t12, the controller first turns on Q12 and Q13, and then turns on Q11 at t3. In this scenario, at time t12, PWM1 is high and PWM2 is low, meaning PWM_Q11 controlling Q11 is high and PWM_Q13 controlling Q13 is low. Therefore, Q13 briefly turns on and then turns off. It should be understood that by controlling the auxiliary switch to turn off when OC (overcurrent) occurs and not turning it back on for the second time period, the output current of the bridge arm can be effectively controlled to stop decreasing. This also avoids repeated OC activations within the second time period, eliminating the need for multiple switching actions to control the output current of the bridge arm and reducing device switching losses.

[0057] It should be noted that during the actual operation of a three-level inverter, if... Figure 2 or Figure 3 In the application scenario shown, when the UPS is operating normally, a mis-activation of the maintenance bypass may occur, potentially causing a phase difference between the voltage waveform output from the main branch and the voltage waveform output from the maintenance bypass. This could lead to two overcurrent (OC) activations within the first time period for the bridge arm's output current. In other words, under some complex operating conditions, when the bridge arm's output current frequently exceeds the current limiting protection threshold, the controller needs to repeatedly turn the auxiliary switching transistor on and off. The auxiliary switching transistor is easily damaged due to overheating or excessively high reverse peak voltage during shutdown. Therefore, the solution proposed in this application can reduce the number of OC activations to a certain extent, lowering the possibility of transistor damage and thus improving the reliability of the three-level inverter. Details are provided below:

[0058] In some feasible implementations, multiple overcurrent (OC) events may occur within the first time period. Here, when the controller detects another OC event within the first time period, it controls the auxiliary switch to turn off and maintains the auxiliary switch off until an OC failure is detected. Then, within the second time period, the controller sequentially turns on the auxiliary switch and the main switch to stop the output current of the bridge arm from decreasing. Here, the OC failure can occur within the first time period or within the second time period; the specific time period can be determined based on the actual application scenario and is not limited here.

[0059] In the specific implementation, see Figure 11 , Figure 11 This is another waveform diagram of the three-level inverter provided in this application. For example... Figure 11 As shown, a detailed description is given taking the output voltage of the bridge arm in the positive half-cycle (i.e., EN is high) as an example. During the first duration (e.g., the switching cycle from t1 to t9), Q11 and Q12 are turned on, while Q13 and Q14 are turned off, and the output current of the bridge arm increases. When the controller detects that OC has become high at t2, i.e., OC is active, it initiates the current limiting blockade of the three-level inverter. The controller can control the main switch and auxiliary switch to turn off sequentially. That is, the controller controls Q11 to turn off at t2. After Q11 is reliably turned off, the controller controls Q12 to turn off at t3. At this time, the output current of the bridge arm drops significantly due to the complete shutdown of the switches. When the controller detects OC failure at t4, the controller can control the auxiliary switch to turn on and the main switch to remain off, i.e., the controller controls Q12 and Q13 to turn on. Here, when the controller detects OC failure, it can directly control Q12 and Q13 to turn on without waiting for the next effective edge of PWM1, or it can control Q12 and Q13 to turn on after the target duration. For example, if the controller detects an OC failure at time t4, it can turn on Q12 and Q13 at time t5. Since PWM1 is high and PWM2 is low at time t5 (i.e., PWM_Q11 controlling Q11 is high and PWM_Q13 controlling Q13 is low), Q13 will briefly turn on and then turn off. At this time, only Q12 is on, and all other switches are off.

[0060] Furthermore, when the controller detects that the OC (overcurrent charge) has re-emerged within the first time period (e.g., when the OC is detected to be re-emerged at time t6), the controller can control the auxiliary switching transistors to turn off and not conduct again within the first time period, i.e., control Q12 and Q13 to turn off, and keep the state of Q12 and Q13 off unchanged within the first time period until the OC failure is detected. Then, within the second time period (e.g., the switching cycle from time t8 to time t13), the controller controls the auxiliary switching transistors and the main switching transistors to turn on sequentially. Specifically, the controller detects that the OC has failed at time t7. At time t8, PWM1 is at a high level and PWM2 is at a low level. Therefore, the controller first controls Q12 and Q13 to conduct, and at time t9 controls Q11 to conduct, exiting the current limiting blockade of the three-level inverter, so as to control the conduction or turn-off of the four switching transistors according to PWM1 and PWM2. Among them, at time t8, PWM1 is at a high level and PWM2 is at a low level, so Q13 conducts briefly and then turns off.

[0061] In this embodiment, when the controller detects an OC failure (e.g., at time t4), it does not need to wait for the next valid PWM edge and directly turns on the auxiliary switches Q12 and Q13. Ideally, the output current of the bridge arm is a freewheeling current and will not rise. However, under some complex operating conditions, such as when the potential of the neutral point N is lower than 0 (e.g., when there is a bypass short circuit in the UPS or other active machines at the inverter output), or when the voltage and current have different polarities (e.g., in the II / IV quadrants of inductive and capacitive loads), or when the UPS is in a common main-bypass operation, the output current of the bridge arm may still rise again when only the auxiliary switches are turned on, causing OC to occur again within the first time period. At this time, the controller needs to control the auxiliary switches to turn off again to control the output current of the bridge arm to decrease. It can be seen that when OC occurs multiple times within the first time period, the controller will control the auxiliary switches to turn on multiple times within the first time period, and then control the auxiliary switches to turn off again after the OC fails, which leads to a sharp increase in switching losses. Therefore, when the controller detects that the OC (overcurrent) condition has re-emerged within the first time period, the auxiliary switch is turned off and remains off for the same duration until the OC condition is detected to have failed. In the second time period, the auxiliary and main switches are sequentially turned on, exiting the current-limiting blockade of the three-level inverter, and the four switches are controlled to turn on or off according to PWM1 and PWM2. It should be understood that by limiting the number of times the auxiliary switch is turned on within the first time period, the switching losses of the device can be effectively reduced.

[0062] It should be noted that, in Figure 11In the waveform diagram shown, during the switching cycle from time t1 to time t8, two overcurrent (OC) events occur within one switching cycle. When an OC failure is detected, the auxiliary switch and the main switch are turned on sequentially during the switching cycle from time t8 to time t13. This control method can lead to situations where the number of OC events is greater than or equal to two within several consecutive cycles. When the output current of the bridge arm frequently exceeds the current limiting protection threshold, the controller needs to repeatedly turn the auxiliary switch on or off. The auxiliary switch is easily damaged due to overheating or excessively high reverse peak voltage during turn-off. Therefore, the solution proposed in this application can reduce the growth rate of the bridge arm's output current to a certain extent and reduce the number of OC events, thereby improving the reliability of the three-level inverter. For details, please refer to the following:

[0063] In some feasible implementations, if the controller detects at least two overcurrent (OC) events within at least two consecutive first time periods, it can control the auxiliary switch to turn off and maintain the off state of the auxiliary switch until an OC failure is detected. Then, for a second time period, it can control the auxiliary switch to turn on and maintain the main switch to turn off, thereby controlling the output current of the bridge arm to decrease or remain constant. Here, the OC failure can occur before or during the second time period, depending on the actual application scenario, and is not limited here. Furthermore, if the controller detects an overcurrent signal remaining unchanged for at least two first time periods, it can maintain the state of the auxiliary switch on and the main switch off until the end of the second time period, at which point it can control the main switch to turn on to stop the decrease in the output current of the bridge arm.

[0064] In the specific implementation, see Figure 13The OC (Overclocking) transistor is activated twice within two consecutive first time periods (e.g., two consecutive switching cycles) before time t3. Specifically, when the OC activates for the second time within the second first time period at time t1, the controller can turn off Q12 and Q13 and maintain their off state until the OC failure is detected (e.g., at time t2). Then, the controller can turn on Q12 and Q13 within the second time period (e.g., the switching cycle from time t3 to time t4) and keep Q11 and Q14 off. For example, if the effective edge of PWM1 arrives at time t3 within the second time period, the controller can turn on Q12 and Q13 and keep Q11 and Q14 off. In other words, the main switch is disabled during the switching cycle from time t3 to time t4. At time t3, PWM1 is high and PWM2 is low. This means PWM_Q11, controlling Q11, is high, and PWM_Q13, controlling Q13, is low. Therefore, Q13 briefly conducts and then turns off. At this time, only Q12 is on, and all other switches are off. Furthermore, if the controller detects that the OC (overcurrent charge) remains inactive during the second time period (i.e., no OC is detected during the second time period), Q12 remains on during the second time period, Q13 is turned on or off according to PWM2, and Q11 and Q14 are disabled. After the second time period ends, when the next valid edge of PWM1 arrives, the controller can turn on Q11, exiting the current limiting blockade of the three-level inverter. For example, after the switching cycle from time t3 to t4 ends, when the new valid edge of PWM1 arrives at time t4, PWM1 is high, and the controller can turn on Q11 to stop the output current of the bridge arm from decreasing, exiting the current limiting blockade of the three-level inverter. The switches in the bridge arm continue to operate according to PWM1 and PWM2.

[0065] It should be understood that under some complex operating conditions, not only may two overcurrent (OC) events occur within a single first time period, but multiple OC events may also occur consecutively within several first time periods. When the output current of the bridge arm frequently exceeds the current limiting protection threshold, the controller needs to repeatedly turn the auxiliary switch on or off. The auxiliary switch is easily damaged due to overheating or excessively high reverse peak voltage during turn-off. Therefore, if the controller detects at least two OC events within at least two consecutive switching cycles, it can control the auxiliary switch to turn off and maintain the off state. Then, regardless of whether the output current of the bridge arm drops below the current limiting protection threshold, the switch will no longer be controlled to operate. This controls the number of OC events, avoids repeated switch operations, and more effectively controls the switching frequency of the switch, reducing device switching losses. Furthermore, when the controller detects an OC failure, it controls the auxiliary switch to turn on and keeps the main switch off within a second time period to control the output current of the bridge arm to decrease or remain constant. In this way, by turning on only the auxiliary switch and disabling the main switch during the second time period, the growth rate of the output current of the bridge arm can be reduced to a certain extent. As a result, the over-current (OC) situation will not occur during the second time period. This also shortens the time when the switches in the bridge arm are fully turned off, reduces the speed at which the bus voltage rises, and solves the problem of the DC bus being prone to overvoltage, which can cause the three-level inverter to shut down.

[0066] In some feasible implementations, when the controller detects an active OC (overcurrent) within a second time period after at least two consecutive first time periods, the controller controls the auxiliary switch to turn off and keeps the main switch off until an OC failure is detected. Then, within a third time period after the second time period, the controller controls the auxiliary switch to turn on. If the OC remains inactive within the third time period, the controller turns on the main switch after the third time period ends. Here, the OC failure can occur within the second or third time period; there is no limitation on this. The third time period can be equal to the second time period. For example, when the second time period equals the first time period, the first, second, and third time periods are all considered one switching cycle.

[0067] In the specific implementation, see Figure 14 , Figure 14 This is another waveform diagram of the three-level inverter provided in this application. For example... Figure 14As shown, before time t1, two consecutive first time intervals are detected with OC activation. If OC activation is detected in the second time interval after the two consecutive first time intervals, such as during the switching cycle from time t1 to time t4, the controller controls the auxiliary switch to turn off. For example, if OC activation occurs at time t2, the controller can control Q12 to turn off at time t2 and maintain the off state of Q12 during the switching cycle from time t2 to time t4. If the controller detects OC failure, such as at time t3, the controller can control the auxiliary switch to turn on after the third time interval (such as the switching cycle from time t4 to time t5). For example, at time t4, when the effective edge of PWM1 arrives, the controller controls the auxiliary switches Q12 and Q13 to turn on, while keeping the main switches Q11 and Q14 off. Since EN is high and PWM2 is low at time t4, Q13 will briefly turn on and then turn off. Furthermore, when the controller detects that the OC remains inactive within the third time period, that is, when no OC is detected to be active during the switching cycle from time t4 to time t5, it can control the main switch to turn on when the next valid edge of PWM1 arrives, thus exiting the current limiting blockade of the three-level inverter. For example, when the valid edge of PWM1 arrives at time t5, the controller can control Q11 to turn on according to PWM1, thus exiting the current limiting blockade of the three-level inverter.

[0068] In this embodiment, during a second time period following at least two consecutive first time periods, only the auxiliary switch is turned on while the main switch is turned off. This reduces the rate of increase in the bridge arm's output current to some extent. Simultaneously, when an overcurrent (OC) event occurs during the second time period, the auxiliary switch is turned off, and the main switch remains off until an OC failure is detected. Then, during a third time period following the second time period, the auxiliary switch is turned on. If the OC remains inactive during the third time period, the main switch is turned on after the third time period ends. Therefore, by turning on the auxiliary switch and disabling the main switch within a single switching cycle, the bridge arm's output current can decrease to below the current-limiting protection threshold within a sufficient time. This eliminates the need for a complete switch shutdown to reduce the bridge arm's output current, shortens the switch shutdown time, reduces the rate of voltage surge on the bus, and solves the problem of DC bus overvoltage causing three-level inverter shutdown.

[0069] Understandably, the above Figure 7 and Figure 8 The three-level inverter shown is a single-arm inverter, meaning it contains only one arm. However, in practical applications, three-level inverters can also have multiple arms. For details, see [link to documentation]. Figure 15 , Figure 15 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 15The three-level inverter shown may include a controller, C1 and C2 connected in series, and A-phase, B-phase, and C-phase bridge arms. Here, C1 and C2 are connected in series between BUS+ and BUS-. One end of C1 is connected to BUS+, the other end of C1 is connected to one end of C2, and the other end of C2 is connected to BUS-. The connection point between the other end of C1 and one end of C2 is the series connection point of C1 and C2. The A-phase, B-phase, and C-phase bridge arms correspond to the A-phase, B-phase, and C-phase outputs of the power converter, respectively. The structures of the A-phase, B-phase, and C-phase bridge arms can be referenced above. Figure 7 The diagram shows a three-level inverter. Phase A includes Q11 and Q14. The series connection terminals of Q11 and Q14 are connected in series with N, and Q12 and Q13 are connected in series. The series connection terminal of Q11 and Q14 is the midpoint O1 of Phase A. Phase B includes Q21 and Q24. The series connection terminals of Q21 and Q24 are connected in series with N, and Q22 and Q23 are connected in series. The series connection terminal of Q21 and Q24 is the midpoint O2 of Phase B. Phase C includes Q31 and Q34. The series connection terminals of Q31 and Q34 are connected in series with N, and Q32 and Q33 are connected in series. The series connection terminal of Q31 and Q34 is the midpoint O3 of Phase C. It should be understood that in... Figures 9 to 14 The corresponding implementation methods are still applicable Figure 15 The three-level inverter shown here will not be described in detail here.

[0070] In other feasible implementations, see Figure 16 , Figure 16 This is another structural schematic diagram of the three-level inverter provided in this application. For example... Figure 16 As shown, a three-level inverter may include a controller, C1 and C2 connected between BUS+ and BUS-, an A-phase bridge arm, a B-phase bridge arm, and a C-phase bridge arm. Here, C1 and C2 are connected in series between BUS+ and BUS-. One end of C1 is connected to BUS+, the other end of C1 is connected to one end of C2, and the other end of C2 is connected to BUS-. The connection point between the other end of C1 and one end of C2 is the series connection point of C1 and C2. The A-phase bridge arm, B-phase bridge arm, and C-phase bridge arm correspond to the A-phase, B-phase, and C-phase outputs of the power converter, respectively. The structures of the A-phase bridge arm, B-phase bridge arm, and C-phase bridge arm can be referred to the above description. Figure 8The diagram shows a three-level inverter. Phase A arm may include Q11, Q12, Q13, and Q14 connected in series. The series connection terminal of Q12 and Q13 is O1. The anode of D11 is connected to the cathode of D21 and the series connection terminal of C1 and C2. The cathode of D11 is connected to the series connection terminal of Q11 and Q12. The anode of D21 is connected to the series connection terminal of Q13 and Q14. Phase B arm may include Q21, Q22, Q23, and Q24 connected in series. The series connection terminal of Q22 and Q23 is O2. The anode of D12 is connected to the cathode of D22 and the series connection terminal of C1 and C2. The cathode of D12 is connected to the series connection terminal of Q11 and Q12. The anode of D22 is connected to the series connection terminal of Q13 and Q14. The C-phase bridge arm may include Q31, Q32, Q33, and Q34 connected in series. The series connection terminal of Q32 and Q33 is O3. The anode of D13 is connected to the cathode of D21, the series connection terminal of C1 and C2, the cathode of D13 is connected to the series connection terminal of Q11 and Q12, and the anode of D23 is connected to the series connection terminal of Q13 and Q14. It should be understood that in Figures 9 to 14 The corresponding implementation methods are still applicable Figure 16 The three-level inverter shown here will not be described in detail here.

[0071] In this embodiment, when the controller detects an overcurrent (OC) signal within the first time period, it initiates the current limiting blockade of the three-level inverter. To reduce the output current of the bridge arm, the controller can sequentially turn off the main switch and the auxiliary switch. When the OC signal fails, the controller can turn on the auxiliary switch to control the output current of the bridge arm to remain decreasing or constant, and detect whether the OC signal re-activates within the first time period. If the controller detects that the OC signal remains inactive within the first time period, it can maintain the auxiliary switch on and the main switch off for the second time period after the first time period. If the controller detects that the overcurrent signal remains inactive within the second time period, it can turn on the main switch after the second time period ends to exit the current limiting blockade of the three-level inverter. It can be seen that by keeping the auxiliary switch on and disabling the main switch within the second time period, the output current of the bridge arm can always be kept below the current limiting protection threshold within the second time period, which can reduce the possibility of the switch being damaged due to overheating caused by overcurrent, and improve the reliability of the three-level inverter to a certain extent. Meanwhile, in situations where... Figure 1 In the case of multiple three-level inverters connected in parallel as shown, or in the case of... Figure 3 In the parallel operation of multiple UPS units shown, the rate of change of the output current of the bridge arm is reduced, preventing a significant drop in the effective value of the output current of the bridge arm and thus isolating the fault point. Furthermore, during the second time period, there is no switching of the transistors, effectively reducing the turn-on and turn-off losses of the transistors.

[0072] See Figure 17 , Figure 17A flowchart illustrating the current limiting control method for the three-level inverter provided in this application. Figure 17 The current limiting control method for the three-level inverter shown is applicable to various types of three-level inverters. This three-level inverter includes a controller and at least one bridge arm. Each of the at least one bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the series connection terminals of the first and fourth switches and the neutral point of the three-level inverter. Alternatively, each of the at least one bridge arm includes a first switch, a second switch, a third switch, and a fourth switch connected in series. The above-described three-level inverter can be found in [reference needed]. Figure 7 and Figure 15 The T-type three-level inverter and the multiphase three-level inverter shown are Figure 8 and Figure 16 The diagram shows a type I three-level inverter and a multi-phase three-level inverter.

[0073] The current limiting protection method for the three-level inverter proposed in this application may specifically include the following steps:

[0074] S101, when the controller detects an overcurrent signal within the first time period, it controls the main switch and the auxiliary switch to turn off in sequence to control the output current of the bridge arm to decrease. When the overcurrent signal fails, it controls the auxiliary switch to turn on to control the output current of the bridge arm to remain decreasing or unchanged.

[0075] Specifically, if the controller detects that the overcurrent signal remains invalid after the overcurrent signal fails, then S102 is executed; if the controller detects that the overcurrent signal becomes effective again within the first time period, then S103 is executed.

[0076] S102, if the controller detects an overcurrent signal that remains unchanged during the first time period, it keeps the auxiliary switch on and the main switch off during the second time period after the first time period. If the controller detects an overcurrent signal that remains unchanged during the second time period, it controls the main switch to turn on after the second time period ends to control the output current of the bridge arm to stop decreasing.

[0077] S103, when the controller detects that the overcurrent signal is active again within the first time period, it controls the auxiliary switch to turn off and keeps the auxiliary switch off until the overcurrent signal is detected to be invalid. Then, within the second time period, it controls the auxiliary switch and the main switch to turn on in sequence to control the output current of the bridge arm to stop decreasing.

[0078] The controller can acquire the drive signals of each switch in the bridge arm, determine the operating state of each switch based on the analysis of its drive signals, and also collect the output current of the bridge arm and compare it with the current limiting protection threshold. When the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, an overcurrent signal is activated; when the output current of the bridge arm falls to a level less than the current limiting protection threshold, the overcurrent signal is deactivated. Optionally, when the output current of the bridge arm rises to a level greater than or equal to the current limiting protection threshold, the overcurrent signal can change from a low level to a high level, activating the overcurrent signal. When the output current of the bridge arm falls to a level less than the current limiting protection threshold, the overcurrent signal can change from a high level to a low level, deactivating the overcurrent signal. It should be understood that the current limiting protection threshold can be preset by a technician. See the embodiments for S101 and S102. Figure 9 The corresponding implementation examples will not be described in detail here.

[0079] In this embodiment, when the controller detects an overcurrent signal within the first time period, it controls the main switch and auxiliary switch to turn off sequentially to control the output current of the bridge arm to decrease. When the controller detects that the overcurrent signal has failed, it immediately controls the auxiliary switch to turn on and the main switch to remain off to control the output current of the bridge arm to decrease or remain unchanged. Specifically, immediately turning on the auxiliary switch when the overcurrent signal fails shortens the time for all four switches to be turned off compared to the wave-by-wave current limiting method. This avoids a surge in the output voltage of the bridge arm when all four switches are off, solving the problem of DC bus overvoltage causing the three-level inverter to shut down, and improving the waveform of the bridge arm's output voltage to some extent. Simultaneously, keeping the main switch off prevents the three-level inverter's current limiting block from being activated again if the bridge arm's output current rises again to a level greater than or equal to the current limiting protection threshold within the current switching cycle, thus preventing increased switching losses. If the controller detects an overcurrent signal and remains in failure during the first time period, it can also maintain the state of the auxiliary switch being turned on and the main switch being turned off during the second time period after the first time period. This can prevent the output current of the bridge arm from rising again to a level greater than or equal to the current limiting protection threshold during the second time period, thereby reducing the possibility of the switch being damaged due to overheating caused by overcurrent and improving the reliability of the three-level inverter.

[0080] In some feasible implementations, if the overcurrent signal is detected to be active again within the first time period, step S103 can be executed. The controller can control the auxiliary switch to turn off when the overcurrent signal is detected to be active again within the first time period, maintaining the auxiliary switch off until the overcurrent signal is detected to be invalid. Then, within the second time period, the auxiliary switch and the main switch are sequentially turned on to control the output current of the bridge arm to stop decreasing. See details below. Figure 11 , Figure 11 The corresponding implementation examples will not be described in detail here.

[0081] In this embodiment, when the controller detects an overcurrent signal failure within the first time period, the output current of the bridge arm is freewheeling when only the auxiliary switch is turned on, and theoretically it will not increase. However, in the actual operation of the three-level inverter, the output current of the bridge arm may continue to rise, causing the overcurrent signal to re-activate. At this time, the controller needs to control the auxiliary switch to turn off again. It can be seen that when the auxiliary switch is on, the overcurrent signal may activate and fail multiple times within the first time period. The controller will control the auxiliary switch to turn on or off multiple times within the first time period, resulting in a sharp increase in switching losses. Therefore, when the controller detects an overcurrent signal re-activating within the first time period, it can control the auxiliary switch to turn off and keep the auxiliary switch off within the first time period. In this way, regardless of whether the overcurrent signal fails, the switch will not be controlled to operate within the first time period, which can avoid the repeated activation of the overcurrent signal within the first time period and also avoid controlling the switch to operate multiple times to control the output current of the bridge arm, thereby reducing the switching losses of the device.

[0082] It should be noted that, in Figure 11 In the waveform diagram shown, two overcurrent signals occur within the first time period (e.g., the switching cycle from t9 to t14), controlling the auxiliary switch to turn off. The auxiliary switch remains off until the overcurrent signal is detected and fails. Then, within the second time period, the auxiliary switch and the main switch are sequentially turned on to stop the output current of the bridge arm from decreasing. This control method can lead to situations where the overcurrent signal (OC) is activated twice or more consecutively within the first time period. Figure 18 Another flowchart illustrating the current limiting control method for the three-level inverter provided in this application. Figure 18 The current limiting control method shown for three-level inverters is applicable to various types of three-level inverters, such as... Figure 7 and Figure 15 The T-type three-level inverter and the multiphase three-level inverter shown are Figure 8 and Figure 16 The diagram shows a type I three-level inverter and a multi-phase three-level inverter. Specifically, the current-limiting protection method for the three-level inverter proposed in this application may include the following steps:

[0083] S201, if the controller detects at least two overcurrent signals in at least two consecutive first time periods, it controls the auxiliary switch to turn off and keeps the auxiliary switch off until the overcurrent signal fails. Then, in the second time period, it controls the auxiliary switch to turn on and keeps the main switch off, so as to control the output current of the bridge arm to decrease or remain unchanged.

[0084] S202, if the controller detects an overcurrent signal and remains in failure for at least two first durations in the second duration, it keeps the auxiliary switch on and the main switch off until the second duration ends, then controls the main switch to turn on to stop the output current of the bridge arm from decreasing.

[0085] The specific implementation methods of S201 and S202 are as follows. Figure 13 The corresponding implementation examples will not be described in detail here.

[0086] In this embodiment, if the controller detects at least two overcurrent signals within at least two consecutive first time periods (i.e., when the output current of the bridge arm frequently exceeds the current limiting protection threshold), the controller needs to repeatedly turn the auxiliary switch on and off. The auxiliary switch is easily damaged due to overheating or excessively high reverse peak voltage during shutdown. Therefore, when the controller detects a second overcurrent signal, it can control the auxiliary switch to turn off and maintain this off state. Then, regardless of whether the overcurrent signal fails, the switch will no longer be controlled. This avoids repeated switching actions, allowing for more effective control of the switch frequency, thereby reducing device switching losses and improving the reliability of the three-level inverter. Simultaneously, during the second time period, not all switches in the bridge arm are turned off, effectively reducing the speed of bus voltage spikes and solving the problem of DC bus overvoltage causing three-level inverter shutdown.

[0087] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A three-level inverter, characterized in that, The three-level inverter includes a controller and at least one bridge arm. Each of the at least one bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the series connection terminals of the first switch and the fourth switch and the neutral point of the three-level inverter. Alternatively, each of the at least one bridge arm includes the first switch, the second switch, the third switch, and the fourth switch connected in series. The first switch and the fourth switch are main switches, and the second switch and the third switch are auxiliary switches. The controller is configured to, when an overcurrent signal is detected to be active within a first time period, control the main switch and the auxiliary switch to turn off sequentially to control the output current of the bridge arm to decrease, and to control the auxiliary switch to turn on when the overcurrent signal is detected to control the output current of the bridge arm to remain decreasing or unchanged. The controller is further configured to, when the overcurrent signal remains unchanged during the first duration, maintain the state of the auxiliary switch being turned on and the main switch being turned off during the second duration after the first duration, and when the overcurrent signal remains unchanged during the second duration, control the main switch to turn on after the second duration ends to control the output current of the bridge arm to stop decreasing; the second duration is greater than or equal to the first duration.

2. The three-level inverter according to claim 1, characterized in that, The first duration is one switching cycle, where one switching cycle is the duration between two valid edges of the first drive signal, or the switching cycle is the duration between two valid edges of the second drive signal.

3. The three-level inverter according to claim 2, characterized in that, The controller is further configured to, when the overcurrent signal is detected to be active again within the first time period, control the auxiliary switch to turn off and keep the auxiliary switch off until the overcurrent signal is detected to be invalid, and then control the auxiliary switch and the main switch to turn on sequentially within the second time period to control the output current of the bridge arm to stop decreasing.

4. The three-level inverter according to claim 3, characterized in that, The controller is further configured to, when at least two overcurrent signals are detected to be active within at least two consecutive first durations, control the auxiliary switch to turn off and keep the auxiliary switch off until the overcurrent signal is detected to fail, control the auxiliary switch to turn on and keep the main switch off within the second duration, so as to control the output current of the bridge arm to decrease or remain unchanged. The controller is further configured to, when the overcurrent signal is detected to remain unchanged during the second duration after at least two first durations, maintain the state of the auxiliary switch being turned on and the main switch being turned off, until the end of the second duration, and then control the main switch to turn on to control the output current of the bridge arm to stop decreasing.

5. A current-limiting protection method for a three-level inverter, characterized in that, The method is applicable to a three-level inverter, which includes a controller and at least one bridge arm. Each of the at least one bridge arm includes a first switch and a fourth switch. A second switch and a third switch are connected in series between the series connection terminals of the first switch and the fourth switch and the neutral point of the three-level inverter. Alternatively, each of the at least one bridge arm includes the first switch, the second switch, the third switch, and the fourth switch connected in series. Wherein, the first switch and the fourth switch are main switches, and the second switch and the third switch are auxiliary switches. When the controller detects an overcurrent signal within a first time period, it controls the main switch and the auxiliary switch to turn off sequentially to control the output current of the bridge arm to decrease. When the overcurrent signal is detected to be invalid, it controls the auxiliary switch to turn on to control the output current of the bridge arm to remain decreasing or unchanged. When the controller detects that the overcurrent signal remains unchanged during the first duration, it keeps the auxiliary switch on and the main switch off during the second duration after the first duration. When the controller detects that the overcurrent signal remains unchanged during the second duration, it controls the main switch to turn on after the second duration ends to control the output current of the bridge arm to stop decreasing. The second duration is greater than or equal to the first duration.

6. The current limiting protection method according to claim 5, characterized in that, The first duration is one switching cycle, wherein one switching cycle is the duration between two valid edges of the drive signal that controls the operation of the main switching transistor, or, one switching cycle is the duration between two valid edges of the drive signal that controls the operation of the auxiliary switching transistor.

7. The current limiting protection method according to claim 6, characterized in that, When the controller detects that the overcurrent signal is active again within the first time period, it controls the auxiliary switch to turn off and keeps the auxiliary switch off until the overcurrent signal is detected to be invalid. Then, within the second time period, it controls the auxiliary switch and the main switch to turn on in sequence to control the output current of the bridge arm to stop decreasing.

8. The current limiting protection method according to claim 7, characterized in that, If the controller detects at least two instances of the overcurrent signal being active within at least two consecutive first time periods, it controls the auxiliary switch to turn off and keeps the auxiliary switch off until the overcurrent signal is detected to be ineffective. Then, within the second time period, it controls the auxiliary switch to turn on and keeps the main switch off, so as to control the output current of the bridge arm to decrease or remain unchanged. The controller is further configured to, when the overcurrent signal is detected to remain unchanged during the second duration after at least two first durations, maintain the state of the auxiliary switch being turned on and the main switch being turned off, until the end of the second duration, and then control the main switch to turn on to control the output current of the bridge arm to stop decreasing.

9. A photovoltaic power generation system, characterized in that, The photovoltaic power generation system includes a photovoltaic unit and a three-level inverter as described in any one of claims 1 to 4; The photovoltaic unit is used to convert light energy into direct current and transmit the direct current to the three-level inverter.

10. An uninterruptible power supply, characterized in that, The uninterruptible power supply includes a rectifier, a DC-DC converter, and at least one three-level inverter as described in any one of claims 1 to 4; the input terminal of the rectifier is used to connect to the AC power grid, the output terminal of the rectifier is connected to the input terminal of the DC-DC converter and the output terminal of the three-level inverter, and the output terminal of the DC-DC converter is used to connect to a DC power source; The rectifier is used to convert AC power received from the AC grid into DC power and transmit the DC power to the DC converter and the three-level inverter. The DC-DC converter is used to convert the DC power into voltage to charge the DC power source.

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