Charge pump regulation system
Patent Information
- Application Number
- CN202610453754.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-04-14
- Filing Date
- 2026-04-08
- Publication Date
- 2026-10-20
Smart Images
Figure FT_1 
Figure FT_2 
Figure FT_3
Abstract
Description
Technical Field
[0001] This invention relates to a charge pump, and more particularly to a charge pump regulation system. Background Technology
[0002] As is well known, programmable nonvolatile memory can be programmed to write data into its memory cells. Furthermore, in programmable erasable nonvolatile memory, erase operations can be performed to modify the data within the memory cells.
[0003] Generally, programming and erasing operations require a relatively high voltage. Therefore, non-volatile memory incorporates a charge pump, which converts the received supply voltage V... DD Increase to the desired voltage, such as the programming voltage or the erase voltage.
[0004] In non-volatile memory, a charge pump is coupled to a power switch. When the non-volatile memory begins programming, the power switch turns on, allowing the programming voltage output by the charge pump to be delivered to the memory cell array. When the non-volatile memory stops programming, the power switch turns off, stopping the delivery of the programming voltage to the memory cell array.
[0005] Similarly, when the non-volatile memory begins the erase operation, the power switch is turned on, allowing the erase voltage output by the charge pump to be delivered to the memory cell array of the non-volatile memory. When the non-volatile memory stops the erase operation, the power switch is turned off, stopping the delivery of the erase voltage to the memory cell array of the non-volatile memory. Summary of the Invention
[0006] This invention relates to a charge pump regulation system, wherein an output voltage generated by the charge pump regulation system is transmitted to a memory cell array via a power switch. The charge pump regulation system includes: a charge pump, a control terminal of which receives a control signal, and an output terminal of which generates the output voltage; a voltage divider, which receives the output voltage and generates a feedback voltage; a comparator, a first input terminal of which receives the feedback voltage, a second input terminal of which receives a reference voltage, and an output terminal of which generates the control signal; and an overshoot mitigation circuit, including a sensing circuit and a response circuit, the sensing circuit being connected to a first sensing node in the comparator, and the response circuit being connected to the output terminal of the charge pump; wherein, upon confirming that the output voltage includes an overshoot voltage, the sensing circuit activates a pull-down signal; and, based on the activated pull-down signal, the response circuit operates and reduces the output voltage.
[0007] To provide a better understanding of the above and other aspects of the present invention, preferred embodiments are described below in detail with reference to the accompanying drawings: Attached Figure Description
[0008] Figure 1A This is a charge pump regulation system according to the first embodiment of the present invention;
[0009] Figure 1B This is a schematic diagram of the output voltage of the charge pump regulation system in the first embodiment;
[0010] Figure 2A This is a charge pump regulation system according to a second embodiment of the present invention;
[0011] Figure 2B This is a schematic diagram of the output voltage of the charge pump regulation system in the second embodiment;
[0012] Figure 3A This is the first comparator and overshoot mitigation circuit in the charge pump regulation system of the second embodiment;
[0013] Figure 3B This is another example of a sensing circuit;
[0014] Figure 3C This is yet another example of a sensing circuit;
[0015] Figure 3D This is another example of a reactive circuit;
[0016] Figure 3E This is yet another example of a reactive circuit;
[0017] Figure 3F This is yet another example of a reactive circuit;
[0018] Figure 4AThis is a second comparator and overshoot mitigation circuit in the charge pump regulation system of the second embodiment;
[0019] Figure 4B This is another example of a sensing circuit;
[0020] Figure 4C This is yet another example of a sensing circuit;
[0021] Figure 5A This is the third comparator and overshoot mitigation circuit in the charge pump regulation system of the second embodiment;
[0022] Figure 5B Another example of a sensing circuit; and
[0023] Figure 5C This is another example of a sensing circuit.
[0024] [Symbol Explanation]
[0025] 100, 200: Charge pump regulation system
[0026] 102: Charge Pump
[0027] 104: Voltage divider
[0028] 106, 220, 320, 420, 520: Comparators
[0029] 130: Memory Cell Array
[0030] 210, 310, 410: Overshoot mitigation circuit
[0031] 230, 330, 332, 334, 430, 432, 434, 530, 532: Sensing circuits
[0032] 240, 340, 342, 344, 346: Reaction circuits
[0033] 322, 324, 326, 422, 424, 426, 522, 538: Current mirror
[0034] 349: Transformer Detailed Implementation
[0035] Please refer to Figure 1A The diagram illustrates a charge pump regulation system according to a first embodiment of the present invention. The charge pump regulation system 100 includes: a charge pump 102, a voltage divider 104, and a comparator 106.
[0036] The charge pump regulation system 100 of the present invention will be described below using a programming operation as an example. When the non-volatile memory is programmed, the output voltage V of the charge pump regulation system 100 is... OUT That is, equal to the programming voltage V PP Furthermore, the output voltage V OUT (Programming voltage V) PP via power switch P SW The signal is transmitted to the memory cell array 130, enabling the non-volatile memory to be programmed. Of course, the charge pump regulation system 100 of this invention can also be used for the erase operation. During the erase operation, the output voltage V of the charge pump regulation system 100... OUT That is, the erasure voltage V EE .
[0037] like Figure 1A As shown, in the charge pump regulation system 100, the output terminal of the charge pump 102 is connected to the power switch P. SW The memory cell array 130 is coupled to non-volatile memory. Furthermore, the power switch P... SW Receive a program enable signal (EN) PGM ).
[0038] The control terminal of charge pump 102 receives a control signal CTL, and the output terminal of charge pump 102 generates an output voltage V. OUT This output voltage V OUT That is, the programming voltage V PP For example, when the control signal CTL is at a logic low level (Lo), the charge pump 102 operates normally. Conversely, when the control signal CTL is at a logic high level (Hi), the charge pump 102 stops operating.
[0039] Voltage divider 104 is connected to the output terminal of charge pump 102 to receive the output voltage V. OUT For example, voltage divider 104 is connected to the output of charge pump 102 and the supply voltage V. SS Between, and the supply voltage V SS This is equal to the ground voltage (0V). Furthermore, voltage divider 102 generates a feedback voltage (V). FB Among them, the output voltage V OUT With feedback voltage V FB There is a ratio R between them ATIO Relationship. For example, voltage divider 102 is a resistive voltage divider with a ratio R. ATIO It can be adjusted appropriately, and R ATIO =VFB / V OUT Among them, R ATIO Greater than 0 and R ATIO Less than or equal to 1.
[0040] The positive input terminal of comparator 106 receives the feedback voltage V. FB The negative input terminal of comparator 106 receives the reference voltage V. REF The output of comparator 106 generates a control signal CTL. When the feedback voltage V... FB Greater than the reference voltage V REF When the control signal CTL is at a logic high level (Hi) and charge pump 102 stops working, the feedback voltage V... FB Less than the reference voltage V REF At this time, the control signal CTL is at logic low (Lo) and the charge pump 102 is working normally.
[0041] In other words, when the charge pump regulation system 100 is operating normally, the feedback voltage V FB Almost equal to the reference voltage V REF Therefore, the output voltage V OUT equals V REF / R ATIO For example, the reference voltage V REF Equal to 2.5V, proportional value R ATIO If the value is equal to 0.285, then the output voltage V OUT (Programming voltage V) PP This is approximately equal to 8.8V. Of course, adjusting the proportional value R appropriately... ATIO This can change the output voltage V of charge pump 102. OUT .
[0042] Please refer to Figure 1B The diagram illustrates the output voltage of the charge pump regulation system according to the first embodiment. For example, at time point t... A Previously, the non-volatile memory was programmed. At this time, the programming enable signal EN... PGM Action, power switch P SW In the closed state, the output voltage V generated by charge pump 102 OUT (Programming voltage V) PP (e.g., 8.8V) via power switch P SW The data is transmitted to memory cell array 130, enabling the non-volatile memory to perform programming operations. At time point t A Afterwards, the non-volatile memory finishes the programming process. At this point, the programming enable signal EN... PGM No action, power switch P SWIn the open state, the output voltage V generated by charge pump 102 OUT (Programming voltage V) PP The signal was not transmitted to memory cell array 130.
[0043] At time t A Due to power switch P SW The change from a closed state to an open state causes the load condition at the output of charge pump 102 to change from a heavy load to a light load. Therefore, at power switch P... SW At the instant of disconnection, an overshoot voltage of approximately 0.5V (9.3V-8.8V) will be generated at the output terminal of charge pump 102. That is, the output voltage V... OUT The voltage instantly rises from 8.8V to approximately 9.3V. Furthermore, due to the control of comparator 106, at time point t... B The output voltage V at the output terminal of charge pump 102 OUT It recovered to approximately 8.8V. The time point t... A up to time point t B It takes about 0.5 μs.
[0044] Because the output voltage V of the charge pump 102 changes the instant the programming operation stops, the charge pump regulation system 100 changes. OUT This includes a large overshoot voltage. Due to the output voltage V... OUT Excessive voltage stress can damage electronic components in non-volatile memory.
[0045] Please refer to Figure 2A The illustration depicts a charge pump regulation system according to a second embodiment of the present invention. Compared to the first embodiment, the second embodiment is a charge pump regulation system 200 having an overshoot reduction circuit 210. The charge pump regulation system 200 includes: a charge pump 102, a voltage divider 104, a comparator 220, and the overshoot reduction circuit 210.
[0046] Overshoot mitigation circuit 210 is connected to at least one sensing node in comparator 220, and is also connected to the output of charge pump 102. Furthermore, overshoot mitigation circuit 210 includes a sensing circuit 230 and a response circuit 240. Sensing circuit 230 is connected to at least one sensing node of comparator 220, and provides a pull-down signal (PD) to response circuit 240. Response circuit 240 is connected to the output of charge pump 102 and the supply voltage V. SS .
[0047] In the overshoot mitigation circuit 210, the sensing circuit 230 detects the voltage change at least one sensing node in the comparator 220 to determine the output voltage V of the charge pump 102. OUT Does it include overshoot voltage? The output voltage V of charge pump 102... OUT Without overshoot voltage, the sensing circuit 230 does not activate the pull-down signal PD, and the response circuit 240 does not operate. This is in contrast to the operation of the charge pump 102 output voltage V. OUT When an overshoot voltage is detected, the sensing circuit 230 pulls down the signal PD, and the response circuit 240 operates. Therefore, the response circuit 240 provides a pull-down path connected to the output of the charge pump 102 and the supply voltage V. SS Between, used to reduce the output voltage V of charge pump 102 OUT .
[0048] Please refer to Figure 2B The diagram illustrates the output voltage of the charge pump regulation system according to the second embodiment. For example, at time point t... A Previously, the non-volatile memory was programmed. At this time, the programming enable signal EN... PGM Action, power switch P SW When in the closed state, the output voltage V generated by charge pump 102 OUT (Programming voltage V) PP (e.g., 8.8V) via power switch P SW The data is transferred to memory cell array 130. Furthermore, at time point t... A Afterwards, the non-volatile memory finishes the programming process. At this point, the programming enable signal EN... PGM No action, power switch P SW When in the off state, the output voltage V generated by charge pump 102 OUT (Programming voltage V) PP The signal was not transmitted to memory cell array 130.
[0049] At time t ADue to power switch P SW When the charge pump 102 switches from a closed state to an open state, the load condition at the output terminal changes from a heavy load to a light load, resulting in an output voltage V. OUT The voltage spikes instantaneously. In other words, the output voltage VOUT includes an overshoot voltage. Furthermore, in the overshoot mitigation circuit 210, the sensing circuit 230 determines the output voltage VOUT based on the voltage change at least one sensing node within the comparator 220. OUT Does it include overshoot voltage? When the sensing circuit 230 confirms the output voltage V OUT When an overshoot voltage occurs, the sensing circuit 230 pulls down the signal PD, causing the reaction circuit 240 to operate and reducing the output voltage V of the charge pump 102. OUT .
[0050] Depend on Figure 2B It can be seen that at time point t A Then, the output voltage V of the solid line OUT The voltage rises only momentarily to approximately 9.12V, meaning the overshoot voltage is only about 0.32V (9.12V - 8.8V). This is compared to the dashed output voltage V in the first embodiment. OUT The overshoot mitigation circuit 210 of the present invention can mitigate an overshoot voltage of approximately 0.18V (0.5V-0.32V). That is, the overshoot mitigation circuit 210 can effectively reduce the overshoot voltage by approximately 36%. Furthermore, at time point t... C The output voltage V at the output terminal of charge pump 102 OUT It recovered to approximately 8.8V. The time point t... A up to time point t C The time is approximately 0.3 μs. In other words, the charge pump regulation system 200 of the second embodiment of the present invention can also effectively shorten the impact caused by overshoot voltage.
[0051] The following details various comparators used in the charge pump regulation system 200 of the second embodiment, as well as the overshoot mitigation circuits used with these comparators.
[0052] Please refer to Figure 3A The diagram illustrates a first comparator and a corresponding overshoot mitigation circuit in the charge pump regulation system of the second embodiment. The overshoot mitigation circuit 310 includes a sensing circuit 330 and a response circuit 340.
[0053] Comparator 320 includes three current mirrors 322, 324, and 326, and transistors M1, M2, and M3. Transistors M1, M2, and M3 are n-type transistors. Transistors M1 and M2 form a differential pair, with one input terminal of the differential pair serving as the positive input terminal of comparator 320, and the other input terminal serving as the negative input terminal. For example, the first drain / source terminal of transistor M1 is connected to the first sensing node s. N1 The second drain / source terminal of transistor M1 is connected to node a, and the gate terminal of transistor M1 serves as the positive input terminal of comparator 320, receiving the feedback voltage V. FB The first drain / source terminal of transistor M2 is connected to node b, and the second drain / source terminal of transistor M2 is connected to node a. The gate terminal of transistor M2 serves as the negative input terminal of comparator 320, receiving the reference voltage V. REF The first drain / source terminal of transistor M3 is connected to node a, and the second drain / source terminal of transistor M3 receives the supply voltage V. SS The gate of transistor M3 receives a bias voltage V. B1 .
[0054] Current mirror 322 receives the supply voltage V DD The current input terminal of the current mirror 322 is connected to the first sensing node s. N1 The current mirror 322's current mirror emitter is connected to node c, and node c is the output of comparator 320, generating a control signal CTL. For example, the current mirror 322 includes transistors M4 and M5, which are p-type transistors. The first drain / source terminal of transistor M4 receives the supply voltage V. DD The second drain / source terminal of transistor M4 is connected to node c, and the gate terminal of transistor M4 is connected to the first sensing node s. N1 The first drain / source terminal of transistor M5 receives the supply voltage V. DD The second drain / source terminal of transistor M5 is connected to the first sensing node s. N1 The gate of transistor M5 is connected to the first sensing node s. N1 Among them, the supply voltage V DD Greater than the supply voltage V SS For example, the supply voltage V DD The supply voltage is 3.3V, V. SS It is 0V.
[0055] Current mirror 324 receives supply voltage V DDThe current input terminal of the current mirror 324 is connected to node b, and the current mirror emitter of the current mirror 324 is connected to the second sensing node s. N2 For example, the current mirror 324 includes transistors M6 and M7, which are p-type transistors. The first drain / source terminal of transistor M6 receives the supply voltage V. DD The second drain / source terminal of transistor M6 is connected to node b, and the gate terminal of transistor M6 is also connected to node b. The first drain / source terminal of transistor M7 receives the supply voltage V. DD The second drain / source terminal of transistor M7 is connected to the second sensing node s. N2 The gate of transistor M7 is connected to node b.
[0056] Current mirror 326 receives the supply voltage V SS The current input terminal of the current mirror 326 is connected to the second sensing node s. N2 The current mirror emitter of current mirror 326 is connected to node c. For example, current mirror 326 includes transistors M8 and M9, which are n-type transistors. The first drain / source terminal of transistor M8 is connected to node c, and the second drain / source terminal of transistor M8 receives the supply voltage V. SS The gate of transistor M8 is connected to the second sensing node s. N2 The first drain / source terminal of transistor M9 is connected to the second sensing node s. N2 The second drain / source terminal of transistor M9 receives the supply voltage V. SS The gate of transistor M9 is connected to the second sensing node s. N2 .
[0057] The sensing circuit 330 includes: transistor M A M B Among them, transistor M A It is a p-type transistor, transistor M B It is an n-type transistor. Transistor M A The first drain / source terminal receives the supply voltage V DD transistor M A The second drain / source terminal is connected to node d, transistor M A The gate terminal is connected to the first sensing node s N1 Node d is the output of sensing circuit 330, and the voltage at node d can be used as a pull-down signal (PD). Transistor M B The first drain / source terminal is connected to node d, transistor M B The second drain / source terminal receives the supply voltage V SS transistor M B The gate terminal receives the bias voltage V from comparator 320. B1Among them, the bias voltage V B1 It is a fixed value, and transistor M B It can be considered as a resistor.
[0058] The reaction circuit 340 includes: a pull-down transistor (M... PD Pull-down transistor M PD It is an n-type transistor. Pull-down transistor M PD The first drain / source terminal is connected to the output terminal of charge pump 102, pulling down transistor M. PD The second drain / source terminal receives the supply voltage V SS Pull-down transistor M PD The gate terminal is connected to node d to receive the pull-down signal PD.
[0059] For example, when charge pump 102 does not generate overshoot voltage, node d is controlled by transistor M. B Pull-down to supply voltage V SS This indicates that the pull-down signal PD is not activated. Additionally, at the instant the charge pump 102 generates overshoot voltage, the output voltage V... OUT The voltage rises rapidly. In comparator 320, the feedback voltage V... FB Greater than the reference voltage V REF And cause the first sensing node s N1 The voltage at node b decreases while the voltage at node b increases. Furthermore, the increased voltage at node b causes a drop in the voltage at the second sensing node s. N2 The voltage drops.
[0060] In the sensing circuit 330, due to the first sensing node s N1 The voltage drop causes transistor M to... A When the transistor M is activated, the voltage at node d is controlled by the transistor M. A Pull-up to the supply voltage V DD This indicates that the pull-down signal PD is activated. In other words, when the pull-down signal PD is activated, the pull-down transistor M in the response circuit 340... PD Turn on. Therefore, pull-down transistor M PD A pull-down path is formed between the two drain / source terminals, connected to the output of charge pump 102 and the supply voltage V. SS Between, the output voltage V of charge pump 102 is made OUT decline.
[0061] Of course, this invention can also be modified. Figure 3A The overshoot mitigation circuit 310 includes a sensing circuit 330 and a response circuit 340. These will be explained below.
[0062] Please refer to Figure 3B The diagram illustrates another example of a sensing circuit. Compared to Figure 3A The sensing circuit 330, in Figure 3B In the sensing circuit 332, a resistor R is used instead of a transistor M. B In other words, the first terminal of resistor R is connected to node d, and the second terminal of resistor receives the supply voltage V. SS .basically, Figure 3B The sensing circuit 332 and Figure 3A The sensing circuit 330 operates in a similar manner, and will not be described in detail here.
[0063] exist Figure 3A and Figure 3B The sensing circuits 330 and 332 are both connected to the first sensing node s of the comparator 320. N1 And according to the first sensing node s N1 Determine the output voltage V by voltage change OUT Is there an overvoltage? Of course, the sensing circuit can also be connected to more sensing nodes.
[0064] Please refer to Figure 3C The diagram illustrates yet another example of a sensing circuit. Compared to Figure 3A The sensing circuit 330, in Figure 3C In the sensing circuit 334, transistor M B The gate is connected to the second sensing node of comparator 320. N2 Apart from that, the connection relationships of other components in sensing circuit 334 are the same as those in sensing circuit 330, and will not be described again here.
[0065] For example, node d of sensing circuit 334 is connected to reaction circuit 340. When charge pump 102 does not generate overshoot voltage, node d is pulled down to the supply voltage V. SS This indicates that the pull-down signal PD is not activated. At the instant that charge pump 102 generates overshoot voltage, the output voltage V... OUT The voltage rises rapidly. In comparator 320, the feedback voltage V... FB Greater than the reference voltage V REF This causes the first sensing node s N1 The voltage at node b decreases while the voltage at node b increases. Furthermore, the increased voltage at node b causes a drop in the voltage at the second sensing node s. N2 The voltage drops.
[0066] In the sensing circuit 334, due to the first sensing node s N1 With the second sensing node s N2 The voltage drop causes transistor M to...A Turn on and transistor M B Shutdown, node d voltage rises to supply voltage V. DD This indicates that the pull-down signal PD is activated. In other words, when the pull-down signal PD is activated, the pull-down transistor M in the response circuit 340... PD Turn on. Therefore, pull-down transistor M PD A pull-down path is formed between the two drain / source terminals, connected to the output of charge pump 102 and the supply voltage V. SS Between, the output voltage V of charge pump 102 is made OUT decline.
[0067] Please refer to Figure 3D This is another example of a reactive circuit, as illustrated in the diagram. Compared to... Figure 3A The reaction circuit 340, in this example of the reaction circuit 342, also includes a transistor M. EN And transistor M EN It is an n-type transistor. Transistor M EN The first drain / source terminal is connected to node d, transistor M EN The second drain / source terminal receives the supply voltage V SS transistor M EN The gate terminal receives the enable signal EN.
[0068] For example, node d of sensing circuit 330 is connected to response circuit 342, forming an overshoot mitigation circuit. When enable signal EN is not activated (e.g., logic high level), transistor M... EN The circuit is turned on and the voltage at node d is equal to the supply voltage V. SS That is, the pull-down signal PD did not activate, and the pull-down transistor M of the reaction circuit 342 was activated. PD Turning off indicates that the overshoot mitigation circuit is not operating. When the enable signal EN is activated (e.g., logic low level), transistor M... EN When turned off, the overshoot mitigation circuit is operational. At this time, the sensing circuit 330 can detect the overshoot voltage and appropriately pull down the PD signal. In other words, the enable signal EN is used to control the timing of the overshoot mitigation circuit's operation and prevent malfunctions.
[0069] Please refer to Figure 3E This is another example of a reactive circuit. Compared to Figure 3D Pull-down transistor M in the reaction circuit 340 PD It is an n-type transistor. Figure 3E Pull-down transistor M in the reaction circuit 344 DIt is a p-type transistor. The reaction circuit 344 includes: a level shifter 349 and a pull-down transistor M. D The first power terminal of transformer 349 receives the output voltage V. OUT The second power supply terminal of transformer 349 receives the supplied voltage V. SS The input of transformer 349 is connected to node d to receive the pull-down signal PD, and the output of the transformer generates an inverted pull-down signal PD. B Furthermore, transistor M D The first drain / source terminal receives the output voltage V OUT transistor M D The second drain / source terminal receives the supply voltage V SS transistor M D The gate terminal receives the inverted pull-down signal PD. B .
[0070] For example, when the pull-down signal PD is not activated, the pull-down signal PD is the supply voltage V. SS The inverted pull-down signal PD output by transformer 349 B For the output voltage V OUT Therefore, the pull-down transistor MD is turned off. When the pull-down signal PD is activated, the pull-down signal PD is the supply voltage V. DD The inverted pull-down signal PD output by transformer 249 B For supply voltage V SS Therefore, pull-down transistor MD is turned on, and pull-down transistor M... D A pull-down path is formed between the two drain / source terminals, connected to the output of charge pump 102 and the supply voltage V. SS Between, the output voltage V of charge pump 102 is made OUT decline.
[0071] Please refer to Figure 3F This is another example of a reactive circuit. Compared to Figure 3E The reaction circuit 344 in this example, the reaction circuit 346, also includes a transistor M. EN And transistor M EN It is an n-type transistor. Transistor M EN The first drain / source terminal is connected to node d, transistor M EN The second drain / source terminal receives the supply voltage V SS transistor M EN The gate terminal receives the enable signal EN.
[0072] Similar to Figure 3DIn the reaction circuit 346, the enable signal EN is used to control the timing of the overshoot mitigation circuit operation and to prevent the overshoot mitigation circuit from malfunctioning.
[0073] According to a second embodiment of the present invention, sensing circuits 330, 332, and 334 can be combined with response circuit 340 to form an overshoot mitigation circuit. Sensing circuits 330, 332, and 334 can be combined with response circuit 342 to form an overshoot mitigation circuit. Sensing circuits 330, 332, and 334 can be combined with response circuit 344 to form an overshoot mitigation circuit. Sensing circuits 330, 332, and 334 can be combined with response circuit 346 to form an overshoot mitigation circuit. All of the above-mentioned overshoot mitigation circuits, when combined with comparator 320, can achieve the purpose of reducing overshoot voltage as described in the present invention.
[0074] Furthermore, this invention can be modified. Figure 3A The comparator 320 and sensing circuit 330 are described below, and p-type transistors are used to replace n-type transistors in the comparator 320 and sensing circuit 330, and n-type transistors are used to replace p-type transistors in the comparator 320 and sensing circuit 330.
[0075] Please refer to Figure 4A The diagram illustrates a second comparator and a corresponding overshoot mitigation circuit in the charge pump regulation system of the second embodiment. The overshoot mitigation circuit 410 includes a sensing circuit 430 and a response circuit 340.
[0076] Comparator 420 includes three current mirrors 422, 424, and 426, and transistor M. 1a M 2a M 3a Among them, transistor M 1a M 2a M 3a It is a p-type transistor. Transistor M 1a M 2a A differential pair is formed, with one input terminal of the differential pair serving as the positive input terminal of comparator 420, and the other input terminal of the differential pair serving as the negative input terminal of comparator 420. For example, transistor M... 1a The first drain / source terminal is connected to the first sensing node s N1 transistor M 1a The second drain / source terminal is connected to node a, transistor M 1a The gate terminal serves as the positive input terminal of comparator 420, receiving the feedback voltage V. FB Transistor M 2a The first drain / source terminal is connected to node b, transistor M 2a The second drain / source terminal is connected to node a, transistor M 2a The gate terminal serves as the negative input terminal of comparator 420, receiving the reference voltage V.REF Transistor M 3a The first drain / source terminal is connected to node a, transistor M 3a The second drain / source terminal receives the supply voltage V DD transistor M 3a The gate terminal receives a bias voltage V B2 .
[0077] Current mirror 422 receives the supply voltage V SS The current input terminal of the current mirror 422 is connected to the first sensing node s. N1 The current mirror emitter of current mirror 422 is connected to node c, and node c serves as the output of comparator 420, generating the control signal CTL. For example, current mirror 422 includes transistor M. 4a M 5a transistor M 4a M 5a It is an n-type transistor. Transistor M 4a The first drain / source terminal receives the supply voltage V SS transistor M 4a The second drain / source terminal is connected to node c, transistor M 4a The gate terminal is connected to the first sensing node s N1 Transistor M 5a The first drain / source terminal receives the supply voltage V SS transistor M 5a The second drain / source terminal is connected to the first sensing node. N1 transistor M 5a The gate terminal is connected to the first sensing node s N1 Among them, the supply voltage V DD Greater than the supply voltage V SS For example, the supply voltage V DD The supply voltage is 3.3V, V. SS It is 0V.
[0078] Current mirror 424 receives supply voltage V SS The current input terminal of the current mirror 424 is connected to node b, and the current mirror emitter of the current mirror 424 is connected to the second sensing node s. N2 For example, the current mirror 424 includes transistor M. 6a M 7a transistor M 6a M 7a It is an n-type transistor. Transistor M 6a The first drain / source terminal receives the supply voltage V SS transistor M 6a The second drain / source terminal is connected to node b, transistor M 6a The gate terminal of transistor M is connected to node b.7a The first drain / source terminal receives the supply voltage V SS transistor M 7a The second drain / source terminal is connected to the second sensing node. N2 transistor M 7a The gate terminal is connected to node b.
[0079] Current mirror 426 receives the supply voltage V DD The current input terminal of the current mirror 426 is connected to the second sensing node s. N2 The current mirror emitter of current mirror 426 is connected to node c. For example, current mirror 426 includes transistor M. 8a M 9a transistor M 8a M 9a It is a p-type transistor. Transistor M 8a The first drain / source terminal is connected to node c, transistor M 8a The second drain / source terminal receives the supply voltage V DD transistor M 8a The gate terminal is connected to the second sensing node s N2 Transistor M 9a The first drain / source terminal is connected to the second sensing node. N2 transistor M 9a The second drain / source terminal receives the supply voltage V DD transistor M 9a The gate terminal is connected to the second sensing node s N2 .
[0080] The sensing circuit 430 is connected to the response circuit 340. The sensing circuit 430 includes: a transistor M. Aa M Ba Among them, transistor M Aa It is an n-type transistor, transistor M Ba It is a p-type transistor. Transistor M Aa The first drain / source terminal receives the supply voltage V SS transistor M Aa The second drain / source terminal is connected to node d, transistor M Aa The gate terminal is connected to the first sensing node s N1 Node d is the output of sensing circuit 430, and the voltage at node d can serve as a pull-down signal PD. Transistor M Ba The first drain / source terminal is connected to node d, transistor M Ba The second drain / source terminal receives the supply voltage V DD transistor M Ba The gate terminal receives the bias voltage V from comparator 420. B2 Among them, the bias voltage VB2 It is a fixed value, and transistor M Ba It can be considered as a resistor.
[0081] For example, when charge pump 102 does not generate overshoot voltage, node d is pulled down to the supply voltage V. SS This indicates that the pull-down signal PD is not activated. Additionally, at the instant the charge pump 102 generates an overshoot voltage, the output voltage V... OUT Rapid rise. In comparator 420, the feedback voltage V FB Greater than the reference voltage V REF And cause the first sensing node s N1 The voltage at node b decreases while the voltage at node b increases. Furthermore, the increased voltage at node b causes a drop in the voltage at the second sensing node s. N2 The voltage drops.
[0082] In the sensing circuit 430, due to the first sensing node s N1 The voltage drop causes transistor M to... Aa Shutdown, node d voltage rises to supply voltage V. DD This indicates that the pull-down signal PD is activated. In other words, when the pull-down signal PD is activated, the pull-down transistor M in the response circuit 340... PD Turn on, pull down transistor M PD A pull-down path is formed between the two drain / source terminals, connected to the output of charge pump 102 and the supply voltage V. SS Between, the output voltage V of charge pump 102 is made OUT decline.
[0083] Similarly, the sensing circuit 430 in the overshoot mitigation circuit 410 can also be modified according to the present invention. Please refer to Figure 4B The diagram illustrates another example of a sensing circuit. Compared to Figure 4A The sensing circuit 430 in the middle, in Figure 4B In the sensing circuit 432, a resistor R is used instead of a transistor M. Ba In other words, the first terminal of resistor R is connected to node d, and the second terminal of resistor receives the supply voltage V. DD .basically, Figure 4B The sensing circuit 432 and Figure 4A The sensing circuit 430 operates in a similar manner, and will not be described in detail here.
[0084] Please refer to Figure 4C The diagram illustrates yet another example of a sensing circuit. Compared to Figure 4A The sensing circuit 430, in Figure 4C In the sensing circuit 434, transistor M BaThe gate is connected to the second sensing node s of comparator 420 N2 Apart from that, the connection relationships of other components in sensing circuit 434 are the same as those in sensing circuit 430, and will not be described again here.
[0085] For example, node d of sensing circuit 434 is connected to reaction circuit 340. When charge pump 102 does not generate overshoot voltage, node d is pulled down to the supply voltage V. SS This indicates that the pull-down signal PD is not activated. At the instant that charge pump 102 generates overshoot voltage, the output voltage V... OUT Rapid rise. In comparator 420, the feedback voltage V FB Greater than the reference voltage V REF And cause the first sensing node s N1 The voltage at node b decreases while the voltage at node b increases. Furthermore, the increased voltage at node b causes a drop in the voltage at the second sensing node s. N2 The voltage drops.
[0086] In the sensing circuit 434, due to the first sensing node s N1 With the second sensing node s N2 The voltage drop causes transistor M to... Aa Turn off and transistor M Ba When activated, the voltage at node d rises to the supply voltage V. DD This indicates that the pull-down signal PD is activated. In other words, when the pull-down signal PD is activated, the pull-down transistor M in the response circuit 340... PD Turn on, pull down transistor M PD A pull-down path is formed between the two drain / source terminals, connected to the output of charge pump 102 and the supply voltage V. SS Between, the output voltage V of charge pump 102 is made OUT decline.
[0087] Furthermore, sensing circuits 430, 432, and 434 can be combined with response circuit 340 to form an overshoot mitigation circuit. Sensing circuits 430, 432, and 434 can be combined with response circuit 342 to form an overshoot mitigation circuit. Sensing circuits 430, 432, and 434 can be combined with response circuit 344 to form an overshoot mitigation circuit. Sensing circuits 430, 432, and 434 can be combined with response circuit 346 to form an overshoot mitigation circuit. All of the above-mentioned overshoot mitigation circuits, combined with comparator 420, can achieve the purpose of reducing overshoot voltage in this invention.
[0088] Please refer to Figure 5A The diagram illustrates the third comparator and corresponding overshoot mitigation circuit in the charge pump regulation system of the second embodiment. Figure 5A The overshoot mitigation circuit 310 is the same as Figure 3A The overshoot mitigation circuit 310 will not be described in detail here.
[0089] Comparator 520 includes a current mirror 522 and a transistor M. 1b M 2b M 3b Among them, transistor M 1b M 2b M 3b It is an n-type transistor. Transistor M 1b M 2b This forms a differential pair, where one input of the differential pair is the positive input of comparator 520, and the other input is the negative input of comparator 520. For example, transistor M... 1b The first drain / source terminal is connected to the first sensing node s N1 transistor M 1b The second drain / source terminal is connected to node a, transistor M 1b The gate terminal serves as the positive input terminal of comparator 520, receiving the feedback voltage V. FB Transistor M 2b The first drain / source terminal is connected to node b, and node b is the output of comparator 520. Transistor M 2b The second drain / source terminal is connected to node a, transistor M 2b The gate terminal serves as the negative input terminal of comparator 520, receiving the reference voltage V. REF Transistor M 3b The first drain / source terminal is connected to node a, transistor M 3b The second drain / source terminal receives the supply voltage V SS transistor M 3b The gate terminal receives a bias voltage V B3 .
[0090] Current mirror 522 receives the supply voltage V DD The current input terminal of the current mirror 522 is connected to the first sensing node s. N1 The current mirror emitter of current mirror 522 is connected to node b. For example, current mirror 522 includes transistor M. 4b M 5b transistor M 4b M 5b It is a p-type transistor. Transistor M 4b The first drain / source terminal receives the supply voltage V DD transistor M 4b The second drain / source terminal is connected to node b, transistor M 4b The gate terminal is connected to the first sensing node s N1 Transistor M 5bThe first drain / source terminal receives the supply voltage V DD transistor M 5b The second drain / source terminal is connected to the first sensing node. N1 transistor M 5b The gate terminal is connected to the first sensing node s N1 Among them, the supply voltage V DD Greater than the supply voltage V SS For example, the supply voltage V DD The supply voltage is 3.3V, V. SS It is 0V.
[0091] In addition, the overshoot mitigation circuit 310 is the same as Figure 3A The overshoot mitigation circuit 310 is described in detail below.
[0092] For example, at the instant when the charge pump 102 generates an overshoot voltage, the output voltage V OUT Rapid rise. In comparator 520, the feedback voltage V FB Greater than the reference voltage V REF And cause the first sensing node s N1 The voltage at node b decreases while the voltage at node b increases.
[0093] In the sensing circuit 330, due to the first sensing node s N1 The voltage drop causes transistor M to... A When activated, the voltage at node d rises to the supply voltage V. DD This indicates that the pull-down signal PD is activated. In other words, when the pull-down signal PD is activated, the pull-down transistor M in the response circuit 340... PD Turn on. Therefore, pull-down transistor M PD A pull-down path is formed between the two drain / source terminals, causing the output voltage V of charge pump 102 to... OUT decline.
[0094] Of course, comparator 520 can also be paired with other overshoot mitigation circuits. For example, sensing circuits 330, 332, and 334 can be paired with response circuit 340 to form an overshoot mitigation circuit. Sensing circuits 330, 332, and 334 can be paired with response circuit 342 to form an overshoot mitigation circuit. Sensing circuits 330, 332, and 334 can be paired with response circuit 344 to form an overshoot mitigation circuit. Sensing circuits 330, 332, and 334 can be paired with response circuit 346 to form an overshoot mitigation circuit. All of the above-mentioned overshoot mitigation circuits, when paired with comparator 520, can achieve the purpose of reducing overshoot voltage as described in this invention.
[0095] Please refer to Figure 5BThe diagram illustrates another example of a sensing circuit. The sensing circuit 530 includes a current mirror 538 and a transistor M. Ab M Cb Among them, transistor M Ab M Cb It is a p-type transistor.
[0096] Transistor M Ab The first drain / source terminal receives the supply voltage V DD transistor M Ab The second drain / source terminal is connected to node d, transistor M Ab The gate terminal is connected to the first sensing node s N1 Node d is the output of sensing circuit 330, and the voltage at node d can be used as a pull-down signal PD. Transistor M Cb The first drain / source terminal receives the supply voltage V DD transistor M Cb The second drain / source terminal is connected to node f, transistor M Cb The gate terminal is connected to node b to receive the control signal CTL from comparator 520.
[0097] The current mirror 538 receives the supply voltage V. SS The current input terminal of current mirror 538 is connected to node f, and the current mirror emitter of current mirror 538 is connected to node d. For example, current mirror 538 includes: transistor M. Bb Transistor M Db transistor M Bb M Db It is an n-type transistor. Transistor M Bb The first drain / source terminal is connected to node d, transistor M Bb The second drain / source terminal receives the supply voltage V SS transistor M Bb The gate terminal of transistor M is connected to node f. Db The first drain / source terminal is connected to node f, transistor M Db The second drain / source terminal receives the supply voltage V SS transistor M Db The gate terminal is connected to node f.
[0098] For example, node d of sensing circuit 530 is connected to reaction circuit 340. At the instant the charge pump 102 generates an overshoot voltage, the output voltage V... OUT Rapid rise. In comparator 520, the feedback voltage V FB Greater than the reference voltage V REF This causes the first sensing node s N1 The voltage at node b decreases while the voltage at node b (control signal CTL) increases.
[0099] In the sensing circuit 530, the voltage at node b increases, causing the voltage at node f to decrease. This is due to the voltage at the first sensing node s... N1 With the voltage drop at node f, transistor M Ab Turn on and transistor M Bb Shutdown, node d voltage rises to supply voltage V. DD This indicates that the pull-down signal PD is activated. In other words, when the pull-down signal PD is activated, the pull-down transistor M in the response circuit 340... PD Turn on. Therefore, pull-down transistor M PD A pull-down path is formed between the two drain / source terminals, connected to the output of charge pump 102 and the supply voltage V. SS Between, the output voltage V of charge pump 102 is made OUT decline.
[0100] Please refer to Figure 5C The diagram illustrates yet another example of a sensing circuit. Compared to Figure 5B The sensing circuit 530, in this example, the sensing circuit 532, also includes a transistor M. Eb transistor M Eb It is an n-type transistor. Transistor M Eb The first drain / source terminal is connected to node f, transistor M Eb The second drain / source terminal receives the supply voltage V SS transistor M Eb The gate terminal receives the enable signal EN.
[0101] For example, node d of sensing circuit 532 is connected to response circuit 340. When enable signal EN is not activated (e.g., logic high level), transistor M... Eb When the circuit is turned on, the voltage at node f equals the supply voltage V. SS This indicates that the reaction circuit 340 is not operating. When the enable signal EN is activated (e.g., logic low level), transistor M... Eb When turned off, the reaction circuit 340 is operational. At this time, the sensing circuit 532 can detect overshoot voltage and appropriately pull down the signal PD. In other words, the enable signal EN is used to control the timing of the reaction circuit 340's operation.
[0102] Of course, sensing circuits 530 and 532 can be combined with response circuit 340 to form an overshoot mitigation circuit. Sensing circuits 530 and 532 can be combined with response circuit 342 to form an overshoot mitigation circuit. Sensing circuits 530 and 532 can be combined with response circuit 344 to form an overshoot mitigation circuit. Sensing circuits 530 and 532 can be combined with response circuit 346 to form an overshoot mitigation circuit. The above-mentioned overshoot mitigation circuits, combined with comparator 520, can all achieve the purpose of reducing overshoot voltage of the present invention.
[0103] Basically, in all the sensing circuits described above in this invention, the circuit is connected to the supply voltage V. SS The components have strong driving capability and are connected to the supply voltage V. DD The electronic components have relatively weak driving capabilities. Taking the sensing circuit 330 as an example, transistor M... B The driving capability is greater than that of transistor M. A The driving capability. Therefore, due to transistor M B The driving capability is greater than that of transistor M. A The driving capability at the output voltage V OUT When overshoot voltage is not included, transistor M B It will pull the voltage at node d to the supply voltage V. SS This indicates that the pull-down signal PD has not been activated.
[0104] As described above, this invention proposes a charge pump regulation system with an overshoot mitigation circuit. The overshoot mitigation circuit includes a sensing circuit and a response circuit. The sensing circuit detects voltage changes at a sensing node to determine whether the output voltage of the charge pump includes an overshoot voltage. When the output voltage of the charge pump does not include an overshoot voltage, the response circuit does not operate. When it is confirmed that the output voltage of the charge pump includes an overshoot voltage, the response circuit operates and reduces the output voltage of the charge pump.
[0105] In summary, although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be determined by the appended claims.
Claims
1. A charge pump regulation system, wherein the output voltage generated by the charge pump regulation system is transmitted to a memory cell array via a power switch, the charge pump regulation system comprising: A charge pump, wherein the control terminal of the charge pump receives a control signal and the output terminal of the charge pump generates the output voltage; A voltage divider receives the output voltage and generates a feedback voltage. A comparator, wherein the first input terminal of the comparator receives the feedback voltage, the second input terminal of the comparator receives the reference voltage, and the output terminal of the comparator generates the control signal; as well as The overshoot mitigation circuit includes a sensing circuit and a response circuit. The sensing circuit is connected to the first sensing node in the comparator, and the response circuit is connected to the output terminal of the charge pump. Specifically, when the sensing circuit confirms that the output voltage includes an overshoot voltage based on a signal from the first sensing node, the sensing circuit activates a pull-down signal; and, based on the activated pull-down signal, the response circuit reduces the output voltage.
2. The charge pump regulation system as claimed in claim 1, wherein there is a proportional relationship between the feedback voltage and the output voltage, the output voltage is approximately equal to the reference voltage divided by the proportional value, the proportional value is greater than zero, and the proportional value is less than or equal to 1.
3. The charge pump regulation system of claim 1, wherein the comparator comprises: A first type transistor, wherein the first drain / source terminal of the first type transistor is connected to the first sensing node, the second drain / source terminal of the first type transistor is connected to the first node, and the gate terminal of the first type transistor receives the feedback voltage; A second first-type transistor, wherein the first drain / source terminal of the second first-type transistor is connected to the second node, the second drain / source terminal of the second first-type transistor is connected to the first node, and the gate terminal of the second first-type transistor receives the reference voltage; A third type I transistor has a first drain / source terminal connected to the first node, a second drain / source terminal receiving a first supply voltage, and a gate terminal receiving a bias voltage. A first current mirror receives a second supply voltage. The current input terminal of the first current mirror is connected to the first sensing node, and the current mirror emitter of the first current mirror is connected to a third node, which is the output terminal of the comparator. The second current mirror receives the second supply voltage, the current input terminal of the second current mirror is connected to the second node, and the current mirror emitter of the second current mirror is connected to the second sensing node. as well as The third current mirror receives the first supply voltage, the current input terminal of the third current mirror is connected to the second sensing node, and the current mirror emitter of the third current mirror is connected to the third node.
4. The charge pump regulation system of claim 3, wherein the first current mirror comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to the third node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as The second type II transistor has a first drain / source terminal receiving the second supply voltage, a second drain / source terminal connected to the first sensing node, and a gate terminal connected to the first sensing node.
5. The charge pump regulation system of claim 4, wherein the second current mirror comprises: The third type II transistor has a first drain / source terminal receiving the second supply voltage, a second drain / source terminal connected to the second node, and a gate terminal connected to the second node. as well as A fourth type II transistor, wherein the first drain / source terminal of the fourth type II transistor receives the second supply voltage, the second drain / source terminal of the fourth type II transistor is connected to the second sensing node, and the gate terminal of the fourth type II transistor is connected to the second node.
6. The charge pump regulation system of claim 5, wherein the third current mirror comprises: A fourth type-1 transistor, wherein the first drain / source terminal of the fourth type-1 transistor is connected to the third node, the second drain / source terminal of the fourth type-1 transistor receives the first supply voltage, and the gate terminal of the fourth type-1 transistor is connected to the second sensing node; as well as A fifth type-1 transistor, wherein the first drain / source terminal of the fifth type-1 transistor is connected to the second sensing node, the second drain / source terminal of the fifth type-1 transistor receives the first supply voltage, and the gate terminal of the fifth type-1 transistor is connected to the second sensing node.
7. The charge pump regulation system of claim 3, wherein the sensing circuit comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to the fourth node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as A fourth type-1 transistor, wherein the first drain / source terminal of the fourth type-1 transistor is connected to the fourth node, the second drain / source terminal of the fourth type-1 transistor receives the first supply voltage, and the gate terminal of the fourth type-1 transistor receives the bias voltage; The voltage of the fourth node serves as the pull-down signal.
8. The charge pump regulation system of claim 3, wherein the sensing circuit comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to the fourth node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as A resistor, the first end of which is connected to the fourth node, and the second end of which receives the first supply voltage; The voltage of the fourth node serves as the pull-down signal.
9. The charge pump regulation system of claim 3, wherein the sensing circuit comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to the fourth node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as A fourth type-1 transistor, wherein the first drain / source terminal of the fourth type-1 transistor is connected to the fourth node, the second drain / source terminal of the fourth type-1 transistor receives the first supply voltage, and the gate terminal of the fourth type-1 transistor is connected to the second sensing node; The voltage of the fourth node serves as the pull-down signal.
10. The charge pump regulation system of claim 9, wherein the first first-type transistor, the second first-type transistor, the third first-type transistor, and the fourth first-type transistor are n-type transistors, the first second-type transistor is a p-type transistor, and the second supply voltage is greater than the first supply voltage; or, the first first-type transistor, the second first-type transistor, the third first-type transistor, and the fourth first-type transistor are p-type transistors, the first second-type transistor is an n-type transistor, and the first supply voltage is greater than the second supply voltage.
11. The charge pump regulation system of claim 1, wherein the reaction circuit comprises: A pull-down transistor, wherein the first drain / source terminal of the pull-down transistor is connected to the output terminal of the charge pump, the second drain / source terminal of the pull-down transistor receives the ground voltage, and the gate terminal of the pull-down transistor receives the pull-down signal; When the pull-down signal is activated, the pull-down transistor is turned on, and a pull-down path is formed between the first drain / source terminal and the second drain / source terminal of the pull-down transistor, connecting the output terminal of the charge pump and the ground voltage.
12. The charge pump regulation system of claim 11, wherein the reaction circuit further comprises: A first transistor, wherein the first drain / source terminal of the first transistor is connected to the gate terminal of the pull-down transistor, the second drain / source terminal of the first transistor receives the ground voltage, and the gate terminal of the first transistor receives a signal. The pull-down transistor and the first transistor are both n-type transistors. When the enable signal is not activated, the first transistor is turned on and the pull-down signal is not activated.
13. The charge pump regulation system of claim 1, wherein the reaction circuit comprises: A transformer, the first power supply terminal of which is connected to the output terminal of the charge pump, the second power supply terminal of which receives a ground voltage, the input terminal of which receives the pull-down signal, and the output terminal of which generates an inverted pull-down signal; as well as A pull-down transistor, wherein the first drain / source terminal of the pull-down transistor is connected to the output terminal of the charge pump, the second drain / source terminal of the pull-down transistor receives the ground voltage, and the gate terminal of the pull-down transistor receives the inverted pull-down signal; When the pull-down signal is activated, the pull-down transistor is turned on, and a pull-down path is formed between the first drain / source terminal and the second drain / source terminal of the pull-down transistor, connecting the output terminal of the charge pump and the ground voltage.
14. The charge pump regulation system of claim 13, wherein the reaction circuit further comprises: A first transistor, wherein the first drain / source terminal of the first transistor is connected to the gate terminal of the pull-down transistor, the second drain / source terminal of the first transistor receives the ground voltage, and the gate terminal of the first transistor receives a signal. The pull-down transistor is a p-type transistor, and the first transistor is an n-type transistor. When the enable signal is not activated, the first transistor is turned on, and the pull-down signal is not activated.
15. The charge pump regulation system of claim 1, wherein the comparator comprises: A first type transistor, wherein the first drain / source terminal of the first type transistor is connected to the first sensing node, the second drain / source terminal of the first type transistor is connected to the first node, and the gate terminal of the first type transistor receives the feedback voltage; The second type-1 transistor has its first drain / source terminal connected to the second node, its second drain / source terminal connected to the first node, its gate terminal receiving the reference voltage, and the second node being the output terminal of the comparator. A third type I transistor has a first drain / source terminal connected to the first node, a second drain / source terminal receiving a first supply voltage, and a gate terminal receiving a bias voltage. as well as A first current mirror receives a second supply voltage. The current input terminal of the first current mirror is connected to the first sensing node, and the current mirror emitter of the first current mirror is connected to the second node.
16. The charge pump regulation system of claim 15, wherein the first current mirror comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to the second node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as The second type II transistor has a first drain / source terminal receiving the second supply voltage, a second drain / source terminal connected to the first sensing node, and a gate terminal connected to the first sensing node.
17. The charge pump regulation system of claim 15, wherein the sensing circuit comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to a third node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as A fourth type-1 transistor, wherein the first drain / source terminal of the fourth type-1 transistor is connected to the third node, the second drain / source terminal of the fourth type-1 transistor receives the first supply voltage, and the gate terminal of the fourth type-1 transistor receives the bias voltage; The voltage of the third node serves as the pull-down signal.
18. The charge pump regulation system of claim 15, wherein the sensing circuit comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to a third node, and the gate terminal of the first type of transistor is connected to the first sensing node; as well as A resistor, the first end of which is connected to a third node, and the second end of which receives the first supply voltage; The voltage of the third node serves as the pull-down signal.
19. The charge pump regulation system of claim 15, wherein the sensing circuit comprises: A first type of transistor, wherein the first drain / source terminal of the first type of transistor receives the second supply voltage, the second drain / source terminal of the first type of transistor is connected to a third node, and the gate terminal of the first type of transistor is connected to the first sensing node; The second type II transistor has a first drain / source terminal receiving the second supply voltage, a second drain / source terminal connected to a fourth node, and a gate terminal connected to the second node. as well as The second current mirror receives the first supply voltage, the current input terminal of the second current mirror is connected to the fourth node, and the current mirror emitter of the second current mirror is connected to the third node. The voltage of the third node serves as the pull-down signal.
20. The charge pump regulation system of claim 19, wherein the second current mirror comprises: A fourth type-1 transistor, wherein the first drain / source terminal of the fourth type-1 transistor is connected to the third node, the second drain / source terminal of the fourth type-1 transistor receives the first supply voltage, and the gate terminal of the fourth type-1 transistor is connected to the fourth node; as well as A fifth type-1 transistor, wherein the first drain / source terminal of the fifth type-1 transistor is connected to the fourth node, the second drain / source terminal of the fifth type-1 transistor receives the first supply voltage, and the gate terminal of the fifth type-1 transistor is connected to the fourth node.
21. The charge pump regulation system of claim 20, wherein the second current mirror further comprises: A sixth type-1 transistor, wherein the first drain / source terminal of the sixth type-1 transistor is connected to the fourth node, the second drain / source terminal of the sixth type-1 transistor receives the first supply voltage, and the gate terminal of the sixth type-1 transistor receives a uniform energy signal; When the enable signal is not activated, the sixth type-1 transistor is turned on, and the voltage of the fourth node is the first supply voltage.