Power factor correction circuit, electronic device and direct current charging pile

Abstract

This application provides a power factor correction circuit, an electronic device, and a DC charging pile. The power factor correction circuit includes: a rectifier bridge and a switching transistor; a conducted interference coupling element connected to the switching transistor and having a parasitic capacitance between them, wherein the interference signal generated by the switching transistor is coupled to the conducted interference coupling element through the parasitic capacitance, and the conducted interference coupling element can emit the interference signal outward; a compensation capacitor, the first end of which is connected to the conducted interference coupling element; a main winding and an auxiliary winding wound on the same magnetic core, the main winding being connected between the rectifier bridge and the switching transistor, and the auxiliary winding being connected between the rectifier bridge and the second end of the compensation capacitor, wherein the number of turns of the auxiliary winding is the same as the number of turns of the main winding, and the auxiliary winding and the main winding are configured in an anti-phase coupling relationship so that the compensation signal induced by the auxiliary winding is coupled to the conducted interference coupling element through the compensation capacitor, and the compensation signal and the interference signal cancel each other out at the conducted interference coupling element.

Description

Technical Field

[0001] This application mainly relates to the field of power factor correction technology, and in particular to a power factor correction circuit, electronic device and DC charging pile. Background Technology

[0002] Power factor correction (PFC) circuits are core power units in switching power supplies, frequency converters, and new energy power supply equipment. They are primarily used to correct the waveform of the grid input current and improve the power factor, and are widely used in home appliances, industrial electrical control, and new energy power. Common PFC circuit topologies include Boost PFC, Buck PFC, Bridgeless PFC, Interleaved PFC, and Totem-Pole PFC. Regardless of the topology used, the rapid turn-on and turn-off of the switching transistors during PFC circuit operation generates drastic voltage and current jumps, resulting in high-frequency electromagnetic interference. Common-mode conducted interference is a key issue causing equipment to exceed EMC (Electromagnetic Compatibility) test limits and interfere with surrounding electronic equipment.

[0003] In various PFC circuits, power switching transistors typically require heat dissipation structures, and an inherent parasitic capacitance exists between the transistor and the heat dissipation structure. This parasitic capacitance is a structural parameter that cannot be eliminated. High-frequency interference signals generated by the high-frequency switching of the transistor will couple to the heat dissipation structure through this parasitic capacitance. As a large-area conductor, the heat dissipation structure will radiate and conduct these high-frequency interference signals outward, forming a major conducted emission source and causing the overall conducted emissions of the circuit to exceed the limits. Therefore, it is necessary to suppress the adverse effects of high-frequency interference signals. Summary of the Invention

[0004] This application addresses the aforementioned technical problems by providing a power factor correction circuit, electronic device, and DC charging pile, which can suppress high-frequency interference signals at the source.

[0005] To address the aforementioned technical problems, this application provides a power factor correction circuit, comprising: a rectifier bridge and a switching transistor; a conducted interference coupling element connected to the switching transistor and having a parasitic capacitance between them, wherein the interference signal generated by the switching transistor is coupled to the conducted interference coupling element through the parasitic capacitance, and the conducted interference coupling element can emit the interference signal outward; a compensation capacitor, the first end of which is connected to the conducted interference coupling element; and a main winding and an auxiliary winding wound on the same magnetic core, the main winding being connected between the rectifier bridge and the switching transistor, and the auxiliary winding being connected between the rectifier bridge and the second end of the compensation capacitor, wherein the number of turns of the auxiliary winding is the same as the number of turns of the main winding, and the auxiliary winding and the main winding are configured in an anti-phase coupling relationship, so that the compensation signal induced by the auxiliary winding is coupled to the conducted interference coupling element through the compensation capacitor, and the compensation signal and the interference signal cancel each other out at the conducted interference coupling element.

[0006] In one embodiment of this application, the compensation signal and the interference signal are out of phase and have matched amplitudes.

[0007] In one embodiment of this application, the winding direction of the auxiliary winding is opposite to that of the main winding.

[0008] In one embodiment of this application, the main winding is wound around the magnetic core, and the auxiliary winding is tightly wound around the outer periphery of the main winding.

[0009] In one embodiment of this application, the first end of the auxiliary winding and the first end of the main winding are both connected to the first DC output terminal of the rectifier bridge, and the first DC output terminal of the rectifier bridge is grounded through an input filter capacitor; the second DC output terminal of the rectifier bridge is grounded; the second end of the auxiliary winding is connected to the second end of the compensation capacitor; the second end of the main winding and one end of the parasitic capacitor are both connected to the drain of the switching transistor.

[0010] In one embodiment of this application, the switching transistor is attached to the surface of the conductive interference coupling element.

[0011] In one embodiment of this application, the conducted interference coupling element includes a heat sink.

[0012] In one embodiment of this application, the difference between the capacitance of the compensation capacitor and the capacitance of the parasitic capacitor is within ±30%.

[0013] In one embodiment of this application, it further includes: a filtering module, wherein the two input terminals of the filtering module are respectively connected to the live wire and the neutral wire of the power grid, and the two output terminals of the filtering module are respectively connected to the two AC input terminals of the rectifier bridge.

[0014] To address the aforementioned technical problems, this application also proposes an electronic device, including the power factor correction circuit described above.

[0015] To address the aforementioned technical problems, this application also proposes a DC charging pile, including the power factor correction circuit described above.

[0016] The power factor correction circuit of this application constructs a compensation coupling circuit symmetrical to the original interference coupling circuit in the power factor correction circuit by setting an auxiliary winding that is anti-coupled to the main winding on the same magnetic core and setting a compensation capacitor. This allows the compensation signal and the interference signal to cancel each other at the conducted interference coupling element, reducing the interference level conducted and radiated by the conducted interference coupling element and realizing source-type conducted emission suppression. Attached Figure Description

[0017] The accompanying drawings are included to provide a further understanding of this application; they are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings: Figure 1 This is a schematic diagram of a power factor correction circuit in the prior art; Figure 2 This is a schematic diagram of a power factor correction circuit according to an embodiment of this application; Figure 3 yes Figure 2 The schematic diagram illustrates the principle of canceling the original interference signal by signal inversion and superposition in the power factor correction circuit of the embodiment shown. Detailed Implementation

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0019] As indicated in this application, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0020] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following drawings denote similar items; therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0021] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0022] The power factor correction circuit of this application can be applied to electronic devices including switching power supplies, frequency converters, and new energy power supply equipment, and this application does not limit its application. This application does not limit the specific circuit topology of the power factor correction circuit; this specification uses a Boost converter-type PFC circuit as an example for illustration, but it is not limited thereto. The power factor correction circuit in this specification is equivalent to a PFC circuit.

[0023] Figure 1 This is a schematic diagram of a power factor correction circuit in the prior art. (Reference) Figure 1 As shown, the power factor correction circuit includes an EMI filter module 110, a rectifier bridge 120, a power switch 130, a heat sink 140, and a boost inductor 150. In some applications, the power switch 130 is mounted on the surface of the heat sink 140 for heat dissipation. There is an inherent parasitic capacitance between the power switch 130 and the heat sink 140. This parasitic capacitance is the inherent capacitance between the drain of the power switch 130 and the heat sink 140, and its capacitance is typically in the range of tens of picofarads, representing a non-eliminable structural parameter. The heat sink 140 is usually a passive heat sink, such as a heatsink.

[0024] The conducted emission problem in existing PFC circuits mainly stems from the following mechanism: During normal operation of the PFC circuit, the power switch 130 is turned on and off at high frequency under the control of the PWM (Pulse Width Modulation) signal of the PFC controller, generating high-frequency dV / dt voltage changes. This high-frequency voltage change forms the original high-frequency interference signal, which is coupled to the heat sink 140 through the parasitic capacitance between the drain of the power switch 130 and the heat sink 140. As a large-area metal conductor, the heat sink 140 receives the coupled interference signal and radiates and conducts it outward, forming the main conducted emission source, causing the overall conducted emission of the circuit to exceed the limit.

[0025] Currently, most methods for suppressing conducted interference in PFC circuits are passive filtering schemes. These involve adding common-mode inductors, X capacitors, Y capacitors, and other filtering devices at the circuit input to attenuate the generated and propagating interference signals. However, these schemes have the following drawbacks: First, it is a passive suppression at the back end, which cannot eliminate interference signals at the source of transmission, and the interference suppression effect is limited. Passive filtering devices act on the stage when the interference signal has already propagated to the circuit input, rather than suppressing it at the source where the interference signal couples to the heat sink. Therefore, the suppression effect is not ideal for conducted interference emitted directly outward through the heat sink.

[0026] Secondly, a large number of filtering components are required, which occupy a lot of circuit board space, increasing equipment cost and overall size. Common-mode inductors, multi-stage filter capacitors, and other components are relatively large, which is particularly prominent in space-constrained applications (such as compact products like charging piles and energy storage devices).

[0027] Third, filtering devices suffer from parameter attenuation under high-frequency operating conditions, making them unsuitable for wide-frequency, high-load operating scenarios. The impedance characteristics of common-mode inductors change with frequency, and impedance drop or resonance may occur at high frequencies, leading to a weakening of high-frequency interference suppression.

[0028] In existing technologies, there are almost no PFC circuit suppression schemes that start from the emission source and cancel the original interference signal by signal inversion and superposition, so it is impossible to achieve source-level conducted emission suppression.

[0029] The following is a brief explanation of some of the terms used in this application.

[0030] In this application, "interference signal" refers to the high-frequency electromagnetic phenomenon itself generated by the high-frequency switching of the power switch in the PFC circuit and coupled to the conducted interference coupling element through parasitic capacitance.

[0031] In this application, a "conducted interference coupling element" refers to a structural component that conducts and transmits interference signals generated by the high-frequency switching of a power switch through parasitic capacitance coupling. The conducted interference coupling element serves as the coupling receiver of the interference signal, the conducted emission source, and the superposition and cancellation node for the inverted signal in this application. Conducted interference coupling elements include, but are not limited to, heat sinks, metal housings, metal brackets, metal shields, or other metal structural components that have parasitic capacitive coupling with the power switch. In some of the following embodiments, a heat sink is described as a typical implementation of the conducted interference coupling element, but the scope of protection of this application is not limited to heat sinks.

[0032] Figure 2 This is a schematic diagram of a power factor correction circuit according to an embodiment of this application. (Reference) Figure 2 As shown, the power factor correction circuit includes a rectifier bridge 210, a switching transistor Q, a conducted interference coupling element 220, a compensation capacitor C2, a main winding 230, and an auxiliary winding 240. The rectifier bridge 210 and the switching transistor Q can respectively correspond to... Figure 1 The rectifier bridge 120 and power switch 130 in the circuit have the same function. The conducted interference coupling element 220 is connected to the switch Q and has a parasitic capacitance C1 between them. The interference signal generated by the switch Q is coupled to the conducted interference coupling element 220 through the parasitic capacitance C1, and the conducted interference coupling element 220 can transmit the interference signal outwards. The first end 251 of the compensation capacitor C2 is connected to the conducted interference coupling element 220. The main winding 230 and the auxiliary winding 240 are wound on the same magnetic core 260. The main winding 230 is connected between the rectifier bridge 210 and the switch Q. The auxiliary winding 240 is connected between the rectifier bridge 210 and the second end 252 of the compensation capacitor C2. The auxiliary winding 240 has the same number of turns as the main winding 230. The auxiliary winding 240 and the main winding 230 are configured in an anti-phase coupling relationship so that the compensation signal induced by the auxiliary winding 240 is coupled to the conducted interference coupling element 220 through the compensation capacitor C2, and the compensation signal and the interference signal cancel each other out at the conducted interference coupling element 220.

[0033] It should be noted that, in this application, "anti-phase coupling" refers to a configuration where, under the condition that the auxiliary winding 240 and the main winding 230 share the same magnetic core 260, the compensation signal induced by the auxiliary winding 240 and the interference signal generated by the main winding 230 during operation are out of phase at the conductive interference coupling element 220 through at least one means of winding direction, terminal wiring method, or circuit topology. Specific implementations of anti-phase coupling include, but are not limited to: the winding direction of the auxiliary winding 240 being opposite to that of the main winding 230; the winding direction of the auxiliary winding 240 being the same as that of the main winding 230 but with reversed terminals; and other configurations that enable the two signals to exhibit an out-of-phase relationship at the conductive interference coupling element 220.

[0034] In some embodiments, both the compensation signal and the interference signal are voltage signals.

[0035] In some embodiments, the interference signal is a high-frequency interference signal caused by the high-frequency switching of the switching transistor Q. The frequency range of this high-frequency interference signal is, for example, 150kHz-30MHz, but is not limited thereto.

[0036] like Figure 2 As shown, in this embodiment, the rectifier bridge 210 consists of a bridge structure composed of four diodes: diode D1, diode D2, diode D3, and diode D4. The anode of diode D1 is connected to the cathode of diode D3, forming the first AC input terminal; the cathode of diode D2 is connected to the anode of diode D4, forming the second AC input terminal; the cathodes of diodes D1 and D4 are interconnected, forming the first DC output terminal 211; and the anodes of diodes D3 and D2 are interconnected, forming the second DC output terminal 212. The rectifier bridge 210 converts the alternating AC input voltage into a unidirectional pulsating DC voltage through the alternating conduction of the four diodes, outputting it from the first DC output terminal 211 and the second DC output terminal 212, thus realizing the rectification and conversion function of AC to DC.

[0037] Figure 3 yes Figure 2 The illustrated embodiment shows a schematic diagram of the principle of canceling the original interference signal by signal inversion and superposition in the power factor correction circuit. (Combined with...) Figure 2 and Figure 3 As shown, two coupling paths are illustrated. One path couples the interference signal to the conducted interference coupling element 220 via the switching transistor Q and parasitic capacitance C1; this path is called the primary interference coupling loop. The second path couples the compensation signal to the conducted interference coupling element 220 via the auxiliary winding 240 and compensation capacitor C2; this path is called the inverting signal coupling loop. The compensation signal and the interference signal are inverted. Assuming the interference signal is in phase, the compensation signal is inverted.

[0038] When the power factor correction circuit is operating normally, the high-frequency switching of the switching transistor Q generates a high-frequency dV / dt voltage change. This high-frequency interference signal is coupled to the conducted interference coupling element 220 through the parasitic capacitance C1, forming a positive-phase conducted interference signal. Simultaneously, the alternating magnetic field generated by the high-frequency operation of the main winding 230 induces an inverse high-frequency voltage compensation signal on the auxiliary winding 240. This compensation signal is coupled to the conducted interference coupling element 220 through the compensation capacitor C2. The compensation signal and the interference signal have essentially equal amplitudes but completely opposite phases, canceling each other out at the conducted interference coupling element 220, which serves as the source of the interference signal.

[0039] The power factor correction circuit of this application constructs a compensation coupling circuit symmetrical to the original interference coupling circuit in the PFC circuit by setting an auxiliary winding 240 that is anti-coupled to the main winding 230 on the same magnetic core 260 and setting a compensation capacitor C2. This allows the compensation signal and the interference signal to cancel each other at the conducted interference coupling element 220, reducing the interference level conducted and radiated by the conducted interference coupling element 220 and realizing source-type conducted emission suppression.

[0040] Compared with the prior art, the power factor correction circuit of this application also has the following beneficial effects: (1) Excellent source suppression effect. This application significantly reduces the interference level emitted by the PFC circuit from the source. Compared with traditional filtering schemes, the conducted interference suppression effect is significantly improved, and it is easier to meet EMC electromagnetic compatibility test standards.

[0041] (2) Simple structure and low cost. This application can achieve source noise suppression function by adding auxiliary winding 240 and compensation capacitor C2. There is no need to add large components such as common mode inductor and multi-stage filter capacitor, which greatly simplifies the circuit structure, reduces the space occupied by the circuit board, and reduces the material cost and assembly cost of the equipment.

[0042] (3) Strong adaptability and stable operation. This application achieves signal cancellation based on the principle of electromagnetic induction symmetry, without frequency limitations, and can be adapted to PFC circuits with different switching frequencies and different load conditions. At the same time, there is no device attenuation problem under high-frequency conditions, and the working stability is far superior to traditional passive filtering schemes.

[0043] (4) High compatibility. This application does not require any changes to the topology, operating logic and power parameters of the original PFC circuit. For the Boost PFC circuit, only the winding of the boost inductor needs to be modified and a compensation capacitor needs to be added. It can be directly adapted to the existing conventional Boost PFC circuit. The modification difficulty is low and the versatility is extremely strong.

[0044] (5) No additional power loss. The auxiliary winding 240 and the compensation capacitor C2 in this application are only used for signal coupling cancellation and do not participate in circuit power transmission. They will not increase the active power loss of the circuit and will not affect the original power factor and conversion efficiency of the PFC circuit. The circuit performance is lossless.

[0045] In some embodiments, the compensation signal and the interference signal are out of phase and matched in amplitude. This application, by configuring the main winding 230 and the auxiliary winding 240 wound on the same magnetic core 260, with the auxiliary winding 240 having the same number of turns as the main winding 230, enables the compensation signal induced by the auxiliary winding 240 to match the amplitude of the interference signal. Under the premise of out of phase, amplitude matching means that the amplitude relationship between the compensation signal and the interference signal coupled to the conducted interference coupling element 220 allows them to cancel each other out. In some embodiments, amplitude matching means that the amplitudes are equal, in which case the compensation signal and the interference signal completely cancel each other out. In other embodiments, amplitude matching means that the amplitudes are close, and the compensation signal and the interference signal are mostly canceled out. According to these embodiments, by designing the circuit so that the compensation signal and the interference signal are out of phase and matched in amplitude, the source-based conducted emission suppression of this application can be achieved.

[0046] In some embodiments, the difference between the capacitance of the compensation capacitor C2 and the capacitance of the parasitic capacitance C1 is within ±30%. In some embodiments, the difference between the capacitance of the compensation capacitor C2 and the capacitance of the parasitic capacitance C1 is within ±20%. In some embodiments, the difference between the capacitance of the compensation capacitor C2 and the capacitance of the parasitic capacitance C1 is within ±10%. In some embodiments, the difference between the capacitance of the compensation capacitor C2 and the capacitance of the parasitic capacitance C1 is within ±5%. In some embodiments, the capacitance of the compensation capacitor C2 is equal to the capacitance of the parasitic capacitance C1.

[0047] By making the capacitance of the compensation capacitor C2 close to that of the parasitic capacitor C1, the amplitudes of the compensation signal and the interference signal can be made more consistent, thereby improving the power factor correction circuit of this application's ability to cancel interference signals.

[0048] In some embodiments, the compensation capacitor C2 is a high-frequency, low-loss ceramic capacitor that can adapt to the high-frequency switching conditions of the PFC circuit, ensuring that the high-frequency signal transmission is attenuated and ensuring the integrity of the compensation signal.

[0049] As mentioned earlier, there are several ways to achieve the anti-phase coupling relationship between the auxiliary winding 240 and the main winding 230. In some embodiments, the winding direction of the auxiliary winding 240 is opposite to that of the main winding 230, thereby achieving that the compensation signal and the interference signal are out of phase. This implementation method is simple.

[0050] In some embodiments, the main winding 230 and the auxiliary winding 240 are concentrically wound around the magnetic core 260. For example, the main winding 230 can be wound around the magnetic core 260 first, and then the auxiliary winding 240 can be tightly wound around the outer periphery of the main winding 230. During the winding process, ensuring that the main winding 230 is tightly attached to the magnetic core 260 and that the auxiliary winding 240 is tightly attached to the main winding 230 can reduce magnetic leakage and further ensure amplitude matching between the compensation signal and the interference signal.

[0051] refer to Figure 2 As shown, in some embodiments, the first end 241 of the auxiliary winding 240 and the first end 231 of the main winding 230 are both connected to the first DC output terminal 211 of the rectifier bridge 210, and the first DC output terminal 211 of the rectifier bridge 210 is grounded through the input filter capacitor C3; the second DC output terminal 212 of the rectifier bridge 210 is grounded; the second end 242 of the auxiliary winding 240 is connected to the second end 252 of the compensation capacitor C2, and the first end 251 of the compensation capacitor C2 is connected to the conducted interference coupling element 220; the second end 232 of the main winding 230 and one end 271 of the parasitic capacitor C1 are both connected to the drain of the switching transistor Q. The source of the switching transistor Q is grounded. The gate of the switching transistor Q is connected to an external control device for receiving control signals.

[0052] In some embodiments, the leads of the auxiliary winding 240 employ a short-pitch wiring method to reduce the interference of lead parasitic parameters on the compensation signal. Here, short-pitch wiring means minimizing the lead length between the auxiliary winding 240 and other components according to the actual circuit topology.

[0053] In some embodiments, the conducted interference coupling element 220 includes a heat sink. The switching transistor Q is attached to the surface of the heat sink, and there is an inherent parasitic capacitance C1 between them.

[0054] like Figure 2 As shown, in some embodiments, the power factor correction circuit further includes a filter module. The two input terminals of the filter module are connected to the live wire L and neutral wire N of the power grid, respectively, and the two output terminals of the filter module are connected to the two AC input terminals of the rectifier bridge 210, namely the first AC input terminal and the second AC input terminal mentioned above. More specifically, the filter module includes a cascaded differential-mode filter module 281 and a common-mode filter module 282. The two input terminals of the filter module are the two input terminals of the differential-mode filter module 281, and the two output terminals of the filter module are the two output terminals of the common-mode filter module 282. The differential-mode filter module 281 includes a differential-mode capacitor C. DM1 The common-mode filter module 282 includes two common-mode capacitors C. CM1 and C CM2 .

[0055] like Figure 2As shown, in some embodiments, the power factor correction circuit further includes a freewheeling diode D5 and an output capacitor C4. The anode of the freewheeling diode D5 is connected to the drain of the switching transistor Q and the second terminal 232 of the main winding 230, and the cathode of the freewheeling diode D5 is connected to the load through the output terminal OUT. The freewheeling diode D5 is used to direct the inductor energy to the output terminal OUT after the switching transistor Q is turned off, while blocking the reverse current. The output capacitor C4 is placed between the output terminal OUT and ground, which is a conventional setting in PFC circuits.

[0056] In some embodiments, the magnetic core 260 of this application is the boost inductor core in a Boost PFC circuit, such as an iron core. In other embodiments, the material of the magnetic core 260 can be any mainstream PFC inductor material, such as ferrite, iron powder core, amorphous / nanocrystalline, etc.

[0057] This application also proposes an electronic device including a power factor correction circuit according to any embodiment of this application. This electronic device, by including the power factor correction circuit, possesses all the beneficial effects of the power factor correction circuit.

[0058] This application also proposes a DC charging pile, including a power factor correction circuit according to any embodiment of this application. In the DC charging pile, the power factor correction circuit serves as a pre-stage power unit for AC-DC conversion, converting the AC grid input into a stable DC bus voltage for use by the subsequent DC-DC converter. High-power charging piles typically use SiCMOSFETs or IGBTs as power switches, with switching frequencies ranging from 20 kHz to 100 kHz, and require large-area heat sinks for heat dissipation. A large parasitic capacitance is formed between the power switch and the heat sink, and the high-frequency interference signals generated by the high-frequency switching of the switch are coupled to the heat sink through this parasitic capacitance, forming a significant conducted emission source. Because the DC charging pile of this application includes this power factor correction circuit, it achieves source superposition and cancellation of interference signals at the heat sink, effectively reducing the conducted emission level of the entire charging pile and meeting electromagnetic compatibility standards.

[0059] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0060] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the present application requires more features than those mentioned. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0061] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used to describe embodiments are sometimes modified by the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in this application are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

Claims

1. A power factor correction circuit, characterized in that, include: Rectifier bridge and switching transistors; A conducted interference coupling element is connected to the switching transistor and has a parasitic capacitance between them. The interference signal generated by the switching transistor is coupled to the conducted interference coupling element through the parasitic capacitance, and the conducted interference coupling element can transmit the interference signal outward. A compensation capacitor, wherein the first terminal of the compensation capacitor is connected to the conducted interference coupling element; and The main winding and the auxiliary winding are wound on the same magnetic core. The main winding is connected between the rectifier bridge and the switching transistor, and the auxiliary winding is connected between the rectifier bridge and the second terminal of the compensation capacitor. The auxiliary winding has the same number of turns as the main winding. The auxiliary winding and the main winding are configured in an anti-phase coupling relationship so that the compensation signal induced by the auxiliary winding is coupled to the conducted interference coupling element through the compensation capacitor, and the compensation signal and the interference signal cancel each other out at the conducted interference coupling element.

2. The power factor correction circuit as described in claim 1, characterized in that, The compensation signal and the interference signal are out of phase and have matched amplitudes.

3. The power factor correction circuit as described in claim 1, characterized in that, The winding direction of the auxiliary winding is opposite to that of the main winding.

4. The power factor correction circuit as described in claim 1, characterized in that, The main winding is wound around the magnetic core, and the auxiliary winding is tightly wound around the outer periphery of the main winding.

5. The power factor correction circuit as described in claim 1, characterized in that, The first end of the auxiliary winding and the first end of the main winding are both connected to the first DC output terminal of the rectifier bridge, and the first DC output terminal of the rectifier bridge is grounded through the input filter capacitor; the second DC output terminal of the rectifier bridge is grounded; the second end of the auxiliary winding is connected to the second end of the compensation capacitor; the second end of the main winding and one end of the parasitic capacitor are both connected to the drain of the switching transistor.

6. The power factor correction circuit as described in claim 1, characterized in that, The switching transistor is attached to the surface of the conductive interference coupling element.

7. The power factor correction circuit as described in claim 1, characterized in that, The conducted interference coupling element includes a heat sink.

8. The power factor correction circuit as described in claim 1, characterized in that, The difference between the capacitance of the compensation capacitor and the capacitance of the parasitic capacitor is within ±30%.

9. The power factor correction circuit according to claim 1, characterized in that, Also includes: The filter module has two input terminals connected to the live wire and neutral wire of the power grid, respectively, and two output terminals connected to the two AC input terminals of the rectifier bridge, respectively.

10. An electronic device, characterized in that, Includes the power factor correction circuit as described in any one of claims 1-9.

11. A DC charging pile, characterized in that, Includes the power factor correction circuit as described in any one of claims 1-9.

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