A method for improving the working efficiency of a buck power supply, a control module and a power supply device

Abstract

This invention relates to the field of power converter technology, and in particular to a method, control module, and power supply device for improving the operating efficiency of a Buck power supply. The invention generates a first set of drive signals to control the main power switch via a main control unit, and based on these signals, generates a second set of drive signals to control the auxiliary power switch via a PWM generation subunit within the main control unit or an external digital logic circuit. By dynamically adjusting the waveform of at least one auxiliary drive signal in relation to the pulse width and switching period of the corresponding reference drive signal, the power supply efficiency is significantly improved. Precise digital timing control effectively reduces switching losses. The invention also significantly optimizes system integration, replacing complex analog circuits with a simple digital architecture, saving valuable PCB space. While ensuring control accuracy and anti-interference capabilities, it provides the flexibility to adjust parameters via software, offering an innovative and practical solution for high-efficiency power supply design.

Description

Technical Field

[0001] This invention relates to the field of power converter technology, and in particular to a method, control module, and power supply device for improving the operating efficiency of Buck power supplies. Background Technology

[0002] Small Buck power modules (hereinafter referred to as "Buck power supplies") are an important component of modern power electronic equipment, widely used in various industrial devices such as data centers, communication base stations, drones, and handheld terminal devices. These Buck power supplies are characterized by their small size, high power density, and harsh operating environments, requiring high energy conversion efficiency to save energy consumption. How to improve the working efficiency of Buck power supplies under severely limited hardware resources has become a focus of research for various companies and institutions.

[0003] To improve the efficiency of Buck power supplies, the main existing methods are as follows: Scheme A, Scheme B, and Scheme C.

[0004] Option A: Improve the topology of the Buck power supply. Optimizing the topology of the power module can improve its efficiency.

[0005] Option B: Soft switching is adopted to reduce switching losses. Through reasonable hardware design, the turn-on and turn-off losses of the switching transistors can be effectively reduced, thereby improving the overall working efficiency of the power module.

[0006] Solution C: Improve the switching timing logic of the Buck power supply by adding an extra switching transistor to optimize the turn-on and turn-off timing of the main circuit switching transistors of the Buck power supply, thereby reducing the overall switching losses of the system and improving its efficiency.

[0007] The problems with the aforementioned existing technologies include: Solution A requires innovative theoretical support. The topologies of modern Buck power supplies are already quite mature, and it is very difficult to improve efficiency by modifying the topology.

[0008] Option B requires additional components to implement soft switching, which is difficult to implement in high-power-density Buck power supplies. Currently, a quarter-brick Buck power supply needs to reach a rated power of 2000W or even 2500W. At such high power densities, PCB (Printed Circuit Board) space is extremely limited, and priority must be given to ensuring the space requirements of the main components, making it difficult to add too many additional components.

[0009] Scheme C requires a more complex control timing design, placing high demands on control design. Due to the lack of functionality in the main control chip of the Buck power supply, mainstream manufacturers mainly use external analog circuits to assist in its implementation. However, external analog circuits still have the following problems: First, they occupy a large amount of space, making PCB layout difficult; second, adjusting control parameters is inconvenient and inflexible; finally, the accuracy of parameter adjustment is limited by the components and easily affected by component parameter drift, and its anti-interference capability is also weak.

[0010] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0011] The technical problem to be solved by this invention is: how to efficiently, accurately, and flexibly implement complex switching timing control in high-power-density Buck power supplies with severely limited hardware resources, so as to reduce switching losses and thus improve the efficiency of Buck power supplies.

[0012] The present invention adopts the following technical solution: Firstly, a method for improving the efficiency of Buck power supplies is provided, including: The main control unit generates the first set of drive signals to control the main power switching transistor. Based on the first set of drive signals, a second set of drive signals for controlling the auxiliary power switch is generated by the PWM generation subunit inside the main control unit or by the external digital logic circuit. The waveform of at least one auxiliary drive signal in the second group of drive signals is dynamically adjusted according to the relationship between the pulse width and the switching period of the corresponding reference drive signal in the first group of drive signals.

[0013] Preferably, the method further includes: When the pulse width of the reference drive signal is less than or equal to 50% of the switching period, the corresponding auxiliary drive signal is always at a high level. When the pulse width of the reference drive signal is greater than 50% of the switching period, the corresponding auxiliary drive signal is configured such that after the falling edge of the reference drive signal, the auxiliary drive signal changes from high level to low level, and remains there for a period of time before changing back to high level. The duration of the low level is proportional to the effective pulse width of the reference drive signal.

[0014] Preferably, the duration of the low level The following relationship must be satisfied: ; ; in, , The time parameter is related to the effective pulse width of the reference drive signal; The effective pulse width of the reference drive signal. The switching cycle.

[0015] Preferably, the main power switching transistors include switching transistors Q1, Q2, Q3, Q4, Q5, and Q6; the auxiliary switching transistors include switching transistors Q7 and Q8. Switches Q7, Q1, Q3, and Q5 are connected in sequence; switches Q8, Q2, Q4, and Q6 are connected in sequence. Among them, the drive signal of switch Q4 is the same as the drive signal of switch Q1, and the drive signal of switch Q6 is complementary to the drive signal of switch Q1. When the pulse width of the drive signal of switch Q1 is less than or equal to 50%, the drive signal of switch Q8 is always high. When the pulse width of the drive signal of switch Q1 is greater than 50%, the drive signal of switch Q8 is maintained at a low level for a period of time based on the falling edge of the drive signal of switch Q1 before being set high. The drive signal for switch Q3 is the same as the drive signal for switch Q2, and the drive signal for switch Q5 is complementary to the drive signal for switch Q2. When the pulse width of the drive signal for switch Q2 is less than or equal to 50%, the drive signal for switch Q7 is always high. When the pulse width of the drive signal for switch Q2 is greater than 50%, the drive signal for switch Q7 is maintained at a low level for a period of time based on the falling edge of the drive signal for switch Q2, and then turned high.

[0016] Preferably, when the number of PWM output ports of the main control unit is sufficient and the on-chip resources are sufficient, a second set of drive signals for controlling the auxiliary power switching transistor is generated by the PWM generation subunit inside the main control unit. When the number of PWM output ports of the main control unit is insufficient and the on-chip resources are inadequate, a second set of drive signals for controlling the auxiliary power switching transistor is generated by external digital logic circuits.

[0017] Preferably, the digital logic circuit is a programmable logic device; When the number of PWM output ports of the main control unit is insufficient, the programmable logic device performs frequency multiplication or logic transformation on at least one reference drive signal from the main control unit to generate the required second set of drive signals.

[0018] In a second aspect, a control module for improving the working efficiency of a Buck power supply is provided, which is used to implement the method for improving the working efficiency of a Buck power supply as described in the first aspect. The control module adopts a fully digital control architecture and includes: a main control unit and a PWM generation subunit inside the main control unit. The main control unit is configured to generate a first set of drive signals for controlling the main power switch, and to generate a second set of drive signals for controlling the auxiliary power switch based on the first set of drive signals through its internal PWM generation subunit. The waveform of at least one auxiliary drive signal in the second group of drive signals is dynamically adjusted according to the relationship between the pulse width and the switching period of the corresponding reference drive signal in the first group of drive signals.

[0019] Preferably, the control module further includes a digital logic circuit, which is connected to the output terminal of the main control unit; the digital logic circuit is used to receive the first set of drive signals and generate a second set of drive signals for controlling the auxiliary power switch. The digital logic circuit is configured such that, for at least one auxiliary drive signal in the second group of drive signals, when the pulse width of the reference drive signal in the first group of drive signals is greater than 50% of the switching period, its waveform remains at a low level for a period of time after the falling edge of the reference drive signal before switching to a high level.

[0020] Preferably, the digital logic circuit is a programmable logic device or a conventional logic gate circuit.

[0021] Thirdly, a power supply device is provided, including a control module for improving the operating efficiency of a Buck power supply as described in the second aspect, and a Buck power supply.

[0022] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention generates a first set of drive signals to control the main power switch via a main control unit, and then generates a second set of drive signals to control the auxiliary power switch via a PWM generation subunit within the main control unit or an external digital logic circuit based on these signals. By dynamically adjusting the waveform of at least one auxiliary drive signal in relation to the pulse width and switching period of the corresponding reference drive signal, three core beneficial effects are achieved: First, it significantly improves power supply efficiency by effectively reducing switching losses through precise digital timing control; second, it greatly optimizes system integration by replacing complex analog circuits with a simple digital architecture, saving valuable PCB space and perfectly adapting to high power density applications; and third, it comprehensively enhances system performance by providing the flexibility to adjust parameters via software while ensuring control accuracy and anti-interference capabilities, enabling the system to possess both high reliability and excellent scalability, providing an innovative and practical solution for high-efficiency power supply design. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic diagram of a high-efficiency Buck power supply main circuit topology provided in an embodiment of the present invention; Figure 2 This is a switching timing diagram of a switching transistor Q1 when the PWM pulse width is ≤50%, provided in an embodiment of the present invention. Figure 3 This is a switching timing diagram of a switching transistor Q1 when the PWM pulse width is >50%, provided in an embodiment of the present invention. Figure 4 This is a flowchart illustrating a method for improving the working efficiency of a Buck power supply according to an embodiment of the present invention; Figure 5 This is a hardware connection diagram of an external digital logic circuit for a main control unit provided in an embodiment of the present invention; Figure 6 This is a PWM signal logic transformation diagram provided in an embodiment of the present invention; Figure 7 This is a signal timing diagram provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a main control unit provided in an embodiment of the present invention; Figure 9 This is another signal timing diagram provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of a carrier modulation PWM generation method provided in an embodiment of the present invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0027] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0028] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0029] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] Example 1: To provide a detailed explanation of the method for improving the working efficiency of a Buck power supply proposed in this embodiment, a specific structure of a Buck power supply is first introduced. In one implementation, such as... Figure 1 The diagram shows the main circuit topology of a high-efficiency Buck power supply. The main power switches include switches Q1, Q2, Q3, Q4, Q5, and Q6; the auxiliary switches include switches Q7 and Q8. Switches Q7, Q1, Q3, and Q5 are connected sequentially; switches Q8, Q2, Q4, and Q6 are connected sequentially. Switches Q1 to Q6 are the main power switches, and switches Q7 and Q8 are the auxiliary power switches. Their operating logic is as follows: Figure 2 and Figure 3 As shown (dead zones are not depicted for the sake of simplifying the view).

[0031] Based on the specific structure of the Buck power supply described above, in order to improve the working efficiency of the Buck power supply, in one embodiment, such as... Figure 4 As shown, the method for improving the working efficiency of a Buck power supply includes: Step 101: The main control unit generates the first set of drive signals for controlling the main power switching transistor.

[0032] The main control unit is typically a microcontroller or digital signal processor, primarily used to generate the basic PWM signals necessary to control the core power loop of the Buck power supply. In one implementation, the main control unit generates PWM signals through its internal PWM generator; these signals are periodic, symmetrical (or fixedly complementary), and are standard PWM waveforms that can be directly generated.

[0033] Step 102: Based on the first set of drive signals, generate a second set of drive signals for controlling the auxiliary power switch tube through the PWM generation subunit inside the main control unit or the external digital logic circuit.

[0034] The waveform of at least one auxiliary drive signal in the second group of drive signals is dynamically adjusted according to the relationship between the pulse width and the switching period of the corresponding reference drive signal in the first group of drive signals.

[0035] When the pulse width of the reference drive signal is less than or equal to 50% of the switching period, the corresponding auxiliary drive signal is always at a high level; when the pulse width of the reference drive signal is greater than 50% of the switching period, the corresponding auxiliary drive signal is configured such that after the falling edge of the reference drive signal, the auxiliary drive signal changes from a high level to a low level, maintains this low level for a period of time, and then changes back to a high level; wherein the duration of the low level is proportional to the effective pulse width of the reference drive signal.

[0036] In one implementation, the duration of the low level... The following relationship must be satisfied: ; ; in, , The time parameter is related to the effective pulse width of the reference drive signal; The effective pulse width of the reference drive signal. The switching cycle.

[0037] In one embodiment, based on the specific structure of the Buck power supply described above, the second set of drive signals includes two auxiliary drive signals, namely the drive signal for switch Q7 and the drive signal for switch Q8, which are used to drive switch Q7 and switch Q8 respectively.

[0038] In one implementation, reference Figure 2 and Figure 3 The eight switching transistors are divided into two groups for control, with Ts being the switching cycle time. Switches Q1, Q4, Q6, and Q8 form one group (Group 1), while switches Q2, Q3, Q5, and Q7 form the other group (Group 2). The drive signals of switches Q1 and Q2 are used as reference drive signals, respectively (i.e., the drive signal of switch Q8 is based on the drive signal of switch Q1, and the drive signal of switch Q7 is based on the drive signal of switch Q2). The phase of the drive signal of switch Q2 lags behind the phase of the drive signal of switch Q1 by 180°.

[0039] In one implementation, reference Figure 2 and Figure 3 First, based on the optimized Buck power supply topology, the timing logic required for PWM drive control is clarified. Among them, the drive signal of switch Q4 is consistent with the drive signal of switch Q1, and the drive signal of switch Q6 is complementary to the drive signal of switch Q1. When the pulse width of the drive signal of switch Q1 is less than or equal to 50%, the drive signal of switch Q8 is always high. When the pulse width of the drive signal of switch Q1 is greater than 50%, the drive signal of switch Q8 is maintained at a low level for a period of time based on the falling edge of the drive signal of switch Q1 before being set high.

[0040] In one embodiment, the drive signal of the switching tube Q3 is consistent with the drive signal of the switching tube Q2, the drive signal of the switching tube Q5 is complementary to the drive signal of the switching tube Q2. When the pulse width of the drive signal of the switching tube Q2 is less than or equal to 50%, the drive signal of the switching tube Q7 is constantly at a high level; when the pulse width of the drive signal of the switching tube Q2 is greater than 50%, the drive signal of the switching tube Q7 maintains a low level for a period of time based on the falling edge of the drive signal of the switching tube Q2 and then is set to a high level.

[0041] In one embodiment, in response to the pulse width variation of the main power switching tubes (switching tube Q1, switching tube Q2), the switching tube Q7 and the switching tube Q8 do not adopt a fixed conduction logic, but are divided into two working conditions: when the pulse width of the main power switching tubes is ≤ 50%, the drive signal of the switching tube Q7 and the drive signal of the switching tube Q8 are constantly at a high level (i.e., continuously conductive), so as to avoid extra loss introduced by frequent switching; when the pulse width of the main power switching tubes is > 50%, the switching tube Q7 and the switching tube Q8 maintain a low level (turn off) for a short time based on the falling edge of the main power switching tubes and then turn on, and the turn-off time (T2=kT1, T4=kT3) is dynamically adjusted by a quantization coefficient k (0<k≤3.0). This segmented logic breaks the rigid mode of fixed timing in the traditional analog circuit, and can adapt to pulse width variations under different loads.

[0042] Since the control timing of the auxiliary power switching tubes (i.e., the switching tube Q7 and the switching tube Q8) is more complex than that of the other 6 switching tubes, the switching tubes Q1 to Q6 require two sets of complementary and phase-shifted PWM drive signals. Generating these PWM drive signals is a basic function of the main control unit, which will not be described in detail in this embodiment. This embodiment focuses on explaining how to generate the drive waveforms of the switching tube Q7 and the switching tube Q8 through digital control.

[0043] In one embodiment, when the number of PWM output ports of the main control unit is insufficient and the on-chip resources are scarce, a second set of drive signals for controlling the auxiliary power switching tubes is generated by an external digital logic circuit. The external digital logic circuit may be a TPLD or a simple inverter. The digital logic circuit is configured to take the first set of drive signals as input, and obtain the drive signals with complex asymmetric timing required for controlling the auxiliary power switching tubes (switching tube Q7 and switching tube Q8) through digital logic operation.

[0044] For example, in an MCU (i.e., the main control unit) with only 5 PWM outputs, 8 switching transistors (Q1-Q8) need to be controlled. Switches Q1-Q6 require 4 complementary signals, which can be considered as 2 pairs of core PWM signals. Specifically, the 5 PWM outputs are divided into channels 1, 2, 3, 4, and 5. Channel 1 (PWM1) drives Q1 and Q4, channel 2 (the inverted version of PWM1) drives Q6, channel 3 (PWM3) drives Q2 and Q3, and channel 4 (the inverted version of PWM3) drives Q5. This leaves only 1 PWM signal (PWM5) to control the auxiliary power switches Q7 and Q8. However, since the driving waveforms of switches Q7 and Q8 are complex and asymmetrical, the remaining PWM signal cannot directly meet the requirements.

[0045] In one embodiment, the digital logic circuit is a programmable logic device; when the number of PWM output ports of the main control unit is insufficient, the programmable logic device performs frequency multiplication or logic transformation on at least one reference drive signal from the main control unit to generate the required second set of drive signals.

[0046] For a main control unit with limited peripheral resources and only 5 available PWM ports, this can be achieved by adding an external TPLD chip (corresponding to the digital logic circuit described above). The circuit connection diagram is shown below. Figure 5 As shown, the signal logic transformation is as follows: Figure 6 As shown, the signal timing is as follows Figure 7 As shown. In Figure 6 In this context, NOT stands for NOT gate, AND stands for AND gate, XOR stands for XOR gate, and NAND stands for NAND gate.

[0047] like Figure 7 As shown, since only one additional PWM signal can be used, this combinational logic needs to multiply the PWM5 signal. The calculation relationships for each time point in the diagram are as follows: ; in, and All of these can be read from the chip's internal registers. To ensure timeliness, the pulse width of PWM5 can be synchronously refreshed within the switching interrupt.

[0048] In one implementation, when the main control unit has a sufficient number of PWM output ports and sufficient on-chip resources, a second set of drive signals for controlling the auxiliary power switch is generated by the PWM generation subunit inside the main control unit. The circuit connection diagram is shown below. Figure 8 As shown, the signal timing is as follows Figure 9As shown in the diagram. Both Ts and Tpwm1 can be read from the chip's internal registers. PWM5 and PWM6 have the same frequency as PWM1, and their waveforms are identical with a 180° phase difference. The rising edge of PWM5 aligns with the falling edge of PWM1, and the rising edge of PWM6 aligns with the falling edge of PWM3. Their pulse widths are T6-T5, calculated using the following formula. They use a sawtooth wave as the carrier wave. A schematic diagram of carrier modulation generating the PWM waveform is shown below. Figure 10 As shown.

[0049] In one implementation, reference Figure 8 The PWM generation subunit inside the main control unit includes the PWM generator within the main control unit and the on-chip inverter NOT. For example... Figure 9 As shown, this scheme generates drive waveforms for switches Q8 and Q7 that are complementary to the waveforms of PWM5 and PWM6, respectively. Therefore, it is only necessary to calculate... and The values ​​of are calculated as follows: ; In summary, this embodiment designs two solutions for MCUs with limited peripheral resources (e.g., only 5 PWM channels) and those with sufficient resources: TPLD expansion (corresponding to generating a second set of drive signals for controlling the auxiliary power switch through external digital logic circuitry) and no peripheral expansion (corresponding to generating a second set of drive signals for controlling the auxiliary power switch through the PWM generation subunit inside the main control unit). Under limited resources, refer to... Figure 5 By multiplying the PWM5 signal using a TPLD, a single additional PWM channel is used to implement the complex timing of switches Q7 and Q8; under sufficient resources, refer to Figure 8 The timing sequence is generated directly using the same frequency PWM signals (PWM5 and PWM6) in conjunction with the on-chip inverter NOT, resulting in almost zero hardware cost. Both solutions avoid the redundant design of complex external analog circuits in the traditional C solution, saving space on high-power-density PCBs where space is at a premium, and adapting to the space requirements of high-power-density modules above 2000W.

[0050] This embodiment generates a first set of drive signals to control the main power switch transistor by the main control unit, and then generates a second set of drive signals to control the auxiliary power switch transistor by the PWM generation subunit inside the main control unit or by external digital logic circuitry based on these signals. By dynamically adjusting the waveform of at least one auxiliary drive signal in relation to the pulse width and switching period of the corresponding reference drive signal, three core beneficial effects are achieved: First, it significantly improves the power supply efficiency by effectively reducing switching losses through precise digital timing control; second, it greatly optimizes system integration by replacing complex analog circuits with a simple digital architecture, saving valuable PCB space and perfectly adapting to high power density applications; and third, it comprehensively enhances system performance by providing the flexibility to adjust parameters through software while ensuring control accuracy and anti-interference capabilities, making the system both highly reliable and highly scalable, providing an innovative and practical solution for high-efficiency power supply design.

[0051] Example 2: This embodiment proposes a control module to improve the working efficiency of Buck power supplies. In one implementation, the control module adopts a fully digital control architecture and includes a main control unit. When the number of PWM output ports of the main control unit is sufficient and the on-chip resources are sufficient, the main control unit is configured to generate a first set of drive signals for controlling the main power switch, and generate a second set of drive signals for controlling the auxiliary power switch based on the first set of drive signals through its internal PWM generation subunit.

[0052] When the number of PWM output ports of the main control unit is insufficient and the on-chip resources are inadequate, the control module further includes a digital logic circuit. The digital logic circuit is connected to the output terminal of the main control unit and is used to generate a second set of drive signals for controlling the auxiliary power switch based on the first set of drive signals.

[0053] The waveform of at least one auxiliary drive signal in the second group of drive signals is dynamically adjusted according to the relationship between the pulse width and the switching period of the corresponding reference drive signal in the first group of drive signals.

[0054] In one implementation, the duration of the low level... The following relationship must be satisfied: ; ; in, , The time parameter is related to the effective pulse width of the reference drive signal; The effective pulse width of the reference drive signal. The switching cycle.

[0055] In one embodiment, based on the specific structure of the Buck power supply described above, the second set of drive signals includes two auxiliary drive signals, namely the drive signal for switch Q7 and the drive signal for switch Q8, which are used to drive switch Q7 and switch Q8 respectively.

[0056] The main control unit is typically a microcontroller or digital signal processor, primarily used to generate the basic PWM signals necessary for controlling the core power circuit of the Buck power supply. In one implementation, the main control unit generates PWM signals through its internal PWM generator. These signals are periodic, symmetrical (or fixed complementary), and are standard PWM waveforms that can be directly generated. The main power switches include switches Q1, Q2, Q3, Q4, Q5, and Q6; the auxiliary switches include switches Q7 and Q8; switches Q7, Q1, Q3, and Q5 are connected sequentially; switches Q8, Q2, Q4, and Q6 are connected sequentially; switches Q1 to Q6 are the main power switches, and switches Q7 and Q8 are the auxiliary power switches, their operating logic referring to... Figure 2 and Figure 3 As shown (dead zones are not depicted for the sake of simplifying the view).

[0057] In one implementation, reference Figure 2 and Figure 3 The eight switching transistors are divided into two groups for control, with Ts being the switching cycle time. Switches Q1, Q4, Q6, and Q8 form one group (Group 1), while switches Q2, Q3, Q5, and Q7 form the other group (Group 2). The drive signals of switches Q1 and Q2 are used as reference drive signals, respectively (i.e., the drive signal of switch Q8 is based on the drive signal of switch Q1, and the drive signal of switch Q7 is based on the drive signal of switch Q2). The phase of the drive signal of switch Q2 lags behind the phase of the drive signal of switch Q1 by 180°.

[0058] In one implementation, firstly, based on the optimized Buck power supply topology, referring to... Figure 2 and Figure 3 The timing logic required for PWM drive control is clarified. The drive signal of switch Q4 is consistent with the drive signal of switch Q1, and the drive signal of switch Q6 is complementary to the drive signal of switch Q1. When the pulse width of the drive signal of switch Q1 is less than or equal to 50%, the drive signal of switch Q8 is always high. When the pulse width of the drive signal of switch Q1 is greater than 50%, the drive signal of switch Q8 is maintained at a low level for a period of time based on the falling edge of the drive signal of switch Q1 before being set high.

[0059] In one embodiment, the driving signal of the switching tube Q3 is consistent with the driving signal of the switching tube Q2, and the driving signal of the switching tube Q5 is complementary to the driving signal of the switching tube Q2. When the pulse width of the driving signal of the switching tube Q2 is less than or equal to 50%, the driving signal of the switching tube Q7 is always at a high level; when the pulse width of the driving signal of the switching tube Q2 is greater than 50%, the driving signal of the switching tube Q7 is kept at a low level for a period of time based on the falling edge of the driving signal of the switching tube Q2 and then pulled high.

[0060] In one embodiment, in response to the pulse width variation of the main power switching tubes (switching tube Q1 and switching tube Q2), the switching tube Q7 and the switching tube Q8 do not adopt a fixed turn-on logic, but are divided into two working conditions: when the pulse width of the main power switching tubes is ≤ 50%, the driving signal of the switching tube Q7 and the driving signal of the switching tube Q8 are always at a high level (i.e., continuously turned on), so as to avoid extra loss caused by frequent switching; when the pulse width of the main power switching tubes is > 50%, the switching tube Q7 and the switching tube Q8 are kept at a low level (turned off) for a short time based on the falling edge of the main power switching tubes and then turned on, and the turn-off time (T2=kT1, T4=kT3) is dynamically adjusted by a quantization coefficient k (0<k≤3.0). This segmented logic breaks the rigid mode of fixed timing in traditional analog circuits, and can adapt to pulse width variations under different loads.

[0061] Since the control timing of the auxiliary power switching tubes (i.e., switching tube Q7 and switching tube Q8) is more complex than that of the other 6 switching tubes, the switching tubes Q1 to Q6 require two sets of complementary and phase-shifted PWM driving signals. Generating these PWM driving signals is a basic function of the main control unit, which will not be described in detail in this embodiment. This embodiment focuses on explaining how to generate the driving waveforms of the switching tube Q7 and the switching tube Q8 through digital control.

[0062] In one embodiment, when the number of PWM output ports of the main control unit is insufficient and the on-chip resources are scarce, a second set of driving signals for controlling the auxiliary power switching tubes is generated by an external digital logic circuit. The external digital logic circuit may be a TPLD or a simple inverter. The digital logic circuit is configured to receive the first set of driving signals as input, and perform digital logic operation to obtain the driving signals with complex asymmetric timing required for controlling the auxiliary power switching tubes (switching tube Q7 and switching tube Q8).

[0063] Wherein, the digital logic circuit is configured such that for the waveform of at least one auxiliary driving signal in the second set of driving signals, when the pulse width of the corresponding reference driving signal in the first set of driving signals is greater than 50% of the switching period, the waveform is kept at a low level for a period of time after the falling edge of the reference driving signal and then switched to a high level.

[0064] For example, in an MCU (i.e., the main control unit) with only 5 PWM outputs, 8 switching transistors (Q1-Q8) need to be controlled. Switches Q1-Q6 require 4 complementary signals, which can be considered as 2 pairs of core PWM signals. Specifically, the 5 PWM outputs are divided into channels 1, 2, 3, 4, and 5. Channel 1 (PWM1) drives Q1 and Q4, channel 2 (the inverted version of PWM1) drives Q6, channel 3 (PWM3) drives Q2 and Q3, and channel 4 (the inverted version of PWM3) drives Q5. This leaves only 1 PWM signal (PWM5) to control the auxiliary power switches Q7 and Q8. However, since the driving waveforms of switches Q7 and Q8 are complex and asymmetrical, the remaining PWM signal cannot directly meet the requirements.

[0065] In one embodiment, the digital logic circuit is a programmable logic device; when the number of PWM output ports of the main control unit is insufficient, the programmable logic device performs frequency multiplication or logic transformation on at least one reference drive signal from the main control unit to generate the required second set of drive signals.

[0066] For a main control unit with limited peripheral resources and only 5 available PWM ports, this can be achieved by adding an external TPLD chip (corresponding to the digital logic circuit described above). The circuit connection diagram is shown below. Figure 5 As shown, the signal logic transformation is as follows: Figure 6 As shown, the signal timing is as follows Figure 7 As shown. In Figure 6 In this context, NOT stands for NOT gate, AND stands for AND gate, XOR stands for XOR gate, and NAND stands for NAND gate.

[0067] like Figure 7 As shown, since only one additional PWM signal can be used, this combinational logic needs to multiply the PWM5 signal. The calculation relationships for each time point in the diagram are as follows: ; in, and All of these can be read from the chip's internal registers. To ensure timeliness, the pulse width of PWM5 can be synchronously refreshed within the switching interrupt.

[0068] In one implementation, when the main control unit has a sufficient number of PWM output ports and sufficient on-chip resources, a second set of drive signals for controlling the auxiliary power switch is generated by the PWM generation subunit inside the main control unit. The circuit connection diagram is shown below. Figure 8 As shown, the signal timing is as follows Figure 9As shown in the diagram. Both Ts and Tpwm1 can be read from the chip's internal registers. PWM5 and PWM6 have the same frequency as PWM1, and their waveforms are identical with a 180° phase difference. The rising edge of PWM5 aligns with the falling edge of PWM1, and the rising edge of PWM6 aligns with the falling edge of PWM3. Their pulse widths are T6-T5, calculated using the following formula. They use a sawtooth wave as the carrier wave. A schematic diagram of carrier modulation generating the PWM waveform is shown below. Figure 10 As shown.

[0069] In one implementation, reference Figure 8 The PWM generation subunit inside the main control unit includes the PWM generator within the main control unit and the on-chip inverter NOT. For example... Figure 9 As shown, this scheme generates drive waveforms for switches Q8 and Q7 that are complementary to the waveforms of PWM5 and PWM6, respectively. Therefore, it is only necessary to calculate... and The values ​​of are calculated as follows: ; In summary, this embodiment designs two solutions for MCUs with limited peripheral resources (e.g., only 5 PWM channels) and those with sufficient resources: TPLD expansion (corresponding to generating a second set of drive signals for controlling the auxiliary power switch through external digital logic circuitry) and no peripheral expansion (corresponding to generating a second set of drive signals for controlling the auxiliary power switch through the PWM generation subunit inside the main control unit). Under limited resources, refer to... Figure 5 By multiplying the PWM5 signal using a TPLD, a single additional PWM channel is used to implement the complex timing of switches Q7 and Q8; under sufficient resources, refer to Figure 8 The timing sequence is generated directly using the same frequency PWM signals (PWM5 and PWM6) in conjunction with the on-chip inverter NOT, resulting in almost zero hardware cost. Both solutions avoid the redundant design of complex external analog circuits in the traditional C solution, saving space on high-power-density PCBs where space is at a premium, and adapting to the space requirements of high-power-density modules above 2000W.

[0070] This embodiment generates a first set of drive signals to control the main power switch transistor by the main control unit, and then generates a second set of drive signals to control the auxiliary power switch transistor by the PWM generation subunit inside the main control unit or by external digital logic circuitry based on these signals. By dynamically adjusting the waveform of at least one auxiliary drive signal in relation to the pulse width and switching period of the corresponding reference drive signal, three core beneficial effects are achieved: First, it significantly improves the power supply efficiency by effectively reducing switching losses through precise digital timing control; second, it greatly optimizes system integration by replacing complex analog circuits with a simple digital architecture, saving valuable PCB space and perfectly adapting to high power density applications; and third, it comprehensively enhances system performance by providing the flexibility to adjust parameters through software while ensuring control accuracy and anti-interference capabilities, making the system both highly reliable and highly scalable, providing an innovative and practical solution for high-efficiency power supply design.

[0071] Example 3: This embodiment proposes a power supply device, which in one implementation includes the control module for improving the working efficiency of the Buck power supply and the Buck power supply described in Embodiment 2.

[0072] This embodiment generates a first set of drive signals to control the main power switch transistor by the main control unit, and then generates a second set of drive signals to control the auxiliary power switch transistor by the PWM generation subunit inside the main control unit or by external digital logic circuitry based on these signals. By dynamically adjusting the waveform of at least one auxiliary drive signal in relation to the pulse width and switching period of the corresponding reference drive signal, three core beneficial effects are achieved: First, it significantly improves the power supply efficiency by effectively reducing switching losses through precise digital timing control; second, it greatly optimizes system integration by replacing complex analog circuits with a simple digital architecture, saving valuable PCB space and perfectly adapting to high power density applications; and third, it comprehensively enhances system performance by providing the flexibility to adjust parameters through software while ensuring control accuracy and anti-interference capabilities, making the system both highly reliable and highly scalable, providing an innovative and practical solution for high-efficiency power supply design.

[0073] For the specific structure of the control module for improving the working efficiency of the Buck power supply, please refer to Embodiment 2, which will not be repeated in this embodiment.

[0074] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for improving the operating efficiency of a Buck power supply, characterized in that, include: The main control unit generates the first set of drive signals to control the main power switching transistor. Based on the first set of drive signals, a second set of drive signals for controlling the auxiliary power switch is generated by the PWM generation subunit inside the main control unit or by the external digital logic circuit. The waveform of at least one auxiliary drive signal in the second group of drive signals is dynamically adjusted according to the relationship between the pulse width and the switching period of the corresponding reference drive signal in the first group of drive signals.

2. The method for improving the working efficiency of a Buck power supply according to claim 1, characterized in that, The method further includes: When the pulse width of the reference drive signal is less than or equal to 50% of the switching period, the corresponding auxiliary drive signal is always at a high level. When the pulse width of the reference drive signal is greater than 50% of the switching period, the corresponding auxiliary drive signal is configured such that after the falling edge of the reference drive signal, the auxiliary drive signal changes from high level to low level, and remains there for a period of time before changing back to high level. The duration of the low level is proportional to the effective pulse width of the reference drive signal.

3. The method for improving the working efficiency of a Buck power supply according to claim 2, characterized in that, The duration of the low level The following relationship must be satisfied: ； ； in, , The time parameter is related to the effective pulse width of the reference drive signal; The effective pulse width of the reference drive signal. The switching cycle.

4. The method for improving the working efficiency of a Buck power supply according to claim 1, characterized in that, The main power switching transistors include switching transistors Q1, Q2, Q3, Q4, Q5, and Q6; the auxiliary switching transistors include switching transistors Q7 and Q8. Switches Q7, Q1, Q3, and Q5 are connected in sequence; switches Q8, Q2, Q4, and Q6 are connected in sequence. Among them, the drive signal of switch Q4 is the same as the drive signal of switch Q1, and the drive signal of switch Q6 is complementary to the drive signal of switch Q1. When the pulse width of the drive signal of switch Q1 is less than or equal to 50%, the drive signal of switch Q8 is always high. When the pulse width of the drive signal of switch Q1 is greater than 50%, the drive signal of switch Q8 is maintained at a low level for a period of time based on the falling edge of the drive signal of switch Q1 before being set high. The drive signal for switch Q3 is the same as the drive signal for switch Q2, and the drive signal for switch Q5 is complementary to the drive signal for switch Q2. When the pulse width of the drive signal for switch Q2 is less than or equal to 50%, the drive signal for switch Q7 is always high. When the pulse width of the drive signal for switch Q2 is greater than 50%, the drive signal for switch Q7 is maintained at a low level for a period of time based on the falling edge of the drive signal for switch Q2, and then turned high.

5. The method for improving the working efficiency of a Buck power supply according to claim 1, characterized in that, When the main control unit has a sufficient number of PWM output ports and sufficient on-chip resources, a second set of drive signals for controlling the auxiliary power switching transistors is generated by the PWM generation subunit inside the main control unit. When the number of PWM output ports of the main control unit is insufficient and the on-chip resources are inadequate, a second set of drive signals for controlling the auxiliary power switching transistor is generated by external digital logic circuits.

6. The method for improving the working efficiency of a Buck power supply according to claim 1, characterized in that, The digital logic circuit is a programmable logic device; When the number of PWM output ports of the main control unit is insufficient, the programmable logic device performs frequency multiplication or logic transformation on at least one reference drive signal from the main control unit to generate the required second set of drive signals.

7. A control module for improving the operating efficiency of a Buck power supply, characterized in that, For implementing the method of improving the working efficiency of Buck power supply as described in any one of claims 1-6, the control module adopts a fully digital control architecture, including a main control unit. When the number of PWM output ports of the main control unit is sufficient and the on-chip resources are sufficient, the main control unit is configured to generate a first set of drive signals for controlling the main power switch, and generate a second set of drive signals for controlling the auxiliary power switch according to the first set of drive signals through its internal PWM generation subunit. When the number of PWM output ports of the main control unit is insufficient and the on-chip resources are inadequate, the control module further includes a digital logic circuit. The digital logic circuit is connected to the output terminal of the main control unit and is used to generate a second set of drive signals for controlling the auxiliary power switch based on the first set of drive signals. The waveform of at least one auxiliary drive signal in the second group of drive signals is dynamically adjusted according to the relationship between the pulse width and the switching period of the corresponding reference drive signal in the first group of drive signals.

8. The control module for improving the working efficiency of a Buck power supply according to claim 7, characterized in that, The digital logic circuit is configured as follows: For the waveform of at least one auxiliary drive signal in the second group of drive signals, when the pulse width of the reference drive signal in the first group of drive signals is greater than 50% of the switching period, the waveform is kept at a low level for a period of time after the falling edge of the reference drive signal before switching to a high level.

9. The control module for improving the working efficiency of a Buck power supply according to claim 7, characterized in that, The digital logic circuit is a programmable logic device or a conventional logic gate circuit.

10. A power supply device, characterized in that, The control module for improving the working efficiency of the Buck power supply as described in any one of claims 7-9 and the Buck power supply.

Images