A transformer driving chip, circuit and isolated power supply

Abstract

This invention relates to the field of transformer drive technology, and discloses a transformer drive chip, circuit, and isolated power supply. The transformer drive chip includes a mode selection unit, an oscillator, a selector, an LDO voltage regulator unit, a first drive MOSFET, a second drive MOSFET, a drive unit, a current sampling unit, a current monitoring unit, and a load sharing control unit. In use, the drive chip compares and judges the detected current by setting the load sharing control unit. When the detected current is large, it can automatically adjust the gate voltage of the first and second power MOSFETs. In this way, when multiple transformer drive chips of this invention are connected in parallel, the current of different transformer drive chips can be adaptively adjusted, preventing individual transformer drive chips from entering an overcurrent or overheating state. That is, the requirement of parallel connection of transformer drive chips to expand output power can be achieved while ensuring operational reliability.

Description

Technical Field

[0001] This invention relates to the field of transformer drive technology, specifically to a transformer drive chip, circuit, and isolated power supply. Background Technology

[0002] In isolated power supply design, the transformer driver circuit drives the primary winding of the isolation transformer, converting the DC voltage input to the primary winding into an AC square wave. This square wave is then coupled through the isolation transformer to generate the required output voltage on the secondary winding. Traditional transformer driver circuits are all single-driver chip designs, and their output power is limited by the current capability and thermal design of the power transistors inside the driver chip, typically with a maximum load capacity of only 1W-2W.

[0003] In certain applications such as industrial control, communication equipment, and medical electronics, isolated power supplies are required to provide higher output power, such as 4W, 5W, or even higher. To meet this need, existing solutions mainly include the following three types: One option is to use a transformer driver with higher power, but such chips are expensive and there are few models to choose from.

[0004] Second: Using discrete components to build push-pull or full-bridge drive circuits, but the design is complex, the reliability is low, and the PCB area is large.

[0005] Thirdly, multiple transformer driver chips can be directly connected in parallel to extend power output. However, due to differences in the on-resistance of the power transistors, drive timing, and PCB routing impedance among the various transformer driver chips, direct parallel connection can lead to severely uneven current distribution. Some transformer driver chips may bear excessive current, resulting in severe overheating, decreased efficiency, and even triggering overcurrent protection or thermal shutdown, leading to extremely low system reliability.

[0006] Based on the above, existing transformer driver chips, due to factors such as collaborative operation, current distribution, heat generation, and current protection, cannot expand output power through efficient parallel connection, resulting in poor safety and reliability. Summary of the Invention

[0007] In view of the shortcomings of the prior art, the present invention provides a transformer driver chip, circuit and isolated power supply. The technical problem to be solved is that the existing transformer driver chips are affected by factors such as cooperative operation, current distribution, heat generation and current protection, and cannot expand the output power through efficient parallel connection. The safety and reliability are also poor.

[0008] To solve the above technical problems, in a first aspect, the present invention provides the following technical solution: a transformer driver chip, comprising a mode selection unit, an oscillator, a selector, an LDO voltage regulator unit, a first driving MOSFET, a second driving MOSFET, a driver unit, a current sampling unit, a current monitoring unit, and a load sharing control unit; The mode selection unit sends a first control signal to the oscillator and a second control signal to the selector based on the input mode selection signal; the first control signal is used to control whether the oscillator generates a clock; the clock generated by the oscillator includes an internal clock and an external clock, and the internal clock and the external clock are input to the two input terminals of the selector; the second control signal is used to control the selector to select one clock from the input internal clock and the external clock and input it to the drive unit; The LDO voltage regulator unit is electrically connected to the driving unit and provides the driving unit with an operating voltage; the driving unit is electrically connected to the gate of the first driving MOS transistor and the gate of the second driving MOS transistor respectively, and provides the driving voltage to the gate of the first driving MOS transistor and the gate of the second driving MOS transistor based on the level of the input clock and the magnitude of the operating voltage. The current sampling unit is used to collect the magnitude of the current flowing through the second driving MOS transistor and generate two detection currents. The current monitoring unit is electrically connected to one of the current detection output terminals of the current sampling unit, and is used to input an overcurrent detection signal to the LDO voltage regulator unit when the first detection voltage corresponding to the one detection current is greater than the reference voltage; the overcurrent detection signal is used to control the LDO voltage regulator unit to stop outputting the operating voltage; The load sharing control unit is electrically connected to another current detection output terminal of the current sampling unit. The control voltage is provided to the LDO voltage regulator unit based on the difference between the second detection voltage corresponding to the other detection current and the reference voltage. The operating voltage output by the LDO voltage regulator unit is positively correlated with the control voltage.

[0009] In one embodiment of the first aspect, the LDO voltage regulator unit includes an operational amplifier AMP1 and a MOSFET PM1; The source of the MOS transistor PM1 is used to input the power supply voltage. The gate of the MOS transistor PM1 is electrically connected to the output terminal of the operational amplifier AMP1. The negative input terminal of the operational amplifier AMP1 is used to input the control voltage. The drain of the MOS transistor PM1 is electrically connected to the positive input terminal of the operational amplifier AMP1 and is used to output the operating voltage. The overcurrent detection signal is input to the operational amplifier AMP1 to control whether the operational amplifier AMP1 is working.

[0010] In one embodiment of the first aspect, the load sharing control unit includes an error amplifier AMP2, a MOSFET NM3, and a load resistor; One end of the load resistor is used to input the power supply voltage, and the other end of the load resistor is electrically connected to the drain of the MOSFET NM3; the gate of the MOSFET NM3 is electrically connected to the output terminal of the error amplifier AMP2, the positive input terminal of the error amplifier AMP2 is electrically connected to the detection current output terminal of the current sampling unit, and the negative input terminal of the error amplifier AMP2 is used to input the reference voltage; the source of the MOSFET NM3 is grounded.

[0011] In one embodiment of the first aspect, the load sharing control unit further includes an error amplifier AMP3 and a MOS transistor PM2; The source of the MOSFET PM2 is used to input the power supply voltage; the gate of the MOSFET PM2 is electrically connected to the output terminal of the error amplifier AMP3, the positive input terminal of the error amplifier AMP3 is used to input the operating voltage, and the negative input terminal of the error amplifier AMP2 is used to input the limiting voltage; the drain of the MOSFET PM2 is electrically connected to the other end of the load resistor.

[0012] In one embodiment of the first aspect, the load sharing control unit further includes a maximum current setting unit, the drain of the MOS transistor NM3 is grounded through the maximum current setting unit, and the maximum current setting unit is used to limit the maximum current flowing through the load resistor to a set threshold current.

[0013] In one embodiment of the first aspect, the current sampling unit includes a current mirror and a mirror MOS transistor; the mirror MOS transistor is connected to the second driving MOS transistor to form a current mirror structure, and the mirror MOS transistor is used to replicate the current flowing through the second driving MOS transistor according to a set ratio; the current mirror is used to replicate the current flowing through the mirror MOS transistor and then output a detection current. The current monitoring unit includes a comparator CMP1, the positive input terminal of which is electrically connected to the detection current output terminal of the current sampling unit, and the negative input terminal of which is used to input the reference voltage. The transformer driver chip also includes a current source IREF and a switch S1. The current source IREF outputs a reference current through the switch S1, and the reference current forms a reference voltage across the corresponding reference resistor. The mode selection signal is used to control the on / off state of the switch S1.

[0014] In one embodiment of the first aspect, the driving unit outputs the driving voltage when the input clock is high; the driving unit includes an even number of inverters connected in series, and the driving current output by each inverter gradually increases along the series connection direction of the inverters; The input terminal of the first inverter is electrically connected to the output terminal of the selector, and the output terminal of the last inverter is used to output the driving voltage; the operating voltage is input to the power supply terminal of the last inverter.

[0015] In one embodiment of the first aspect, the transformer driver chip further includes a chip body, and the mode selection unit, oscillator, selector, LDO voltage regulator unit, first driving MOSFET, second driving MOSFET, driving unit, current sampling unit, current monitoring unit and load sharing control unit are all disposed on the chip body; The chip body is equipped with a mode selection pin MODE, a clock pin CLK, a drive connection pin DRV1, a power supply pin VIN, a drive connection pin DRV2, a current monitoring pin IMON, a load sharing control pin ILS, a reference pin IREF, and a ground pin. The mode selection pin MODE is electrically connected to the mode selection signal input terminal of the mode selection unit; the clock pin CLK is electrically connected to the external clock output terminal of the oscillator; the drive connection pin DRV1 is electrically connected to the drain of the first drive MOSFET; the drive connection pin DRV2 is electrically connected to the drain of the second drive MOSFET; the power supply pin VIN is electrically connected to the LDO voltage regulator unit and is used to input the power supply voltage; the current monitoring pin IMON and the load sharing control pin ILS are respectively electrically connected to the two current detection output terminals of the current sampling unit; the reference pin IREF is respectively electrically connected to the current monitoring unit and the load sharing control unit and is used to input the reference voltage; the ground pin is used for grounding.

[0016] Secondly, the present invention also provides a transformer driving circuit, including the above-mentioned transformer driving chip; the number of the transformer driving chip is greater than 1. In all transformer driver chips, the mode selection unit of one transformer driver chip receives a mode selection signal, and the selector of that transformer driver chip selects an internal clock for output; the mode selection signal input of the mode selection unit of the remaining transformer driver chips is grounded, and the selector of the remaining transformer driver chips selects an external clock for output. The external clock outputs of the oscillators of all transformer driver chips are electrically connected to each other; The reference voltage connection terminals of all transformer driver chips are electrically connected to each other and grounded through a reference resistor; The current sampling units of all transformer driver chips have one current detection output terminal connected to each other and grounded through a current monitoring resistor. The other current detection output terminal of the current sampling unit of each transformer driver chip is grounded through a shared control resistor; The power supply terminals of the LDO voltage regulator units of all transformer driver chips are electrically connected to each other for input power supply voltage; The drains of the first driving MOSFETs of all transformer driver chips are electrically connected to each other; the drains of the second driving MOSFETs of all transformer driver chips are electrically connected to each other.

[0017] Thirdly, the present invention also provides an isolated power supply, including the above-mentioned transformer drive circuit; it also includes a transformer TR, a diode D1, a diode D2, a capacitor CL, and a resistor RL; The power supply terminal of the LDO regulator unit of all transformer driver chips is electrically connected to the center tap of the primary winding of the transformer TR. The drain of the first driving MOSFET of all transformer driver chips is electrically connected to one end of the primary winding of transformer TR; the drain of the second driving MOSFET of all transformer driver chips is electrically connected to the other end of the primary winding of transformer TR. One end of the secondary winding of the transformer TR is electrically connected to the anode of diode D1, and the other end of the secondary winding of the transformer TR is electrically connected to the anode of diode D2. The cathode of diode D1 is electrically connected to the cathode of diode D2, one end of capacitor CL, and one end of resistor RL, respectively. The other end of capacitor CL and the other end of resistor RL are both electrically connected to the center tap of the secondary winding of transformer TR.

[0018] The beneficial effects of this invention compared to the prior art are: First, by setting up a load-sharing control unit to compare and judge the detected current, the gate voltage of the first power MOSFET and the second power MOSFET can be automatically adjusted when the detected current is large. In this way, when multiple transformer driver chips of the present invention are connected in parallel, the current between different transformer driver chips can be adaptively adjusted to prevent a single transformer driver chip from entering an overcurrent or overheating state. That is, the requirement of parallel connection of transformer driver chips to expand output power can be achieved while ensuring operational reliability. Secondly, when all the transformer driver chips are connected in parallel to form an isolated power supply, the master and slave clocks of all the transformer driver chips are synchronized, which can ensure that the switching actions of all parallel chips are completely synchronized, eliminating current spikes and additional losses caused by differences in switching timing, and ensuring the stable operation of the parallel system. In addition, when all the transformer driver chips are connected in parallel to form an isolated power supply, each transformer driver chip realizes total overcurrent protection through the current monitoring unit and realizes current sharing trigger judgment through the load sharing control unit. The combination of the two ensures high efficiency under light load and safety and balance under heavy load / overload. Finally, the current sharing effect between different transformer-driven chips reduces the chip current that originally had the largest current. According to the Black equation (electromigration lifetime model), the reduction of current stress can significantly improve chip life, thereby increasing the effective life of the system by several times. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the transformer driver chip in Embodiment 1; Figure 2 for Figure 1 Circuit diagram of the load sharing control unit, LDO voltage regulator unit and drive unit in the system; Figure 3 This is a circuit diagram of the transformer drive circuit in Example 2; Figure 4 This is a circuit diagram of the isolated power supply in Example 3. Detailed Implementation

[0020] The illustrative embodiments of this application include, but are not limited to, a transformer driver chip, a circuit, and a switching power supply.

[0021] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0022] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. Words such as “comprising” or “including” mean that the element or object preceding “comprising” or “including” covers the element or object listed following “comprising” or “including” and its equivalents, and does not exclude other elements or objects. Words such as “connected” or “linked” are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0023] Example 1 like Figure 1 As shown, this embodiment provides a transformer driver chip, including a mode selection unit 1, an oscillator 2, a selector 3, an LDO voltage regulator unit 4, a first driving MOSFET NM1, a second driving MOSFET NM2, a driver unit 5, a current sampling unit 6, a current monitoring unit 7, and a load sharing control unit 8. The mode selection unit 1 sends a first control signal CT1 to the oscillator 2 and a second control signal CT2 to the selector 3 based on the input mode selection signal. The first control signal CT1 is used to control whether the oscillator 2 generates a clock. The clock generated by the oscillator 2 includes an internal clock and an external clock, which are input to the two input terminals of the selector 3. The internal clock and the external clock have the same frequency. The second control signal CT2 is used to control the selector 3 to select one clock from the input internal clock and the external clock and input it to the drive unit. The LDO voltage regulator unit 4 is electrically connected to the drive unit 5, providing the drive unit 5 with the operating voltage VDRV; the drive unit 5 is electrically connected to the gate of the first drive MOS transistor NM1 and the gate of the second drive MOS transistor NM2 respectively, and provides the drive voltage VV to the gate of the first drive MOS transistor NM1 and the gate of the second drive MOS transistor NM2 based on the input clock level and the magnitude of the operating voltage VDRV. The current sampling unit 6 is used to collect the magnitude of the current flowing through the second driving MOSFET NM2 and generate two detection currents Is; The current monitoring unit 7 is electrically connected to one of the current detection output terminals of the current sampling unit 6. It is used to input an overcurrent detection signal VOCP to the LDO voltage regulator unit 4 when the first detection voltage VMON corresponding to the one detection current Is is greater than the reference voltage VREF. The overcurrent detection signal VOCP is used to control the LDO voltage regulator unit 4 to stop outputting the working voltage VDRV. The load sharing control unit 8 is electrically connected to the other current detection output terminal of the current sampling unit 6. The difference between the second detection voltage VLS corresponding to the other detection current Is and the reference voltage VREF is used to provide the control voltage VADJ to the LDO voltage regulator unit. The operating voltage VDRV output by the LDO voltage regulator unit 4 is positively correlated with the control voltage VADJ. The first detection voltage VMON and the second detection voltage VLS are generated by the two detection currents Is flowing through the corresponding resistors.

[0024] In practical use, the present invention first compares and judges the detected current Is by setting a load sharing control unit 8. When the detected current Is is large, the gate voltage of the first power MOSFET NM1 and the second power MOSFET NM2 can be automatically adjusted. In this way, when multiple transformer driver chips of the present invention are connected in parallel, the current between different transformer driver chips can be adaptively adjusted to prevent a single transformer driver chip from entering an overcurrent or overheating state. That is, the requirement of parallel connection of transformer driver chips to expand output power can be achieved while ensuring operational reliability. Secondly, when all the transformer driver chips are connected in parallel to form an isolated power supply, the master and slave clocks of all the transformer driver chips are synchronized, which can ensure that the switching actions of all parallel chips are completely synchronized, eliminating current spikes and additional losses caused by differences in switching timing, and ensuring the stable operation of the parallel system. In addition, when all the transformer driver chips are connected in parallel to form an isolated power supply, each transformer driver chip achieves total overcurrent protection through the current monitoring unit 7 and current sharing trigger judgment through the load sharing control unit 8. The combination of the two ensures high efficiency under light load and safety and balance under heavy load / overload. Finally, the current sharing effect between different transformer-driven chips reduces the chip current that originally had the largest current. According to the Black equation (electromigration lifetime model), the reduction of current stress can significantly improve chip life, thereby increasing the effective life of the system by several times.

[0025] Furthermore, in this embodiment, the mode selection signal can be a digital signal. When the mode selection signal is high, the first control signal generated by the mode selection unit 1 controls the oscillator 2 to generate a clock, and the second control signal generated by the mode selection unit 1 controls the selector 3 to select the internal clock output. When the mode selection signal is low, the first control signal generated by the mode selection unit 1 controls the oscillator 2 not to generate a clock, and the second control signal generated by the mode selection unit 1 controls the selector 3 to select the external clock output.

[0026] Furthermore, in this embodiment, the driving voltage VV is positively correlated with the operating voltage VDRV. That is, the larger the operating voltage VDRV, the larger the driving voltage VV; the smaller the operating voltage VDRV, the smaller the driving voltage VV.

[0027] Specifically, in this implementation, such as Figure 2 As shown, the LDO voltage regulator unit 4 includes an operational amplifier AMP1 and a MOSFET PM1, where the MOSFET PM1 is a PMOS transistor; The source of MOSFET PM1 is used to input the power supply voltage VCC. The gate of MOSFET PM1 is electrically connected to the output terminal of operational amplifier AMP1. The negative input terminal of operational amplifier AMP1 is used to input the control voltage VADJ. The drain of MOSFET PM1 is electrically connected to the positive input terminal of operational amplifier AMP1 and is used to output the operating voltage VDRV. The overcurrent detection signal VOCP is input to the operational amplifier AMP1 to control whether the operational amplifier AMP1 is working.

[0028] In practical use, when an overcurrent detection signal VOCP is detected, the operational amplifier AMP1 stops working, thereby causing the drive unit 5 to stop outputting the drive voltage VV, thus achieving overcurrent protection.

[0029] Specifically, in this embodiment, the load sharing control unit 8 includes an error amplifier AMP2, a MOS transistor NM3, and a load resistor R1, wherein the MOS transistor NM3 is an NMOS transistor; One end of the load resistor R1 is used to input the power supply voltage VCC, and the other end of the load resistor R1 is electrically connected to the drain of the MOSFET NM3; the gate of the MOSFET NM3 is electrically connected to the output of the error amplifier AMP2, the positive input of the error amplifier AMP2 is electrically connected to the current detection output of the current sampling unit 6, and the negative input of the error amplifier AMP2 is used to input the reference voltage VREF; the source of the MOSFET NM3 is grounded.

[0030] In practical use, when the voltage level at the positive input terminal of error amplifier AMP2 changes, the voltage difference between the positive and negative input terminals of AMP2 changes, thereby adjusting the gate voltage of MOSFET NM3, which in turn adjusts the current IADJ. The change in current IADJ alters the voltage drop across the load resistor R1, ultimately changing the control voltage VADJ. This change in control voltage VADJ leads to a change in the operating voltage VDRV, which in turn changes the drive voltage VV. Ultimately, this adjusts the on / off state (i.e., the impedance) of the first drive MOSFET NM1 and the second drive MOSFET NM2, achieving current feedback adjustment.

[0031] In practical applications, to prevent the operating voltage VDRV from becoming too low, i.e., to prevent the current flowing through the first driving MOSFET NM1 and the second driving MOSFET NM2 from decreasing indefinitely, Figure 2 In the load sharing control unit 8, there are also error amplifier AMP3 and MOS transistor PM2, where MOS transistor PM2 is a PMOS transistor; The source of MOSFET PM2 is used to input the power supply voltage VCC; the gate of MOSFET PM2 is electrically connected to the output terminal of error amplifier AMP3. The positive input terminal of error amplifier AMP3 is used to input the operating voltage VDRV, and the negative input terminal of error amplifier AMP2 is used to input the limiting voltage VLIM; the drain of MOSFET PM2 is electrically connected to the other end of the load resistor.

[0032] In practical applications, setting a limiting voltage VLIM can limit the minimum value of the operating voltage VDRV. When the operating voltage VDRV drops to the limiting voltage VLIM, the impedance-limited negative feedback loop composed of error amplifier AMP3 and MOSFET PM2 intervenes, preventing the operating voltage VDRV from decreasing further and keeping it approximately equal to the limiting voltage VLIM. Consequently, the on-resistance of the first power MOSFET NM1 and the second power MOSFET NM2 is also limited.

[0033] Furthermore, in order to avoid excessive current flowing through the load resistor R1, the load sharing control unit 8 also includes a maximum current setting unit 80. The drain of the MOSFET NM3 is grounded through the maximum current setting unit 80. The maximum current setting unit 80 is used to limit the maximum current flowing through the load resistor R1 to a set threshold current.

[0034] Specifically, in this embodiment, as Figure 1 As shown, the current sampling unit 6 includes a current mirror 60 and a mirror MOSFET NMS. The mirror MOSFET NMS is connected to the second driving MOSFET NM2 to form a current mirror structure. The mirror MOSFET NMS is used to replicate the current flowing through the second driving MOSFET NM2 according to a set ratio. The current mirror 60 is used to replicate the current flowing through the mirror MOSFET and then output the detection current. In use, the set ratio is set according to the size ratio of the mirror MOSFET NMS and the second driving MOSFET NM2, which is not limited here. The current monitoring unit 7 includes a comparator CMP1. The positive input terminal of the comparator CMP1 is electrically connected to the detection current output terminal of the current sampling unit 6, and the negative input terminal of the comparator CMP1 is used to input the reference voltage VREF. In this embodiment, the reference voltage VREF can be generated internally or externally. When the reference voltage VREF is generated internally, in... Figure 1In addition, the present invention also includes a current source IREF and a switch S1. The current source IREF outputs a reference current through the switch S1, and the reference current acts on the reference resistor to form a reference voltage VREF. A mode selection signal is used to control the on and off of the switch S1. When the mode selection signal is high, the switch S1 is turned on, and when the mode selection signal is low, the switch S1 is turned off. In addition, by controlling the on and off of the switch S1 through the mode selection signal, when multiple transformer driver chips are connected in parallel, only the switch S1 of one transformer driver chip needs to be turned on, that is, only one current source IREF works, which can reduce power consumption.

[0035] Specifically, in this embodiment, as Figure 2 As shown, the drive unit 5 includes an even number of inverters INV connected in series. Along the series connection direction of the inverters INV, the drive current output by each inverter INV gradually increases. The drive current can be gradually increased by controlling the size of the MOS transistor in each inverter INV. The input terminal of the first inverter INV is electrically connected to the output terminal of selector 2, and the output terminal of the last inverter INV is used to output the drive voltage VV; the operating voltage VDRV is input to the power supply terminal of the last inverter INV.

[0036] Furthermore, in this embodiment, in Figure 1 In addition, the driver chip also includes a VCC regulator, which generates the bias voltage and limit voltage VLIM required by the driver chip based on the magnitude of the power supply voltage VCC.

[0037] Furthermore, in this embodiment, in Figure 1 In addition, the present invention also includes a chip body 10, and a mode selection unit 1, an oscillator 2, a selector 3, an LDO voltage regulator unit 4, a first driving MOSFET NM1, a second driving MOSFET NM2, a driving unit 5, a current sampling unit 6, a current monitoring unit 7, and a load sharing control unit 8 are all disposed on the chip body 10. The chip body 10 has a mode selection pin MODE, a clock pin CLK, a drive connection pin DRV1, a power supply pin VIN, a drive connection pin DRV2, a current monitoring pin IMON, a load sharing control pin ILS, a reference pin IREF, and a ground pin GND. The mode selection pin MODE is electrically connected to the mode selection signal input terminal of mode selection unit 1; the clock pin CLK is electrically connected to the external clock output terminal of oscillator 2; the drive connection pin DRV1 is electrically connected to the drain of the first drive MOSFET NM1; the drive connection pin DRV2 is electrically connected to the drain of the second drive MOSFET NM2; the power supply pin VIN is electrically connected to LDO voltage regulator unit 4 and is used to input the power supply voltage VCC; the current monitoring pin IMON and the load sharing control pin ILS are electrically connected to the two current detection output terminals of current sampling unit 60, respectively; the reference pin IREF is electrically connected to current monitoring unit 7 and load sharing control unit 8, respectively, and is used to input the reference voltage VREF; the ground pin GND is used for grounding.

[0038] In a further embodiment, an enable pin EN can also be provided on the chip body 10. The enable pin EN is used to input the enable signal VEN. The transformer driver chip only starts to work when the enable signal VEN is present.

[0039] Example 2 This embodiment provides a transformer drive circuit, including the transformer drive chip in Embodiment 1; the number of transformer drive chips is greater than 1. In all transformer driver chips, the mode selection unit 1 of one transformer driver chip receives the mode selection signal, and the selector 3 of one transformer driver chip selects the internal clock for output; the mode selection signal input terminal of the mode selection unit 1 of the remaining transformer driver chips is grounded, and the selector 3 of the remaining transformer driver chips selects the external clock for output; the selected transformer driver chip is used as the master chip, and the remaining transformer driver chips are all used as slave chips, that is, the mode selection pin MODE of the master chip receives the mode selection signal, and the mode selection pin MODE of the slave chip is grounded; The external clock output terminals of the oscillator 2 of all transformer driver chips are electrically connected to each other, that is, the clock pins CLK of all transformer driver chips are electrically connected to each other; in this way, all slave chips share the external clock output of the oscillator 2 of the master chip, thereby ensuring timing synchronization. The reference voltage connection terminals of all transformer driver chips are electrically connected to each other, namely the reference pin IREF of all transformer driver chips, and grounded through the reference resistor REF. The current sampling units 6 of all transformer driver chips are electrically connected to each other, that is, the current monitoring pins IMON of all transformer driver chips are electrically connected to each other and grounded through the current monitoring resistor RMON; at this time, the first detection voltage VMON is the voltage on the current monitoring resistor RMON. The other current detection output terminal of the current sampling unit 6 of each transformer driver chip is grounded through a shared control resistor RLSx, where x is a positive integer and the maximum value is the same as the number of transformer driver chips; at this time, the second detection voltage VLS is the voltage on the shared control resistor. The power supply terminals of the LDO voltage regulator unit 4 of all transformer driver chips are electrically connected to each other, that is, the power supply pins VIN of all transformer driver chips are electrically connected to each other for input power supply voltage VCC. The drains of the first driving MOSFET NM1 of all transformer driver chips are electrically connected to each other, that is, the driving connection pins DRV1 of all transformer driver chips are electrically connected to each other; the drains of the second driving MOSFET NM2 of all transformer driver chips are electrically connected to each other, that is, the driving connection pins DRV2 of all transformer driver chips are electrically connected to each other.

[0040] An exemplary circuit diagram of a transformer drive circuit including two transformer drive chips is shown below. Figure 3 As shown. In one implementation, three, four, or five transformer driver chips from Embodiment 1 can be connected in parallel to expand the output power, depending on actual needs.

[0041] The operation of a single transformer driver chip in this embodiment is as follows: If the detection current Is increases, then the voltage VLS increases → the current IADJ increases → the control voltage VADJ decreases → the operating voltage VDRV decreases → the on-resistance of the first driving MOSFET NM1 and the second driving MOSFET NM2 increases → the current decreases → the detection current Is decreases → the voltage VLS decreases. Finally, in the feedback, the voltage VLS is maintained at approximately equal to the reference voltage VREF. The larger this small voltage difference between VLS and VREF, the lower the control voltage VADJ, until the intermediate voltage VDRV reaches the limit voltage VLIM.

[0042] The operation of the transformer drive circuit in this embodiment is as follows: When the load sharing control unit 8 of any transformer driver chip detects that its chip output current exceeds the load sharing start threshold, the chip will output a control voltage VADJ based on the error between the chip's detected current Is and the reference voltage VREF.

[0043] The control voltage VADJ acts on the LDO regulator unit 4 of the chip itself, reducing the operating voltage VDRV output by the LDO regulator unit. The reduction in the operating voltage VDRV causes the gate voltage of the first driving MOSFET NM1 and the second driving MOSFET NM2 of the chip to decrease, thereby increasing their on-resistance.

[0044] According to the current sharing principle of parallel circuits, if the impedance of one path increases, the current it receives will inevitably decrease. Therefore, the output current of the driver chip decreases, and the excess current will be automatically distributed to other parallel driver chips that have not yet triggered current sharing or have lower impedance.

[0045] The above negative feedback process continues until the output current of all parallel drive chips is lower than the load sharing start-up threshold, or the current of each chip reaches a basic balance.

[0046] The above process ensures that each driver chip can actively adjust at the edge of heavy load or overload, preventing a single driver chip from entering the overcurrent or overheat state first, and distributing thermal and electrical stress evenly to all parallel driver chips, thereby maximizing the overall available power and reliability of the system.

[0047] Example 3 like Figure 4 As shown, this embodiment provides an isolated power supply, including the transformer drive circuit in Embodiment 2; it also includes a transformer TR, diode D1, diode D2, capacitor CL, and resistor RL; The power supply terminal of the LDO regulator unit 4 of all transformer driver chips is electrically connected to the center tap of the primary winding of the transformer TR. The drain of the first driving MOS transistor NM1 of all transformer driver chips is electrically connected to one end of the primary winding of transformer TR; the drain of the second driving MOS transistor NM2 of all transformer driver chips is electrically connected to the other end of the primary winding of transformer TR. One end of the secondary winding of transformer TR is electrically connected to the anode of diode D1, and the other end of the secondary winding of transformer TR is electrically connected to the anode of diode D2. The cathode of diode D1 is electrically connected to the cathode of diode D2, one end of capacitor CL, and one end of resistor RL, respectively. The other end of capacitor CL and the other end of resistor RL are both electrically connected to the center tap of the secondary winding of transformer TR.

[0048] Based on the above description, those skilled in the art can make various changes and modifications without departing from the technical concept of this invention. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A transformer driver chip, characterized in that, It includes a mode selection unit, an oscillator, a selector, an LDO voltage regulator unit, a first driving MOSFET, a second driving MOSFET, a drive unit, a current sampling unit, a current monitoring unit, and a load sharing control unit; The mode selection unit sends a first control signal to the oscillator and a second control signal to the selector based on the input mode selection signal; the first control signal is used to control whether the oscillator generates a clock; the clock generated by the oscillator includes an internal clock and an external clock, and the internal clock and the external clock are input to the two input terminals of the selector; the second control signal is used to control the selector to select one clock from the input internal clock and the external clock and input it to the drive unit; The LDO voltage regulator unit is electrically connected to the driving unit and provides the driving unit with an operating voltage; the driving unit is electrically connected to the gate of the first driving MOS transistor and the gate of the second driving MOS transistor respectively, and provides the driving voltage to the gate of the first driving MOS transistor and the gate of the second driving MOS transistor based on the input clock level and the magnitude of the operating voltage. The current sampling unit is used to collect the magnitude of the current flowing through the second driving MOS transistor and generate two detection currents. The current monitoring unit is electrically connected to one of the current detection output terminals of the current sampling unit, and is used to input an overcurrent detection signal to the LDO voltage regulator unit when the first detection voltage corresponding to the one detection current is greater than the reference voltage; the overcurrent detection signal is used to control the LDO voltage regulator unit to stop outputting the operating voltage; The load sharing control unit is electrically connected to another current detection output terminal of the current sampling unit. The control voltage is provided to the LDO voltage regulator unit based on the difference between the second detection voltage corresponding to the other detection current and the reference voltage. The operating voltage output by the LDO voltage regulator unit is positively correlated with the control voltage.

2. The transformer driver chip according to claim 1, characterized in that, The LDO voltage regulator unit includes an operational amplifier AMP1 and a MOSFET PM1; The source of the MOS transistor PM1 is used to input the power supply voltage. The gate of the MOS transistor PM1 is electrically connected to the output terminal of the operational amplifier AMP1. The negative input terminal of the operational amplifier AMP1 is used to input the control voltage. The drain of the MOS transistor PM1 is electrically connected to the positive input terminal of the operational amplifier AMP1 and is used to output the operating voltage. The overcurrent detection signal is input to the operational amplifier AMP1 to control whether the operational amplifier AMP1 is working.

3. A transformer driver chip according to claim 1, characterized in that, The load sharing control unit includes an error amplifier AMP2, a MOSFET NM3, and a load resistor; One end of the load resistor is used to input the power supply voltage, and the other end of the load resistor is electrically connected to the drain of the MOSFET NM3; the gate of the MOSFET NM3 is electrically connected to the output terminal of the error amplifier AMP2, the positive input terminal of the error amplifier AMP2 is electrically connected to the detection current output terminal of the current sampling unit, and the negative input terminal of the error amplifier AMP2 is used to input the reference voltage; the source of the MOSFET NM3 is grounded.

4. A transformer driver chip according to claim 3, characterized in that, The load sharing control unit also includes an error amplifier AMP3 and a MOSFET PM2; The source of the MOSFET PM2 is used to input the power supply voltage; the gate of the MOSFET PM2 is electrically connected to the output terminal of the error amplifier AMP3, the positive input terminal of the error amplifier AMP3 is used to input the operating voltage, and the negative input terminal of the error amplifier AMP2 is used to input the limiting voltage; the drain of the MOSFET PM2 is electrically connected to the other end of the load resistor.

5. A transformer driver chip according to claim 4, characterized in that, The load sharing control unit further includes a maximum current setting unit. The drain of the MOS transistor NM3 is grounded through the maximum current setting unit. The maximum current setting unit is used to limit the maximum current flowing through the load resistor to a set threshold current.

6. A transformer driver chip according to claim 1, characterized in that, The current sampling unit includes a current mirror and a mirror MOS transistor; the mirror MOS transistor is connected to the second driving MOS transistor to form a current mirror structure, and the mirror MOS transistor is used to replicate the current flowing through the second driving MOS transistor according to a set ratio; the current mirror is used to replicate the current flowing through the mirror MOS transistor and then output the detection current. The current monitoring unit includes a comparator CMP1, the positive input terminal of which is electrically connected to the detection current output terminal of the current sampling unit, and the negative input terminal of which is used to input the reference voltage. The transformer driver chip also includes a current source IREF and a switch S1. The current source IREF outputs a reference current through the switch S1, and the reference current forms a reference voltage across the corresponding reference resistor. The mode selection signal is used to control the on / off state of the switch S1.

7. A transformer driver chip according to claim 1, characterized in that, The driving unit outputs the driving voltage when the input clock is high; the driving unit includes an even number of inverters connected in series, and the driving current output by each inverter gradually increases along the series connection direction of the inverters. The input terminal of the first inverter is electrically connected to the output terminal of the selector, and the output terminal of the last inverter is used to output the driving voltage. The operating voltage is input to the power supply terminal of the terminal inverter.

8. A transformer driver chip according to any one of claims 1-7, characterized in that, The transformer driver chip also includes a chip body, and the mode selection unit, oscillator, selector, LDO voltage regulator unit, first driving MOSFET, second driving MOSFET, driving unit, current sampling unit, current monitoring unit and load sharing control unit are all disposed on the chip body; The chip body is equipped with a mode selection pin MODE, a clock pin CLK, a drive connection pin DRV1, a power supply pin VIN, a drive connection pin DRV2, a current monitoring pin IMON, a load sharing control pin ILS, a reference pin IREF, and a ground pin. The mode selection pin MODE is electrically connected to the mode selection signal input terminal of the mode selection unit; the clock pin CLK is electrically connected to the external clock output terminal of the oscillator; the drive connection pin DRV1 is electrically connected to the drain of the first drive MOSFET; the drive connection pin DRV2 is electrically connected to the drain of the second drive MOSFET; the power supply pin VIN is electrically connected to the LDO voltage regulator unit and is used to input the power supply voltage; the current monitoring pin IMON and the load sharing control pin ILS are respectively electrically connected to the two current detection output terminals of the current sampling unit; the reference pin IREF is respectively electrically connected to the current monitoring unit and the load sharing control unit and is used to input the reference voltage; the ground pin is used for grounding.

9. A transformer drive circuit, characterized in that, Includes the transformer driver chip according to any one of claims 1-8; the number of the transformer driver chips is greater than 1; In all transformer driver chips, the mode selection unit of one transformer driver chip inputs the mode selection signal, and the selector of the transformer driver chip selects the internal clock for output. The mode selection signal input terminal of the mode selection unit of the residual transformer driver chip is grounded, and the selector of the residual transformer driver chip selects an external clock for output. The external clock outputs of the oscillators of all transformer driver chips are electrically connected to each other; The reference voltage connection terminals of all transformer driver chips are electrically connected to each other and grounded through a reference resistor; The current sampling units of all transformer driver chips have one current detection output terminal connected to each other and grounded through a current monitoring resistor. The other current detection output terminal of the current sampling unit of each transformer driver chip is grounded through a shared control resistor; The power supply terminals of the LDO voltage regulator units of all transformer driver chips are electrically connected to each other for input power supply voltage; The drains of the first driving MOSFETs of all transformer driver chips are electrically connected to each other; the drains of the second driving MOSFETs of all transformer driver chips are electrically connected to each other.

10. An isolated power supply, characterized in that, Includes the transformer drive circuit as described in claim 9; further includes a transformer TR, diode D1, diode D2, capacitor CL, and resistor RL; The power supply terminal of the LDO regulator unit of all transformer driver chips is electrically connected to the center tap of the primary winding of the transformer TR. The drain of the first driving MOSFET of all transformer driver chips is electrically connected to one end of the primary winding of transformer TR; the drain of the second driving MOSFET of all transformer driver chips is electrically connected to the other end of the primary winding of transformer TR. One end of the secondary winding of the transformer TR is electrically connected to the anode of diode D1, and the other end of the secondary winding of the transformer TR is electrically connected to the anode of diode D2. The cathode of diode D1 is electrically connected to the cathode of diode D2, one end of capacitor CL, and one end of resistor RL, respectively. The other end of capacitor CL and the other end of resistor RL are both electrically connected to the center tap of the secondary winding of transformer TR.

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