A hybrid-mode three-phase four-wire vienna rectifier

Abstract

This invention discloses a hybrid-mode three-phase four-wire Vienna rectifier, relating to the field of power electronics technology. It includes a main power topology and a three-phase control loop. The main power topology includes an AC source, EMI filter, input inductor, rectifier bridge, bidirectional switching unit, upper and lower filter capacitors, and output load. The three-phase control loop includes a voltage acquisition unit, an error amplification unit, a zero-crossing detection unit, and a segmented modulation unit. This topology adds a neutral line to the three-wire system, allowing decoupling into three independent Boost converters operating in parallel, simplifying control logic and reducing hardware costs. Simultaneously, the segmented modulation unit implements CRM & DCM frequency conversion control, with the rectifier operating in CRM mode during the input voltage peak range and switching to constant-frequency DCM mode at the input voltage zero-crossing point. This control method limits the maximum operating frequency while maintaining unity power factor throughout, effectively reducing total harmonic distortion of the input current, minimizing the peak input current, and suppressing output voltage ripple.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a hybrid-mode three-phase four-wire Vienna rectifier. Background Technology

[0002] With the widespread application of power electronic equipment, Vienna rectifiers, with their advantages of fewer switching devices, lower voltage stress, higher efficiency, and stronger reliability, have become the preferred topology for medium and high power factor correction devices, and are widely used in new energy, communication power supplies, and industrial power quality management. Currently, the mainstream modulation methods for Vienna rectifiers mainly include Carrier Pulse Width Modulation (CBPWM) and Space Vector Pulse Width Modulation (SVPWM). CBPWM is simple to implement, but suffers from low DC voltage utilization, weak midpoint potential regulation, and high input current harmonics. While SVPWM offers better harmonic suppression and higher voltage utilization, its algorithms are complex, computationally intensive, and require high hardware timing accuracy, typically relying on high-speed digital controllers, resulting in higher hardware costs. Furthermore, traditional SVPWM uses fixed-frequency modulation, which is prone to current distortion, spikes, and high-frequency oscillations under light load and grid voltage zero-crossing conditions, leading to a decrease in overall efficiency and power quality.

[0003] Current research, both domestically and internationally, largely focuses on three-phase three-wire Vienna rectifiers, with relatively insufficient research on three-phase four-wire topologies and their high-performance control strategies. Compared to the three-wire system, the four-wire Vienna rectifier adds a neutral line, decoupling the three-phase circuit into three independent Boost converters operating in parallel. Each phase is controlled independently, exhibiting excellent adaptability to three-phase imbalance, grid distortion, and phase loss conditions, making it more practical for engineering applications. The DCM (Digital Current Management) mode Vienna rectifier offers numerous advantages, including zero-current turn-on of the switching transistors, no reverse recovery of the diodes, and simple control; however, it can only maintain a high input power factor at low input voltages. The CRM (Concentrated Power Factor) mode rectifier inherits some advantages of the DCM mode and can achieve unity power factor across the entire voltage range; however, its switching frequency variation range is too large, making EMI filter design difficult. At higher input voltages, the excessively high switching frequency leads to excessive rectifier losses and reduced efficiency.

[0004] Therefore, it is crucial to find a three-phase four-wire Vienna rectifier capable of hybrid mode control. Summary of the Invention

[0005] In view of this, the present invention implements CRM & DCM frequency conversion control through a segmented modulation unit. The three-phase four-wire Vienna rectifier operates in CRM mode during the peak input voltage range and switches to constant frequency DCM mode at the zero-crossing point of the input voltage. This control strategy can limit the maximum operating frequency and maintain unity power factor throughout, effectively reducing total harmonic distortion of the input current, reducing the peak input current, and suppressing output voltage ripple. The specific scheme is as follows: This invention relates to a hybrid-mode three-phase four-wire Vienna rectifier, comprising a main power topology and a three-phase control loop; the main power topology includes an AC source, EMI filter, input inductor, rectifier bridge, bidirectional switching unit, upper and lower filter capacitors, and DC load; the three-phase control loop includes a voltage acquisition unit, an error amplification unit, a zero-crossing detection unit, and a segmented modulation unit.

[0006] The main power topology (1) consists of a three-phase AC voltage source e a ~ e c (101) EMI high-frequency filter circuit (102) Three-phase input inductor L a ~ L c (103) Three-phase rectifier bridge (104) Phase A first bidirectional switching unit (105) Phase B second bidirectional switching unit (106) Phase C third bidirectional switching unit (107) Upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) and output load R 0 (110) Composition; Three-phase AC voltage source e a ~ e c (101) is the power frequency input power supply of the three-phase rectifier. Its three phase lines are connected to the three-phase input terminals of the EMI high-frequency filter circuit (102). The power frequency neutral point of the three-phase AC voltage source is the grid neutral terminal N. This power frequency neutral point N is grounded and connected to the grounding loop of the EMI high-frequency filter circuit (102). The three-phase output terminals of the EMI high-frequency filter circuit are connected in series with the three-phase input inductors. L a ~ L c (103); The three-phase rectifier bridge (104) consists of diodes D 1 , D 2 , D 3 , D 4 ,D 5 , D 6 Composition, diode D 1 , D 3 , D 5 The cathodes are connected together to form a DC positive bus, and the diodes D 2 , D 4 , D 6 The anodes are connected together to form a DC negative bus; input inductor L a Outgoing terminal access D 1 Anode and D 2 The A-phase line node between the cathodes, input inductance L b Outgoing terminal access D 3 Anode and D 4 The input inductance is located at the B-phase line node between the cathodes. L c Outgoing terminal access D 5 Anode and D 6 The C-phase line node between the cathodes; the first bidirectional switching unit (105) of phase A consists of a switching tube. Q 1 , Q 2 The source is connected in series and the gate is connected in parallel, with the gate connected to the A-phase drive signal. V Drv_a The second bidirectional switching unit (106) of phase B consists of a switching transistor. Q 3 , Q 4 The source is connected in series and the gate is connected in parallel, with the gate connected to the B-phase drive signal. V Drv_b The third bidirectional switch unit (107) of phase C is composed of Q 5 , Q 6 It is composed of a source connected in series and a gate connected in parallel, with the gate connected to the C-phase drive signal. V Drv_c Switching transistor Q 1 , Q 3 , Q 5The drains of the transistors are connected one-to-one to the phase line nodes of phases A, B, and C, respectively. Q 2 , Q 4 , Q 6 The drains of the capacitors are connected to the same point, which is defined as the DC midpoint M; the upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) Series connection of the first and last capacitors, filter capacitors C 1 The upper end connects to the DC positive bus and the filter capacitor. C 2 The lower end connects to the DC negative busbar. C 1 and C 2 The series connection point is the DC midpoint M, and the lead of the DC midpoint M is connected back to the internal grounding branch of the EMI high-frequency filter circuit (102); output load R 0 (110) Connected between the DC positive bus and the DC negative bus; the power frequency neutral point N and the DC neutral point M of the three-phase AC voltage source are both grounding points.

[0007] The three-phase control loop (2) consists of a voltage acquisition unit (201), an error amplification unit (202), a zero-crossing detection unit (203), and a segmented modulation unit (204); the voltage acquisition unit (201) includes an upper bus voltage acquisition unit (2011) and a capacitor. C 1 Parallel connection of the lower bus voltage acquisition unit (2012) and capacitor. C 2 The upper and lower bus voltage acquisition units are connected in parallel, with the midpoint of the upper and lower bus voltage acquisition units connected to the DC midpoint M and grounded; the input terminal of the error amplification unit (202) is connected to the output terminal of the voltage acquisition unit (201), and the output terminal of the error amplification unit (202) is connected to the inverting input terminal of the third comparator CMP3 (2041) in the dual-mode frequency conversion segmented modulation unit; the reference voltage terminal of the error amplification unit (202) is grounded; the sampling terminal of the zero-crossing detection unit (203) is connected to the three-phase input inductor. L a ~ L cThe two ends of (103) are connected in parallel. The output of the zero-crossing detection unit (203), the S-terminus of the third RS flip-flop RS3 (2044), and the first input of the OR gate in the adaptive ramp waveform generation unit (2047) are connected. The segmented modulation unit (204) includes a third comparator CMP3 (2041), a first RS flip-flop RS1 (2042), a second RS flip-flop RS2 (2043), a third RS flip-flop RS3 (2044), an AND gate (2045), a maximum switching frequency limiting generation unit (2046), and an adaptive ramp waveform generation unit (2047). The first input of the segmented modulation unit (204) is the inverting input of the third comparator CMP3 (2041) connected to the output of the error amplification unit (202). The second input of the segmented modulation unit (204) is the S-terminus of the third RS flip-flop RS3 (2044) connected to the output of the error amplification unit (202). The output terminal of the zero-crossing detection unit (203) is connected to the first input terminal of the OR gate in the adaptive ramp waveform generation unit (2047), which is connected to the output terminal of the zero-crossing detection unit (203). The output terminal of the segmented modulation unit (204) is the Q terminal of the first RS flip-flop RS1 (2042), which is connected to the gate of the first bidirectional switching unit (105) of phase A. The segmented modulation unit (204) can control the first bidirectional switching unit (105) of phase A, the second bidirectional switching unit (106) of phase B, and the third bidirectional switching unit (107) of phase C of the three-phase four-wire Vienna rectifier, so that the rectifier works in DCM mode and CRM mode. This circuit can limit the maximum operating frequency of the above bidirectional switching units and maintain unity power factor throughout the process, effectively reducing the total harmonic distortion of the input current, reducing the peak value of the input current, and suppressing the output voltage ripple.

[0008] The main power topology (1) is a three-phase four-wire structure. A neutral line is added on the basis of the three-phase three-wire topology, which can decouple the three-phase four-wire Vienna rectifier into three independent single-phase Boost converters that operate in parallel. Even if the three-phase input is unbalanced or a phase loss fault occurs, the device can still achieve the power factor correction function normally. For the three-phase control loop (2), namely the A-phase, B-phase, and C-phase control loops, the control methods of each phase are the same, with only a phase difference of 120°. The analysis of the three-phase control loop is based on the A-phase as an example. The analysis process of the B and C phases is completely consistent with that of the A-phase.

[0009] The voltage acquisition unit (201) includes an upper bus voltage acquisition unit (2011), a lower bus voltage acquisition unit (2012), and a two-input selector (2013); the upper bus voltage acquisition unit consists of a resistor. R 1 and R 2 Composition and capacitance C1 Parallel connection, the lower bus voltage acquisition unit consists of resistors R 3 and R 4 Composition and capacitance C 2 The upper and lower bus voltage acquisition units are connected in parallel, with the midpoint of the upper and lower bus voltage acquisition units connected to the DC midpoint M and grounded. The output terminals of the upper and lower bus voltage acquisition units are connected to the input terminals of a two-input selector (2013). The two input selectors are controlled by a three-phase AC voltage source. When the three-phase AC voltage source is in the positive half-cycle, the first terminal of the selector is activated; when the three-phase AC voltage source is in the negative half-cycle, the second terminal of the selector is activated. The output terminal of the two-input selector outputs... V FB It is connected to the input terminal of the error amplification unit (202).

[0010] The error amplification unit (202) consists of a PI compensation circuit (2021), an error amplifier EA (2022), and a first reference power supply. v 1 (2023) The first terminal of the PI compensation circuit (2021) is connected to the output terminal of the error amplifier EA (2022), and the second terminal is connected to the inverting input terminal of the third comparator CMP3 (2041) in the segmented modulation unit (204); the inverting input terminal of the error amplifier EA (2022) is connected to the output signal of the voltage acquisition unit (201). V FB The non-inverting input terminal is connected to the first reference power supply. v 1 (2023) Positive electrode, v 1 Negative terminal grounded; error amplification unit (202) outputs error compensation signal. V comp And connected to the inverting input of the third comparator CMP3 (2041), this error compensation signal V comp As a PWM modulation amplitude reference, it realizes the voltage regulation of the upper and lower output buses. At the same time, it works with the adaptive ramp waveform generation unit (2047) to complete the CRM&DCM hybrid mode regulation and suppress the output voltage ripple problem caused by three-phase imbalance.

[0011] The zero-crossing detection unit (203) includes a sampling transformer. T 1 (2031) Voltage divider resistors R 4 , R 5 , R 6 , R 7First comparator CMP1 (2032), second comparator CMP2 (2033), fourth reference power supply v 4 Fifth reference power supply v 5 The two-input selector (2034) is used; the zero-crossing detection unit (203) is also divided into phase A, phase B, and phase C for sampling due to the different sampling inductor current signals. Taking phase A as an example: sampling transformer T 1 (2031) Primary-side coupling acquires the current signal of the input inductor. i La Its first secondary winding's same-name terminal is grounded, and its different-name terminal is connected to the... R 4 , R 5 The first sampling branch, formed by series connection, R 4 One end is grounded and the other end is connected to R 5 The connection node is the output terminal of the first sampling branch. R 5 The other end is connected to the opposite-named terminal of the first secondary winding; sampling transformer T 1 (2031) The opposite-named terminal of the second secondary winding is grounded, and the same-named terminal is connected to the grounding circuit. R 6 , R 7 The second sampling branch is formed by series connection. R 6 One end is grounded and the other end is connected to R 7 This connection node is the output terminal of the second sampling branch. R 7 The other end is connected to the same-name terminal of the second secondary winding; the non-inverting input terminal of the first comparator CMP1 (2032) is connected to the output terminal of the first sampling branch, and the inverting input terminal is connected to the fourth reference power supply. v 4 The positive electrode, v 4 The negative terminal is grounded; the non-inverting input of the second comparator CMP2 (2033) is connected to the output of the second sampling branch, and the inverting input is connected to the fifth reference power supply. v 5 The positive electrode, v 5The negative terminal is grounded; the two input terminals of the two-input selector (2034) are respectively connected to the output terminals of the first comparator CMP1 (2032) and the second comparator CMP2 (2033). The two-input selector is controlled by the three-phase AC voltage source. When the three-phase AC voltage source is in the positive half-cycle, the first terminal of the selector is turned on, and when the three-phase AC voltage source is in the negative half-cycle, the second terminal of the selector is turned on. The output terminal of the two-input selector (2034) is connected to the subsequent zero-crossing detection logic unit to output the zero-crossing detection signal. V ZCD_a The zero-crossing detection unit (203) collects the zero-crossing moment of the three-phase input inductor current and outputs a zero-crossing feedback signal. V ZCD_a The signals are respectively fed into the S terminal of the third RS flip-flop RS3 (2044) and the first input terminal of the OR gate in the adaptive ramp waveform generation unit (2047) to provide timing judgment basis for CRM and DCM dual-mode switching.

[0012] The segmented modulation unit (204) includes a third comparator CMP3 (2041), a first RS flip-flop RS1 (2042), a second RS flip-flop RS2 (2043), a third RS flip-flop RS3 (2044), an AND gate (2045), a maximum switching frequency limiting generation unit (2046), and an adaptive ramp waveform generation unit (2047); the non-inverting input of the third comparator CMP3 (2041) is connected to the sawtooth wave output by the adaptive ramp waveform generation unit (2047). V Saw1_a The output of the third comparator CMP3 (2041) is simultaneously connected to the R terminal of the first RS flip-flop RS1 (2042) and the R terminal of the third RS flip-flop RS3 (2044); the output of the maximum switching frequency limiting generator (2046) is connected to the R terminal of the second RS flip-flop RS2 (2043); the first input of the AND gate (2045) is connected to the R terminal of the second RS flip-flop RS2 (2043). The output terminal and the second input terminal are connected to the Q output terminal of the third RS flip-flop RS3 (2044), and the output terminal of the AND gate circuit AND (2045) is connected to the S terminal of the first RS flip-flop RS1 (2042); the Q output terminal of the first RS flip-flop RS1 (2042) outputs the drive signal. V Drv_a It is connected to the gate of the first bidirectional switching unit (105) of phase A; at the same time V Drv_a Connect to the second input terminal of the OR gate in the adaptive ramp waveform generation unit (2047).

[0013] Optionally, the maximum switching frequency limiting generation unit (2046) includes a current source. I RefFifth capacitor C 5 Fourth switch S 4 Third reference power supply v 3 And the fourth comparator CMP4; current source I Ref The negative terminal, the fifth capacitor C 5 First and fourth switches S 4 The first terminal is connected to and grounded; current source I Ref The positive terminal, the fifth capacitor C 5 The second end, the fourth switch S 4 The second terminal is connected to the non-inverting input of the fourth comparator CMP4, and the fourth switch... S 4 The control terminal is connected to the second RS flip-flop RS2 (2043). Output terminal; the inverting input terminal of the fourth comparator CMP4 is connected to the third reference power supply. v 3 The positive terminal connection, v 3 The negative terminal is grounded; the output of the fourth comparator CMP4 is connected to the R terminal of the second RS flip-flop RS2 (2043).

[0014] Optionally, the adaptive ramp waveform generation unit (2047) includes an OR gate and an inverter. F 1 Second reference power supply v 2 First switch S 1 Second switch S 2 Filtering unit R 3 and C 3 Voltage-controlled current source i vccs_a Fourth capacitor C 4 and the third switch S 3 The first input of the OR gate is connected to a zero-crossing detection signal. V ZCD_a The second input of the OR gate is connected to the drive signal. V Drv_a The output of the OR gate, the first switch S 1 Control terminal and inverterF 1 Input connection; second reference power supply v 2 Positive electrode and first switch S 1 First end connection; first switch S 1 The second end, in the filter unit R 3 First end and second switch S 2 The first end is connected; inverter F 1 The output terminal and the second switch S 2 The control terminal connection; the filter unit R 3 and C 3 The connection node is connected to a voltage-controlled current source. i vccs_a The positive terminal of the voltage control terminal; the voltage-controlled current source i vccs_a Output terminal, fourth capacitor C 4 First end, third switch S 3 The first end is connected to the output end of the adaptive ramp waveform generation unit, and is used to output a sawtooth wave signal. V Saw1_a Third switch S 3 Control terminal access signal Second reference power supply v 2 negative terminal, second switch S 2 The second and third capacitors C 3 The second terminal, voltage-controlled current source i vccs_a The negative terminal of the voltage control terminal, the fourth capacitor C 4 The second and third switches S 3 The second end of each is grounded.

[0015] Optionally, the switching transistor inside the bidirectional switching unit Q 1 , Q 2 , Q 3 , Q 4 , Q5 , Q 6 All are transistors or MOSFETs. The sources of two transistors in the same group are interconnected and their gates are connected in parallel, sharing a common drive signal to realize the on / off control of the bidirectional switching unit.

[0016] Optionally, the upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) has the same capacitance and model. The midpoint M of the series connection can realize the equalization of output voltage and suppress the problem of bus voltage deviation caused by three-phase imbalance.

[0017] Beneficial effects: (1) Traditional three-phase three-wire Vienna rectifiers have complex control logic and large amount of computation, and are highly dependent on high-speed MCUs or DSPs, resulting in high hardware costs. This topology adds a neutral line, decouples the three-phase circuit into three independent Boost converters that operate in parallel, and each phase is controlled independently. Even if the three-phase input is unbalanced or a phase loss fault occurs, the device can still achieve the power factor correction function normally, greatly improving the adaptability of the working conditions and reducing hardware costs. (2) The present invention realizes CRM&DCM frequency conversion control through a dual-mode segmented modulation unit. The rectifier operates in CRM mode in the peak range of the input voltage and switches to constant frequency DCM mode at the zero crossing point of the input voltage. This control strategy can limit the maximum operating frequency and maintain unity power factor throughout the process, effectively reducing the total harmonic distortion of the input current, reducing the peak value of the input current, and suppressing the output voltage ripple. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 (a) is a schematic diagram of a three-phase three-wire Vienna rectifier. Figure 1 (b) is a schematic diagram of a three-phase four-wire Vienna rectifier. Figure 1 (c) is a schematic diagram of a single-phase Vienna rectifier; Figure 2 This invention discloses the operating state and equivalent circuit diagram of a single-phase Vienna rectifier after decoupling of a three-phase four-wire Vienna rectifier in DCM mode. Figure 3This is a schematic diagram of the main power topology and three-phase control loop structure of a hybrid-mode controlled three-phase four-wire Vienna rectifier disclosed in an embodiment of the present invention. Figure 4 This is a schematic diagram of key waveforms of phase A of a hybrid-mode controlled three-phase four-wire Vienna rectifier disclosed in an embodiment of the present invention. Figure 5 The circuit signal simulation results of phase A of a hybrid-mode controlled three-phase four-wire Vienna rectifier in DCM mode are shown in an embodiment of the present invention. Figure 6 The circuit signal simulation results of phase A of a three-phase four-wire Vienna rectifier with hybrid mode control disclosed in an embodiment of the present invention are shown in CRM&DCM mode. Figure 7 The circuit signal simulation results of phase A of a hybrid-mode controlled three-phase four-wire Vienna rectifier in CRM mode are shown in an embodiment of the present invention. Figure 8 The input voltage of a hybrid-mode controlled three-phase four-wire Vienna rectifier disclosed in this embodiment of the invention. v a ~ v c Input current i a ~ i c Output voltage V o Inductor current i La ~ i Lc The simulation waveform diagram. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Figure 1 (a) A schematic diagram of a traditional three-phase three-wire Vienna rectifier is given; Figure 1 (b) A schematic diagram of a three-phase four-wire Vienna rectifier structure is given. This topology adds a neutral line to the three-wire system and can be decoupled into three independent Boost converters operating in parallel. Figure 1 (c) A schematic diagram of a decoupled single-phase Vienna rectifier structure is given; Figure 2 The diagram shows the operating state and equivalent circuit of the decoupled single-phase Vienna rectifier in DCM mode. This invention discloses a hybrid-mode controlled three-phase four-wire Vienna rectifier, which includes a main power topology (1) and a three-phase control loop (2). See [link to relevant documentation]. Figure 3 As shown; The main power topology (1) consists of a three-phase AC voltage source e a ~ e c (101) EMI high-frequency filter circuit (102) Three-phase input inductor L a ~ L c (103) Three-phase rectifier bridge (104) Phase A first bidirectional switching unit (105) Phase B second bidirectional switching unit (106) Phase C third bidirectional switching unit (107) Upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) and DC load R 0 (110) The three-phase control loop (2) is composed of a voltage acquisition unit (201), an error amplification unit (202), a zero-crossing detection unit (203) and a segmented modulation unit (204).

[0022] The working principle of the three-phase four-wire Vienna rectifier (taking phase A as an example) in this embodiment of the invention is as follows: [The following text appears to be a separate, unrelated section:] ...resistor... R 3 With capacitor C 3 This constitutes a filtering unit to filter out interference from the switching frequency; the third switch... S 3 The control terminal and the output terminal of the first RS flip-flop RS1 (2042) Connected to receive Through the first switch S 1 Second switch S 2 and the third switch S 3 Coordinated control to achieve control of the fourth capacitor C 4 The charging and discharging process is used to obtain the conduction time, whose slope is controlled by the first bidirectional switching unit (105) of phase A. T on_a Inductor current discharge time T off_a and switching cycle Ts_a Controlled sawtooth wave V Saw1_a The charging current is: ; In the formula, D y_a for A The duty cycle corresponding to when the first bidirectional switching unit (105) is turned on is D R_a Inductor current i La The duty cycle corresponding to the drop to zero. g 1 Voltage-controlled current source i VCCS_a The control coefficient, v 2 Second reference power supply

[0023] On-time of the first bidirectional switching unit (105) of phase A: ; Therefore, the input current of a three-phase four-wire Vienna rectifier (taking phase A as an example) can be expressed as: ; In the formula, L a For phase A input inductance, i La_pk Input inductor for phase A L a Peak current, V m_a The amplitude of the sinusoidal input voltage for phase A; when the three-phase four-wire Vienna rectifier (taking phase A as an example) is operating in steady state, the error signal is relatively narrow due to the narrow bandwidth of the entire control loop. V comp The fourth capacitor in the adaptive ramp waveform generation unit (2047) remains essentially constant over half a cycle. C 4 Voltage-controlled current source i VCCS_a control coefficient g 1 and input inductance L a Both are constant; at the same time, the input current of the rectifier is a standard sine wave, thus achieving unity power factor and low input current distortion.

[0024] Since the switching frequency of the hybrid-mode three-phase four-wire Vienna rectifier remains at the cutoff frequency in the DCM segment and varies with wt in the CRM segment, the expression for the rectifier's switching frequency can be written as: ; In the formula, f set Here, α represents the set transition frequency, and α represents the x-coordinate of the transition point. Since the switching frequencies of DCM and CRM modes are equal at the transition point, the following expression can be derived: ; The peak value expression for the A-phase inductor current of a hybrid-mode three-phase four-wire Vienna rectifier is: ; The non-inverting input of the third comparator CMP3 (2041) is connected to the sawtooth wave output of the adaptive ramp waveform generation unit (2047). V Saw1_a The inverting input terminal is connected to the output signal of the error amplifier unit (202). V comp The output terminal is connected to the R terminal of the first RS flip-flop RS1 (2042) and the R terminal of the third RS flip-flop RS3 (2044); the maximum switching frequency limiting generation unit (2046) is composed of a current source. I Ref Fifth capacitor C 5 Fourth switch S 4 Third reference power supply v 3 Composed of the fourth comparator CMP4, the output of the second RS flip-flop RS2 (2043) Control the fourth switch S 4 The on / off state is controlled by the current source. I Ref For the fifth capacitor C 5 Sawtooth waves are generated by charging and discharging. V Saw2_a ,Will V Saw2_a With the third reference power supply v 3 By comparison, the resulting pulse signal is the cutoff frequency signal; the PWM signal of the first bidirectional switching unit (105) of phase A is sampled, and the PWM signal and the cutoff frequency signal are respectively connected to the S and R terminals of the second RS flip-flop RS2 (2043), and the output terminal of the second RS flip-flop RS2 (2043) is... Connect to the first input terminal of the AND gate (2045); output terminal of the zero-crossing detection unit (203). V ZCD_a The S terminal of the third RS flip-flop RS3 (2044) is connected, the R terminal of the third RS flip-flop RS3 (2044) is connected to the output terminal of the third comparator CMP3 (2041), and the output terminal Q of the third RS flip-flop RS3 (2044) is connected to the second input terminal of the AND gate AND (2045). The output signal of the AND gate AND (2045) and the output signal of the third comparator CMP3 (2041) are respectively used as the S terminal and R terminal input of the first RS flip-flop RS1. At the beginning of each switching cycle, the first bidirectional switching unit (105) of phase A is turned on, and the input inductor... L a current i La Starting from zero, the inductor stores energy; when the signal at the non-inverting input of the third comparator CMP3 (2041) rises... V Saw1_a Greater than the inverting input signal V comp At that time, the first bidirectional switching unit (105) of phase A is disconnected, and the input inductor... L a Energy release, inductor current i La It begins to decline from its peak. When... i La When it drops to zero, the zero-crossing detection unit (203) detects it. V ZCD_a When the rectifier transitions from a high level to a low level, it compares its operating frequency with its cutoff frequency. If the CRM mode frequency is higher than the cutoff frequency, it switches to DCM mode and operates at the cutoff frequency. If the CRM operating frequency is lower than the cutoff frequency, the rectifier remains in CRM mode. To implement PFC functionality, the compensation circuit of the error amplifier EA (2022) needs to be configured so that the bandwidth of the voltage control loop is less than 20Hz. After the rectifier stabilizes, the signal at the inverting input of the third comparator CMP3 (2041) is... V comp It remains stable within half a power frequency cycle. Meanwhile, the fourth capacitor in the adaptive ramp waveform generation unit (2047)... C 4 Control coefficient g 1 and input inductance L a They are all constant.

[0025] The waveforms of key points in both working modes are as follows: Figure 4As shown, when the rectifier operates in CRM mode, at the beginning of a cycle, the first bidirectional switching unit (105) of phase A is turned on. V Drv_a For high, inductor current i La Starting from zero; in the adaptive ramp waveform generation unit (2047), the voltage controls the current source. i vccs_a For the fourth capacitor C 4 Charge, V Saw1_a Starting from zero, in the maximum switching frequency limiting generation unit (2046), the current source... I Ref The fifth capacitor C 5 Charge, V Saw2_a Starting from zero and rising; when V Saw1_a Rise to V comp When they are equal, the output of the third comparator CMP3 (2041) is the voltage at the R terminal of the third RS flip-flop RS3 (2044). V RS3_R When the current is high, the Q outputs of the first RS flip-flop RS1 (2042) and the third RS flip-flop RS3 (2044) become low, the first bidirectional switching unit (105) of phase A is turned off, and the inductor current... i La From the peak, it drops to zero. V ZCD_a Positive, voltage controls current source i vccs_a Grounding, stop supplying power to the fourth capacitor. C 4 Charge, V Saw1_a Decrease to zero; when V Saw2_a When the voltage reaches 1V, the output of the fourth comparator CMP4 is the voltage at the R terminal of the second RS flip-flop RS2 (2043). V RS2_R For high, the fourth switch S 4 drive signal V S4_Drv For high, V Saw2_a The grounding becomes zero at this time. i La The voltage did not drop to zero; the output signal of the zero-crossing detection unit (203) is the S-terminal voltage of the third RS flip-flop RS3 (2044). V RS3_SThe voltage at its Q terminal is low. V RS3_Q Also low, the output of AND gate (2045) is the source voltage of the first RS flip-flop RS1 (2042). V RS1_S The value is still low, the first RS flip-flop RS1 (2042) does not activate, so the fourth switch... S 4 drive signal V S4_Drv Maintain at a high level. V Saw2_a Still zero; when i a When it drops to 0, V ZCD_a When the voltage drops to zero, the zero-crossing detection unit (203) outputs a pulse signal to the S terminal of the third RS flip-flop RS3 (2044), causing the Q terminal output of the third RS flip-flop RS3 (2044) to go high. The AND gate (2045) then outputs the S terminal voltage of the first RS flip-flop RS1 (2042). V RS1_S When the output is high, the Q output of the first RS flip-flop RS1 (2042) becomes high, the first bidirectional switch unit (105) of phase A is turned on, and the next cycle begins.

[0026] When the rectifier operates in DCM mode, at the beginning of a cycle, the first bidirectional switching unit (105) of phase A is turned on. V Drv_a For high, inductor current i La Starting from zero; in the adaptive ramp waveform generation unit (2047), the voltage controls the current source. i vccs_a For the fourth capacitor C 4 Charge, V Saw1_a Starting from zero, in the maximum switching frequency limiting generation unit (2046), the current source... I Ref The fifth capacitor C 5 Charge, V Saw2_a Starting from zero and rising; when V Saw1_a Rise to V comp When they are equal, the output of the third comparator CMP3 (2041) is the voltage at the R terminal of the third RS flip-flop RS3 (2044). V RS3_RWhen the current is high, the Q outputs of the first RS flip-flop RS1 (2042) and the third RS flip-flop RS3 (2044) become low, the first bidirectional switching unit (105) of phase A is turned off, and the inductor current... i La From the peak, it drops to zero. V ZCD_a Positive, voltage controls current source i vccs_a Grounding, stop supplying power to the fourth capacitor. C 4 Charge, V Saw1_a Decrease to zero; when i La When it drops to zero, V Saw2_a Before it is charged to 1V, the output of the fourth comparator CMP4 is the voltage at the R terminal of the second RS flip-flop RS2 (2043). V RS2_R Low, fourth switch S 4 drive signal V S4_Drv When the AND gate (2045) outputs low, the rectifier operates in DCM mode. V ZCD_a When the zero-crossing signal becomes zero, the zero-crossing detection unit (203) outputs a pulse signal to the S terminal of the third RS flip-flop RS3 (2044), and the Q terminal output of the third RS flip-flop RS3 (2044) goes high; when V Saw2_a The voltage rises to 1V, and the output of the fourth comparator CMP4 is the voltage at the R terminal of the second RS flip-flop RS2 (2043). V RS2_R For high, the fourth switch S 4 drive signal V S4_Drv For high, V Saw2_a When grounding becomes zero, the output of the AND gate is the voltage at the source terminal of the first RS flip-flop RS1 (2042). V RS1_S When the output is high, the Q output of the first RS flip-flop RS1 (2042) becomes high, the first bidirectional switch unit (105) of phase A is turned on, and the next cycle begins.

[0027] Figures 5 to 7 The following are simulation results of the circuit signal waveforms of a mixed-mode three-phase four-wire Vienna rectifier (taking phase A as an example) in DCM mode, at the transition point between DCM and CRM modes, and in CRM mode. The transition frequency set in this simulation is 71kHz. When the operating frequency is below 71kHz, it operates in CRM mode.

[0028] like Figure 8 The figure shows the simulation results of the hybrid mode three-phase four-wire Vienna rectifier control method. The CRM&DCM frequency conversion control is realized through a dual-mode segmented modulation unit. The rectifier operates in CRM mode in the peak range of the input voltage and switches to constant frequency DCM mode at the zero crossing point of the input voltage. This control method can limit the maximum operating frequency and maintain unity power factor throughout the process, effectively reducing the total harmonic distortion of the input current, reducing the peak value of the input current, and suppressing the output voltage ripple.

[0029] The above provides a detailed description of a hybrid-mode three-phase four-wire Vienna rectifier provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A hybrid-mode three-phase four-wire Vienna rectifier, characterized in that, Including the main power topology and three-phase control loop; The main power topology (1) consists of a three-phase AC voltage source e a ~ e c (101) EMI high-frequency filter circuit (102) Three-phase input inductor L a ~ L c (103) Three-phase rectifier bridge (104) Phase A first bidirectional switching unit (105) Phase B second bidirectional switching unit (106) Phase C third bidirectional switching unit (107) Upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) and output load R 0 (110) Composition; Three-phase AC voltage source e a ~ e c (101) is the power frequency input power supply of the three-phase rectifier. Its three phase lines are connected to the three-phase input terminals of the EMI high-frequency filter circuit (102). The power frequency neutral point of the three-phase AC voltage source is the grid neutral terminal N. This power frequency neutral point N is grounded and connected to the grounding loop of the EMI high-frequency filter circuit (102). The three-phase output terminals of the EMI high-frequency filter circuit are connected in series with the three-phase input inductors. L a ~ L c (103); The three-phase rectifier bridge (104) consists of diodes D 1 , D 2 , D 3 , D 4 , D 5 , D 6 Composition, diode D 1 , D 3 , D 5 The cathodes are connected together to form a DC positive bus, and the diodes D 2 , D 4 , D 6 The anodes are connected together to form a DC negative bus; input inductor L a Outgoing terminal access D 1 Anode and D 2 The A-phase line node between the cathodes, input inductance L b Outgoing terminal access D 3 Anode and D 4 The input inductance is located at the B-phase line node between the cathodes. L c Outgoing terminal access D 5 Anode and D 6 The C-phase line node between the cathodes; the first bidirectional switching unit (105) of phase A consists of a switching tube. Q 1 , Q 2 The source is connected in series and the gate is connected in parallel, with the gate connected to the A-phase drive signal. V Drv_a The second bidirectional switching unit (106) of phase B consists of a switching transistor. Q 3 , Q 4 The source is connected in series and the gate is connected in parallel, with the gate connected to the B-phase drive signal. V Drv_b The third bidirectional switch unit (107) of phase C is composed of Q 5 , Q 6 It is composed of a source connected in series and a gate connected in parallel, with the gate connected to the C-phase drive signal. V Drv_c Switching transistor Q 1 , Q 3 , Q 5 The drains of the transistors are connected one-to-one to the phase line nodes of phases A, B, and C, respectively. Q 2 , Q 4 , Q 6 The drains of the capacitors are connected to the same point, which is defined as the DC midpoint M; the upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) Series connection of the first and last capacitors, filter capacitors C 1 The upper end connects to the DC positive bus and the filter capacitor. C 2 The lower end connects to the DC negative busbar. C 1 and C 2 The series connection point is the DC midpoint M, and the lead of the DC midpoint M is connected back to the internal grounding branch of the EMI high-frequency filter circuit (102); output load R 0 (110) Connected between the DC positive bus and the DC negative bus; the power frequency neutral point N and the DC neutral point M of the three-phase AC voltage source are both grounding points; The three-phase control loop (2) consists of a voltage acquisition unit (201), an error amplification unit (202), a zero-crossing detection unit (203), and a segmented modulation unit (204); the voltage acquisition unit (201) includes an upper bus voltage acquisition unit (2011) and a capacitor. C 1 Parallel connection of the lower bus voltage acquisition unit (2012) and capacitor. C 2 The upper and lower bus voltage acquisition units are connected in parallel, with the midpoint of the upper bus voltage acquisition unit connected to the DC midpoint M and grounded; the input terminal of the error amplification unit (202) is connected to the output terminal of the voltage acquisition unit (201), and the output terminal of the error amplification unit (202) is connected to the inverting input terminal of the third comparator CMP3 (2041) in the segmented modulation unit; the reference voltage terminal of the error amplification unit (202) is grounded; the sampling terminal of the zero-crossing detection unit (203) is connected to the three-phase input inductor. L a ~ L c The two ends of (103) are connected in parallel. The output of the zero-crossing detection unit (203), the S-terminus of the third RS flip-flop RS3 (2044), and the first input of the OR gate in the adaptive ramp waveform generation unit (2047) are connected. The segmented modulation unit (204) includes a third comparator CMP3 (2041), a first RS flip-flop RS1 (2042), a second RS flip-flop RS2 (2043), a third RS flip-flop RS3 (2044), an AND gate (2045), a maximum switching frequency limiting generation unit (2046), and an adaptive ramp waveform generation unit (2047). The first input of the segmented modulation unit (204) is the inverting input of the third comparator CMP3 (2041) connected to the output of the error amplification unit (202). The second input of the segmented modulation unit (204) is the S-terminus of the third RS flip-flop RS3 (2044) connected to the output of the error amplification unit (202). The output terminal of the zero-crossing detection unit (203) is connected to the first input terminal of the OR gate in the adaptive ramp waveform generation unit (2047), which is connected to the output terminal of the zero-crossing detection unit (203). The output terminal of the segmented modulation unit (204) is the Q terminal of the first RS flip-flop RS1 (2042), which is connected to the gate of the first bidirectional switching unit (105) of phase A. The segmented modulation unit (204) can control the first bidirectional switching unit (105) of phase A, the second bidirectional switching unit (106) of phase B, and the third bidirectional switching unit (107) of phase C of the three-phase four-wire Vienna rectifier, so that the rectifier works in DCM mode and CRM mode. This circuit can limit the maximum operating frequency of the above bidirectional switching units and maintain unity power factor throughout the process, effectively reducing the total harmonic distortion of the input current, reducing the peak value of the input current, and suppressing the output voltage ripple.

2. The hybrid-mode three-phase four-wire Vienna rectifier according to claim 1, characterized in that, The main power topology (1) is a three-phase four-wire structure. A neutral line is added on the basis of the three-phase three-wire topology, which can decouple the three-phase four-wire Vienna rectifier into three independent single-phase Boost converters that operate in parallel. Even if the three-phase input is unbalanced or a phase loss fault occurs, the device can still achieve the power factor correction function normally. For the three-phase control loop (2), namely the A-phase, B-phase, and C-phase control loops, the control methods of each phase are the same, with only a phase difference of 120°. The analysis of the three-phase control loop is based on the A-phase as an example. The analysis process of the B and C phases is completely consistent with that of the A-phase.

3. The hybrid-mode three-phase four-wire Vienna rectifier according to claim 1, characterized in that, The voltage acquisition unit (201) includes an upper bus voltage acquisition unit (2011), a lower bus voltage acquisition unit (2012), and a two-input selector (2013); the upper bus voltage acquisition unit consists of a resistor. R 1 and R 2 Composition and capacitance C 1 Parallel connection, the lower bus voltage acquisition unit consists of resistors R 3 and R 4 Composition and capacitance C 2 The upper and lower bus voltage acquisition units are connected in parallel, with the midpoint of the upper and lower bus voltage acquisition units connected to the DC midpoint M and grounded. The output terminals of the upper and lower bus voltage acquisition units are connected to the input terminals of a two-input selector (2013). The two input selectors are controlled by a three-phase AC voltage source. When the three-phase AC voltage source is in the positive half-cycle, the first terminal of the selector is activated; when the three-phase AC voltage source is in the negative half-cycle, the second terminal of the selector is activated. The output terminal of the two-input selector outputs... V FB It is connected to the input terminal of the error amplification unit (202).

4. The hybrid-mode three-phase four-wire Vienna rectifier according to claim 1, characterized in that, The error amplification unit (202) consists of a PI compensation circuit (2021), an error amplifier EA (2022), and a first reference power supply. v 1 (2023) The first terminal of the PI compensation circuit (2021) is connected to the output terminal of the error amplifier EA (2022), and the second terminal is connected to the inverting input terminal of the third comparator CMP3 (2041) in the segmented modulation unit (204); the inverting input terminal of the error amplifier EA (2022) is connected to the output signal of the voltage acquisition unit (201). V FB The non-inverting input terminal is connected to the first reference power supply. v 1 (2023) Positive electrode, v 1 Negative terminal grounded; error amplification unit (202) outputs error compensation signal. V comp And connected to the inverting input of the third comparator CMP3 (2041), this error compensation signal V comp As a PWM modulation amplitude reference, it realizes the voltage regulation of the upper and lower output buses. At the same time, it works with the adaptive ramp waveform generation unit (2047) to complete the CRM&DCM hybrid mode regulation and suppress the output voltage ripple problem caused by three-phase imbalance.

5. A hybrid-mode three-phase four-wire Vienna rectifier according to claim 1, characterized in that, The zero-crossing detection unit (203) includes a sampling transformer. T 1 (2031) Voltage divider resistors R 4 , R 5 , R 6 , R 7 First comparator CMP1 (2032), second comparator CMP2 (2033), fourth reference power supply v 4 Fifth reference power supply v 5 The two-input selector (2034) is used; the zero-crossing detection unit (203) is also divided into phase A, phase B, and phase C for sampling due to the different sampling inductor current signals. Taking phase A as an example: sampling transformer T 1 (2031) Primary-side coupling acquires the current signal of the input inductor. i La Its first secondary winding's same-name terminal is grounded, and its different-name terminal is connected to the... R 4 , R 5 The first sampling branch, formed by series connection, R 4 One end is grounded and the other end is connected to R 5 The connection node is the output terminal of the first sampling branch. R 5 The other end is connected to the opposite-named terminal of the first secondary winding; sampling transformer T 1 (2031) The opposite-named terminal of the second secondary winding is grounded, and the same-named terminal is connected to the grounding circuit. R 6 , R 7 The second sampling branch is formed by series connection. R 6 One end is grounded and the other end is connected to R 7 This connection node is the output terminal of the second sampling branch. R 7 The other end is connected to the same-name terminal of the second secondary winding; the non-inverting input terminal of the first comparator CMP1 (2032) is connected to the output terminal of the first sampling branch, and the inverting input terminal is connected to the fourth reference power supply. v 4 The positive electrode, v 4 The negative terminal is grounded; the non-inverting input of the second comparator CMP2 (2033) is connected to the output of the second sampling branch, and the inverting input is connected to the fifth reference power supply. v 5 The positive electrode, v 5 The negative terminal is grounded; the two input terminals of the two-input selector (2034) are respectively connected to the output terminals of the first comparator CMP1 (2032) and the second comparator CMP2 (2033). The two-input selector is controlled by the three-phase AC voltage source. When the three-phase AC voltage source is in the positive half-cycle, the first terminal of the selector is turned on, and when the three-phase AC voltage source is in the negative half-cycle, the second terminal of the selector is turned on. The output terminal of the two-input selector (2034) is connected to the subsequent zero-crossing detection logic unit to output the zero-crossing detection signal. V ZCD_a The zero-crossing detection unit (203) collects the zero-crossing moment of the three-phase input inductor current and outputs a zero-crossing feedback signal. V ZCD_a The signals are respectively fed into the S terminal of the third RS flip-flop RS3 (2044) and the first input terminal of the OR gate in the adaptive ramp waveform generation unit (2047) to provide timing judgment basis for CRM and DCM dual-mode switching.

6. A hybrid-mode three-phase four-wire Vienna rectifier according to claim 1, characterized in that, The switching transistor inside the bidirectional switching unit Q 1 , Q 2 , Q 3 , Q 4 , Q 5 , Q 6 All are transistors or MOSFETs. The sources of two transistors in the same group are interconnected and their gates are connected in parallel, sharing a common drive signal to realize the on / off control of the bidirectional switching unit.

7. A hybrid-mode three-phase four-wire Vienna rectifier according to claim 1, characterized in that, The upper bus filter capacitor C 1 (108) Lower bus filter capacitor C 2 (109) has the same capacitance and model. The midpoint M of the series connection can realize the output voltage equalization and suppress the bus voltage deviation caused by the three-phase imbalance.

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