Relaxation oscillator and method for generating an oscillating signal in a relaxation oscillator

Abstract

This invention provides a relaxation oscillator and a method for generating an oscillation signal in the relaxation oscillator. The relaxation oscillator includes a capacitor, a resistor, an inverting amplifier, and a first logic inverter, wherein a first terminal of the resistor is coupled to a first terminal of the capacitor. The inverting amplifier is used to generate a first digital signal based on an analog signal at the first terminal of the capacitor, and the first logic inverter is used to generate a second digital signal based on the first digital signal, wherein a second terminal of the resistor is used to pull up or pull down the analog signal based on the first digital signal, and a second terminal of the capacitor is used to receive the second digital signal.

Description

Technical Field

[0001] This invention relates to oscillator design, and more particularly to a relaxation oscillator and a method for generating at least one oscillation signal in the relaxation oscillator. Background Technology

[0002] With the increasing prevalence of smart devices, the market demand for wireless sensing devices (such as wearable electronics) is growing rapidly. Power consumption and chip area are crucial considerations for wearable electronics. Oscillators are an important building block in these systems, and different types of oscillators have different advantages and disadvantages. For example, crystal oscillators offer lower phase noise and better frequency stability, but their longer startup time, higher power consumption, and the need for external crystal components lead to higher manufacturing costs, making them unsuitable for wearable electronics. Furthermore, while ring oscillators offer good power efficiency, their performance is highly sensitive to variations in manufacturing processes, voltage, and temperature. Compared to ring oscillators, relaxation oscillators offer better frequency stability, frequency adjustment capabilities, and a better figure of merit (FOM), making them more suitable for use in wireless sensing devices.

[0003] However, existing relaxation oscillators still have some drawbacks. For example, the architecture of existing technologies requires the use of continuous-time comparators and common-mode feedback circuits, which typically require a large number of transistors, thus generating additional flicker noise and thermal noise. While the high-frequency components of this noise can be suppressed by low-pass filters, low-frequency noise is difficult to reduce, making existing relaxation oscillators unsuitable for wearable electronic devices primarily used for sensing low-frequency signals.

[0004] Therefore, a novel relaxation oscillator architecture and related methods are needed to simplify the circuit complexity (e.g., the number of transistors) of relaxation oscillators, thereby addressing the problems of existing technologies. Summary of the Invention

[0005] The purpose of this invention is to provide a relaxation oscillator and a method for generating at least one oscillation signal in the relaxation oscillator, in order to meet the requirements of oscillators in wearable electronic devices.

[0006] At least one embodiment of the present invention provides a relaxation oscillator. The relaxation oscillator includes a capacitor, a resistor, an inverting amplifier, and a first logic inverter, wherein a first terminal of the resistor is coupled to a first terminal of the capacitor. The inverting amplifier is used to generate a first digital signal based on an analog signal at the first terminal of the capacitor, and the first logic inverter is used to generate a second digital signal based on the first digital signal, wherein a second terminal of the resistor is used to pull up or pull down the analog signal based on the first digital signal, and a second terminal of the capacitor is used to receive the second digital signal.

[0007] At least one embodiment of the present invention provides a method for generating at least one oscillation signal in a relaxation oscillator. The method includes: generating a first digital signal using an inverting amplifier of the relaxation oscillator based on an analog signal at a first terminal of a capacitor of the relaxation oscillator; generating a second digital signal using a first logic inverter based on the first digital signal; receiving the second digital signal using a second terminal of the capacitor; and pulling up or down the analog signal using a resistor of the relaxation oscillator based on the first digital signal.

[0008] The relaxation oscillator and related methods provided by embodiments of the present invention can construct a relaxation oscillator using resistors, capacitors, and simple logic gates. Compared to prior art relaxation oscillators, the architecture of the present invention can significantly reduce the number of transistors used, resulting in a substantial reduction in overall circuit area and minimizing the generation of additional flicker noise and thermal noise. Therefore, the present invention can implement an oscillator that meets the requirements of wearable electronic devices with little or no side effects. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of a relaxation oscillator according to an embodiment of the present invention.

[0010] Figure 2 According to an embodiment of the present invention Figure 1 The diagram shows a schematic of the signals involved in the relaxation oscillator.

[0011] Figure 3 According to an embodiment of the present invention Figure 1 The diagram shows a relaxation oscillator where the threshold voltage of the logic inverter is higher than the ideal level.

[0012] Figure 4 According to an embodiment of the present invention Figure 1 The diagram shows a relaxation oscillator with a threshold voltage lower than the ideal level for the logic inverter.

[0013] Figure 5This is a schematic diagram of the workflow of a method for generating at least one oscillation signal in a relaxation oscillator according to an embodiment of the present invention.

[0014] Symbol Explanation

[0015] 10: Relaxation Oscillator

[0016] 110: Inverter

[0017] 120: and the door

[0018] 121: NAND gate

[0019] 122: Inverter

[0020] 130: Inverter

[0021] 140: Frequency divider

[0022] 141: D-type flip-flop

[0023] R0: Resistor

[0024] C0: Capacitor

[0025] VC, EN, VA, VB, VX, VY, VOUT: Signals

[0026] t20, t21, t22, t23, t24: Time points

[0027] VDD: Power supply level

[0028] VTH: Threshold

[0029] t30, t31, t32, t33, t34, t40, t41, t42, t43, t44: Time points

[0030] TD, TU, TP: Time Difference

[0031] VTH1, VTH2: Thresholds

[0032] S510, S520, S530, S540: Steps Detailed Implementation

[0033] Figure 1 This is a schematic diagram of a relaxation oscillator 10 according to an embodiment of the present invention. In this embodiment, the relaxation oscillator 10 includes a capacitor C0, a resistor R0, an inverting amplifier, and a first logic inverter such as inverter 130 (in... Figure 1 (Indicated by "INV" for brevity), where the inverting amplifier can be a second logic inverter such as inverter 110 (in Figure 1 (The symbol "INV" is used for brevity). For example... Figure 1 As shown, the first terminal of resistor R0 (e.g. Figure 1 The lower terminal of resistor R0 (as shown) is coupled to the first terminal of capacitor C0 (e.g., Figure 1 The upper terminal of capacitor C0 is shown. In this embodiment, inverting amplifier 110 is used to generate a first digital signal (such as signal VA) based on an analog signal (such as signal VC) on the first terminal of capacitor C0, and inverter 130 is used to generate a second digital signal (such as signal VY) based on signal VA, wherein the second terminal of resistor R0 (e.g., Figure 1 The upper terminal of resistor R0 (shown) is used to pull up or pull down signal VC according to signal VA, and the second terminal of capacitor C0 (e.g.) Figure 1 The lower terminal of the capacitor C0 shown is used to receive the signal VY.

[0034] like Figure 1 As shown, the relaxation oscillator 10 may further include a frequency divider 140, wherein the frequency divider 140 is coupled to the inverter 130 and is used to divide the signal VY to generate an oscillating output signal (such as the signal VOUT). In this embodiment, the frequency divider 140 may include a flip-flop, such as a D-type flip-flop (DFF) 141, wherein the clock terminal of the D-type flip-flop 141 is coupled to the output terminal of the inverter 130, and the data input terminal of the D-type flip-flop 141 (e.g., ...) is also coupled to the output terminal of the inverter 130. Figure 1 The terminal marked "D" of the D-type flip-flop 141 shown is coupled to the inverted data output terminal of the D-type flip-flop 141 (e.g., Figure 1 The terminal marked "QB" of the D-type flip-flop 141 shown, and the data output terminals of the D-type flip-flop 141 (e.g.) Figure 1 The terminal marked "Q" of the D-type flip-flop 141 shown is used to output the signal VOUT.

[0035] Additionally, the relaxation oscillator 10 may further include an AND gate 120, which is used to generate a third digital signal, such as signal VX, based on the enable signal EN and signal VA, wherein the second terminal of resistor R0 receives signal VX. In this embodiment, the AND gate 120 may include a NAND gate 121 and an inverter 122, wherein the NAND gate 121 can perform a NAND logic operation on the enable signal EN and signal VA to generate signal VB, and the inverter 122 can generate signal VX based on signal VB.

[0036] Figure 2 According to an embodiment of the present invention Figure 1The diagram illustrates the signals (such as EN, VX, VY, and VC) involved in the relaxation oscillator 10. In a disable phase (e.g., between time points t20 and t21), signal EN is set to a first reference level (such as a ground level) (which can be considered a logic value "0"), signal VX is fixed at that ground level, signal VY is fixed at a second reference level (such as a power supply level) (which can be considered a logic value "1"), and signal VC is fixed at that ground level. In a enable phase (e.g., between time points t21 and t22), signal EN is set to the power supply level, signal VX is pulled to the power supply level, signal VY is pulled to the ground level, and signal VC is pulled up from the ground level to the threshold VTH of inverter 110 from a reference level difference equal to the power supply level minus the ground level. In a pull-down phase (e.g., between time points t22 and t23), signal VA is pulled to the ground level in response to signal VC being higher than the threshold VTH, signal VX is pulled to the ground level, signal VY is pulled to the supply level, and signal VC is pulled down to the threshold VTH from the difference between the threshold VTH and the reference level. In a pull-up phase (e.g., between time points t23 and t24), signal VA is pulled to the supply level in response to signal VC being lower than the threshold VTH, signal VX is pulled to the supply level, signal VY is pulled to the ground level, and signal VC is pulled up to the threshold VTH from the difference between the threshold VTH and the reference level.

[0037] In this embodiment, the ground level can be 0, and the power supply level can be VDD, wherein the reference level difference can be VDD - 0 = VDD. Specifically, the signal EN can be set to 0 to enable the relaxation oscillator 10 to operate in the disabled phase, such that the signals VX, VY, and VC of the relaxation oscillator 10 are initialized to 0, VDD, and 0, respectively. At time point t21, the signal EN can be pulled from 0 to VDD to enable the relaxation oscillator 10 to enter the start-up phase from the disabled phase, wherein the AND gate 120 can pull the signal VX (corresponding to the second terminal of resistor R0) from 0 to VDD in response to the signal EN, and the inverter 130 can pull the signal VY (corresponding to the second terminal of capacitor C0) from VDD to 0 in response to the signal VX. Therefore, the signal VC on the first terminal of capacitor C0 can be pulled from VDD to 0 at the second terminal of capacitor C0 and pulled from 0 to -VDD at time t21, wherein the signal VC can be pulled up from -VDD at the second terminal of resistor R0 and pulled up from -VDD at time t21.

[0038] At time t22, inverter 110 can pull down signal VA to 0 in response to signal VC being pulled up to threshold VTH, so that relaxation oscillator 10 enters the pull-down phase from the start-up phase. AND gate 120 can pull down signal VX (corresponding to the second terminal of resistor R0) from VDD to 0 in response to signal VA, and inverter 130 can pull down signal VY (corresponding to the second terminal of capacitor C0) from 0 to VDD in response to signal VX. Therefore, signal VC on the first terminal of capacitor C0 can be pulled from VTH to (VTH+VDD) at time t22 in response to the second terminal of capacitor C0 being pulled from 0 to VDD, and signal VC can be pulled down from (VTH+VDD) at time t22 in response to signal VX on the second terminal of resistor R0 being pulled to 0.

[0039] At time t23, inverter 110 can pull signal VA up to VDD in response to signal VC being pulled down to threshold VTH, so that relaxation oscillator 10 enters the pull-up phase from the pull-down phase. AND gate 120 can pull signal VX (corresponding to the second terminal of resistor R0) up from 0 to VDD in response to signal VA, and inverter 130 can pull signal VY (corresponding to the second terminal of capacitor C0) from VDD to 0 in response to signal VX. Therefore, signal VC on the first terminal of capacitor C0 can be pulled from VTH to (VTH-VDD) at time t22 in response to the second terminal of capacitor C0 being pulled down to 0 from VDD, and signal VC can be pulled up from (VTH-VDD) at time t23 in response to signal VX on the second terminal of resistor R0 being pulled up to VDD. Next, the relaxation oscillator 10 can repeatedly perform the pull-down phase operation from time point t22 to t23 and the pull-up phase operation from time point t23 to t24.

[0040] It should be noted that when the threshold voltage VTH of inverter 110 is at the ideal level (e.g., 0.5 × VDD), the duty cycle of signals VX and VY can be 50% (i.e., the time spent at the first reference level is equal to the time spent at the second reference level). In this case, signals VX and VY can serve as the oscillation output signals of relaxation oscillator 10. In some cases, the threshold voltage VTH of inverter 110 may be higher than the ideal level due to process offset (i.e., VTH > 0.5 × VDD). In other cases, the threshold voltage VTH of inverter 110 may be lower than the ideal level due to process offset (i.e., VTH < 0.5 × VDD).

[0041] Figure 3 According to an embodiment of the present invention Figure 1The diagram shows the threshold voltage VTH of the inverter 110 in the relaxation oscillator 10 when it is higher than the ideal level (e.g., the threshold voltage VTH of the inverter 110 = VTH1 > 0.5 × VDD). Figure 3 The operation of time points t30 and t31 in the embodiment and Figure 2 The operation at time points t20 and t21 in the embodiment is the same, and will not be repeated here. Compared to Figure 2 The time point t22 of the embodiment, Figure 3 The inverter 110 of the embodiment can pull down the signal VA to 0 in response to the signal VC being pulled up to the threshold VTH1 at time point t32, so that the signal VX is pulled down from VDD to 0 and the signal VY is pulled up from 0 to VDD, wherein the signal VC at the first terminal of capacitor C0 can be pulled up from VTH1 to (VTH1+VDD) at time point t32, and the signal VC can be pulled down from (VTH1+VDD) starting at time point t32. Furthermore, compared to... Figure 2 The time point t23 of the embodiment, Figure 3 The inverter 110 of the embodiment can pull up the signal VA to VDD in response to the signal VC being pulled down to the threshold VTH1 at time point t33, so that the signal VX is pulled up to VDD from 0 and the signal VY is pulled down to 0 from VDD, wherein the signal VC on the first terminal of capacitor C0 can be pulled up from VTH1 to (VTH1-VDD) at time point t33, and the signal VC can be pulled up starting from (VTH1-VDD) at time point t33. It should be noted that the voltage difference between the first and second terminals of resistor R0 at time t32 is VTH1 + VDD - 0 = VTH1 + VDD, and the voltage difference between the first and second terminals of resistor R0 at time t33 is VTH1 - VDD - VDD = VTH1 - (2×VDD). When VTH1 > 0.5×VDD, |VTH1 + VDD| > |VTH1 - (2×VDD)|, which makes the speed at which signal VC is pulled down from time t32 to t33 greater than the speed at which signal VC is pulled up from time t33 to t34. Therefore, the time difference TD between time t32 and t33 (corresponding to the length of time when signal VX is 0) can be less than the time difference TU between time t33 and t34 (corresponding to the length of time when signal VX is VDD), making the working period of signals VX and VY not equal to 50%. However, the problem that the working cycle is not equal to 50% can be solved by frequency divider 140. In particular, the time length of signal VOUT that is VDD and the time length of signal VOUT that is 0 after frequency divider 140 divides signal VY are both equal to the time difference between time points t32 and t34 (as shown in TP).

[0042] Figure 4 According to an embodiment of the present invention Figure 1 The diagram shows the threshold voltage VTH of the inverter 110 in the relaxation oscillator 10 when it is lower than the ideal level (e.g., the threshold voltage VTH of the inverter 110 = VTH2 < 0.5×VDD). Figure 4 The operation of time points t40 and t41 in the embodiment and Figure 2 The operation at time points t20 and t21 in the embodiment is the same, and will not be repeated here. Compared to Figure 2 The time point t22 of the embodiment, Figure 4 The inverter 110 of the embodiment can pull down the signal VA to 0 in response to the signal VC being pulled up to the threshold VTH2 at time point t42, so that the signal VX is pulled down from VDD to 0 and the signal VY is pulled up from 0 to VDD, wherein the signal VC at the first terminal of capacitor C0 can be pulled up from VTH2 to (VTH2+VDD) at time point t42, and the signal VC can be pulled down from (VTH2+VDD) starting at time point t42. Furthermore, compared to... Figure 2 The time point t23 of the embodiment, Figure 4The inverter 110 of the embodiment can pull up the signal VA to VDD in response to the signal VC being pulled down to the threshold VTH2 at time point t43, so that the signal VX is pulled up to VDD from 0 and the signal VY is pulled down to 0 from VDD, wherein the signal VC on the first terminal of capacitor C0 can be pulled up from VTH2 to (VTH2-VDD) at time point t43, and the signal VC can be pulled up starting from (VTH2-VDD) at time point t43. It should be noted that the voltage difference between the first and second terminals of resistor R0 at time t42 is VTH2 + VDD - 0 = VTH2 + VDD, and the voltage difference between the first and second terminals of resistor R0 at time t43 is VTH2 - VDD - VDD = VTH2 - (2×VDD). When VTH2 < 0.5×VDD, |VTH2 + VDD| < |VTH2 - (2×VDD)|, which means that the speed at which signal VC is pulled down from time t42 to t43 can be less than the speed at which signal VC is pulled up from time t43 to t44. Therefore, the time difference TD between time t42 and t43 (corresponding to the length of time when signal VX is 0) can be greater than the time difference TU between time t43 and t44 (corresponding to the length of time when signal VX is VDD), making the working period of signals VX and VY not equal to 50%. However, the problem that the working cycle is not equal to 50% can be solved by frequency divider 140. In particular, the time length of signal VOUT that is VDD and the time length of signal VOUT that is 0 after frequency divider 140 divides signal VY are both equal to the time difference between time points t42 and t44 (as shown in TP).

[0043] Figure 5 According to an embodiment of the present invention, an oscillator is used in a relaxation oscillator (e.g.) Figure 1 This diagram illustrates the workflow of a method for generating at least one oscillation signal (e.g., signals VX, VY, and VOUT) in the relaxation oscillator 10. It should be noted that... Figure 5 The illustrated workflow is for illustrative purposes only and is not intended to limit the invention. For example, one or more steps may be performed... Figure 5 The workflow shown has been added, deleted, or modified. Furthermore, these steps do not necessarily need to be followed exactly to achieve the same result. Figure 5 Execute in the order shown.

[0044] In step S510, the relaxation oscillator can utilize an inverting amplifier (e.g., Figure 1 The inverter 110 shown is based on a capacitor of the relaxation oscillator (e.g., Figure 1 An analog signal (e.g., on a first terminal of the capacitor C0) shown Figure 1The signal VC shown generates a first digital signal (e.g., Figure 1 The signal VA is shown.

[0045] In step S520, the relaxation oscillator may utilize a first logic inverter (e.g., Figure 1 The inverter 130 shown generates a second digital signal (e.g., based on the first digital signal) according to the first digital signal. Figure 1 The signal VY is shown.

[0046] In step S530, the relaxation oscillator can receive the second digital signal using a second terminal of the capacitor.

[0047] In step S540, the relaxation oscillator utilizes a resistor (e.g.) within it. Figure 1 The resistor R0 shown pulls up or down the analog signal according to the first digital signal.

[0048] In summary, the architecture and related methods provided by the embodiments of the present invention can construct relaxation oscillators using resistors, capacitors, and simple logic gates. In particular, the architecture of the present invention does not require operational amplifiers or common-mode feedback circuits, thus significantly reducing the overall number of transistors and avoiding the generation of additional flicker noise and thermal noise. Furthermore, the embodiments of the present invention do not significantly increase additional costs. Therefore, the present invention can implement oscillators suitable for wearable electronic devices with little or no side effects.

[0049] The foregoing outlines the features of several embodiments, enabling those skilled in the art to fully understand the various implementations of the invention. Those skilled in the art should recognize that the invention provides a basis for designing or modifying other processes and structures to achieve substantially the same functionality and / or results as the embodiments described above. Furthermore, such equivalent configurations do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made without departing from that spirit and scope.

Claims

1. A relaxation oscillator, comprising: A capacitor; A resistor, wherein a first terminal of the resistor is coupled to a first terminal of the capacitor; An inverting amplifier is used to generate a first digital signal based on an analog signal at the first terminal of the capacitor; A first logic inverter is used to generate a second digital signal based on the first digital signal; The second terminal of the resistor is used to pull up or pull down the analog signal according to the first digital signal, and the second terminal of the capacitor is used to receive the second digital signal.

2. The relaxation oscillator as claimed in claim 1, wherein the inverting amplifier is a second logic inverter.

3. The relaxation oscillator as claimed in claim 1, further comprising: A frequency divider, coupled to the first logic inverter, is used to divide the second digital signal to generate an oscillating output signal.

4. The relaxation oscillator of claim 3, wherein the frequency divider comprises: A flip-flop, wherein a clock terminal of the flip-flop is coupled to an output terminal of the first logic inverter, a data input terminal of the flip-flop is coupled to an inverted data output terminal of the flip-flop, and a data output terminal of the flip-flop is used to output the oscillation output signal.

5. The relaxation oscillator as claimed in claim 1, further comprising: An AND gate is used to generate a third digital signal based on a uniform energy signal and the first digital signal, wherein the second terminal of the resistor receives the third digital signal.

6. The relaxation oscillator as claimed in claim 5, wherein: During a disabled phase, the enable signal is set to a first reference level, the third digital signal is fixed at the first reference level, the second digital signal is fixed at a second reference level, and the analog signal is fixed at the first reference level. During a startup phase, the enable signal is set to the second reference level, the third digital signal is pulled to the second reference level, the second digital signal is pulled to the first reference level, and the analog signal is pulled up from the first reference level minus a reference level difference to a threshold of the inverting amplifier, wherein the reference level difference is equal to the second reference level minus the first reference level; During the pull-down phase, the first digital signal is pulled to the first reference level in response to the analog signal being higher than the threshold, the third digital signal is pulled to the first reference level, the second digital signal is pulled to the second reference level, and the analog signal is pulled down from the threshold plus the reference level difference to the threshold. as well as During a pull-up phase, the first digital signal is pulled to the second reference level in response to the analog signal being below the threshold, the third digital signal is pulled to the second reference level, the second digital signal is pulled to the first reference level, and the analog signal is pulled up from the threshold minus the reference level difference to the threshold.

7. A method for generating at least one oscillation signal in a relaxation oscillator, comprising: A first digital signal is generated by an inverting amplifier of the relaxation oscillator based on an analog signal on a first terminal of a capacitor of the relaxation oscillator. A first logic inverter is used to generate a second digital signal based on the first digital signal; The second digital signal is received using a second terminal of the capacitor; and The analog signal is pulled up or down using a resistor of the relaxation oscillator according to the first digital signal.

8. The method of claim 7, further comprising: The second digital signal is divided by a frequency divider of the relaxation oscillator to generate an oscillating output signal.

9. The method of claim 7, further comprising: An AND gate of the relaxation oscillator generates a third digital signal based on the consistency energy signal and the first digital signal, wherein the second terminal of the resistor receives the third digital signal.

10. The method of claim 9, wherein the resistor of the relaxation oscillator pulls up or down the analog signal according to the first digital signal, comprising: During a disabling phase, the enable signal is set to a first reference level, such that the third digital signal is fixed at the first reference level, the second digital signal is fixed at a second reference level, and the analog signal is fixed at the first reference level. During a startup phase, the enable signal is set to the second reference level, such that the third digital signal is pulled to the second reference level, the second digital signal is pulled to the first reference level, and the analog signal is pulled up from the first reference level minus a reference level difference to a threshold of the inverting amplifier, wherein the reference level difference is equal to the second reference level minus the first reference level. In the pull-down phase, in response to the analog signal being higher than the threshold, the first digital signal is pulled to the first reference level, so that the third digital signal is pulled to the first reference level, the second digital signal is pulled to the second reference level, and the analog signal is pulled down from the threshold plus the reference level difference to the threshold. as well as In a pull-up phase, in response to the analog signal being below the threshold, the first digital signal is pulled to the second reference level, such that the third digital signal is pulled to the second reference level, the second digital signal is pulled to the first reference level, and the analog signal is pulled up from the threshold minus the reference level difference to the threshold.

Images