Short period sequence mixing implementation device
Patent Information
- Application Number
- CN202611439587.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-16
- Publication Date
- 2026-10-20
AI Technical Summary
在捷变频通信、6G动态频谱接入、软件无线电场景中，大量其他整数或非整数有理频点变频需求，只能被迫使用高开销通用变频架构，导致系统延迟高、功耗大、硬件面积冗余严重
[0018]本发明通过时序控制模块生成匹配旋转因子周期的计数索引，将一个完整周期内全部复旋转因子以硬件固定常数值形式直接布线接入MUX阵列的各输入支路，由MUX阵列根据索引选通对应支路的固定复常数输出与输入基带信号完成复数相乘。由于全部旋转因子均以硬连线数学常数固化于组合逻辑通路中，无需配置存储单元进行访存读取，也无需部署迭代单元或实时乘法器进行逐级逼近或实时运算，从而在彻底消除存储访问延迟与功耗、迭代数据依赖与截断误差、实时乘法资源开销的同时，以静态支路映射方式覆盖任意Fs/M类有理分数短周期频点，突破了现有轻量化方案仅支持Fs/2、Fs/4的局限，在捷变频通信、6G动态频谱接入、软件无线电等场景中实现了全场景适配、超低延迟与极低功耗的统一。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of broadband communication technology, specifically to a short-period sequence mixing implementation device. Background Technology
[0002] Digital downconversion (DDC) and digital upconversion (DUC) are the core units of RF baseband processing, with their core function being complex phase rotation and spectrum shifting. Existing commercial DDC / DUC systems have long relied on three general-purpose architectures: NCO+ROM lookup table mixing, CORDIC iterative mixing, and general-purpose complex multiplication mixing. While these general-purpose architectures are adaptable to arbitrary continuous angle rotations, they suffer from severe hardware redundancy and performance defects in short-period fixed local oscillator scenarios.
[0003] Existing lightweight short-cycle mixing technologies have significant limitations, supporting only two fixed special frequency points, Fs / 2 and Fs / 4. There are no extended solutions to adapt to commonly used rational fractional short-cycle scenarios with integer phase periods, such as Fs / M. In frequency-agile communication, 6G dynamic spectrum access, and software-defined radio scenarios, numerous other integer or non-integer rational frequency point conversion requirements necessitate the use of high-overhead general-purpose conversion architectures, resulting in high system latency, high power consumption, and severe hardware redundancy. Traditional conversion architectures are all computationally driven, relying on phase accumulation iteration, angle iterative approximation, and real-time complex multiplication to complete phase rotation, inherently containing data dependencies and timing delays. Furthermore, existing lightweight solutions fail to exploit the symmetrical redundancy characteristics of rational finite phase periods, making static branch mapping conversion impossible. These limitations prevent them from simultaneously meeting the engineering requirements of full-scenario adaptability, ultra-low latency, and extremely low power consumption. Therefore, how to eliminate the reliance on phase accumulation iteration, angle iterative approximation, and real-time complex multiplication in the computation-driven mode for short-cycle fixed local oscillator scenarios of Fs / M type, and achieve complex mixing that takes into account all scenarios, ultra-low latency, and extremely low power consumption, has become an urgent problem to be solved. Summary of the Invention
[0004] This invention aims to provide a short-period sequence mixing implementation device that abandons the three types of computation-driven architectures: NCO+ROM lookup, CORDIC iteration, and general complex multiplication. Instead, it adopts a pure combinational logic complex mixing architecture consisting of a timing control module, a minimal constant coefficient operation branch pool, and a MUX multiplexer array.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a short-period sequence mixing implementation device, comprising a timing control module, a simplified constant coefficient operation branch pool, and a MUX multiplexer array;
[0006] The timing control module is a counter that generates a period index based on the system timing. The index range matches the rotation factor period. In the simplified constant coefficient operation branch pool, all complex rotation factors within a complete period are directly wired into each input branch of the MUX multiplexer array in the form of fixed constant values in hardware. Each branch corresponds to an analytical solution at a fixed phase point.
[0007] The MUX multiplexer array selects the fixed complex constant output of the corresponding mathematical branch according to the index of the counter, and performs complex multiplication with the input baseband signal to achieve complex mixing.
[0008] Preferably, the target transfer frequency adapted by the device satisfies ,in, The current link sampling rate is given by M and k, where M and k are integers, and the corresponding normalized angular frequency is given by M. The corresponding complex rotation phase sequence is The sequence has finite periodicity, and its period is an integer divisor of M; all complex twitch factors within a period All are fixed constants, and all rotation factors have been solved mathematically in advance.
[0009] Preferably, the timing control module is a pure state-based rotary counter, configured with any coprime integer pairs k and M, and adapted to phase stepping. All finite phase periodic sequences are used to output branch gating, quadrant control, and mirror enable timing signals.
[0010] Preferably, for a local oscillator signal sequence with a finite period of M... A counter with a maximum count value of M is used to select the constant coefficient multiplication branch.
[0011] Preferably, the simplified constant coefficient operation branch pool is based on the triple symmetry characteristic of finite phase grid points, eliminating all redundant operations and retaining the minimum reference Givens rotation branches.
[0012] Preferably, the triple symmetry characteristics include four-quadrant rotational symmetry, conjugate symmetry, and I / Q symmetry.
[0013] Preferably, the MUX multiplexer array is linked with the timing control module to time-division select the reference branch to complete the I / Q signal reference complex weighting.
[0014] Preferably, the device further includes a symmetric multiplexing mapping module, which generates a frequency conversion output of all finite phases by multiplexing the reference branch through channel interchange and sign inversion logic.
[0015] Preferably, for special phase points with phase factors of ±1 and ±j, complex multiplication degenerates into sign inversion and real-imaginary part interchange.
[0016] Preferably, all the complex twisting factors are fixed in the circuit structure in the form of hard-wired mathematical constant branches, forming a pure combinational logic gating path.
[0017] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0018] This invention generates a counting index matching the rotation factor period through a timing control module. All complex rotation factors within a complete period are directly wired into each input branch of the MUX array in the form of fixed hardware constant values. The MUX array then selects the fixed complex constant output of the corresponding branch based on the index and performs complex multiplication with the input baseband signal. Since all rotation factors are hardwired mathematical constants fixed in the combinational logic path, there is no need to configure memory units for memory access or deploy iterative units or real-time multipliers for step-by-step approximation or real-time calculation. This completely eliminates memory access latency and power consumption, iterative data dependency and truncation errors, and real-time multiplication resource overhead. Simultaneously, it covers any short-period frequency point of rational fractions of class Fs / M using a static branch mapping method, breaking through the limitation of existing lightweight solutions that only support Fs / 2 and Fs / 4. This achieves full-scenario adaptation, ultra-low latency, and extremely low power consumption in scenarios such as frequency-agile communication, 6G dynamic spectrum access, and software-defined radio. Attached Figure Description
[0019] Figure 1 This is a schematic block diagram of the short-period sequence mixing implementation device of the present invention;
[0020] Figure 2 This is a block diagram of the digital complex mixer implementation of the Fs / 8 of the present invention. Detailed Implementation
[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.
[0022] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.
[0023] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.
[0024] Please see Figures 1-2 As shown, the present invention provides a short-period sequence mixing implementation device, characterized in that it includes a timing control module, a minimal constant coefficient operation branch pool, and a MUX multiplexer array;
[0025] The timing control module is a counter that generates a periodic index based on the system timing, and the index range matches the rotation factor period. The timing control module is a pure state-based rotary counter with no accumulation, no iteration, and no ROM, configured with arbitrary coprime integer pairs k and M, and adapted to phase steps. For all finite-phase periodic sequences, output branch gating, quadrant control, and mirror enable timing signals. For a local oscillator signal sequence with a finite period of M. A counter with a maximum count value of M is used to select the constant coefficient multiplication branch.
[0026] In the simplified constant coefficient operation branch pool, all complex twitch factors within a complete cycle are directly wired into each input branch of the MUX multiplexer array in the form of fixed constant values in hardware. Each branch corresponds to an analytical solution at a fixed phase point. Based on the triple symmetry characteristic of finite phase grid points, the simplified constant coefficient operation branch pool eliminates all redundant operations and retains the minimum reference Givens rotation branches. The triple symmetry characteristic includes four-quadrant rotational symmetry, conjugate symmetry, and I / Q symmetry. All complex twitch factors are fixed in the circuit structure in the form of hard-wired mathematical constant branches, forming a pure combinational logic gating path.
[0027] The minimal constant coefficient operation branch pool, based on the triple symmetry characteristics of finite phase grid points, eliminates all redundant operations, retains the minimum reference Givens rotation branches, and is transformed into a pure shift, addition and subtraction static hardware structure through CSE common subexpression elimination and RAG-n directed addition graph deep simplification, without real-time multipliers or iteration units.
[0028] For example, The frequency shift, and the corresponding relative digital frequency, is: Its corresponding digital phase sequence is This phase sequence is a cycle of 8 fixed phases, such as: , that is:
[0029] Of these eight complex numbers, only one requires a fixed coefficient for calculation. Other than that, there are only simple number selection methods such as pass-through, sign transformation, and I / Q swap.
[0030] Input Multiplying it by a complex number gives:
[0031] ;
[0032] ;
[0033] ;
[0034] ;
[0035] ;
[0036] ;
[0037] ;
[0038] ;
[0039] By using a 3-bit binary counter to sequentially select one of these 8 branches, the mixing result can be output.
[0040] For example The frequency shift corresponding to the digital frequency is: That is, 12 fixed phase periods, such as: ;
[0041] Based on the three symmetry properties of four-quadrant rotational symmetry, conjugate symmetry, and I / Q symmetry, it can be simplified to:
[0042] ,
[0043] The table also requires calculating two complex coefficient values, but in reality... They are two symmetric values of I and Q, that is .
[0044] Therefore, the above table of 12 complex constants can be written as:
[0045] ;
[0046] Therefore, the only true constant coefficients are It is its conjugate value. This is the ultimate simplification: out of 12 channels, only one requires calculation of a true constant coefficient. Then, the number selection outputs the 12 corresponding I / Q complex multiplication values.
[0047] The MUX multiplexer array selects the fixed complex constant output of the corresponding mathematical branch according to the index of the counter, and performs complex multiplication with the input baseband signal to achieve complex mixing. The MUX multiplexer array is linked with the timing control module to select the reference branch in a time-division multiplexing manner to complete the reference complex weighting of the I / Q signals. In addition, the device also includes a symmetrical multiplexing mapping module, which generates a frequency conversion output of all finite phases by multiplexing the reference branch through channel swapping and sign inversion logic.
[0048] Furthermore, the target transfer frequency adapted to the device meets the requirements. ,in, The current link sampling rate is given by M and k, where M and k are integers, and the corresponding normalized angular frequency is given by M. The corresponding complex rotation phase sequence is The sequence has finite periodicity, and its period is an integer divisor of M; all complex twitch factors within a period It does not dynamically calculate based on samples and requires no iterative approximation; all rotation factors can be mathematically solved in advance with no approximation error; as long as the frequency points belong to the Fs / M integer equal division system, they all satisfy the characteristics of the period constant and have unified and extremely simple implementation conditions.
[0049] This device supports bidirectional frequency conversion mode, enabling downconversion at the DDC receiver and upconversion at the DUC transmitter. The entire process is free of iteration, table lookup, and real-time complex multiplication, and hardware redundancy is completely eliminated, making it suitable for short-cycle frequency conversion requirements in all scenarios.
[0050] Taking the target shift frequency of Fs / 8 as an example, its corresponding digital phase circle is divided into eight equal parts. The implementation steps are as follows:
[0051] Step 1: Implement the I-channel using combinational circuits Q-path is implemented using combinational circuits. Then These 8 combinational logic blocks are connected sequentially to the 8 input ports of an I-way multiplexer; similarly, then:
[0052] These eight combinational logics are connected sequentially to the eight input ports of the Q-way multiplexer;
[0053] Step 2: A counter with a finite cycle generates digital selection control signals for the I / Q multiplexers;
[0054] Step 3: The digital selection control signal controls the I-channel output of the I-channel multiplexer and the Q-channel output of the Q-channel multiplexer, thus completing the equivalent complex digital mixing operation.
[0055] In summary, this invention generates a counting index that matches the rotation factor period through a timing control module, and directly wires all complex rotation factors within a complete period into each input branch of the MUX array in the form of fixed constant values in hardware. The MUX array then selects the fixed complex constant output of the corresponding branch according to the index and performs complex multiplication with the input baseband signal.
[0056] Since all twiddle factors are hardwired mathematical constants and fixed in the combinational logic path, there is no need to configure storage units for memory access or read, nor is there a need to deploy iterative units or real-time multipliers for step-by-step approximation or real-time operation. Thus, while completely eliminating memory access latency and power consumption, iterative data dependency and truncation error, and real-time multiplication resource overhead, it covers any short-cycle frequency point of rational fractions of class Fs / M in a static branch mapping manner, breaking through the limitation of existing lightweight solutions that only support Fs / 2 and Fs / 4.
[0057] The above description is merely an exemplary embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural transformations made using the contents of the present invention specification and drawings under the technical concept of the present invention, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.
Claims
1. A short-period sequence mixing implementation device, characterized in that, Includes a timing control module, a simplified constant coefficient operation branch pool, and a MUX multiplexer array; The timing control module is a counter that generates a period index based on the system timing. The index range matches the rotation factor period. In the simplified constant coefficient operation branch pool, all complex rotation factors within a complete period are directly wired into each input branch of the MUX multiplexer array in the form of fixed constant values in hardware. Each branch corresponds to an analytical solution at a fixed phase point. The MUX multiplexer array selects the fixed complex constant output of the corresponding mathematical branch according to the index of the counter, and performs complex multiplication with the input baseband signal to achieve complex mixing.
2. The short-period sequence mixing implementation device according to claim 1, characterized in that, The target transfer frequency adapted to the device satisfies ,in, The current link sampling rate is given by M and k, where M and k are integers, and the corresponding normalized angular frequency is given by M. The corresponding complex rotation phase sequence is The sequence has finite periodicity, and its period is an integer divisor of M; all complex twitch factors within a period All are fixed constants, and all rotation factors have been solved mathematically in advance.
3. The short-period sequence mixing implementation device according to claim 1, characterized in that, The timing control module is a pure state-rotation counter, configured with arbitrary coprime integer pairs k and M, and adapted to phase stepping. All finite phase periodic sequences are used to output branch gating, quadrant control, and mirror enable timing signals.
4. The short-period sequence mixing implementation device according to claim 3, characterized in that, For a local oscillator signal sequence with a finite period of M A counter with a maximum count value of M is used to select the constant coefficient multiplication branch.
5. The short-period sequence mixing implementation device according to claim 1, characterized in that, The simplified constant coefficient operation branch pool is based on the triple symmetry characteristic of finite phase grid points, eliminating all redundant operations and retaining the minimum reference Givens rotational branches.
6. The short-period sequence mixing implementation device according to claim 5, characterized in that, The triple symmetry characteristics include four-quadrant rotational symmetry, conjugate symmetry, and I / Q symmetry.
7. The short-period sequence mixing implementation device according to claim 1, characterized in that, The MUX multiplexer array works in conjunction with the timing control module to time-division select the reference branch and complete the complex weighting of the I / Q signal reference.
8. The short-period sequence mixing implementation device according to claim 7, characterized in that, The device also includes a symmetric multiplexing mapping module, which generates a frequency conversion output of all finite phases by multiplexing the reference branch through channel interchange and sign inversion logic.
9. The short-period sequence mixing implementation device according to claim 1, characterized in that, For phase points with phase factors of ±1 and ±j, complex multiplication degenerates into sign inversion and real-imaginary part interchange.
10. A short-period sequence mixing implementation device according to claim 1, characterized in that, All the complex twisting factors are fixed in the circuit structure in the form of hard-wired mathematical constant branches, forming a pure combinational logic gating path.