High voltage floating fully differential operational amplifier adapted for linear two-temperature calibration procedure

Abstract

This invention discloses a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process, belonging to the field of operational amplifier technology. The high-voltage floating fully differential operational amplifier includes a floating fully differential input stage, a high-voltage side, a tail current source, a temperature tracking bias circuit, and a floating fully differential output stage. The floating fully differential input stage is connected to the high-voltage side and the tail current source, and the floating fully differential output stage is connected to the tail current source and the temperature tracking bias circuit. A cascade node exists between the floating fully differential input stage and the high-voltage side, and the temperature tracking bias circuit is connected to the cascade node. The temperature tracking bias circuit generates a first bias voltage based on the node voltage at the cascade node and outputs it to the floating fully differential output stage. The floating fully differential output stage biases the tail current source based on the first bias voltage, and the tail current source is used to stabilize the internal voltage difference of the floating fully differential input stage in conjunction with the high-voltage side. The high-voltage operational amplifier of this invention can be adapted to back-end tuning methods.

Description

Technical Field

[0001] This invention relates to the field of operational amplifier technology, and in particular to a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process. Background Technology

[0002] In high-voltage precision analog circuit systems, input offset voltage and its temperature drift are the core error factors restricting the accuracy of the circuit over a wide operating temperature range. Compared to conventional low-voltage operational amplifiers, high-voltage floating fully differential operational amplifiers have a more unique operating architecture. The circuit design must simultaneously meet the requirements of high voltage withstand capability, strong output drive capability, and maintain a small input offset voltage and temperature drift coefficient over a wide temperature range. This makes the structural temperature drift problem of this type of amplifier more prominent and more difficult to suppress than that of low-voltage op-amps.

[0003] Currently, most operational amplifiers of this type use MOSFETs to form a differential input structure. Their offset and temperature drift mainly originate from threshold voltage mismatch and current factor mismatch of the MOSFET devices. Existing research also focuses on these two types of mismatches and has established a classical approximate model for the input offset voltage: Vos ≈ ΔV TH + (I D / g m )·(Δβ / β), where Vos is the input offset voltage; ΔV TH I represents the absolute difference in threshold voltages between the two MOSFETs in the differential input structure. D This refers to the static drain bias current of the MOSFET; g m β is the transconductance of the MOSFET; β is the current gain factor of the MOSFET. This model can effectively explain the offset and temperature drift characteristics of conventional low-voltage MOSFET input operational amplifiers caused by inherent device mismatch. However, the circuit structure of high-voltage floating operational amplifiers is more complex, and there are additional temperature drift influencing factors not present in low-voltage operational amplifiers. This causes their temperature drift characteristics to no longer conform to the temperature drift variation law of conventional low-voltage operational amplifiers, making it difficult for the above-mentioned classical approximation model of input offset voltage to accurately characterize its actual offset temperature drift characteristics. Consequently, the overall structure temperature drift curvature of high-voltage floating fully differential operational amplifiers is too large. Under this premise, relying solely on back-end trimming (Trim) for error compensation is prone to many problems such as complex calibration, insufficient stability, and large residual temperature drift.

[0004] This section is intended to provide background or context for the embodiments of the invention set forth in the claims. The description herein is not an admission that it is prior art simply because it is included in this section. Summary of the Invention

[0005] This invention provides a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process. The high-voltage floating fully differential operational amplifier includes a floating fully differential input stage, a high-voltage side, a tail current source, a temperature tracking bias circuit, and a floating fully differential output stage. The floating fully differential input stage is connected to the high-voltage side and the tail current source, and the floating fully differential output stage is connected to the tail current source and the temperature tracking bias circuit. A cascade node exists between the floating fully differential input stage and the high-voltage side, and the temperature tracking bias circuit is connected to the cascade node. The temperature tracking bias circuit generates a first bias voltage based on the node voltage at the cascade node and outputs it to the floating fully differential output stage. The floating fully differential output stage biases the tail current source based on the first bias voltage, and the tail current source is used to stabilize the internal voltage difference of the floating fully differential input stage in conjunction with the high-voltage side.

[0006] Optionally, the temperature tracking bias circuit includes a reference voltage generation module and a first bias voltage generation module; the reference voltage generation module is connected to the cascaded node and the first bias voltage generation module, and is used to generate a reference voltage based on the node voltage; the first bias voltage generation module is connected to the floating fully differential output stage, and is used to generate a first bias voltage based on the reference voltage.

[0007] Optionally, the reference voltage generation module includes a first MOSFET connected by a diode and a second MOSFET connected by a diode, and the first bias voltage generation module includes a third MOSFET connected by a diode; the first MOSFET is connected to the cascade node and the second MOSFET, and is used to generate a reference common-mode voltage based on the node voltage; the second MOSFET is connected to the third MOSFET, and is used to generate a reference voltage based on the reference common-mode voltage; the third MOSFET is connected to the floating fully differential output stage, and is used to generate a first bias voltage based on the reference voltage.

[0008] Optionally, the operating range of the first MOSFET is in the deep subthreshold region, the operating range of the second MOSFET is at the boundary between the weak inversion region and the strong inversion region, and the operating range of the third MOSFET is in the strong inversion region.

[0009] Optionally, the reference voltage generation module includes a fourth MOSFET connected to a diode, and the first bias voltage generation module includes a fifth MOSFET connected to a diode; the fourth MOSFET is connected to the cascade node and the fifth MOSFET to generate a reference voltage based on the node voltage; the fifth MOSFET is connected to the floating fully differential output stage to generate a first bias voltage based on the reference voltage.

[0010] Optionally, the fourth MOSFET is a high-voltage device and the fifth MOSFET is a low-voltage device, with the fourth MOSFET operating in the shallow subthreshold region and the fifth MOSFET operating in the deep subthreshold region.

[0011] Optionally, the high-voltage floating fully differential operational amplifier adapted to the linear dual-temperature calibration process also includes a dual-temperature calibration interface, which is connected to a dual-temperature calibration system; wherein, the dual-temperature calibration system is used to perform temperature drift calibration on the high-voltage floating fully differential operational amplifier.

[0012] Optionally, the tail current source or high-voltage side is configured to maintain a predetermined saturation margin within the operating temperature range.

[0013] Optionally, the tail current source includes a floating tail current source module and an operational amplifier's internal low-dropout regulator. The floating tail current source module is connected to the floating fully differential input stage, the operational amplifier's internal low-dropout regulator, the temperature tracking bias circuit, and the floating fully differential output stage. The operational amplifier's internal low-dropout regulator is connected to the temperature tracking bias circuit. The temperature tracking bias circuit is also used to generate a second bias voltage and a third bias voltage based on the node voltage, and outputs the second bias voltage to the floating tail current source module and the third bias voltage to the operational amplifier's internal low-dropout regulator. The operational amplifier's internal low-dropout regulator is used to cooperate with the temperature tracking bias circuit to stabilize the internal voltage of the floating tail current source module. The floating tail current source module is used to cooperate with the high-voltage side to stabilize the internal voltage difference of the floating fully differential input stage.

[0014] Optionally, the floating fully differential output stage includes a folded cascode amplifier stage, which is connected to the tail current source and the temperature tracking bias circuit; wherein the folded cascode amplifier stage is used to bias the tail current source according to the first bias voltage.

[0015] Optionally, the floating fully differential output stage further includes: a common-mode feedback circuit, connected to the folded cascode amplifier stage, for receiving the differential output voltage signal from the folded cascode amplifier stage and stabilizing the output common-mode level of the high-voltage floating fully differential operational amplifier based on the differential output voltage signal; and a Class AB output stage, connected to the folded cascode amplifier stage, for receiving the differential output voltage signal from the folded cascode amplifier stage and performing signal power amplification and load driving based on the differential output voltage signal.

[0016] The high-voltage floating fully differential operational amplifier adapted to the linear dual-temperature calibration process provided in this embodiment of the invention includes a floating fully differential input stage, a high-voltage side, a tail current source, a temperature tracking bias circuit, and a floating fully differential output stage. The floating fully differential input stage is connected to the high-voltage side and the tail current source, and the floating fully differential output stage is connected to the tail current source and the temperature tracking bias circuit. Furthermore, there is a cascade node between the floating fully differential input stage and the high-voltage side, and the temperature tracking bias circuit is connected to the cascade node. The floating fully differential input stage receives a differential input voltage signal, which determines the node voltage at the cascade node between the floating fully differential input stage and the high-voltage side. This application connects a temperature tracking bias circuit at the cascade node. Since this temperature tracking bias circuit can generate a first bias voltage based on the node voltage, when the floating fully differential output stage is connected to the temperature tracking bias circuit and the tail current source is connected, the temperature tracking bias circuit can apply this first bias voltage to the floating fully differential output stage. This causes the floating fully differential output stage to bias the tail current source according to the first bias voltage, thereby setting the voltage magnitude of the temperature tracking node (the bias node between the floating fully differential input stage and the tail current source). In this way, the VDS changes of the high-voltage side, the floating fully differential input stage related devices, and the tail current source related devices are suppressed.

[0017] Specifically, the temperature tracking bias circuit ensures that the difference between the node voltage and the first bias voltage remains constant throughout the entire temperature range. This means that the first bias voltage changes synchronously and with the same amplitude as the node voltage's potential change. The voltage of the temperature tracking node is set by the first bias voltage, further implying that the voltage of the temperature tracking node can change synchronously with the node voltage, and the relative voltage difference between the two remains constant throughout the entire temperature range. Thus, since the node voltage and the temperature tracking node voltage are the upper and lower voltages of the floating fully differential input stage, respectively, the voltage difference (V) between the upper and lower terminals of the floating fully differential input stage is guaranteed. DS It is basically stable throughout the entire temperature range, which makes gds(T) closer to first-order linearity.

[0018] It should be noted that the input offset of a high-voltage floating fully differential operational amplifier can be expressed as the sum of the conventional term and the additional term: V os_total ≈ ΔV TH + (I D / g m )·(Δβ / β) + ΔV extra Among them, the additional term ΔV extra Corresponding to the inter-branch ΔV of the floating fully differential input stage caused by branch mismatch under high-voltage mismatch conditions. DS After the device output conductance (g) dsThe additional current mismatch resulting from the transformation (T) can be approximated by the following equivalent relationship: ΔI DS,extra ≈ ΔV DS ·g ds (T); ΔV extra ≈ ΔI DS,extra / g m,eq .

[0019] Therefore, in the floating fully differential input stage caused by branch mismatch, the inter-branch ΔV DS Based on the premise that it is approximately independent of temperature within the temperature range, due to g ds (T) is close to first-order linear, therefore ΔV DS ·g ds (T) If it is closer to the first-order temperature drift term, then the additional term ΔV extra It is also closer to linear, which makes this high-voltage floating fully differential operational amplifier compatible with back-end trimming. That is, the error faced by subsequent dual-temperature calibration is closer to the basic offset and residual near-linear temperature drift, rather than a complex drift term containing obvious high-order curvature. Subsequent dual-temperature calibration is easier to complete back-end trimming at two temperature points, which can improve the offset and temperature drift consistency of the high-voltage floating fully differential operational amplifier over a wide temperature range. This solves the problems of existing high-voltage floating fully differential operational amplifiers that rely solely on back-end trimming for error compensation, which are prone to complex calibration, insufficient stability, and large residual temperature drift. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic block diagram of a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process in an embodiment of the present invention. Figure 2 This is a schematic diagram of the temperature tracking bias path of a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process in an embodiment of the present invention. Figure 3 This is a schematic diagram of a temperature tracking bias circuit according to an embodiment of the present invention; Figure 4 for Figure 3 The diagram shows the functional relationship between the voltage of each node and the temperature in the temperature tracking bias circuit. Figure 5This is a schematic diagram of another temperature tracking bias circuit in an embodiment of the present invention; Figure 6 for Figure 5 The diagram shows the functional relationship between voltage and temperature at each node in the temperature tracking bias circuit. Figure 7 A schematic block diagram of a high-voltage precision analog circuit system provided in an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the compensation process for dual-temperature calibration using a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration procedure, according to an embodiment of the present invention.

[0021] The above figures include the following reference numerals: 10. Floating fully differential input stage; 20. High voltage side; 102. Cascade node; 30. Tail current source; 301. Floating tail current source module; 302. Operational amplifier internal low dropout regulator; 40. Temperature tracking bias circuit; 401. Reference voltage generation module; 4011. First MOSFET; 4012. Second MOSFET; 4013. Fourth MOSFET; 402. First bias voltage generation module; 4021. Third MOSFET; 4022. Fifth MOSFET; 50. Floating fully differential output stage; 501. Folded cascode amplifier stage; 502. Common-mode feedback circuit; 503. Class AB output stage; 60. Dual-temperature calibration interface; 70. Dual-temperature calibration system; 701. On-chip adjustment interface; 702. Comparison decision module; 703. Digital search control module; 704. Parameter storage module. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0023] As described in the background section, the classical approximation model of the input offset voltage of existing operational amplifiers is: V os ≈ΔV TH + (I D / g m This type of model can better explain the relationship between ΔV and Δβ / β in a typical MOS input structure. TH The study addresses the offset and temperature drift caused by Δβ / β, but it does not adequately consider the additional temperature drift channels generated by cascaded devices, tail current sources, and floating nodes in high-voltage structures.

[0024] In two symmetrical differential branches with consistent bias, the common temperature variations of device parameters often manifest as common-mode drift, which cancels out in the differential output. What truly translates into differential offset temperature drift is the mismatch between these common temperature variations and the branch, especially the asymmetry of the high-voltage cascade node. DS The coupling between changes. Therefore, for this type of high-voltage structure, a more suitable description of the additional drift is: the inter-branch ΔV caused by high-voltage mismatch. DS After the device output conductance g ds (T) is converted into additional current mismatch, and then referred back to the input terminal by equivalent transconductance: ΔV DS → ΔI DS ≈ ΔV DS ·g ds (T) → ΔV os ≈ ΔI DS / g m,eq , It is important to note that the key to the above relationship lies not in simply writing the additional term as a static error, but in distinguishing between two levels: when the V of the sensitive device... DS As temperature drifts, g ds (T) will be additionally modulated, thus causing the additional current term to exhibit a significant curvature; conversely, if the V of the relevant sensitive device is made to be less distorted through the circuit structure... DS If it remains essentially constant within the temperature range, then g ds (T) can be designed to be closer to first-order linear. Furthermore, if ΔV is formed by branch mismatch... DS If it is approximately independent of temperature within the temperature range, then in g ds (T) Assuming the product term ΔV is approximately linear, DS ·g ds (T) is also closer to first-order linearity, and is therefore more suitable for subsequent two-temperature calibration.

[0025] Figure 1 This is a schematic block diagram of a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process, provided as an embodiment of this application. Figure 1 As shown, a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process includes a floating fully differential input stage 10, a high-voltage side 20, a tail current source 30, a temperature tracking bias circuit 40, and a floating fully differential output stage 50. The floating fully differential input stage 10 is connected to the high voltage side 20 and the tail current source 30. The floating fully differential output stage 50 is connected to the tail current source 30 and the temperature tracking bias circuit 40. The floating fully differential input stage 10 and the high voltage side 20 have a cascade node 102. The temperature tracking bias circuit 40 is connected to the cascade node 102. The temperature tracking bias circuit 40 is used to track the node voltage V at the cascaded node 102. c Generate the first bias voltage V b1 The output is then sent to the aforementioned floating fully differential output stage 50, which is used to adjust the first bias voltage V according to the aforementioned first bias voltage V. b1 The tail current source 30 is biased and used to cooperate with the high voltage side 20 to stabilize the internal voltage difference of the floating fully differential input stage 10.

[0026] Figure 2 This is a schematic diagram of the temperature tracking bias path of a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process, as shown in an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 In the above embodiment, the floating fully differential input stage 10 is used to receive the differential input voltage signal (V). inp V inn The differential input voltage signal determines the node voltage V at the cascade node 102 between the floating fully differential input stage 10 and the high-voltage side 20. c This application connects a temperature tracking bias circuit 40 at the aforementioned cascade node 102. Because this temperature tracking bias circuit 40 can adjust the temperature based on the node voltage V... c Generate the first bias voltage V b1 Thus, when the temperature tracking bias circuit 40 is connected to the floating fully differential output stage 50 and the floating fully differential output stage 50 is connected to the tail current source 30, the temperature tracking bias circuit 40 can measure the first bias voltage V. b1 The first bias voltage V is applied to the floating fully differential output stage 50, causing the floating fully differential output stage 50 to adjust according to the first bias voltage V. b1 The tail current source 30 is biased to set the voltage magnitude of the temperature tracking node ip / in (the bias node between the floating fully differential input stage 10 and the tail current source 30).

[0027] Specifically, the temperature tracking bias circuit 40 enables the node voltage V to... c With the first bias voltage V b1 The difference remains constant throughout the entire temperature range, which means that the first bias voltage V b1 It will change with the node voltage V cThe potential changes synchronously with the same amplitude; while the voltage magnitude of the temperature tracking node ip / in is determined by the first bias voltage V. b1 This setting, in turn, means that the voltage magnitude of the temperature tracking node ip / in can vary with the node voltage V. c The voltage changes synchronously, and the relative pressure difference between the two remains constant throughout the entire temperature range. Thus, since the voltage at this node and the voltage at the temperature tracking node ip / in are the upper and lower voltages of the floating fully differential input stage 10, respectively, the Vi of the high-voltage side 20, the related devices of the floating fully differential input stage 10, and the related devices of the tail current source 30... DS Changes are suppressed, thus ensuring the voltage difference (V) between the upper and lower terminals of the floating fully differential input stage 10. DS It remains essentially stable across the entire temperature range, thus allowing g to... ds (T) is closer to first-order linearity.

[0028] It should be noted here that: ΔV DS This represents the drain-source voltage difference caused by the mismatch between the left and right corresponding branches of the high-voltage floating fully differential operational amplifier, rather than the V of a single sensitive device. DS It is not generated solely by the floating fully differential output stage 50; its temperature is approximately independent within the temperature range, i.e., "ΔV". DS "Approximately constant"; while the temperature tracking bias circuit 40 first sets the V of each of the two sensitive devices in the corresponding left and right branches to be "approximately constant"; DS The temperature slopes should be as consistent as possible, and the temperature coefficient of the difference should be close to zero, i.e., "sensitive device V" DS "Maintain stability." Therefore, "sensitive device V" DS "Maintain stability" and "ΔV" DS "Approximately constant" corresponds to two levels: stability of the single-branch operating point and stability of the inter-branch difference.

[0029] Furthermore, based on the above description of the input offset or additional drift of the high-voltage floating fully differential operational amplifier, it can be seen that in g ds (T) The inter-branch ΔV of the floating fully differential input stage 10, which has been linearized and is caused by branch mismatch. DS Based on the premise that it is approximately independent of temperature within this temperature range, then ΔV DS ·g ds(T) is closer to the first temperature drift term, which makes this high-voltage floating fully differential operational amplifier compatible with the back-end trimming method. That is, the error faced by subsequent dual-temperature calibration is closer to the basic offset and residual approximately linear temperature drift, rather than a complex drift term containing obvious higher-order curvature. Subsequent dual-temperature calibration is easier to complete the back-end trimming at the two temperature points, which can improve the offset and temperature drift consistency of the high-voltage floating fully differential operational amplifier over a wide temperature range. This solves the problem that existing high-voltage floating fully differential operational amplifiers rely solely on the back-end trimming method for error compensation, which easily leads to complex calibration, insufficient stability, and large residual temperature drift.

[0030] Specifically, the aforementioned floating fully differential input stage 10 includes a control terminal, a first terminal, and a second terminal. The high-voltage side 20 is connected to the first terminal of the floating fully differential input stage 10, and the tail current source 30 is connected to the second terminal of the floating fully differential input stage 10. Its control terminal is used to receive the differential input voltage signal (V). inp V inn ).

[0031] For example, the floating fully differential input stage 10 includes a PMOS. In this case, the control terminal of the floating fully differential input stage 10 is the gate of the PMOS, the first terminal of the floating fully differential input stage 10 is the source of the PMOS, and the second terminal of the floating fully differential input stage 10 is the drain of the PMOS.

[0032] Specifically, the high-voltage side 20 can be a high-voltage cascaded branch. For example, the high-voltage cascaded branch is a high-voltage current source. Further, this high-voltage current source is implemented by connecting a low-voltage current mirror in series with a high-voltage common-gate transistor, wherein the low-voltage current mirror is connected to the high-voltage power supply, and the high-voltage common-gate transistor is connected to the floating fully differential input stage 10.

[0033] Specifically, the aforementioned floating fully differential output stage 50 includes a control terminal, a first terminal, and a second terminal. The tail current source 30 is connected to the first terminal of the floating fully differential output stage 50, the temperature tracking bias circuit 40 is connected to the control terminal of the floating fully differential output stage 50, and the second terminal of the floating fully differential output stage 50 is used to output a differential output voltage signal (V). odiff It is understandable that the floating fully differential output stage 50 actually converts differential current into differential voltage for output.

[0034] For example, the floating fully differential output stage 50 includes an NMOS. In this case, the control terminal of the floating fully differential output stage 50 is the gate of the NMOS, the first terminal of the floating fully differential output stage 50 is the source of the NMOS, and the second terminal of the floating fully differential output stage 50 is the drain of the NMOS. Additionally, the floating fully differential output stage 50 also includes a current source device, and the drain (second terminal) of the NMOS in the floating fully differential output stage 50 is connected to the current source device.

[0035] In some exemplary embodiments, the high-voltage floating fully differential operational amplifier adapted to the linear dual-temperature calibration process includes a floating fully differential input stage 10 (PMOS), a high-voltage side 20, a tail current source 30, a temperature tracking bias circuit 40, and a floating fully differential output stage 50 (NMOS and corresponding current source device). The gate of the PMOS is connected to the differential input voltage signal (V). inp V inn The source of the PMOS is connected to the high-voltage side 20, and the drain of the PMOS is connected to the tail current source 30; the current source device in the floating fully differential output stage 50 is connected to the drain of the NMOS in the floating fully differential output stage 50, the source of the NMOS is connected to the tail current source 30, and the gate of the NMOS is connected to the temperature tracking bias circuit 40.

[0036] Figure 3 and Figure 5 This is a schematic diagram of the temperature tracking bias circuit 40 in an embodiment of the present invention. Figure 4 for Figure 3 The diagram shows the functional relationship between voltage and temperature at each node in the temperature tracking bias circuit 40, where the horizontal axis represents temperature and the vertical axis represents voltage. Figure 6 for Figure 5 The diagram shows the functional relationship between voltage and temperature at each node in the temperature tracking bias circuit 40, where the horizontal axis represents temperature and the vertical axis represents voltage.

[0037] Please refer to Figure 1 , Figure 3 and Figure 4 (or reference) Figure 1 , Figure 5 and Figure 6 In some optional embodiments, the temperature tracking bias circuit 40 includes a reference voltage generation module 401 and a first bias voltage generation module 402; the reference voltage generation module 401 is connected to the cascaded node 102 and the first bias voltage generation module 402, and is used to generate a bias voltage based on the node voltage (V). c ) generates a reference voltage (V sshThe first bias voltage generation module 402 is connected to the floating fully differential output stage 50 and is used to generate a bias voltage based on the reference voltage (V). ssh The first bias voltage (V) is generated. b1 ).

[0038] In the above embodiments, the reference voltage generation module 401 can make the reference voltage (V) it generates... ssh ) and the node voltage (V) of cascaded node 102 c The difference between the two values ​​remains constant throughout the entire temperature range; the first bias voltage generation module 402 enables the first bias voltage (V) it generates to remain constant throughout the entire temperature range. b1 ) and the reference voltage (V) generated by the reference voltage generation module 401 ssh The difference between the reference voltage generation module 401 and the cascaded node 102 and the first bias voltage generation module 402, and the first bias voltage generation module 402 and the floating fully differential output stage 50, can ensure that the node voltage (V) remains constant throughout the temperature range. c ) and the first bias voltage (V b1 The difference remains constant throughout the entire temperature range.

[0039] Based on the established connection relationships between the reference voltage generation module 401 and the first bias voltage generation module 402 in the temperature tracking bias circuit 40, the connection relationship between the reference voltage generation module 401 and the cascade node 102, and the connection relationship between the first bias voltage generation module 402 and the floating fully differential output stage 50, the aforementioned "difference remains constant throughout the entire temperature range" indicates that the temperature slope of the target node is designed to be approximately equal after considering device size, bias current, and operating area selection. If V c -V ssh and V ssh -V b1 If both are approximately constant, then V c V ssh With V b1 They should have approximately the same temperature slope; V incm The slope is determined by the voltage drop distribution between the first MOSFET 4011 and the second MOSFET 4012.

[0040] Specifically, the first bias voltage generating module 402 can be connected to the control terminal of the floating fully differential output stage 50. Additionally, the temperature tracking bias circuit 40 may also include a first current source device and a second current source device. The first current source device is connected to the reference voltage generating module 401 and the first bias voltage generating module 402, and the second current source device is connected to the first bias voltage generating module 402.

[0041] For example, in the case where the floating fully differential output stage 50 includes an NMOS, the first bias voltage generation module 402 is connected to the gate of the NMOS.

[0042] like Figure 3 and Figure 4 As shown, in some optional embodiments, the reference voltage generation module 401 includes a first MOSFET 4011 connected by a diode and a second MOSFET 4012 connected by a diode, and the first bias voltage generation module 402 includes a third MOSFET 4021 connected by a diode; the first MOSFET 4011 is connected to the cascaded node 102 and the second MOSFET 4012, and is used to generate a bias voltage based on the node voltage (V). c ) generates a reference common-mode voltage (V incm The second MOSFET 4012 is connected to the third MOSFET 4021 and is used to adjust the reference common-mode voltage (V) according to the above-mentioned reference common-mode voltage (V). incm The above reference voltage (V) is generated. ssh The third MOSFET 4021 is connected to the floating fully differential output stage 50 and is used to adjust the output voltage according to the reference voltage (V). ssh The first bias voltage (V) is generated. b1 ).

[0043] In the above embodiment, by connecting the first MOSFET 4011 and the second MOSFET 4012, which are connected in series with two diodes, the first MOSFET 4011 is connected to the cascade node 102, the second MOSFET 4012 is connected to the third MOSFET 4021, and the third MOSFET 4021 is connected to the floating fully differential output stage 50, and by introducing an IPTAT temperature-sensitive bias, the operating states of the first MOSFET 4011 and the second MOSFET 4012 can be controlled by the IPTAT positive temperature characteristic bias current (a bias current proportional to the absolute temperature). This allows the reference voltage generation module 401 to generate a node voltage (V) that changes linearly with temperature and is connected to the cascade node 102. c The difference between the reference voltage (V) and the reference voltage (V) remains constant throughout the entire temperature range. ssh ); and regulate the operating state of the third MOSFET 4021, so that the first bias voltage generation module 402 generates a voltage that changes linearly with temperature and is related to the reference voltage (V). ssh The difference between the first bias voltage (V) and the first bias voltage (V) remains constant throughout the entire temperature range. b1 Thus, for a high-voltage floating fully differential operational amplifier, the voltage difference (V) between the first and second terminals of the floating fully differential input stage 10 can be made... DS It remains basically stable during temperature changes, thus providing a relatively stable V to the floating fully differential input stage 10, the high-voltage side 20, and the tail current source 30. DS Window (V)DS (basically stable), so that the output conductance (g) of the related devices in the floating fully differential input stage 10 is... ds (T) is closer to first-order linearity, and thus the ΔV formed by branch mismatch is closer to first-order linearity. DS Based on the premise that it is approximately independent of temperature within the temperature range, ΔV DS ·g ds (T) is closer to the first temperature drift term, thereby reducing the overall temperature drift curvature deviation of the high-voltage floating fully differential operational amplifier, making the high-voltage floating fully differential operational amplifier more suitable for subsequent dual-temperature calibration, so that the subsequent dual-temperature trim mainly deals with residual linear drift, rather than dealing with strong curvature error.

[0044] Optionally, the first bias voltage generation module 402 further includes an active device, through which the third MOSFET 4021 is connected to the floating fully differential output stage 50. This active device is a high-voltage MOSFET connected in a diode configuration, and its operating region is adjusted according to the current-voltage ratio to align with the voltage range of the floating fully differential output stage 50. b1 The direct connection of the common-gate transistor is the same; its purpose is to be able to generate an equivalent voltage source and then raise it by a voltage of V through this source. TH The voltage allows the common gate transistor and tail current source 30 in the floating fully differential output stage 50 to operate normally in the saturation region and prevents the low-voltage current mirror from being broken down by the high voltage.

[0045] It is necessary to clarify the connection of the "diode-connected first MOSFET 4011" here. For the first MOSFET 4011, the connection method in which its gate and drain are connected together is a diode connection; similarly, for the second MOSFET 4012, the connection method in which its gate and drain are connected together is a diode connection; and for the third MOSFET 4021, the connection method in which its gate and drain are connected together is a diode connection. The aforementioned IPTAT temperature-sensitive bias can be introduced through the IPTAT branch, which refers to the current source branch that provides a bias current proportional to the absolute temperature to the relevant diode-connected MOSFET.

[0046] Specifically, the source of the first MOSFET 4011 can be connected to the cascade node 102. The drain of the first MOSFET 4011 can be connected to the source of the second MOSFET 4012. The drain of the second MOSFET 4012 can be connected to the drain of the third MOSFET 4021. The source of the third MOSFET 4021 can be connected to the control terminal of the floating fully differential output stage 50. Alternatively, if the temperature tracking bias circuit 40 further includes the first current source device, the active device, and the second current source device, the third MOSFET 4021 can be connected to the control terminal of the floating fully differential output stage 50 through the active device. The first current source device can be connected to the drains of the second MOSFET 4012 and the third MOSFET 4021, and the active device can also be connected to the second current source device.

[0047] For example, when the floating fully differential output stage 50 includes an NMOS, the source of the third MOS transistor 4021 is connected to the gate of the NMOS. Alternatively, when the temperature tracking bias circuit 40 also includes the first current source device, the active device, and the second current source device, the source of the third MOS transistor 4021 is connected to the gate of the NMOS through the active device.

[0048] like Figure 3 As shown, in some optional embodiments, the operating range of the first MOS transistor 4011 is in the deep subthreshold region, the operating range of the second MOS transistor 4012 is at the boundary between the weak inversion region and the strong inversion region, and the operating range of the third MOS transistor 4021 is in the strong inversion region.

[0049] In the above embodiments, the three operating regions are used to combine different gate-source voltage temperature coefficients, DC voltage drops, and drive capabilities. When the first MOSFET 4011 operates in the deep subthreshold region, its gate-source voltage is highly sensitive to temperature and bias current, and can be used to form the required temperature slope. Here, it is mainly used to offset the temperature change voltage drop caused by the differential pair operating in the deep subthreshold region. When the second MOSFET 4012 operates at the boundary between the weak inversion region and the strong inversion region, it is used to transition between the temperature slope, curvature, and DC voltage drop. Here, it is used based on the temperature-invariant V... incm Reproduce V c The temperature change slope; when the third MOSFET 4021 operates in the strong inversion region, it is used to form a relatively stable bias output and meet the driving and swing requirements of the subsequent common gate MOSFET. Here, it is used to move V. ssh The slope curve is kept constant, and the voltage is increased. The above working region is an optimal combination to achieve slope matching of the target node. The specific device size, bias current, and high-voltage or low-voltage device type should be determined based on the actual process, withstand voltage requirements, and simulation results.

[0050] Among them, the saturation region condition of the MOSFET, the deep subthreshold, the boundary between the weak inversion region and the strong inversion region, and the strong inversion belong to different dimensions of the operating state description. The diode-connected MOSFET usually meets the corresponding saturation condition when it is turned on, while the inversion degree of the three MOSFETs (the first MOSFET 4011, the second MOSFET 4012, and the third MOSFET 4021) is determined by the bias current and the device size relationship.

[0051] like Figure 5 and Figure 6 As shown, in some optional embodiments, the reference voltage generation module 401 includes a fourth MOSFET 4013 connected to a diode, and the first bias voltage generation module 402 includes a fifth MOSFET 4022 connected to a diode; the fourth MOSFET 4013 is connected to the cascade node 102 and the fifth MOSFET 4022, and is used to generate a bias voltage based on the node voltage (V). c The above reference voltage (V) is generated. ssh The fifth MOSFET 4022 is connected to the floating fully differential output stage 50 and is used to adjust the output voltage according to the reference voltage (V). ssh The first bias voltage (V) is generated. b1 ).

[0052] In the above embodiment, by connecting the fourth MOSFET 4013 and the fifth MOSFET 4022, connecting the fourth MOSFET 4013 to the cascade node 102, and connecting the fifth MOSFET 4022 to the floating fully differential output stage 50, a node voltage (V) with a slope close to that of the reference voltage generation module 401, which generates a linearly temperature-dependent node voltage (V) and is connected to the cascade node 102, can be constructed. c The difference between the reference voltage (V) and the reference voltage (V) remains constant throughout the entire temperature range. ssh The first bias voltage generation module 402 generates a voltage that varies linearly with temperature and is compared with a reference voltage (V). ssh The difference between the first bias voltage (V) and the first bias voltage (V) remains constant throughout the entire temperature range. b1 The DC-level staggered bias nodes provide a more stable V to the floating fully differential input stage 10, the high-voltage side 20, and the tail current source 30. DS The window allows the output conductance (g) of the related devices in the floating fully differential input stage 10 to be adjusted. ds (T) is closer to first-order linear. Therefore, in this V DS Under basically stable conditions, the ΔV caused by branch mismatch DS Based on the premise that it is approximately independent of temperature within the temperature range, ΔV DS ·g ds(T) is closer to the first temperature drift term, which can reduce the temperature drift curvature deviation of the overall structure of the high-voltage floating fully differential operational amplifier, making the high-voltage floating fully differential operational amplifier more suitable for subsequent dual-temperature calibration, so that the subsequent dual-temperature trim mainly deals with residual linear drift, rather than dealing with strong curvature error.

[0053] Specifically, the source of the fourth MOSFET 4013 can be connected to the cascade node 102. The drain of the fourth MOSFET 4013 can be connected to the drain of the fifth MOSFET 4022. The source of the fifth MOSFET 4022 can be connected to the control terminal of the floating fully differential output stage 50. Alternatively, if the temperature tracking bias circuit 40 further includes the first current source device, the active device, and the second current source device, the fifth MOSFET 4022 can be connected to the control terminal of the floating fully differential output stage 50 through the active device. The first current source device can be connected to the drains of the fourth MOSFET 4013 and the fifth MOSFET 4022, and the active device can also be connected to the second current source device.

[0054] For example, when the floating fully differential output stage 50 includes an NMOS, the source of the fifth MOS transistor 4022 is connected to the gate of the NMOS. Alternatively, when the temperature tracking bias circuit 40 further includes the first current source device, the active device, and the second current source device, the source of the fifth MOS transistor 4022 is connected to the gate of the NMOS through the active device.

[0055] like Figure 5 As shown, in some optional embodiments, the fourth MOSFET 4013 is a high-voltage device, the fifth MOSFET 4022 is a low-voltage device, and the operating range of the fourth MOSFET 4013 is in the shallow subthreshold region, while the operating range of the fifth MOSFET 4022 is in the deep subthreshold region.

[0056] In the above embodiments, the significant threshold voltage (V) of the high-voltage device is utilized. TH ) and threshold voltage temperature coefficient (dV TH / d T The characteristics of the deep subthreshold device form a temperature tracking reference, utilizing the temperature-varying gate-source voltage (V) of the deep subthreshold device. GS The (T) characteristic introduces the required DC voltage difference and enables multiple key bias nodes (cascade node 102 between the high-voltage side 20 and the floating fully differential input stage 10, and the connection node between the floating fully differential input stage 10 and the tail current source 30) to maintain approximately synchronous slope changes during temperature variations.

[0057] Among them, cascade node 102 can correspond to node V. cThe connection node between the floating fully differential input stage 10 and the tail current source 30 corresponds to the input-side tracking node ip / in. The design goal here is not to require all nodes to be at the same potential or have the exact same slope, but rather to match the temperature slopes of the nodes at both ends of the same sensing device, thereby ensuring their V... DS It remains basically stable within the target temperature range.

[0058] Figure 7 This is a schematic block diagram of a high-voltage precision analog circuit system provided as an embodiment of the present invention. Figure 1 and Figure 7 As shown, in some optional embodiments, the high-voltage floating fully differential operational amplifier adapted to the linear dual-temperature calibration process further includes a dual-temperature calibration interface 60, which is connected to a dual-temperature calibration system 70; wherein, the dual-temperature calibration system 70 is used to perform temperature drift calibration on the high-voltage floating fully differential operational amplifier.

[0059] Based on the above description, it can be seen that in a high-voltage floating fully differential operational amplifier, due to g ds (T) is closer to first-order linear, and the ΔV formed by the mismatch is... DS Within the temperature range, it is approximately independent of temperature, thus adding a current error term ΔV. DS ·g ds (T) is already closer to linear before entering dual-temperature calibration. Based on this, in the above embodiment, after connecting the dual-temperature calibration system 70 to the high-voltage floating fully differential operational amplifier via the dual-temperature calibration interface 60, the dual-temperature calibration system 70 faces residual errors closer to the first-order term, rather than a complex combination of errors containing significant additional drift curvature. Thus, the dual-temperature calibration system 70 can more easily perform trimming at both temperature points.

[0060] In summary, this application does not simply rely on subsequent algorithms (back-end trimming) to compensate for a high-voltage structure with a large temperature drift curvature. Instead, it uses a method of "linearizing the structure first (including the high-voltage floating fully differential operational amplifier of the above-mentioned floating fully differential input stage 10, high-voltage side 20, tail current source 30, temperature tracking bias circuit 40 and floating fully differential output stage 50), algorithm (residual linear temperature drift dual-temperature trimming) and then finishing" to make the dual-temperature calibration mainly deal with the residual offset and the approximately linear temperature drift term.

[0061] like Figure 7As shown, optionally, the dual-temperature calibration system 70 includes an on-chip adjustment interface 701, a comparison decision module 702, a digital search control module 703, and a parameter storage module 704. The dual-temperature calibration system 70 is connected to the internal dual-temperature calibration interface 60 of the high-voltage floating fully differential operational amplifier, and is used to inject compensation current according to the adjustment code given by the on-chip digital search control module 703; the on-chip adjustment interface 701, the comparison decision module 702, the digital search control module 703, and the parameter storage module 704 are used to search for and write the basic offset adjustment parameters and residual temperature drift adjustment parameters in calibration mode.

[0062] Figure 8 This is a schematic diagram illustrating the compensation process for dual-temperature calibration using a high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration procedure, according to an embodiment of the present invention. Figure 8 As shown, exemplarily, the aforementioned high-voltage floating fully differential operational amplifier can be used in conjunction with the on-chip dual-temperature calibration system 70. At the first temperature point T1, the basic offset can be calibrated; at the second temperature point T2, the remaining linear temperature drift can be corrected; the calibration results are written to the parameter storage module 704 and loaded into the operational amplifier bias node or trim node during runtime.

[0063] In order to make g ds The temperature behavior of (T) is smoother and closer to first-order linearity. In some alternative embodiments, the tail current source 30 or the high-voltage side 20 is configured to maintain a predetermined saturation margin within the operating temperature range.

[0064] The predetermined saturation margin can be understood as the margin between the actual drain-source voltage of the relevant MOS device and the minimum drain-source voltage required for it to enter the saturation region, for example, V. DS -V DS,sat Maintain a positive value and not fall below the design lower limit. By avoiding the device entering the linear region or weak saturation state under worst-case process corner, supply voltage, and temperature conditions, the effect of output current and output conductance on temperature-induced V can be reduced. DS The additional sensitivity to change makes g ds The change in (T) is smoother and easier to approximate with a first-order term. The specific value of this saturation margin and the linearization effect should be determined in conjunction with the device model and simulation or test results.

[0065] like Figure 1 or Figure 7As shown, to further ensure that the tail current source 30 can stably cooperate with the internal voltage of the floating fully differential input stage 10 on the high-voltage side 20, in some optional embodiments, the tail current source 30 includes a floating tail current source module 301 and an operational amplifier internal low-dropout regulator 302; the floating tail current source module 301 is connected to the floating fully differential input stage 10, the operational amplifier internal low-dropout regulator 302, the temperature tracking bias circuit 40, and the floating fully differential output stage 50, and the operational amplifier internal low-dropout regulator 302 is connected to the temperature tracking bias circuit 40; wherein, the temperature tracking bias circuit 40 is also used to adjust the voltage according to the node voltage (V c ) generates a second bias voltage (V b2 ) and third bias voltage (V b3 ), and output the aforementioned second bias voltage (V b2 The above-mentioned floating tail current source module 301 and the output of the above-mentioned third bias voltage (V) are connected to the above-mentioned floating tail current source module 301 and the third bias voltage (V) is output. b3 The low-dropout regulator 302 inside the op-amp is used to work with the temperature tracking bias circuit 40 to stabilize the internal voltage of the floating tail current source module 301. The floating tail current source module 301 is used to work with the high-voltage side 20 to stabilize the internal voltage difference of the floating fully differential input stage 10.

[0066] like Figure 1 or Figure 7 As shown, optionally, the floating tail current source module 301 includes an NMOS transistor. The gate of the NMOS transistor is connected to the temperature tracking bias circuit 40, the source of the NMOS transistor is connected to the low-dropout regulator 302 inside the operational amplifier, and the drain of the NMOS transistor is connected to the second terminal of the floating fully differential input stage 10 and the first terminal of the floating fully differential output stage 50, respectively. For example, when the floating fully differential input stage 10 is a PMOS transistor and the floating fully differential output stage 50 is an NMOS transistor, the drain of the NMOS transistor in the floating tail current source module 301 is connected to the drain of the corresponding PMOS transistor in the floating fully differential input stage 10 and the source of the corresponding NMOS transistor in the floating fully differential output stage 50.

[0067] like Figure 1 or Figure 7 As shown, in some optional embodiments, the floating fully differential output stage 50 includes a folded cascode amplifier stage 501, which is connected to the tail current source 30 and the temperature tracking bias circuit 40; wherein the folded cascode amplifier stage 501 is used to bias the tail current source 30 according to the first bias voltage.

[0068] In the above embodiment, by applying a first bias voltage to the common gate transistor connected to it, the common gate transistor determines the voltage magnitude of the input-side tracking node (i.e., the connection node between the floating fully differential input stage 10 and the tail current source 30), thereby causing the V of the related devices of the floating fully differential input stage 10 to... DS It remains essentially unchanged when the temperature changes.

[0069] Specifically, the aforementioned folded common-source common-gate amplifier stage 501 includes a common-gate transistor and a current source device connected to the drain of the common-gate transistor. Optionally, the common-gate transistor is an NMOS transistor.

[0070] like Figure 1 or Figure 7 As shown, in some optional embodiments, in order to output the differential input voltage signal of the floating fully differential input stage, the floating fully differential output stage 50 further includes: a common-mode feedback circuit 502, connected to the folded cascode amplifier stage 501, for receiving the differential output voltage signal (V) output by the folded cascode amplifier stage 501. odiff ), and based on the above differential output voltage signal (V odiff The common-mode level of the output of the aforementioned high-voltage floating fully differential operational amplifier is stabilized; the Class AB output stage 503, connected to the aforementioned folded cascode amplifier stage 501, is used to receive the differential output voltage signal (V) output from the aforementioned folded cascode amplifier stage 501. odiff ), and based on the above differential output voltage signal (V odiff It performs signal power amplification and load driving.

[0071] Understandably, the differential input voltage signal of the floating fully differential input stage is transmitted to the single-ended Class AB output stage via the high-voltage cascade branch and subsequent internal gain path.

[0072] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A high-voltage floating fully differential operational amplifier adapted to a linear dual-temperature calibration process, characterized in that, It includes a floating fully differential input stage, a high-voltage side, a tail current source, a temperature tracking bias circuit, and a floating fully differential output stage; The floating fully differential input stage is connected to the high-voltage side and the tail current source, the floating fully differential output stage is connected to the tail current source and the temperature tracking bias circuit, and there is a cascade node between the floating fully differential input stage and the high-voltage side, and the temperature tracking bias circuit is connected to the cascade node. The temperature tracking bias circuit is used to generate a first bias voltage based on the node voltage at the cascade node and output it to the floating fully differential output stage. The floating fully differential output stage is used to bias the tail current source based on the first bias voltage. The tail current source is used to cooperate with the high-voltage side to stabilize the internal voltage difference of the floating fully differential input stage.

2. The high-voltage floating fully differential operational amplifier according to claim 1, characterized in that, The temperature tracking bias circuit includes a reference voltage generation module and a first bias voltage generation module; The reference voltage generation module is connected to the cascaded node and the first bias voltage generation module, and is used to generate a reference voltage based on the node voltage. The first bias voltage generation module is connected to the floating fully differential output stage and is used to generate the first bias voltage according to the reference voltage.

3. The high-voltage floating fully differential operational amplifier according to claim 2, characterized in that, The reference voltage generation module includes a first MOSFET connected by a diode and a second MOSFET connected by a diode, and the first bias voltage generation module includes a third MOSFET connected by a diode. The first MOSFET is connected to the cascade node and the second MOSFET, and is used to generate a reference common-mode voltage based on the node voltage; The second MOSFET is connected to the third MOSFET and is used to generate the reference voltage based on the reference common-mode voltage; The third MOS transistor is connected to the floating fully differential output stage and is used to generate the first bias voltage according to the reference voltage.

4. The high-voltage floating fully differential operational amplifier according to claim 3, characterized in that, The first MOSFET operates in the deep subthreshold region, the second MOSFET operates at the boundary between the weak inversion region and the strong inversion region, and the third MOSFET operates in the strong inversion region.

5. The high-voltage floating fully differential operational amplifier according to claim 2, characterized in that, The reference voltage generation module includes a fourth MOS transistor connected to a diode, and the first bias voltage generation module includes a fifth MOS transistor connected to a diode. The fourth MOS transistor is connected to the cascade node and the fifth MOS transistor, and is used to generate the reference voltage according to the node voltage; The fifth MOS transistor is connected to the floating fully differential output stage and is used to generate the first bias voltage according to the reference voltage.

6. The high-voltage floating fully differential operational amplifier according to claim 5, characterized in that, The fourth MOSFET is a high-voltage device, and the fifth MOSFET is a low-voltage device. The operating range of the fourth MOSFET is in the shallow subthreshold region, and the operating range of the fifth MOSFET is in the deep subthreshold region.

7. The high-voltage floating fully differential operational amplifier according to any one of claims 1 to 6, characterized in that, The high-voltage floating fully differential operational amplifier also includes a dual-temperature calibration interface, which is connected to a dual-temperature calibration system; wherein, the dual-temperature calibration system is used to perform temperature drift calibration on the high-voltage floating fully differential operational amplifier.

8. The high-voltage floating fully differential operational amplifier according to any one of claims 1 to 6, characterized in that, The tail current source or the high-voltage side is configured to maintain a predetermined saturation margin within the operating temperature range.

9. The high-voltage floating fully differential operational amplifier according to any one of claims 1 to 6, characterized in that, The tail current source includes a floating tail current source module and an operational amplifier internal low dropout regulator. The floating tail current source module is connected to the floating fully differential input stage, the operational amplifier internal low dropout regulator, the temperature tracking bias circuit, and the floating fully differential output stage. The operational amplifier internal low dropout regulator is connected to the temperature tracking bias circuit. The temperature tracking bias circuit is further configured to generate a second bias voltage and a third bias voltage based on the node voltage, and output the second bias voltage to the floating tail current source module and the third bias voltage to the operational amplifier's internal low-dropout regulator. The operational amplifier's internal low-dropout regulator is configured to work with the temperature tracking bias circuit to stabilize the internal voltage of the floating tail current source module. The floating tail current source module is configured to work with the high-voltage side to stabilize the internal voltage difference of the floating fully differential input stage.

10. The high-voltage floating fully differential operational amplifier according to any one of claims 1 to 6, characterized in that, The floating fully differential output stage includes a folded cascode amplifier stage, which is connected to the tail current source and the temperature tracking bias circuit; wherein, the folded cascode amplifier stage is used to bias the tail current source according to the first bias voltage.

11. The high-voltage floating fully differential operational amplifier according to claim 10, characterized in that, The floating fully differential output stage also includes: A common-mode feedback circuit, connected to the folded cascode amplifier stage, is used to receive the differential output voltage signal from the folded cascode amplifier stage and stabilize the output common-mode level of the high-voltage floating fully differential operational amplifier based on the differential output voltage signal. The Class AB output stage is connected to the folded cascode amplifier stage and is used to receive the differential output voltage signal from the folded cascode amplifier stage, and to amplify the signal power and drive the load based on the differential output voltage signal.

Images