A power amplifier circuit applied to a PLL direct modulation type radio frequency transmitting system

Abstract

This invention discloses a power amplifier circuit for a PLL direct modulation RF transmission system, comprising two identical power control systems. Each power control system includes a power transistor module, a carrier signal control module, and a power filter control module. The power transistor module provides power to the entire module, transmitting the baseband signal. The carrier signal control module controls the carrier signal from the PLL divider, performing power distribution; its output is directly used as the input to the power transistor module. The power filter control module generates the common-gate bias voltage of the power transistor module and performs filtering and selection control on this voltage; its output is directly used as the common-gate voltage of the power transistor module, controlling the operating state of the switching power amplifier. This invention not only allows for flexible application in low-power modes but also helps reduce noise caused by output impedance pulling and parasitic capacitance.

Description

Technical Field

[0001] This invention relates to the field of radio frequency transceiver front-end integrated circuit technology, and in particular to a power amplifier circuit applied to a PLL direct modulation type radio frequency transmission system. Background Technology

[0002] The radio frequency (RF) front-end is the core module for wireless communication in mobile terminal devices. Located between the antenna and the RF transceiver, it is responsible for receiving and transmitting wireless information. Transmitting wireless information is a crucial component of the entire RF front-end. The RF front-end performs carrier conversion, power amplification, and filtering on the signal before transmitting it through the antenna. Important performance parameters include spectral purity and transmit power, which requires the power amplifier circuit to avoid introducing excessive spurious signals.

[0003] To improve the anti-interference capability of applications, some frequency-based signal modulation protocols generally do not use low-IF transmission systems to save resources and power consumption. Instead, direct frequency conversion is used. This type of system has a simple structure and usually uses a switching power amplifier (PA) to achieve the required transmission power. However, the switching PA introduces nonlinear effects. A PLL direct modulation RF transmission system refers to directly modulating the RF carrier after digital filtering of the digital baseband signal. This means directly controlling the PLL divider digitally to perform frequency modulation, and the modulated carrier frequency is directly transmitted to the switching power amplifier module. It eliminates the need for a mixer, IF DAC, and IF filter, resulting in higher integration and lower power consumption. However, the PLL divider output frequency is directly connected to the PA. Although the voltage-controlled oscillator (VCO) frequency is different from the carrier frequency, the switching PA causes a sudden change in input impedance during the 0 / 1 switching process, thus pulling the VCO frequency and generating frequency spurious signals. Furthermore, the switching PA itself is nonlinear, and the parasitic capacitance at the output end further exacerbates its own frequency spurious signals. To address the impact of input impedance on the VCO, a power amplifier circuit is proposed, ultimately optimizing carrier frequency spurious signals. Summary of the Invention

[0004] The purpose of this invention is to provide a power amplifier circuit for a PLL direct modulation radio frequency transmission system to solve the problems in the background art.

[0005] To solve the above technical problems, the present invention provides a power amplifier circuit for a PLL direct modulation radio frequency transmission system, including two identical power control systems, each of which includes a power transistor module, a carrier signal control module, and a power filter control module. The power transistor module provides power to the entire module and transmits the baseband signal. The carrier signal control module controls the carrier signal coming from the PLL frequency divider to complete the power distribution function, and its output is directly used as the input of the power tube module. The power filtering control module generates the common-gate bias voltage of the power transistor module and performs filtering and selection control on this voltage. Its output is directly used as the common-gate voltage of the power transistor module to control the working state of the switching power amplifier.

[0006] In one embodiment, the power transistor module is a common source and common gate structure, or other arbitrary switching structure, including common gate transistor M1, common gate transistor M2, common source transistor M3, and common source transistor M4; Common source transistor M4 is the carrier signal switching input transistor, and its gate terminal is connected to the control port ADJ2. ADJ2 is the open-loop control signal for the number of power groups. Common source transistor M2 is the mode control transistor, and its gate terminal is connected to voltage VB. This voltage register is adjustable and determines the maximum power output of the power amplifier. Common source transistor M3 is the common source carrier signal input transistor, and its gate terminal is connected to the signal input port ADJ1. ADJ1 is the logic output of the numerically controlled frequency divider in the carrier signal control module, which is used to reasonably control the relationship between the carrier signal and the number of power groups. Common source transistor M1 is the common source switch transistor, which is closest to the output pin. Its gate terminal is controlled by the enable signal EN and is used to turn the entire power amplifier on and off. Common-gate transistors M1, M2, M3, and M4 are connected in series to form a power amplifier unit. This common-source common-gate structure rationally allocates the type and number of transistors according to the external power supply, inductance, and power requirements. The power units are combined into N groups, with each group having the following order: M*1, M*2, M*4, M*8…M* The number of units enables N-bit power adjustment.

[0007] The power amplifier circuit for a PLL direct modulation RF transmission system as described in claim 2 is characterized in that the gate terminal of the common source transistor M4 is connected to a capacitor to ground, which corresponds to C*1, C*2, C*4, C*8…C* according to the grouping method of the power transistors. The filter capacitance value is used to filter out the influence of switch switching on the input signal.

[0008] In one embodiment, the carrier signal control module includes a linear regulator, a carrier digital control circuit, and a power transistor allocation logic module; The linear regulator generates a stable power signal to the power transistor distribution logic module, which is used to isolate the carrier signal of the digitally controlled frequency divider and the power amplifier unit, and reduce the pull of the power amplifier input impedance change on the voltage-controlled oscillator frequency. The carrier digital logic control module is used to encode the carrier, configure the maximum power of the power amplifier, configure the power step size, and configure the time of each power step. Its function is to ensure that the power amplifier's switching transistors are at minimum bias voltage VB before and after the power amplifier officially starts operating. The number of steps slowly turns the pre-selected power groups on or off between the set maximum and minimum power, reducing the pull of the power amplifier input impedance change on the voltage-controlled oscillator frequency; The digital frequency divider in the carrier digital logic control module outputs the encoded carrier signal SIGNAL, which is coupled to a power transistor distribution logic module with independent power isolation via a capacitor AC. After being shaped and amplified by a buffer amplifier, the signal is ANDed with the power amplifier master enable signal EN using logic A1, splitting it into two paths. These paths are then XORed with the phase control signal PHASE_CTR to output the carrier signals for two power amplifiers. When the phase control signal PHASE_CTR is logic 0, the two power amplifiers are superimposed, and the power adjustment is at its maximum. When the phase control signal PHASE_CTR is logic 1, the two power amplifiers are subtracted, and the power adjustment is at its minimum. The carrier signals controlled by the phase signal are then further subdivided by relevant logic to determine the number of power transistor groups, M*1, M*2, M*4, M*8…M* The number of power transistor groups can be arbitrarily ORed or combined; the power group number register ADJ <n:0>The two sets of power amplifier enable signals EN_PA0 and EN_PA1 are respectively processed through a BUF to generate two sets of switch control signals ADJ2. <n:0>_PA0、ADJ2 <n:0>_PA1 reduces the impact of drain-source parasitic capacitance and gate-drain parasitic capacitance on the output power signal, and reduces spurious signals at the carrier frequency.

[0009] In one embodiment, the power filtering control module includes a VB voltage generation module, a decoder, a filtering control module, and a power bias register logic module. The VB voltage generation module generates the common-gate bias voltage of the power transistor, changing the operating state of the power transistor. It is grouped and mirrored through a current mirror branch I1, forming a total output current I2 in the form of current rudders, which in turn form voltage VB under the action of the output resistor. The grouping of the mirrored current rudders is as follows: I0 is a normally open current branch, the other current branches are controlled by the power control register, and there are -1 groups of branches I*1, I*2, and I*4. Among them, I*1 and I*2 are controlled by the lower two bits of the power control register, and the remaining -1 group of current branches are controlled by the higher three bits of the power control register, forming a variety of power voltages to control the operating state and power of the power transistor. The decoder provides corresponding control words to the VB voltage generation module and the filter control module to adjust the VB voltage and filter frequency. The N0 bit power control register separates high-order and low-order control. The high-order control POW_H register uses temperature decoding to output POW_H<-1:0>, and the low-order control register POW_L uses normal binary decoding to output POW_L<1:0>. Temperature decoding ensures that the current steering remains smooth during switching, preventing unnecessary spurious noise in the output power. Binary decoding effectively reduces resource overhead. The filter selection control register LPF_SEL<2:0> uses temperature decoding to output LPF_SEL<7:0>, which is used to select a suitable filter resistor. The filtering control module mainly consists of an RC low-pass filter and a selector. The RC low-pass filter is used to filter out power spurious signals coupled into the VB voltage by the output power through its own capacitance, thus maintaining the stability of the output power. The fixed capacitor C is selected according to the actual frequency point and placed close to the power transistor. The resistors R are divided into R, R, 2R, 4R, 8R...64R from the position close to the gate of the power transistor. The VB voltage is connected to the left end of the 64R resistor. The other resistor terminals OUT7~OUT0 are used as the input terminals of the selector and are selected to be connected to the voltage VB under the control of the register LPF_SEL<7:0>, forming a resistor short circuit and changing the filtering frequency of the filter. The power bias register control logic module is used to control the bias voltage register POW according to state requirements. <n0:0>The register's default value is 0, at which point the VB voltage is at its minimum, and the power transistor is in a slightly enabled state. When the power amplifier is operating normally, the POW... <n0:0>In the =0 state, carrier digital logic control is performed to sequentially turn on the power switching transistors; when the power amplifier is working normally, in POW... <n0:0>In the =0 state, carrier digital logic control is performed, sequentially turning off the power switching transistors. When the carrier signal sends a normal code value information 1, the bias voltage register will gradually increase from 0 to its maximum value. At this time, the VB voltage reaches its maximum, the power reaches its maximum, and the code value information 1 is sent normally. After maintaining this for one code value cycle, the bias voltage register will gradually decrease from its maximum value to its minimum value of 0 and maintain this value until the next code value information 1 is sent. This power bias register control logic module will reasonably set the time of power code value change according to the frequency and application.

[0010] The present invention provides a power amplifier circuit for a PLL direct modulation radio frequency transmission system. The entire power amplifier circuit includes two identical power control systems (the grouping method can be arbitrary). This is because dividing the power transistors into two groups of controls not only allows for flexible application in low-power mode, but also helps to reduce noise caused by output impedance pull and parasitic capacitance. Attached Figure Description

[0011] Figure 1 This is a functional block diagram of a power amplifier circuit for a PLL direct modulation RF transmission system provided by the present invention. Figure 2 This is a schematic diagram of the power transistor module; Figure 3 This is a schematic diagram of the carrier signal control module; Figure 4 This is a schematic diagram of the power filtering control module. Detailed Implementation

[0012] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a power amplifier circuit for a PLL direct modulation RF transmission system based on the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0013] This invention provides a power amplifier circuit for a PLL direct modulation RF transmission system. The entire power amplifier circuit comprises two identical power control systems (the grouping method can be arbitrary). This is because dividing the power transistors into two control groups not only allows for flexible application in low-power modes but also helps reduce noise caused by output impedance pulling and parasitic capacitance. Each power control system includes: The power transistor module is the core of the entire power control system, used to provide power to the entire module and transmit baseband signals. The carrier signal control module is used to control the carrier signal coming from the PLL divider to complete the power distribution function. Its output is directly used as the input of the power transistor module. The power filtering control module is mainly used to generate the common gate bias voltage of the power transistor module and to filter and select this voltage. Its output is directly used as the common gate voltage of the power transistor module to control the working state of the switching power amplifier.

[0014] The structure of the power transistor module is as follows: Figure 2 The cascode structure shown, or any other switching structure, uses cascode transistor M4 as the carrier signal input transistor, with its gate connected to control port ADJ2. ADJ2 is the open-loop control signal for the number of power groups. Cascode transistor M2 is the mode control transistor for this switching power amplifier, with its gate connected to voltage VB. This voltage register is adjustable and determines the maximum power the power amplifier can transmit. M3 is the common-source carrier signal input transistor for this power amplifier, with its gate connected to signal input port ADJ1. ADJ1 is the logic output of the digitally controlled frequency divider in the carrier signal control module, used to rationally control the relationship between the carrier signal and the number of power groups. M1 is the common-gate switch transistor for this power amplifier, closest to the output pin, with its gate controlled by the enable signal EN, used to turn the entire PA module off and on. M1, M2, M3, and M4 are connected in series to form a power unit of the PA. This cascode structure rationally allocates the type and number of transistors according to the external power supply, inductance, and power level (the power unit can be any type and any number of transistors stacked together). The power units are combined into N groups, with each group having the following order: M*1, M*2, M*4, M*8…M* The number of units enables N-bit power adjustment, and the typical power step can be set to 1dB (the number of units and groups is selected based on the power level). Therefore, by grouping the power transistors, the carrier signal control module can sequentially turn on the power switching transistors in groups, achieving a gradual increase in power and reducing the noise impact of drastic power changes on the PA; furthermore, the PA's input impedance will also switch gradually, weakening the frequency pulling effect on the voltage-controlled oscillator. To further reduce the impact of gate-source and gate-drain parasitic capacitances, the gate terminal of the common-source transistor M4 is connected to a capacitor to ground, which corresponds to C*1, C*2, C*4, C*8…C* according to the power transistor grouping method. The filter capacitance value is used to filter out the influence of switch switching on the input signal.

[0015] like Figure 3 As shown, the carrier signal control module includes a linear regulator, a carrier digital control circuit, and a power transistor distribution logic module. The linear regulator generates a stable power signal for the power transistor distribution logic module, primarily used to isolate the carrier signal from the digitally controlled frequency divider and the PA power module, reducing the impact of PA input impedance variations on the voltage-controlled oscillator frequency. The carrier digital logic control module is mainly used to encode the carrier, configure the PA's maximum power, configure the power step size, and configure the time of each power step. Its function is to ensure that the PA's switching transistors are at minimum bias voltage VB before and after the PA officially starts operating. The number of steps gradually turns the pre-selected power groups on or off between the set maximum and minimum power, reducing the pull of the PA input impedance change on the voltage-controlled oscillator frequency.

[0016] The digitally controlled frequency divider in the carrier digital logic control module outputs the encoded carrier signal SIGNAL. This signal is coupled via a capacitor AC to a power transistor distribution logic module with independent power supply isolation. After being shaped and amplified by a buffer amplifier, it is ANDed with the PA total enable signal EN using logic A1, splitting into two paths. These paths are then XORed with the phase control signal PHASE_CTR to output two sets of PA carrier signals. When PHASE_CTR is logic 0, the two PA sets are superimposed, and the power is adjustable to the maximum. When PHASE_CTR is logic 1, the two PA sets are subtracted, and the power is adjustable to the minimum. Finally, the carrier signals controlled by the phase signals are further subdivided by relevant logic to determine the number of power transistor groups, resulting in M*1, M*2, M*4, M*8…M* The number of power transistor groups can be arbitrarily ORed and combined (mainly allocated according to the application scenario and power level). In this embodiment, it is divided into M groups, and the output signal is ADJ1. Reducing the number of channels occupied by the carrier signal can effectively isolate crosstalk between carrier signals and reduce spurious signals at the carrier frequency. The power group number register ADJ... <n:0>The two PA enable signals EN_PA0 and EN_PA1 are respectively processed through a BUF to generate two sets of switch control signals ADJ2. <n:0>_PA0、ADJ2 <n:0>_PA1 reduces the impact of drain-source parasitic capacitance and gate-drain parasitic capacitance on the output power signal, and reduces spurious signals at the carrier frequency.

[0017] like Figure 4 As shown, the power filtering control module includes a VB voltage generation module, a decoder, a filtering control module, and a power bias register logic module. The VB voltage generation module is mainly used to generate the common-gate bias voltage of the power transistor, changing its operating state. It uses a current mirror branch I1 to group and mirror the currents, forming a total output current I2 in the form of current rudders, which, under the action of the output resistor, forms the voltage VB. The grouping of the mirrored current rudders is as follows: I0 is a normally open current branch, the other current branches are controlled by the power control register, and branches I*1, I*2, and I*4 share... -1 group; where I*1 and I*2 are controlled by the lower two bits of the power control register, and the rest... -1 group of current branches is controlled by the high three bits of the power control register, forming a total of A power voltage is used to control the operating state and power of the power transistor.

[0018] The decoder provides corresponding control words to the VB voltage generation module and the filter control module respectively, adjusting the VB voltage and the filter frequency. The N0 bit power control register separates high-order and low-order control; the high-order control POW_H register uses temperature decoding to output POW_H< -1:0>, the low-level control register POW_L normally decodes the output POW_L<1:0> (2 bits are selected here, but any number of bits can be used). Temperature decoding ensures smooth switching of the current steering mechanism, preventing unnecessary spurious emissions into the output power, while binary decoding effectively reduces resource overhead. The filter selection control register LPF_SEL<2:0> uses temperature-decoded output LPF_SEL<7:0> to select a suitable filter resistor.

[0019] The filter control module mainly consists of an optional RC low-pass filter and a selector. The RC low-pass filter is used to filter out power spurious signals coupled into the VB voltage by the output power through its own capacitance, thereby maintaining stable output power. C is a fixed capacitor, selected according to the actual frequency point, and placed close to the power transistor. R is usually classified as R, R, 2R, 4R, 8R...64R from the position closest to the power transistor gate. The VB voltage is connected to the left end of the 64R resistor. The other resistor terminals OUT7~OUT0 are used as input terminals of the selector and are selected to be connected to the voltage VB under the control of the register LPF_SEL<7:0>, forming a resistor short circuit and changing the filter frequency.

[0020] The power bias register control logic module is used to control the bias voltage register POW according to state requirements. <n0:0>The change. The default value of this register is 0, at which time the VB voltage is at its minimum, the power transistor is in a slightly turned-on state, and there is basically no output power. When the PA is working normally, in the POW... <n0:0>In the =0 state, carrier digital logic control is performed to sequentially turn on the power switching transistors; when PA is working normally, in POW <n0:0>In the =0 state, carrier digital logic control is performed, sequentially turning off the power switches. When the carrier signal sends the normal code value information 1, the bias voltage register will gradually increase from 0 to its maximum value. At this point, the VB voltage reaches its maximum, the power reaches its maximum, and the code value information 1 is transmitted normally. After maintaining this position for one code value period, the bias voltage register will start from its maximum value. The value is gradually reduced to a minimum of 0 and held until the next code value of 1 is sent. This power bias register control logic module appropriately sets the timing of power code value changes based on the frequency and application. Under the control of this module, the power amplifier not only isolates the frequency pulling effect caused by input impedance changes but also reduces the power pulling effect of its own output impedance and parasitic capacitance.

[0021] The power amplifier circuit provided by this invention is applied to a PLL direct modulation type radio frequency transmission system. The entire power amplifier circuit contains two identical power control systems (the grouping method can include any form). This is because dividing the power transistors into two groups of controls not only allows for flexible application in low-power mode, but also helps to reduce noise caused by output impedance pulling and parasitic capacitance.

[0022] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. For example, the number of groups in the entire power amplifier circuit can be further increased, the power units can be stacked with any type and any number of transistors, the number of power allocation groups can be selected according to the power level, the logical combination of the number of power transistor groups and the carrier input signal can also be arbitrarily allocated according to the application scenario and power level, and the number of bits and the decoding method of the power control register can be arbitrarily selected according to the application. Any changes or modifications made by those skilled in the art based on the above disclosure are within the scope of protection of the claims.

Claims

1. A power amplifier circuit for a PLL direct modulation type radio frequency transmission system, characterized in that, It includes two identical power control systems, each of which contains a power transistor module, a carrier signal control module, and a power filter control module. The power transistor module provides power to the entire module and transmits the baseband signal. The carrier signal control module controls the carrier signal coming from the PLL frequency divider to complete the power distribution function, and its output is directly used as the input of the power tube module. The power filtering control module generates the common-gate bias voltage of the power transistor module and performs filtering and selection control on this voltage. Its output is directly used as the common-gate voltage of the power transistor module to control the working state of the switching power amplifier.

2. The power amplifier circuit for a PLL direct modulation type RF transmission system as described in claim 1, characterized in that, The power transistor module is a common source and common gate structure, or other arbitrary switching structure, including common gate transistor M1, common gate transistor M2, common source transistor M3, and common source transistor M4; Common source transistor M4 is the carrier signal switching input transistor, and its gate terminal is connected to the control port ADJ2. ADJ2 is the open-loop control signal for the number of power groups. Common source transistor M2 is the mode control transistor, and its gate terminal is connected to voltage VB. This voltage register is adjustable and determines the maximum power output of the power amplifier. Common source transistor M3 is the common source carrier signal input transistor, and its gate terminal is connected to the signal input port ADJ1. ADJ1 is the logic output of the numerically controlled frequency divider in the carrier signal control module, which is used to reasonably control the relationship between the carrier signal and the number of power groups. Common source transistor M1 is the common source switch transistor, which is closest to the output pin. Its gate terminal is controlled by the enable signal EN, which is used to turn the entire power amplifier module off and on. Common-gate transistors M1, M2, M3, and M4 are connected in series to form a power amplifier unit. This common-source common-gate structure rationally allocates the type and number of transistors according to the external power supply, inductance, and power requirements. The power units are combined into N groups, with each group having the following order: M*1, M*2, M*4, M*8…M* The number of units enables N-bit power regulation.

3. The power amplifier circuit for a PLL direct modulation RF transmission system as described in claim 2, characterized in that, The gate terminal of the common-source transistor M4 is connected to a capacitor to ground, which corresponds to C*1, C*2, C*4, C*8…C* according to the grouping method of the power transistors. The filter capacitance value is used to filter out the influence of switch switching on the input signal.

4. The power amplifier circuit for a PLL direct modulation type RF transmission system as described in claim 1, characterized in that, The carrier signal control module includes a linear regulator, a carrier digital control circuit, and a power transistor allocation logic module. The linear regulator generates a stable power signal to the power transistor distribution logic module, which is used to isolate the carrier signal of the digitally controlled frequency divider and the power amplifier unit, and reduce the pull of the power amplifier input impedance change on the voltage-controlled oscillator frequency. The carrier digital logic control module is used to encode the carrier, configure the maximum power of the power amplifier, configure the power step size, and configure the time of each power step. Its function is to ensure that the power amplifier's switching transistors are at minimum bias voltage VB before and after the power amplifier officially starts operating. The number of steps slowly turns the pre-selected power groups on or off between the set maximum and minimum power, reducing the pull of the power amplifier input impedance change on the voltage-controlled oscillator frequency; The digital frequency divider in the carrier digital logic control module outputs the encoded carrier signal SIGNAL, which is coupled to a power transistor distribution logic module with independent power isolation via a capacitor AC. After being shaped and amplified by a buffer amplifier, the signal is ANDed with the power amplifier master enable signal EN using logic A1, splitting it into two paths. These paths are then XORed with the phase control signal PHASE_CTR to output the carrier signals for two power amplifiers. When the phase control signal PHASE_CTR is logic 0, the two power amplifiers are superimposed, and the power adjustment is at its maximum. When the phase control signal PHASE_CTR is logic 1, the two power amplifiers are subtracted, and the power adjustment is at its minimum. The carrier signals controlled by the phase signal are then further subdivided by relevant logic to determine the number of power transistor groups, M*1, M*2, M*4, M*8…M* The number of power transistor groups can be arbitrarily ORed or combined; the power group number register ADJ <n:0>The two sets of power amplifier enable signals EN_PA0 and EN_PA1 are respectively processed through a BUF to generate two sets of switch control signals ADJ2. <n:0>_PA0、ADJ2 <n:0> _PA1 reduces the impact of drain-source parasitic capacitance and gate-drain parasitic capacitance on the output power signal, and reduces spurious signals at the carrier frequency.

5. The power amplifier circuit for a PLL direct modulation RF transmission system as described in claim 1, characterized in that, The power filtering control module includes a VB voltage generation module, a decoder, a filtering control module, and a power bias register logic module. The VB voltage generation module generates the common gate bias voltage of the power transistor, thereby changing the operating state of the power transistor. It is grouped and mirrored through a current mirror branch I1, forming a total output current I2 in the form of a current rudder, and forming a voltage VB under the action of the output resistor; The mirror current rudders are grouped as follows: I0 is the normally open current branch, the other current branches are controlled by the power control register, and branches I*1, I*2, and I*4 are shared. -1 group; I*1 and I*2 are controlled by the lower two bits of the power control register, while the remaining bits are controlled by the lower two bits of the power control register. -1 current branch is controlled by the high three bits of the power control register, forming a variety of power voltages to control the operating state and power of the power transistor; The decoder provides corresponding control words to the VB voltage generation module and the filter control module to adjust the VB voltage and filter frequency. The N0 bit power control register separates high-order and low-order control. The high-order control POW_H register uses temperature decoding to output POW_H<-1:0>, and the low-order control register POW_L uses normal binary decoding to output POW_L<1:0>. Temperature decoding ensures that the current steering remains smooth during switching, preventing unnecessary spurious noise in the output power. Binary decoding effectively reduces resource overhead. The filter selection control register LPF_SEL<2:0> uses temperature decoding to output LPF_SEL<7:0>, which is used to select a suitable filter resistor. The filtering control module mainly consists of an RC low-pass filter and a selector. The RC low-pass filter is used to filter out power spurious signals coupled into the VB voltage by the output power through its own capacitance, thus maintaining the stability of the output power. The fixed capacitor C is selected according to the actual frequency point and placed close to the power transistor. The resistors R are divided into R, R, 2R, 4R, 8R...64R from the position close to the gate of the power transistor. The VB voltage is connected to the left end of the 64R resistor. The other resistor terminals OUT7~OUT0 are used as the input terminals of the selector and are selected to be connected to the voltage VB under the control of the register LPF_SEL<7:0>, forming a resistor short circuit and changing the filtering frequency of the filter. The power bias register control logic module is used to control the bias voltage register POW according to state requirements. <n0:0>The register's default value is 0, at which point the VB voltage is at its minimum, and the power transistor is in a slightly enabled state. When the power amplifier is operating normally, the POW... <n0:0>In the =0 state, carrier digital logic control is performed to sequentially turn on the power switching transistors; when the power amplifier is working normally, in POW... <n0:0> In the =0 state, carrier digital logic control is performed, sequentially turning off the power switching transistors. When the carrier signal sends a normal code value information 1, the bias voltage register will gradually increase from 0 to its maximum value. At this time, the VB voltage reaches its maximum, the power reaches its maximum, and the code value information 1 is sent normally. After maintaining this for one code value cycle, the bias voltage register will gradually decrease from its maximum value to its minimum value of 0 and maintain this value until the next code value information 1 is sent. This power bias register control logic module will reasonably set the time of power code value change according to the frequency and application.< / n0:0>

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