Multi-gain mode filter with improved linearity

Abstract

This disclosure relates to a multi-gain mode filter with improved linearity. A wireless circuit is provided, including multiple receive paths and filter circuitry configured to receive signals from the multiple receive paths. The filter circuitry may include a transconductance circuit. The transconductance circuit may include a pull-down transistor having two or more different threshold voltages. The transconductance circuit may also include a pull-up transistor having two or more different threshold voltages. Programmable current sources and programmable resistors may be coupled to the source terminals of the pull-down and pull-up transistors and can be selectively tuned depending on whether the transconductance circuit operates in a first gain mode or a second gain mode. The pull-down and pull-up transistors may have adjustable driveability.

Description

[0001] This application claims priority to U.S. Patent Application No. 19 / 177,176, filed April 11, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates in general to electronic devices, and more specifically to electronic devices having wireless communication circuitry. Background Technology

[0003] Electronic devices may possess wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuitry, which includes one or more antennas. The wireless transceiver circuitry within the wireless communication circuitry uses the antennas to transmit and receive radio frequency signals.

[0004] The receiver in a transceiver circuit may include a baseband filter. The baseband filter may include a transconductance unit configured to provide high input impedance to avoid loading the preceding stage. Designing a transconductance unit with stable linearity for the receiver can be challenging. Summary of the Invention

[0005] One aspect of this disclosure provides a wireless receiver including multiple reception paths and a filter circuit configured to receive signals from the multiple reception paths. The filter circuit includes a transconductance circuit. The transconductance circuit includes: a first pull-down transistor having a first threshold voltage; and a second pull-down transistor coupled in parallel with the first pull-down transistor and having a second threshold voltage different from the first threshold voltage. The transconductance circuit may further include a third pull-down transistor coupled in parallel with the first and second pull-down transistors and having a third threshold voltage different from the first and second threshold voltages, wherein the first, second, and third pull-down transistors have gate terminals coupled to a first input terminal of the transconductance circuit.

[0006] The transconductance circuit may further include: a fourth pull-down transistor having the first threshold voltage; a fifth pull-down transistor coupled in parallel with the fourth pull-down transistor and having the second threshold voltage; and a sixth pull-down transistor coupled in parallel with the fourth and fifth pull-down transistors and having the third threshold voltage, wherein the fourth, fifth, and sixth pull-down transistors have gate terminals coupled to a second input terminal different from the first input terminal of the transconductance circuit. The transconductance circuit may further include: a first programmable current source coupled to the source terminals of the first, second, and third pull-down transistors; and a second programmable current source coupled to the source terminals of the fourth, fifth, and sixth pull-down transistors. The transconducting circuit may further include: a first programmable resistor having a first terminal coupled to the first programmable current source and a second terminal coupled to the node; a second programmable resistor having a first terminal coupled to the second programmable current source and a second terminal coupled to the node; and a third programmable current source coupled to the node.

[0007] One aspect of this disclosure provides a transconductance circuit comprising: a first pull-up transistor having a source terminal, a drain terminal coupled to a first output terminal, and a gate terminal configured to receive an input signal, wherein the first pull-up transistor has a first threshold voltage; a second pull-up transistor having a source terminal shorted to the source terminal of the first pull-up transistor, a drain terminal shorted to the drain terminal of the first pull-up transistor, and a gate terminal configured to receive the input signal, wherein the second pull-up transistor has a second threshold voltage different from the first threshold voltage; and a first programmable current source having a first terminal coupled to the source terminals of the first and second pull-up transistors and a second terminal coupled to a positive power supply line. The transconductance circuit may further include a third pull-up transistor having a source terminal shorted to the source terminal of the first pull-up transistor, a drain terminal shorted to the drain terminal of the first pull-up transistor, and a gate terminal configured to receive the input signal, wherein the third pull-up transistor has a third threshold voltage different from the first threshold voltage and the second threshold voltage.

[0008] One aspect of this disclosure provides a transconductance circuit comprising: a first programmable pull-down switch having a gate terminal configured to receive an input signal, wherein the first programmable pull-down switch has a first threshold voltage and is adjusted to provide a first drive strength; and a second programmable pull-down switch coupled in parallel with the first programmable pull-down switch and having a gate terminal configured to receive the input signal, wherein the second programmable pull-down switch has a second threshold voltage different from the first threshold voltage and is adjusted to provide a second drive strength different from the first drive strength, wherein the transconductance circuit has linearity optimized based on the first drive strength and the second drive strength. The transconductance circuit may further include a third programmable pull-down switch coupled in parallel with the first programmable pull-down switch and having a gate terminal configured to receive the input signal, wherein the third programmable pull-down switch has a third threshold voltage different from the first threshold voltage and the second threshold voltage and is adjusted to provide a third drive strength different from the first drive strength to optimize the linearity of the transconductance circuit.

[0009] The transconducting circuit may further include a programmable current source having a first terminal coupled to the source terminals of the first and second programmable pull-down switches and a second terminal coupled to a ground line, wherein the programmable current source is activated during a first gain mode and deactivated during a second gain mode. The transconducting circuit may also include a programmable source degradation resistor directly coupled to the source terminals of the first and second programmable pull-down switches, wherein the programmable source degradation resistor is adjusted to provide a first resistance during the first gain mode and a second resistance less than the first resistance during the second gain mode. Attached Figure Description

[0010] Figure 1 These are illustrations of exemplary electronic devices with wireless circuitry according to some implementation schemes.

[0011] Figure 2 It is a diagram of an exemplary wireless circuit having one or more transceivers according to some implementation schemes.

[0012] Figure 3 This is a diagram illustrating an exemplary continuous-time filter circuit based on some implementation schemes.

[0013] Figure 4 This is a diagram illustrating an exemplary discrete-time filter circuit based on some implementation schemes.

[0014] Figure 5 It is a circuit diagram of an exemplary transconductance circuit based on some implementation schemes.

[0015] Figure 6 This illustrates, according to some implementation schemes, for at least Figures 3 to 5 Diagrams illustrating at least two different operating modes of the transconductance circuit of the type shown.

[0016] Figure 7 It is a graph of transconductance (Gm) as a function of input voltage (Vin) for various transconductance circuits with different transistor threshold voltages according to some implementation schemes.

[0017] Figure 8 It is a graph of the third-order transconductance (Gm3) of various combinations of transistor threshold voltages with equal weights according to some implementation schemes, as a function of transistor gate-to-source voltage (Vgs).

[0018] Figure 9 It is a graph of the third-order transconductance (Gm3) of various combinations of transistor threshold voltages with different weights according to some implementation schemes, as a function of transistor gate-to-source voltage (Vgs).

[0019] Figure 10 It is a circuit diagram of an adjustable pull-up switch based on some implementation schemes.

[0020] Figure 11 It is a circuit diagram of an adjustable pull-down switch based on some implementation schemes. Detailed Implementation

[0021] Electronic devices such as Figure 1 The device 10 may be equipped with wireless circuitry. The wireless circuitry may include receivers configured to combine multiple receive (RX) chains. Such receivers may include baseband filters with high linearity requirements. The baseband filter may be a continuous-time filter or a discrete-time filter. The baseband filter may include transconductance circuitry configured to serve as the input stage of the filter. The overall linearity of the baseband filter is governed by the linearity of the input transconductance circuitry.

[0022] According to one embodiment, the transconductance circuit may include multiple pull-down switches and multiple pull-up switches coupled between a programmable current source and a programmable source degradation resistor. The pull-down switches may include n-type transistors with different threshold voltage levels. The pull-up switches may include p-type transistors with different threshold voltage levels. The pull-up and pull-down transistors may have adjustable drive strength. The pull-up transistors, pull-down transistors, programmable current source, and programmable source degradation transistors may be selectively tuned (adjusted) depending on whether the transconductance circuit operates in low-gain or high-gain mode. Baseband filters configured and operated in this manner are technically advantageous and beneficial for providing improved linearity and noise figure across different gain modes and over PVT (process, voltage, temperature) variations.

[0023] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a pendant device, a headset or earpiece, a device embedded in glasses or worn on a user's head, or other wearable or micro-devices, a television set, a computer monitor not containing an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in an information kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0024] like Figure 1 As shown in the functional block diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some embodiments, part or all of housing 12 may be formed of a dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, housing 12 or at least some of the structures constituting housing 12 may be formed of metallic elements.

[0025] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices integrated within device 10, and / or removable storage media.

[0026] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0027] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as Wi-Fi). ® Protocols used for other short-range wireless communication links, such as Bluetooth. ®This includes protocols such as other Wireless Personal Area Network (WPAN) protocols, IEEE 802.11ad protocols (e.g., Ultra Wideband protocols), cellular phone protocols (e.g., 3G, 4G (LTE), 5G, etc.), sixth-generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., Radio Detection and Ranging (RADAR) protocols or other desired distance detection protocols for signals transmitted at millimeter-wave and centimeter-wave frequencies), or any other desired communication protocol. Each communication protocol may be associated with a corresponding Radio Access Technology (RAT), which specifies the physical connection method used to implement the protocol.

[0028] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays (e.g., touch-sensitive displays and / or force-sensitive displays), light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses for detecting motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as touchpads, mice and joysticks, and other input-output devices may be coupled to device 10 via wired or wireless connections (e.g., some of the input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0029] Input-output circuitry 20 may include wireless circuitry 24 to support or perform radio frequency (RF) signal transmission and / or reception of device 10. Wireless circuitry 24 may be used for wireless communication. Wireless communication performed by wireless circuitry 24 may include or involve wireless data communication (e.g., where wireless data is carried by RF signals transmitted bidirectionally or unidirectionally between wireless circuitry 24 and other communication equipment), RF signal transmission, RF signal reception, and / or radio-based spatial ranging / sensing (e.g., radio detection and ranging (radar) operation, short-range object detection such as object detection based on near-field RF signals, etc.). RF signals transmitted by wireless circuitry 24 may include or carry wireless data (e.g., organized into frames, packets, symbols, datagrams, etc.), radar or other spatial ranging waveforms, continuous wave signals, chirped signals, control signals, management signals, reference signals, beacon signals, tones, impulses, waveforms associated with one or more communication protocols, and / or any other RF waveforms or signals.

[0030] Therefore, wireless circuit 24 is sometimes referred to herein as wireless communication circuit 24, communication circuit 24, or simply circuit 24. Wireless circuit 24 may include one or more antennas. Wireless circuit 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, and / or any other circuitry for transmitting and / or receiving RF signals using antennas. Some or all components of wireless circuit 24 may be disposed on the same substrate (e.g., printed circuit board, semiconductor substrate, chip, integrated circuit (IC), IC package, etc.), mounted to the same substrate, communicatively coupled to the same substrate, and / or integrated within the same substrate, or may be distributed between two or more substrates (e.g., printed circuit board, semiconductor substrate, chip, IC, IC package, etc.).

[0031] Wireless circuit 24 can transmit and / or receive radio frequency signals within the corresponding frequency band of a radio frequency (sometimes referred to herein as a communication band or simply a "band"). The frequency band handled by wireless circuit 24 may include wireless local area network (WLAN) bands (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz) and / or other Wi-Fi ® Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) bands, such as 2.4GHz Bluetooth. ®Frequency bands or other WPAN communication bands; cellular phone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc., 6G bands between 100 GHz and 1000 GHz (e.g., sub-THz bands, THz bands, EHF bands, or THF bands) etc.); other centimeter or millimeter wave bands between 10 GHz and 300 GHz; near-field communication bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); in IEEE Ultra-wideband (UWB) bands operating under the 802.15.4 protocol and / or other ultra-wideband communication protocols; communication bands under the 3GPP wireless communication standard family; communication bands under the IEEE 802.XX standard family; and / or any other desired bands of interest.

[0032] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. For example... Figure 2 As shown, wireless circuitry 24 may include processing circuitry such as processing circuitry 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processing circuitry 26 may be a baseband processor, application processor, general-purpose processor, microprocessor, microcontroller, digital signal processor, host processor, dedicated signal processing hardware, or other type of processor. Processing circuitry 26 may be coupled to transceiver 28 via path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be disposed on RF transmission line path 36 between transceiver 28 and antenna 42.

[0033] exist Figure 2In the example, for clarity, wireless circuit 24 is illustrated as including only a single processing unit 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processing units 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processing unit 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry 30 configured to output uplink signals to antenna 42, may include receiver circuitry 32 configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmission line path 36. If desired, one or more RF transmission line paths 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0034] The RF transmit line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmit line path 36 may have a positive transmit line signal path coupled to the positive antenna feed terminal on the antenna 42. The RF transmit line path 36 may also have a ground transmit line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmit line paths 36.

[0035] RF transmission path 36 may include a means for communication with device 10 ( Figure 1 The transmitting lines in device 10 route the radio frequency antenna signals within the device. The transmitting lines in device 10 may include coaxial cables, microstrip transmitting lines, stripline transmitting lines, edge-coupled microstrip transmitting lines, edge-coupled stripline transmitting lines, and transmitting lines formed by combinations of these types of transmitting lines. The transmitting lines in device 10 (such as the transmitting lines in radio frequency transmitting line path 36) may be integrated into rigid and / or flexible printed circuit boards.

[0036] During wireless transmission, processing circuitry 26 can provide a transmission signal (e.g., a digital signal or a baseband signal) to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting the transmission (baseband) signal received from processing circuitry 26 into a corresponding radio frequency (RF) signal. For example, transceiver circuitry 28 may include mixer circuitry for up-converting (or modulating) the transmission (baseband) signal to RF before transmission via antenna 42. The processing circuitry 26 communicates with transceiver 28. Figure 2 The examples provided are merely illustrative. Generally, transceiver 28 can communicate with a baseband processor, application processor, general-purpose processor, microcontroller, microprocessor, or one or more processors within circuit 18. Transceiver circuit 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 can transmit radio frequency (RF) signals via transmitter (TX) 30 through RF transmission line path 36 and front-end module 40 via antenna 42. Antenna 42 can transmit the RF signal to external wireless equipment by radiating it into free space.

[0037] During wireless reception, antenna 42 can receive radio frequency (RF) signals from external wireless equipment. The received RF signals can be transmitted to transceiver 28 via RF transmission path 36 and front-end module 40. Transceiver 28 may include circuitry, such as receiver (RX) 32, for receiving signals from front-end module 40 and for converting the received RF signals into corresponding baseband signals. For example, transceiver 28 may include mixer circuitry for down-converting (or demodulating) the received RF signals to baseband frequencies before transmitting the received signals via path 34 to processing circuitry 26.

[0038] Front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) via radio frequency transmit line path 36. For example, FEM 40 may include front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifier circuitry 50 and / or one or more low-noise amplifier circuitry 52), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 with the impedance of radio frequency transmit line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each front-end module component in the front-end module assembly can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip. If desired, amplifier circuit 48 and / or other components in front-end 40 (such as filter circuit 44) can also be implemented as part of transceiver circuit 28.

[0039] Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuitry 14) to regulate the frequency response and wireless performance of antenna 42 over time.

[0040] The transceiver 28 may be separate from the front-end module 40. For example, the transceiver 28 may be formed on another substrate such as the main logic board of device 10, a rigid printed circuit board, or a flexible printed circuit that is not part of the front-end module 40. Although for clarity... Figure 1In the example, control circuitry 14 is shown separate from wireless circuitry 24, but wireless circuitry 24 may include processing circuitry and / or storage circuitry, the processing circuitry forming part of processing circuitry 18, and the storage circuitry forming part of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 may be implemented on wireless circuitry 24). As an example, portions of transceiver 28 (e.g., a host processor on transceiver 28) and / or processing circuitry 26 may form part of control circuitry 14. Control circuitry 14 (e.g., portions of control circuitry 14 formed on processing circuitry 26, portions of control circuitry 14 formed on transceiver 28, and / or portions of control circuitry 14 separate from wireless circuitry 24) may provide control signals (e.g., via one or more control paths in device 10) for the operation of front-end module 40.

[0041] Transceiver circuitry 28 may include processing WLAN communication bands (e.g., Wi-Fi). ® (IEEE 802.11) or other WLAN communication bands such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), Wi-Fi ® 6E band (e.g., 5925MHz to 7125MHz) and / or other Wi-Fi ® Wireless LAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz Bluetooth. ® Wireless personal area network transceiver circuits for frequency bands or other WPAN communication bands; cellular phone transceiver circuits for processing cellular phone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G new radio frequency range 1 (FR1) band below 10 GHz, 5G new radio frequency range 2 (FR2) band between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuits for processing near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.); ultra-wideband (UWB) transceiver circuits for processing communications using the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols; and / or any other desired radio frequency transceiver circuits for covering any other desired communication frequency bands of interest.

[0042] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna structure, slot antenna structure, planar inverted F-shaped antenna structure, helical antenna structure, monopole antenna, dipole, a combination of these designs, etc. Two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). Parasitic elements may be included in antenna 42 to adjust antenna performance. Antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0043] Some transceiver architectures may include multiple receiver paths. A typical receiver topology including multiple receiver paths involves a narrowband filter in each of the multiple receiver paths. Having a narrowband filter in each receiver path can consume a significant amount of circuit area, especially when the number of receiver paths is large. Configuring a single wideband filter to combine multiple receiver paths can help significantly reduce power consumption while minimizing area overhead. Designing such a wideband filter that meets noise and linearity performance criteria across a wide range of operating conditions can be challenging.

[0044] According to one implementation, a filter (such as...) is provided. Figure 3 The receiver is a filter circuit 60. The filter circuit 60 may have inputs coupled to one or more mixers or other filters and outputs coupled to a data converter such as an analog-to-digital converter (ADC) or other filters. One or more mixers may output a corresponding down-converted (demodulated) baseband signal to the input of the filter 60. Multiple mixers at the input of the filter circuit 60 may be part of different receiving paths of the wireless circuit 24. This type of filter circuit 60, configured to receive baseband signals from multiple receiver paths, may be a wideband baseband filter. Therefore, the receiver 32 (see [link to receiver circuit 60]) includes such a wideband baseband filter 60. Figure 2 () is a broadband receiver.

[0045] like Figure 3As shown, the baseband filter circuit 60 may include an input stage and an output stage. The input stage of the filter circuit 60 may be a programmable transconductance circuit 62, while the output stage of the filter circuit 60 may be a transimpedance amplifier 64 having one or more feedback components. A "transconductance" circuit can refer to and is defined herein as an electronic circuit configured to convert an input voltage into an output current. The transimpedance amplifier 64 may have a differential input coupled to the output of the transconductance circuit 62 and a differential output coupled to a subsequent ADC. A programmable feedback capacitor 66 and / or a programmable feedback resistor 68 may be coupled between the differential output and differential input of the transimpedance amplifier 64. Figure 3 The filter circuit 60 shown represents a continuous-time filter circuit.

[0046] Figure 3 The example of the filter circuit 60 being implemented as a continuous-time filter is illustrative. Figure 4 This is a diagram illustrating another specific implementation of the filter circuit 60. For example... Figure 4 As shown, the input stage of filter circuit 60 can be a programmable transconductance circuit 62, but the output stage of filter circuit 60 can be a switched capacitor circuit 70. Switched capacitor circuit 70 may have a differential input coupled to the output of transconductance circuit 62 and a differential output coupled to a subsequent ADC. Switched capacitor circuit 70 typically includes one or more capacitors 72 coupled to one or more associated switches 74. One of the switches 74 can be selectively activated to switch a corresponding capacitor in capacitor 74 into use, and vice versa. Figure 4 The filter circuit 60 shown represents a discrete-time filter circuit. Figure 4 The filter circuit 60 is an example of a discrete-time filter and Figure 3 The example of filter circuit 60 as a continuous-time filter is illustrative and not intended to limit the scope of embodiments of the invention. Other ways of implementing filter circuit 60 may be implemented if desired.

[0047] Generally speaking, the overall linearity and noise performance of the filter circuit 60 can be governed by the linearity and noise characteristics of the input transconductance circuit 62. Figure 5 This is a circuit diagram of an exemplary transconductance circuit 62 according to some implementation schemes. Transconductance circuit 62 has a symmetrical structure (e.g., the left half has the same structure as the right half). For example... Figure 5As shown, the transconductance circuit 62 may include a plurality of pull-down switches, a plurality of pull-up switches, a plurality of programmable current sources, and a plurality of programmable resistors. A “pull-down” switch or transistor can refer to and is defined herein as a device configured to pull a node driven by the switch down toward ground. The pull-down switches may include pull-down transistors Na1, Na2, Nb1, Nb2, Nc1, and Nc2, which, as an example, may be implemented as n-type metal-oxide-semiconductor (NMOS) transistors. A “pull-up” switch or transistor can refer to and is defined herein as a device configured to pull a node driven by the switch up toward a positive supply voltage Vdd. The pull-up switches may include pull-up transistors Pa1, Pa2, Pb1, Pb2, Pc1, and Pc2, which, as an example, may be implemented as p-type metal-oxide-semiconductor (PMOS) transistors. All the various pull-up switches and pull-down transistors have gates coupled to input terminals IN1 and IN2, and may all be referred to as “input” transistors. Figure 5 The example of the transistor in the transconductance circuit 62 being implemented as a MOS transistor is exemplary. In general, the pull-down and pull-up switches of the transconductance circuit 62 can be implemented using the following: metal-oxide-semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), junction field-effect transistors (JFETs), tunnel field-effect transistors (TFETs), fin field-effect transistors (FinFETs), silicon-on-insulator (SOI) transistors, carbon nanotube transistors, nanowire transistors, combinations of these transistors, and / or other types of transistors.

[0048] Transistor Na1 may have a gate terminal coupled to the first input terminal IN1 of circuit 62, a drain terminal coupled to the first output terminal OUT1 of circuit 62, and a source terminal coupled to the differential tail node 114. When referring to the current-conducting terminals of a metal-oxide-semiconductor transistor, the terms "source" and "drain" are sometimes used interchangeably. Therefore, the source terminal and drain terminal are sometimes referred to as "source-drain" terminals (e.g., a transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal). Furthermore, the term "activation" relating to a switch (or transistor) may refer to or be defined herein as the action of placing the switch in a "conducting" state or a low-impedance state such that the two terminals of the switch are electrically connected to conduct current. Activating a switch may sometimes be referred to as turning on or closing a switch. The term "deactivation" relating to a switch (or transistor) may refer to or be defined herein as the action of placing the switch in a "deactivating" state or a high-impedance state such that the two terminals of the switch / transistor are electrically disconnected with minimal leakage current. Deactivating a switch may sometimes be referred to as turning off or opening a switch.

[0049] Transistor Nb1 may have a gate terminal coupled to the first input terminal IN1, a drain terminal coupled to the first output terminal OUT1, and a source terminal coupled to the differential tail node 114. Arranged in this way, transistor Nb1 can be considered as being coupled "in parallel" with transistor Na1. Similarly, transistor Nc1 may have a gate terminal coupled to the first input terminal IN1, a drain terminal coupled to the first output terminal OUT1, and a source terminal coupled to the differential tail node 114. Arranged in this way, transistor Nc1 can be considered as being coupled "in parallel" with transistors Na1 and Nb1. The term "in parallel" can refer to, and is defined herein, a connection in which the source-drain terminals of two transistors are shorted to each other (i.e., the source terminals of the two transistors are shorted, and the drain terminals of the two transistors are shorted).

[0050] At another input terminal, transistor Na2 may have a gate terminal coupled to the second input terminal IN2 of circuit 62, a drain terminal coupled to the second output terminal OUT2 of circuit 62, and a source terminal coupled to the differential tail node 116. Input terminals IN1 and IN2 may be used as differential input ports across the conduction circuit 62 (e.g., input terminal IN1 may receive a first input signal, while input terminal IN2 may receive a second input signal that is inverted relative to the first input signal; the first and second input signals may together form a differential input signal). Output terminals OUT1 and OUT2 may be used as differential output ports across the conduction circuit 62. Transistor Nb2 may have a gate terminal coupled to the second input terminal IN2, a drain terminal coupled to the second output terminal OUT2, and a source terminal coupled to the differential tail node 116. Arranged in this way, transistor Nb2 may be considered as being coupled "in parallel" with transistor Na2. Similarly, transistor Nc2 may have a gate terminal coupled to the second input terminal IN2, a drain terminal coupled to the second output terminal OUT2, and a source terminal coupled to the differential tail node 116. Arranged in this way, transistor Nc2 can be considered to be coupled in parallel with transistors Na2 and Nb2.

[0051] Programmable current sources may include programmable current sources 110-1, 110-2, 110-3, 120-1, 120-2, and 120-3. These programmable current sources can be digitally controlled using multiple bits. For example, programmable current source 110-1 can be controlled by a 3-bit signal. When the 3-bit signal is “000”, current source 110-1 can be deactivated (e.g., completely turned off to not conduct current). When the 3-bit signal is “111”, current source 110-1 can be fully activated (e.g., fully turned on to conduct the maximum current). When the 3-bit signal has an intermediate value (such as “100”), current source 110-1 can be partially activated, with a portion of it turned on to conduct an intermediate current less than the maximum current. Programmable current sources 110-2, 110-3, 120-1, 120-2, and 120-3 can each be digitally controlled using their respective control bits. This example of a programmable current source controlled using a 3-bit signal is illustrative. In general, programmable current sources can be controlled using any number of bits. Programmable current source 110-1 has a first terminal coupled to differential tail node 114 and a second terminal coupled to ground power supply line 102 (e.g., a ground line providing ground voltage Vss). Programmable current source 110-2 has a first terminal coupled to differential tail node 116 and a second terminal coupled to ground power supply line 102. Current sources 110-1 and 110-2, coupled to differential tail nodes 114 and 116 respectively, can be referred to as “differential mode” current sources.

[0052] Programmable resistors may include programmable resistors 112-1, 112-2, 122-1, and 122-2. These programmable resistors may have tunable (adjustable) resistance. Programmable resistor 112-1 may have a first terminal coupled to differential tail node 114 and a second terminal coupled to common tail node 118. Programmable resistor 112-2 may have a first terminal coupled to differential tail node 116 and a second terminal coupled to common tail node 118. Resistors 112-1 and 112-2 connected to the source terminal of the pull-down transistor may sometimes be referred to as source “degenerate” resistors. Using source degenerate resistors for pull-down transistors may technically be advantageous to help improve the linearity of transconductance circuit 62. Programmable current source 110-3 has a first terminal coupled to common tail node 118 and a second terminal coupled to ground power supply line 102. The current source 110-3 coupled to the common tail node 118 inserted between the differential tail nodes 114 and 116 can be referred to as the "common mode" current source.

[0053] On the pull-up side, transistor Pa1 may have a gate terminal coupled to the first input terminal IN1, a drain terminal coupled to the first output terminal OUT1, and a source terminal coupled to the differential tail node 124. Transistor Pb1 may have a gate terminal coupled to the first input terminal IN1, a drain terminal coupled to the first output terminal OUT1, and a source terminal coupled to the differential tail node 124. Arranged in this way, transistor Pb1 can be considered as being coupled in parallel with transistor Pa1. Similarly, transistor Pc1 may have a gate terminal coupled to the first input terminal IN1, a drain terminal coupled to the first output terminal OUT1, and a source terminal coupled to the differential tail node 124. Arranged in this way, transistor Pc1 can be considered as being coupled in parallel with transistors Pa1 and Pb1.

[0054] At the other input terminal, transistor Pa2 may have a gate terminal coupled to the second input terminal IN2, a drain terminal coupled to the second output terminal OUT2, and a source terminal coupled to the differential tail node 126. Transistor Pb2 ​​may have a gate terminal coupled to the second input terminal IN2, a drain terminal coupled to the second output terminal OUT2, and a source terminal also coupled to the differential tail node 126. Arranged in this way, transistor Pb2 ​​can be considered as being coupled "in parallel" with transistor Pa2. Similarly, transistor Pc2 may have a gate terminal coupled to the second input terminal IN2, a drain terminal coupled to the second output terminal OUT2, and a source terminal also coupled to the differential tail node 126. Arranged in this way, transistor Pc2 can be considered as being coupled "in parallel" with transistors Pa2 and Pb2.

[0055] Programmable current source 120-1 has a first terminal coupled to differential tail node 124 and a second terminal coupled to positive power supply line 100 (e.g., a positive power supply terminal on which a positive power supply voltage Vdd is provided). Programmable current source 120-2 has a first terminal coupled to differential tail node 126 and a second terminal coupled to positive power supply line 100. Current sources 120-1 and 120-2, coupled to differential tail nodes 124 and 126 respectively, may be referred to as “differential mode” current sources.

[0056] Programmable resistor 122-1 may have a first terminal coupled to differential tail node 124 and a second terminal coupled to common tail node 128. Programmable resistor 122-2 may have a first terminal coupled to differential tail node 126 and a second terminal coupled to common tail node 128. Resistors 122-1 and 122-2 connected to the source terminals of the pull-up transistor are sometimes referred to as source “degenerate” resistors. Using source degenerate resistors for pull-up transistors may technically be advantageous to help improve the linearity of transconductance circuit 62. Programmable current source 120-3 has a first terminal coupled to common tail node 128 and a second terminal coupled to positive power supply line 100. Current source 120-3 coupled to common tail node 128 interposed between differential tail nodes 124 and 126 may be referred to as a “common mode” current source.

[0057] Combination Figure 5 The described type of transconductance circuit 62 can be configured to operate in several different gain modes. Figure 6 This is a diagram illustrating at least two different gain modes in which the transconductance circuit 62 can operate. For example... Figure 6 As shown, the transconductance circuit 62 can be configured to operate in a first (low) gain mode 400 and a second (high) gain mode 402. Low gain mode 400 can be used when the input signal swing is relatively large (e.g., the required signal gain is relatively small). During low gain mode, the differential mode current sources can be fully activated (e.g., current sources 110-1, 110-2, 120-1, and 120-2 are all switched to use using all "1" control bits), while the common mode current sources are deactivated (e.g., current sources 110-3 and 120-3 are switched out of use or completely turned off using all "0" control bits). During low gain mode, source degradation resistors 112-1, 112-2, 122-1, and 122-2 can all be adjusted to increase their resistance values ​​relative to the high gain mode. The resistance values ​​of resistors 112-1 and 112-2 should be the same. The resistance values ​​of resistors 122-1 and 122-2 should also be identical. Increasing the resistance value of the source degradation resistor when the common-mode current source is disabled will not affect the voltage margin of the transconductance circuit 62. Using the source degradation resistor for both the pull-down and pull-up transistors may technically be advantageous to help improve the linearity of the transconductance circuit 62. With this configuration and operation, the linearity performance of circuit 62 can be optimized in low-gain mode.

[0058] In contrast, a high-gain mode 402 can be used when the input signal swing is relatively small (e.g., when a larger gain is required to amplify the input signal). During high-gain mode, differential mode current sources can be disabled (e.g., current sources 110-1, 110-2, 120-1, and 120-2 are all switched out of use or turned off using all "0" bits), while common mode current sources are fully activated (e.g., current sources 110-3 and 120-3 are switched in or turned on using all "1" bits). During high-gain mode, source degradation resistors 112-1, 112-2, 122-1, and 122-2 can all be adjusted to reduce their resistance values ​​relative to the low-gain mode to help improve the voltage margin of circuit 62. The resistance values ​​of resistors 112-1 and 112-2 should be the same as each other. The resistance values ​​of resistors 122-1 and 122-2 should also be the same as each other. With this configuration and operation, the noise performance of circuit 62 can be optimized in low-gain mode, while providing sufficient voltage margin for the signal generated across the differential output of transconductance circuit 62.

[0059] This demonstrates how the transconductance circuit 62 can operate in both low-gain and high-gain modes. Figure 6 The examples are illustrative. Generally, the transconductance circuit 62 can be configured to operate in two or more gain modes, three or more different gain modes, four or more different gain modes, five to ten different gain modes, or more than ten different gain modes. The states of the programmable current sources and source degradation transistors can be adjusted accordingly for each gain mode. For example, in an intermediate gain mode that provides a gain greater than that of the low gain mode but less than that of the high gain mode, at least some of the programmable current sources can be partially activated (e.g., by using digital control bits with both "0" and "1"). In the intermediate gain mode, the resistance value of the source degradation resistor should be adjusted to be less than its resistance in the low gain mode and greater than its resistance in the high gain mode.

[0060] As mentioned above Figure 3 and Figure 4 As described, the overall linearity of the baseband filter 60 depends primarily on the linearity of the transconductance circuit 62. The linearity of the transconductance circuit is a function of its transconductance. The transconductance, or "Gm," of a circuit can be defined as the ratio of the change in output current to the change in input voltage. Conventional transconductance circuits typically exhibit a transconductance Gm that varies significantly over a range of PVT (process, voltage, temperature) variations. This variation in the transconductance Gm of the transconductance circuit can reduce the overall linearity of the baseband filter.

[0061] According to some implementation schemes, the transconductance circuit 62 may be equipped with transistors with different threshold voltages. Transistors with different threshold voltages may exhibit different Gm distributions. Figure 7This is a graph of the transconductance Gm of transconductance circuit 62 as a function of input voltage Vin. Curve 200 can represent the first transconductance distribution associated with circuit 62 having pull-up and pull-down transistors implemented entirely using a first threshold voltage. Curve 202 can represent the second transconductance distribution associated with circuit 62 having pull-up and pull-down transistors implemented entirely using a second threshold voltage different from the first threshold voltage. Curve 204 can represent the third transconductance distribution associated with circuit 62 having pull-up and pull-down transistors implemented entirely using a third threshold voltage different from the first and second threshold voltages.

[0062] As an example, the first threshold voltage may be greater than the second threshold voltage, and the second threshold voltage may be greater than the third threshold voltage. For instance, a transistor with a first threshold voltage may be referred to as a "standard threshold voltage" (SVT) device; a transistor with a second threshold voltage may be referred to as a "low threshold voltage" (LVT) device; and a transistor with a third threshold voltage may be referred to as an "ultra-low threshold voltage" (ULVT) device. As another example, a transistor with a first threshold voltage may be referred to as a "high threshold voltage" (HVT) device; a transistor with a second threshold voltage may be referred to as an SVT device; and a transistor with a third threshold voltage may be referred to as an LVT device.

[0063] like Figure 7 As shown, each of curves 200, 202, and 204 exhibits significant variation across the input voltage range. In contrast, curve 206 represents the transconductance distribution associated with circuit 62, which has pull-up and pull-down transistors with different threshold voltages. (Reference) Figure 5 The first portion of the transistor (e.g., transistors Na1, Na2, Pa1, and Pa2) may have a first threshold voltage; the second portion of the transistor (e.g., transistors Nb1, Nb2, Pb1, and Pb2) may have a second threshold voltage; and the third portion of the transistor (e.g., transistors Nc1, Nc2, Pc1, and Pc2) may have a third threshold voltage. (Return to Reference) Figure 7 Compared to curves 200, 202, and 204, curve 206 is relatively flat across the input voltage range. In other words, using transistors with different threshold voltages (e.g., a combination of SVT, LVT, and ULVT transistors) within the transconductance circuit 62 may be technically advantageous and beneficial for providing a more stable and robust Gm over the PVT variation range.

[0064] Another measure of the linearity of the transconductance circuit 62 is its third transconductance, or “Gm3”. Gm3 is the third derivative of the transconductance Gm. As an example, if not properly mitigated, the third-order nonlinearity Gm3 can lead to gain compression and third-order intermodulation distortion.

[0065] Figure 8 This is a graph of the third-order transconductance Gm3 of a pull-up or pull-down transistor as a function of the gate-to-source voltage Vgs. Curve 210 may represent the Gm3 distribution of a conventional transconductance circuit including all transistors with the same threshold voltage (e.g., all LVT transistors). Curve 212 may represent the Gm3 distribution of a transconductance circuit with all SVT transistors. Curve 214 may represent the Gm3 distribution of a transconductance circuit with all ULVT transistors. Curve 216 may represent the Gm3 distribution of transconductance circuit 62, where half of the pull-down and pull-up transistors (e.g., transistors Na1, Na2, Pa1, and Pa2) are SVT transistors, and the other half of the pull-down and pull-up transistors (e.g., transistors Nb1, Nb2, Pb1, and Pb2) are ULVT transistors. In this arrangement, transistors Nc1, Nc2, Pc1, and Pc2 may be omitted from transconductance circuit 62. Figure 8 As shown, curve 216 provides a much flatter Gm3 distribution compared to curve 210. Therefore, using transistors with different threshold voltages can provide improved linearity than a conventional topology that uses transistors with all the same threshold voltage.

[0066] Figure 9 Another graph of Gm3 as a function of the gate-to-source voltage Vgs for pull-up or pull-down transistors is shown. Curve 220 can represent the Gm3 distribution of the transconductance path with all ULVT transistors. Curve 222 can represent the Gm3 distribution of the transconductance path with all LVT transistors. Curve 224 can represent the Gm3 distribution of the transconductance path with all SVT transistors. If the size of the ULVT transistor is relatively smaller than the transistor associated with curve 220, then the dashed curve 220' can represent the Gm3 distribution. If the size of the LVT transistor is relatively smaller than the size of the transistor associated with curve 222, then the dashed curve 222' can represent the Gm3 distribution. If the size of the SVT transistor is relatively smaller than the size of the transistor associated with curve 224, then the dashed curve 224' can represent the Gm3 distribution.

[0067] Curve 226 can represent the Gm3 distribution of the transconductance circuit 62, where the first part of the pull-down and pull-up transistors (e.g., transistors Na1, Na2, Pa1, and Pa2) are ULVT transistors, the second part of the pull-down and pull-up transistors (e.g., transistors Nb1, Nb2, Pb1, and Pb2) are LVT transistors, and the third part of the pull-down and pull-up transistors (e.g., transistors Nc1, Nc2, Pc1, and Pc2) are SVT transistors. Figure 9As shown, curve 226 provides a much flatter Gm3 distribution over a wide range of Vgs compared to any other curve. According to some implementations, the weights of transistors with different threshold voltages can be adjusted to optimize for a flatter Gm3 distribution. As an example, it can be determined that using 40% SVT transistors, 45% ULVT transistors, and 15% LVT transistors produces the flattest Gm3 distribution. As another example, it can be determined that using 30% SVT transistors, 20% ULVT transistors, and 50% LVT transistors produces the flattest Gm3 distribution. These percentage weights refer to the relative sizes of the parallel transistors and are merely illustrative. Therefore, having different weights among, for example, pull-down transistors Na1, Nb1, and Nc1 can help further enhance the linearity of the transconductance circuit 62. The relative weights of pull-down transistors Na1, Nb1, and Nc1 can be applied to pull-down transistors Na2, Nb2, and Nc2, pull-up transistors Pa1, Pb1, and Pc1, and pull-up transistors Pa2, Pb2, and Pc2, respectively.

[0068] It can be adjusted Figure 5 The width or driveability of each transistor is shown to adjust the relative weights of the pull-down and pull-up transistors. Although Figure 5 Each transistor is shown as a single discrete transistor, but Figure 5 Each pull-up transistor can optionally be implemented as follows: Figure 10 The illustrated adjustable (programmable) pull-up switch Px. The pull-up switch Px can represent... Figure 5 The pull-up transistors are any one of Pa1, Pb1, Pc1, Pa2, Pb2, and Pc2. Figure 10 The diagram illustrates how a pull-up switch Px can comprise an array of p-type transistors 300 selectively activated by corresponding switches 302. A greater number of switches 302 can be activated to increase the overall drive strength of switch Px, thereby increasing the effective width or relative percentage weight of the switch. A smaller number of switches 302 can be activated to decrease the overall drive strength of switch Px, thereby decreasing the effective width or relative percentage weight of the switch. A switch Px implemented in this way is sometimes referred to as a programmable pull-up transistor or switch.

[0069] Similarly, Figure 5 Each pull-down transistor can optionally be implemented as follows: Figure 11 The illustrated adjustable (programmable) pull-down switch Nx. The pull-down switch Nx can represent... Figure 5 The pull-down transistors in the circuit are any one of Na1, Nb1, Nc1, Na2, Nb2, and Nc2. Figure 11The diagram illustrates how a pull-down switch Nx can comprise an array of n-type transistors 310 selectively activated by corresponding switches 312. A greater number of switches 312 can be activated to increase the overall drive strength of switch Nx, thereby increasing the effective width or relative percentage weight of the switch. A smaller number of switches 312 can be activated to decrease the overall drive strength of switch Nx, thereby decreasing the effective width or relative percentage weight of the switch. A switch Nx implemented in this way is sometimes referred to as a programmable pull-down transistor or switch.

[0070] The above text combined Figures 1 to 11 The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage device circuitry 16 and / or wireless communication circuitry 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless circuitry 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0071] According to one embodiment, a wireless receiver includes: a plurality of receiving paths; and a filter circuit configured to receive signals from the plurality of receiving paths, wherein the filter circuit includes a transconductance circuit including: a first pull-down transistor having a first threshold voltage; and a second pull-down transistor coupled in parallel with the first pull-down transistor and having a second threshold voltage different from the first threshold voltage.

[0072] According to another embodiment, the filter circuit optionally further includes: a transimpedance amplifier having an input coupled to the transconductance circuit; and a programmable resistor and capacitor coupled across the input and output of the transconductance circuit.

[0073] According to another embodiment, the filter circuit optionally further includes a switched capacitor circuit having an input coupled to the transconductance circuit and an output coupled to the analog-to-digital converter.

[0074] According to another embodiment, the transconductance circuit optionally further includes a third pull-down transistor, which is coupled in parallel with the first pull-down transistor and the second pull-down transistor and has a third threshold voltage different from the first threshold voltage and the second threshold voltage, wherein the first pull-down transistor, the second pull-down transistor and the third pull-down transistor have gate terminals coupled to a first input terminal of the transconductance circuit.

[0075] According to another embodiment, the transconductance circuit optionally further includes: a fourth pull-down transistor having the first threshold voltage; a fifth pull-down transistor coupled in parallel with the fourth pull-down transistor and having the second threshold voltage; and a sixth pull-down transistor coupled in parallel with the fourth and fifth pull-down transistors and having the third threshold voltage, wherein the fourth, fifth, and sixth pull-down transistors have gate terminals coupled to a second input terminal of the transconductance circuit that is different from the first input terminal.

[0076] According to another embodiment, the transconductance circuit optionally further includes: a first programmable current source coupled to the source terminals of the first pull-down transistor, the second pull-down transistor, and the third pull-down transistor; and a second programmable current source coupled to the source terminals of the fourth pull-down transistor, the fifth pull-down transistor, and the sixth pull-down transistor.

[0077] According to another embodiment, the transconductance circuit optionally further includes: a first programmable resistor having a first terminal coupled to the first programmable current source and a second terminal coupled to the node; a second programmable resistor having a first terminal coupled to the second programmable current source and a second terminal coupled to the node; and a third programmable current source coupled to the node.

[0078] According to another embodiment: during a first gain mode, the first programmable current source and the second programmable current source are optionally fully activated, and the third programmable current source is optionally deactivated; during a second gain mode, the first programmable current source and the second programmable current source are optionally deactivated, and the third programmable current source is optionally fully activated; and during a third gain mode, at least some of the programmable current sources of the first programmable current source and the second programmable current source are optionally partially activated.

[0079] According to another embodiment: during the first gain mode, the first programmable resistor and the second programmable resistor are optionally adjusted to a first resistance value; and during the second gain mode, the first programmable resistor and the second programmable resistor are optionally adjusted to a second resistance value less than the first resistance value.

[0080] According to another embodiment, the transconductance circuit optionally further includes: a first pull-up transistor coupled in series with the first pull-down transistor; a second pull-up transistor coupled in parallel with the first pull-up transistor; and a third pull-up transistor coupled in parallel with the first pull-up transistor and the second pull-up transistor, wherein the first pull-up transistor, the second pull-up transistor and the third pull-up transistor have gate terminals coupled to the first input terminal of the transconductance circuit.

[0081] According to one embodiment, a transconductance circuit includes: a first pull-up transistor having a source terminal, a drain terminal coupled to a first output terminal, and a gate terminal configured to receive an input signal, wherein the first pull-up transistor has a first threshold voltage; a second pull-up transistor having a source terminal shorted to the source terminal of the first pull-up transistor, a drain terminal shorted to the drain terminal of the first pull-up transistor, and a gate terminal configured to receive the input signal, wherein the second pull-up transistor has a second threshold voltage different from the first threshold voltage; and a first programmable current source having a first terminal coupled to the source terminals of the first and second pull-up transistors and a second terminal coupled to a positive power supply line.

[0082] According to another embodiment, the transconductance circuit optionally includes a third pull-up transistor having a source terminal shorted to the source terminal of the first pull-up transistor, a drain terminal shorted to the drain terminal of the first pull-up transistor, and a gate terminal configured to receive the input signal, wherein the third pull-up transistor has a third threshold voltage different from the first threshold voltage and the second threshold voltage.

[0083] According to another embodiment, the transconductance circuit optionally includes: a fourth pull-up transistor having a source terminal, a drain terminal coupled to a second output terminal, and a gate terminal configured to receive an additional input signal inverted relative to the input signal, wherein the fourth pull-up transistor has the first threshold voltage; a fifth pull-up transistor having a source terminal shorted to the source terminal of the fourth pull-up transistor, a drain terminal shorted to the drain terminal of the fourth pull-up transistor, and a gate terminal configured to receive the additional input signal, wherein the fifth pull-up transistor has the second threshold voltage; and a sixth pull-up transistor having a source terminal shorted to the source terminal of the fourth pull-up transistor, a drain terminal shorted to the drain terminal of the fourth pull-up transistor, and a gate terminal configured to receive the additional input signal, wherein the sixth pull-up transistor has the third threshold voltage.

[0084] According to another embodiment, the transconductance circuit optionally includes: a second programmable current source having a first terminal coupled to the source terminals of the fourth, fifth, and sixth pull-up transistors and a second terminal coupled to the positive power supply line; a first programmable resistor having a first terminal coupled to the first programmable current source and a second terminal coupled to the node; a second programmable resistor having a first terminal coupled to the second programmable current source and a second terminal coupled to the node; and a third programmable current source having a first terminal coupled to the node and a second terminal coupled to the positive power supply line.

[0085] According to another embodiment: during a first gain mode configured to generate a first gain amount, the first programmable current source and the second programmable current source are optionally fully activated, while the third programmable current source is optionally deactivated; during a second gain mode configured to generate a second gain amount greater than the first gain amount, the first programmable current source and the second programmable current source are optionally deactivated, while the third programmable current source is optionally fully activated; and during a third gain mode configured to generate a third gain amount greater than the first gain amount and less than the second gain amount, the first programmable current source, the second programmable current source, and the third programmable current source are optionally partially activated.

[0086] According to one embodiment, a transconductance circuit includes: a first programmable pull-down switch having a gate terminal configured to receive an input signal, wherein the first programmable pull-down switch has a first threshold voltage and is adjusted to provide a first drive strength; and a second programmable pull-down switch coupled in parallel with the first programmable pull-down switch and having a gate terminal configured to receive the input signal, wherein the second programmable pull-down switch has a second threshold voltage different from the first threshold voltage and is adjusted to provide a second drive strength different from the first drive strength, wherein the transconductance circuit has linearity optimized based on the first drive strength and the second drive strength.

[0087] According to another embodiment, the transconductance circuit optionally includes a third programmable pull-down switch coupled in parallel with the first programmable pull-down switch and having a gate terminal configured to receive the input signal, wherein the third programmable pull-down switch has a third threshold voltage different from the first threshold voltage and the second threshold voltage and is adjusted to provide a third drive strength different from the first drive strength to optimize the linearity of the transconductance circuit.

[0088] According to another embodiment, the first programmable pull-down switch optionally includes: an n-type transistor array; and a plurality of switches, each of the plurality of switches being coupled in series with a corresponding n-type transistor in the n-type transistor array.

[0089] According to another embodiment, the transconductance circuit optionally includes a programmable current source having a first terminal coupled to the source terminals of the first programmable pull-down switch and the second programmable pull-down switch, and a second terminal coupled to a ground line, wherein the programmable current source is activated during a first gain mode and deactivated during a second gain mode.

[0090] According to another embodiment, the transconductance circuit optionally includes a programmable source degradation resistor directly coupled to the source terminal of the first programmable pull-down switch and the second programmable pull-down switch, wherein the programmable source degradation resistor is adjusted to provide a first resistance during the first gain mode and a second resistance less than the first resistance during the second gain mode.

[0091] The foregoing is merely illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

[0092] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

Claims

1. A wireless receiver, the wireless receiver comprising: Multiple receiving paths; and A filter circuit configured to receive signals from the plurality of receiving paths, wherein the filter circuit includes a transconductance circuit including... A first pull-down transistor, the first pull-down transistor having a first threshold voltage, and The second pull-down transistor is coupled in parallel with the first pull-down transistor and has a second threshold voltage that is different from the first threshold voltage.

2. The wireless receiver according to claim 1, wherein the filter circuit further comprises: A transimpedance amplifier having an input terminal coupled to the transconductance circuit; and A programmable resistor and a capacitor, the programmable resistor and the capacitor being coupled across the input and output terminals of the transconductance circuit.

3. The wireless receiver according to claim 1, wherein the filter circuit further comprises: A switched capacitor circuit having an input terminal coupled to the transconductance circuit and an output terminal coupled to the analog-to-digital converter.

4. The wireless receiver according to claim 1, wherein the transconductance circuit further comprises: A third pull-down transistor, which is coupled in parallel with the first and second pull-down transistors and has a third threshold voltage different from the first and second threshold voltages, wherein the first, second, and third pull-down transistors have gate terminals coupled to a first input terminal of the transconductance circuit.

5. The wireless receiver according to claim 4, wherein the transconductance circuit further comprises: A fourth pull-down transistor, the fourth pull-down transistor having the first threshold voltage; The fifth pull-down transistor is coupled in parallel with the fourth pull-down transistor and has the second threshold voltage; and A sixth pull-down transistor, which is coupled in parallel with the fourth and fifth pull-down transistors and has the third threshold voltage, wherein the fourth, fifth, and sixth pull-down transistors have gate terminals coupled to a second input terminal, which is different from the first input terminal, of the transconductance circuit.

6. The wireless receiver of claim 5, wherein the transconductance circuit further comprises: A first programmable current source, the first programmable current source being coupled to the source terminals of the first pull-down transistor, the second pull-down transistor and the third pull-down transistor; and A second programmable current source is coupled to the source terminals of the fourth, fifth, and sixth pull-down transistors.

7. The wireless receiver of claim 6, wherein the transconductance circuit further comprises: A first programmable resistor has a first terminal coupled to the first programmable current source and a second terminal coupled to a node; A second programmable resistor has a first terminal coupled to the second programmable current source and a second terminal coupled to the node; and A third programmable current source is coupled to the node.

8. The wireless receiver according to claim 7, wherein: During the first gain mode, the first programmable current source and the second programmable current source are fully activated, and the third programmable current source is deactivated. During the second gain mode, the first programmable current source and the second programmable current source are deactivated, and the third programmable current source is fully activated; and During the third gain mode, at least some of the programmable current sources, including the first programmable current source and the second programmable current source, are partially activated.

9. The wireless receiver according to claim 8, wherein: During the first gain mode, the first programmable resistor and the second programmable resistor are adjusted to a first resistance value; and During the second gain mode, the first programmable resistor and the second programmable resistor are adjusted to a second resistance value that is less than the first resistance value.

10. The wireless receiver of claim 5, wherein the transconductance circuit further comprises: The first pull-up transistor is coupled in series with the first pull-down transistor. The second pull-up transistor is coupled in parallel with the first pull-up transistor. and A third pull-up transistor is coupled in parallel with the first pull-up transistor and the second pull-up transistor, wherein the first pull-up transistor, the second pull-up transistor and the third pull-up transistor have gate terminals coupled to the first input terminal of the transconductance circuit.

11. A transconductance circuit, the transconductance circuit comprising: A first pull-up transistor has a source terminal, a drain terminal coupled to a first output terminal, and a gate terminal configured to receive an input signal, wherein the first pull-up transistor has a first threshold voltage; A second pull-up transistor has a source terminal shorted to the source terminal of the first pull-up transistor, a drain terminal shorted to the drain terminal of the first pull-up transistor, and a gate terminal configured to receive the input signal, wherein the second pull-up transistor has a second threshold voltage different from the first threshold voltage; and A first programmable current source has a first terminal coupled to the source terminals of the first pull-up transistor and the second pull-up transistor and a second terminal coupled to a positive power supply line.

12. The transconductance circuit according to claim 11, further comprising: A third pull-up transistor has a source terminal shorted to the source terminal of the first pull-up transistor, a drain terminal shorted to the drain terminal of the first pull-up transistor, and a gate terminal configured to receive the input signal, wherein the third pull-up transistor has a third threshold voltage different from the first threshold voltage and the second threshold voltage.

13. The transconductance circuit according to claim 12, further comprising: A fourth pull-up transistor having a source terminal, a drain terminal coupled to a second output terminal, and a gate terminal configured to receive an additional input signal inverted relative to the input signal, wherein the fourth pull-up transistor has the first threshold voltage; A fifth pull-up transistor having a source terminal shorted to the source terminal of the fourth pull-up transistor, a drain terminal shorted to the drain terminal of the fourth pull-up transistor, and a gate terminal configured to receive the additional input signal, wherein the fifth pull-up transistor has the second threshold voltage; and A sixth pull-up transistor having a source terminal shorted to the source terminal of the fourth pull-up transistor, a drain terminal shorted to the drain terminal of the fourth pull-up transistor, and a gate terminal configured to receive the additional input signal, wherein the sixth pull-up transistor has the third threshold voltage.

14. The transconductance circuit according to claim 13, further comprising: A second programmable current source has a first terminal coupled to the source terminals of the fourth pull-up transistor, the fifth pull-up transistor, and the sixth pull-up transistor, and a second terminal coupled to the positive power supply line. A first programmable resistor has a first terminal coupled to the first programmable current source and a second terminal coupled to a node; A second programmable resistor has a first terminal coupled to the second programmable current source and a second terminal coupled to the node; and A third programmable current source has a first terminal coupled to the node and a second terminal coupled to the positive power supply line.

15. The transconductance circuit according to claim 14, wherein: During the first gain mode configured to generate a first gain amount, the first programmable current source and the second programmable current source are fully activated, while the third programmable current source is deactivated. During a second gain mode configured to generate a second gain greater than the first gain, the first programmable current source and the second programmable current source are deactivated, while the third programmable current source is fully activated. and During a third gain mode configured to generate a third gain greater than the first gain and less than the second gain, the first programmable current source, the second programmable current source, and the third programmable current source are partially activated.

16. A transconductance circuit, the transconductance circuit comprising: A first programmable pull-down switch has a gate terminal configured to receive an input signal, wherein the first programmable pull-down switch has a first threshold voltage and is adjusted to provide a first drive strength; and A second programmable pull-down switch, which is coupled in parallel with the first programmable pull-down switch and has a gate terminal configured to receive the input signal, wherein the second programmable pull-down switch has a second threshold voltage different from the first threshold voltage and is adjusted to provide a second drive strength different from the first drive strength, wherein the transconductance circuit has linearity optimized based on the first drive strength and the second drive strength.

17. The transconductance circuit according to claim 16, further comprising: A third programmable pull-down switch, coupled in parallel with the first programmable pull-down switch and having a gate terminal configured to receive the input signal, wherein the third programmable pull-down switch has a third threshold voltage different from the first threshold voltage and the second threshold voltage and is adjusted to provide a third drive strength different from the first drive strength to optimize the linearity of the transconductance circuit.

18. The transconductance circuit of claim 16, wherein the first programmable pull-down switch comprises: n-type transistor array; and A plurality of switches, each of which is coupled in series with a corresponding n-type transistor in the n-type transistor array.

19. The transconductance circuit according to claim 16, further comprising: A programmable current source having a first terminal coupled to the source terminals of the first programmable pull-down switch and the second programmable pull-down switch, and a second terminal coupled to a ground line, wherein the programmable current source is activated during a first gain mode and deactivated during a second gain mode.

20. The transconductance circuit according to claim 19, further comprising: A programmable source degradation resistor, the programmable source degradation resistor being directly coupled to the source terminals of the first programmable pull-down switch and the second programmable pull-down switch, wherein the programmable source degradation resistor is adjusted to provide a first resistance during the first gain mode and a second resistance less than the first resistance during the second gain mode.

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