Attenuator control mode isolation circuit and radio frequency attenuation circuit for chip testing

Abstract

This application relates to the field of chip testing technology, and provides an attenuator control mode isolation circuit and an RF attenuation circuit for chip testing. The attenuator control mode isolation circuit for chip testing includes: an attenuator, a serial control interface, a DIP switch, and a mode switching enable switch. The attenuator includes a latch enable terminal. The mode switching enable switch is connected between the latch enable terminal, the serial control interface, and the DIP switch, and has a first connection state and a second connection state. When the mode switching enable switch is in the first connection state, the latch enable terminal is connected to the serial control interface and disconnected from the DIP switch, so that the attenuator sets the attenuation value according to the serial control signal input from the serial control interface. When the mode switching enable switch is in the second connection state, the latch enable terminal is connected to the DIP switch and disconnected from the serial control interface, so that the attenuator sets the attenuation value according to the asynchronous control signal output from the DIP switch.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to an attenuator control mode isolation circuit and an RF attenuation circuit for chip testing. Background Technology

[0002] In radio frequency signal processing, test and measurement equipment, and communication equipment, it is usually necessary to provide radio frequency test signals of different frequencies and power levels to the chip under test (DUT) to complete tests such as frequency response, gain, sensitivity, linearity, and input power scanning. During the above tests, the radio frequency signal not only needs to have a wide frequency coverage range, but also needs to be able to adjust the attenuation according to different test conditions, so as to form a variety of attenuation signals with different amplitudes to meet the test requirements of the DUT under different input power conditions.

[0003] In existing technologies, when generating RF test signals with different attenuation values, there are usually problems such as insufficient flexibility in attenuation adjustment, inconvenience in switching between different attenuation states, or low accuracy in setting attenuation values. These issues make it difficult to meet the requirements for rapid and stable switching of multiple attenuation signals during chip testing, thereby affecting chip testing efficiency and the reliability of test results. Summary of the Invention

[0004] In view of this, embodiments of this application provide an attenuator control mode isolation circuit and an RF attenuation circuit for chip testing, in order to solve the problems in the prior art where attenuation state switching is inconvenient, attenuation adjustment flexibility is insufficient, and attenuation value setting accuracy is low when adjusting RF signals to different attenuation values.

[0005] A first aspect of this application provides an attenuator control mode isolation circuit, the circuit including: an attenuator, a serial control interface, a DIP switch, and a mode switching enable switch, the attenuator including a latch enable terminal; wherein: the mode switching enable switch is connected between the latch enable terminal, the serial control interface, and the DIP switch, and has a first connection state and a second connection state; when the mode switching enable switch is in the first connection state, the latch enable terminal is connected to the serial control interface and disconnected from the DIP switch, so that the attenuator sets an attenuation value according to the serial control signal input by the serial control interface; when the mode switching enable switch is in the second connection state, the latch enable terminal is connected to the DIP switch and disconnected from the serial control interface, so that the attenuator sets an attenuation value according to the asynchronous control signal output by the DIP switch; the attenuator is used to attenuate the radio frequency signal used for chip testing according to the set attenuation value, so as to obtain an attenuated radio frequency signal for providing to the chip under test.

[0006] A second aspect of this application provides a radio frequency attenuation circuit, which includes a wideband signal generation unit and an attenuator control mode isolation circuit. The output terminal of the wideband signal generation unit is connected to the attenuator in the attenuator control mode isolation circuit, and the attenuator control mode isolation circuit is used to adjust the attenuation of the wideband signal output by the wideband signal generation unit.

[0007] A third aspect of this application provides a chip testing apparatus, which includes an RF attenuation circuit and a host computer. The host computer is communicatively connected to a wideband signal generation unit in the RF attenuation circuit and is used to send signal generation control commands to the wideband signal generation unit. The wideband signal generation unit is used to generate a wideband signal with corresponding frequency parameters according to the signal generation control commands. The attenuator control mode isolation circuit in the RF attenuation circuit is used to adjust the attenuation of the wideband signal and to provide the attenuated wideband signal to the chip under test.

[0008] A fourth aspect of this application provides a chip testing method, comprising: sending a signal generation control command to a wideband signal generation unit via a host computer; generating a wideband signal with corresponding frequency parameters via the wideband signal generation unit according to the signal generation control command; selecting the control mode of an attenuator via a mode switching enable switch, enabling the latch enable terminal of the attenuator to be connected to either a serial control interface or a DIP switch, and configuring the attenuation value of the attenuator according to the control mode of the attenuator; adjusting the attenuation of the wideband signal via the attenuator, and providing the attenuated wideband signal to the chip under test for testing.

[0009] The beneficial effects of this application embodiment compared with the prior art are as follows: The attenuator control mode isolation circuit in this application embodiment includes: an attenuator, a serial control interface, a DIP switch, and a mode switching enable switch. The attenuator includes a latch enable terminal; wherein: the mode switching enable switch is connected between the latch enable terminal, the serial control interface, and the DIP switch, and has a first connection state and a second connection state; when the mode switching enable switch is in the first connection state, the latch enable terminal is connected to the serial control interface and disconnected from the DIP switch, so that the attenuator sets the attenuation value according to the serial control signal input by the serial control interface; when the mode switching enable switch is in the second connection state, the latch enable terminal is connected to the DIP switch and disconnected from the serial control interface, so that the attenuator sets the attenuation value according to the asynchronous control signal output by the DIP switch; finally, the attenuator sets the attenuation value according to the set attenuation value. This application attenuates the radio frequency (RF) signal used for chip testing to obtain an attenuated RF signal for the chip under test. It uses a mode switching enable switch to selectively activate either the serial control interface or the control path corresponding to the DIP switch. This allows the attenuator to flexibly select between serial and asynchronous control modes depending on the application scenario, improving the convenience and flexibility of switching between different attenuation control modes. Simultaneously, it isolates the DIP switch in serial control mode and the serial control interface in asynchronous control mode, preventing interference from control signals outside the current control mode. This improves the reliability of control mode switching and the accuracy of attenuation value setting, thus avoiding the problems of inconvenient attenuation state switching, insufficient attenuation adjustment flexibility, and low accuracy of attenuation value setting when adjusting RF signals to different attenuation values ​​in related technologies. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of an attenuator control mode isolation circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of another attenuator control mode isolation circuit provided in an embodiment of this application; Figure 3 This is a schematic diagram of another attenuator control mode isolation circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of another attenuator control mode isolation circuit provided in the embodiments of this application; Figure 5This is a schematic diagram of a radio frequency attenuation circuit provided in an embodiment of this application; Figure 6 This is a schematic diagram of a reference clock circuit provided in an embodiment of this application; Figure 7 This is a schematic diagram of a positive power supply unit provided in an embodiment of this application; Figure 8 This is a schematic diagram of a negative power supply unit provided in an embodiment of this application; Figure 9 This is a schematic diagram of a chip testing device provided in an embodiment of this application; Figure 10 This is a schematic diagram of a chip testing method provided in an embodiment of this application; Explanation of reference numerals in the attached figures: 1-Attenuator 1; 10-Latch enable terminal 10; 2-Serial control interface 2; 3-DIP switch 3; 4-Mode switching enable switch 4; 41-Analog switch 41; 42-Mechanical switch 42; 5-RF attenuation circuit 5; 6-Wideband signal generation unit 6; 7-Attenuator control mode isolation circuit 7; 8-Host computer 8; 9-Chip testing device 9. Detailed Implementation

[0012] In the following description, specific details such as particular method structures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known methods, apparatuses, and approaches are omitted to avoid unnecessary detail from obscuring the description of this application.

[0013] The following will describe in detail, with reference to the accompanying drawings, an attenuator control mode isolation circuit 7 according to an embodiment of this application.

[0014] Figure 1 This is a schematic diagram of an attenuator control mode isolation circuit 7 for chip testing provided in an embodiment of this application, as shown below. Figure 1 As shown, the attenuator control mode isolation circuit 7 includes: attenuator 1, serial control interface 2, DIP switch 3 and mode switching enable switch 4. Attenuator 1 includes latch enable terminal 10.

[0015] In some examples, attenuator 1 may include an RF input pin, an RF output pin, and multiple control pins; attenuator 1 can be connected to the RF signal path through the RF input pin and the RF output pin, and connected to the serial control interface 2, the DIP switch 3, and the mode switching enable switch 4 through the control pins.

[0016] The RF input pin is used to receive RF signals for chip testing (i.e., signals that need to be attenuated), and the RF output pin is used to output signals attenuated by the attenuator 1.

[0017] For example, such as Figure 2 As shown, the control pins may include at least some of the following: SERIN pin, latch enable pin, SEROUT pin, PUP pin, ASM1 pin, ASM2 pin, S / A pin, and CLK pin. The SERIN pin can be used as a serial data input pin, the CLK pin as a clock input pin, the LE pin as a latch enable pin, and the SEROUT pin as a serial data output pin. The S / A pin, ASM1 pin, and ASM2 pin can be used as control pins associated with asynchronous control modes. Different control pins can be combined according to the control mode of attenuator 1 to form a serial control path or an asynchronous control path for setting the attenuation value. It is understood that the latch enable pin 10 can be the latch enable pin of attenuator 1.

[0018] Attenuator 1 is used to attenuate the radio frequency signal used for chip testing according to a set attenuation value, so as to obtain an attenuated signal to be provided to the chip under test. For example, the signal to be attenuated is input to the radio frequency input pin of attenuator 1, and after being attenuated by attenuator 1 according to the set attenuation value, the attenuated signal is output from the radio frequency output pin of attenuator 1.

[0019] The control signals include serial control signals and asynchronous control signals. Serial control interface 2 is used to input serial control signals to attenuator 1. These serial control signals may include at least one of serial data, a clock signal, and a latch enable signal, so that attenuator 1 sets its attenuation value according to the control data input from serial control interface 2. DIP switch 3 is used to input asynchronous control signals to attenuator 1. These asynchronous control signals may be a combination of levels determined by the DIP switch 3's DIP state, so that attenuator 1 sets its corresponding attenuation value according to the level combination signal.

[0020] For example, the DIP switch 3 includes multiple switch positions, each of which is connected to a control pin of the attenuator 1 to provide a corresponding level combination signal to the attenuator 1 through the DIP state of different switch positions. For example, the DIP switch 3 may include a first switch position, a second switch position, a third switch position, and a fourth switch position. The first switch position is connected to the LE pin of the attenuator 1, the second switch position is connected to the ASM1 pin of the attenuator 1, the third switch position is connected to the ASM2 pin of the attenuator 1, and the fourth switch position is connected to the S / A pin of the attenuator 1. Each switch position can be connected to a power supply terminal or a ground terminal through a pull-up resistor or a pull-down resistor so that the corresponding control pin is at a high level or a low level according to the on or off state of the switch position.

[0021] In asynchronous control mode, the S / A pin of the attenuator 1 is set to a low level and the LE pin is set to a high level by the DIP switch 3 and its peripheral circuit, so that the attenuator 1 determines the corresponding attenuation state according to the level combination of the ASM1 pin and the ASM2 pin.

[0022] For example, when both ASM1 and ASM2 are high, attenuator 1 can be in the reference attenuation state; when both ASM1 and ASM2 are low, attenuator 1 can be set to the first attenuation state, such as a 3dB attenuation state; when both ASM1 and ASM2 are high, attenuator 1 can be set to the second attenuation state, such as a 28dB attenuation state; when both ASM1 and ASM2 are low, attenuator 1 can be set to the third attenuation state, such as a 31dB attenuation state. The above correspondence between level combinations and attenuation states is only an example, and the specific correspondence can be determined according to the model and pin definition of attenuator 1.

[0023] It is understandable that if both the serial control interface 2 and the DIP switch 3 are connected to the control pins of the attenuator 1, the attenuator 1 may be affected by both the serial control signal and the asynchronous control signal during the control mode switching process. This may cause the level or timing state of the latch enable terminal 10 to be affected by signals from other control modes, resulting in problems such as abnormal control data latching, incorrect attenuation value setting, or unstable control mode switching. Based on this, this embodiment of the application sets a mode switching enable switch 4 to selectively turn on and off the control paths corresponding to the serial control interface 2 and the DIP switch 3, thereby achieving isolated switching between the serial control mode and the asynchronous control mode.

[0024] Specifically, the mode switching enable switch 4 is connected between the latch enable terminal 10, the serial control interface 2, and the DIP switch 3, and has a first connection state and a second connection state. The first connection state can correspond to the serial control mode, and the second connection state can correspond to the asynchronous control mode.

[0025] When the mode switching enable switch 4 is in the first connection state, the latch enable terminal 10 is connected to the serial control interface 2 and disconnected from the DIP switch 3. At this time, the serial control interface 2 can provide a serial control signal to the attenuator 1, and the attenuator 1 sets the attenuation value according to the serial control signal input by the serial control interface 2. At the same time, since the DIP switch 3 is disconnected from the latch enable terminal 10, even if the asynchronous control signal output by the DIP switch 3 is applied, the asynchronous control signal will not act on the latch enable terminal 10, thereby avoiding interference from the current DIP state of the DIP switch 3 on the attenuation value setting in the serial control mode.

[0026] When the mode switching enable switch 4 is in the second connection state, the latch enable terminal 10 is connected to the DIP switch 3 and disconnected from the serial control interface 2. At this time, the DIP switch 3 can provide an asynchronous control signal to the attenuator 1, and the attenuator 1 sets the attenuation value according to the asynchronous control signal output by the DIP switch 3. At the same time, since the serial control interface 2 is disconnected from the latch enable terminal 10, the serial control signal output by the serial control interface 2 will not act on the latch enable terminal 10, thereby avoiding interference from the serial control interface 2 on the attenuation value setting in the asynchronous control mode.

[0027] In this embodiment, by connecting the mode switching enable switch 4 between the latch enable terminal 10 of the attenuator 1, the serial control interface 2, and the DIP switch 3, the attenuator 1 isolates the DIP switch 3 in the serial control mode and isolates the serial control interface 2 in the asynchronous control mode. This avoids the serial control signal and the asynchronous control signal from acting on the latch enable terminal 10 of the attenuator 1 at the same time, improves the reliability of the control mode switching, and improves the accuracy of the attenuation value setting.

[0028] According to the solution provided in the embodiments of this application, the attenuator control mode isolation circuit 7 includes: an attenuator 1, a serial control interface 2, a DIP switch 3, and a mode switching enable switch 4. The attenuator 1 includes a latch enable terminal 10. The mode switching enable switch 4 is connected between the latch enable terminal 10, the serial control interface 2, and the DIP switch 3, and has a first connection state and a second connection state. When the mode switching enable switch 4 is in the first connection state, the latch enable terminal 10 is connected to the serial control interface 2 and disconnected from the DIP switch 3, so that the attenuator 1 sets the attenuation value according to the serial control signal input from the serial control interface 2. When the mode switching enable switch 4 is in the second connection state, the latch enable terminal 10 is connected to the DIP switch 3 and disconnected from the serial control interface 2, so that the attenuator 1 sets the attenuation value according to the asynchronous control signal output from the DIP switch 3. Finally, the attenuator 1 sets the attenuation value according to the desired attenuation value. The set attenuation value attenuates the RF signal used for chip testing to obtain an attenuated RF signal for the chip under test. This application uses a mode switching enable switch 4 to selectively enable the control paths corresponding to the serial control interface 2 and the DIP switch 3, allowing the attenuator 1 to flexibly select between serial control mode and asynchronous control mode according to the usage scenario. This improves the convenience and flexibility of switching between different attenuation control modes. At the same time, the attenuator 1 isolates the DIP switch 3 in serial control mode and isolates the serial control interface 2 in asynchronous control mode, avoiding interference from control signals in non-current control modes to the attenuator 3. This improves the reliability of control mode switching and the accuracy of attenuation value setting, thereby avoiding the problems of inconvenient attenuation state switching, insufficient attenuation adjustment flexibility, and low accuracy of attenuation value setting when adjusting RF signals with different attenuation values ​​in related technologies.

[0029] In some examples, such as Figure 3 As shown, the mode switching enable switch 4 includes a mechanical switch 42 and an analog switch 41; the mechanical switch 42 is used to generate a mode selection signal; the analog switch 41 includes a selection control terminal, a common terminal, a first strobe terminal, and a second strobe terminal. The selection control terminal is connected to the mechanical switch 42, the common terminal is connected to the latch enable terminal 10, the first strobe terminal is connected to the serial control interface 2, and the second strobe terminal is connected to the DIP switch 3; the analog switch 41 enables the common terminal to be connected to the first strobe terminal or the second strobe terminal according to the mode selection signal.

[0030] It is understood that the mechanical switch 42 can be a slide switch, toggle switch, push-button switch, or single-pole double-throw switch, etc. One end of the mechanical switch 42 can be connected to a power supply terminal or a ground terminal, and the other end is used to output a mode selection signal. The mechanical switch 42 has a first switching state and a second switching state; when the mechanical switch 42 is in the first switching state, the mechanical switch 42 outputs a first-level signal to the selection control terminal of the analog switch 41, so that the analog switch 41 is in a first connected state; when the mechanical switch 42 is in the second switching state, the mechanical switch 42 outputs a second-level signal to the selection control terminal of the analog switch 41, so that the analog switch 41 is in a second connected state. The first-level signal and the second-level signal can be opposite level signals, for example, the first-level signal is a high-level signal and the second-level signal is a low-level signal; or, the first-level signal is a low-level signal and the second-level signal is a high-level signal.

[0031] Specifically, in the first connection state, analog switch 41 connects the common terminal to the first strobe terminal and disconnects the common terminal from the second strobe terminal. At this time, the latch enable terminal 10 of attenuator 1 is connected to the serial control interface 2 through the common terminal and the first strobe terminal, and disconnected from the DIP switch 3. Thus, attenuator 1 can set the attenuation value according to the serial control signal input from the serial control interface 2, and the asynchronous control signal output by the DIP switch 3 will not act on the latch enable terminal 10.

[0032] In the second connection state, analog switch 41 connects the common terminal to the second strobe terminal and disconnects the common terminal from the first strobe terminal. At this time, the latch enable terminal 10 of attenuator 1 is connected to DIP switch 3 through the common terminal and the second strobe terminal, and disconnected from serial control interface 2. Thus, attenuator 1 can set the attenuation value according to the asynchronous control signal output by DIP switch 3, and the serial control signal output by serial control interface 2 will not affect latch enable terminal 10.

[0033] In some examples, the analog switch 41 may also include an enable terminal, which is used to control whether the analog switch 41 is in an active operating state. The selection control terminal may also be connected to a fixed level terminal via a pull-up resistor or a pull-down resistor, so that the selection control terminal is kept at a preset level when the mechanical switch 42 does not output a valid mode selection signal, thus preventing the analog switch 41 from switching erroneously due to the selection control terminal being left floating.

[0034] For example, taking an analog switch 41 (which is a dual-channel analog switch) controlling two attenuators 1 as an example, the two attenuators 1 include a first attenuator and a second attenuator, as follows: Figure 4 As shown, mechanical switch 42 is used to generate mode selection signal LE_SEL. The mode selection signal LE_SEL is input to the selection control terminal SEL of analog switch 41 to control the synchronous switching of the two switching channels of analog switch 41.

[0035] The common terminals of analog switch 41 include D+ and D- terminals, wherein D+ is connected to the latch enable terminal 10 of the first attenuator and D- is connected to the latch enable terminal 10 of the second attenuator; the first selection terminal of analog switch 41 includes MHL+ and MHL- terminals, wherein MHL+ is connected to the serial control interface 2 corresponding to the first attenuator and MHL- is connected to the serial control interface 2 corresponding to the second attenuator; wherein USB+ is connected to the DIP switch 3 corresponding to the first attenuator and USB- is connected to the DIP switch 3 corresponding to the second attenuator.

[0036] In this example, when the mode selection signal LE_SEL controls the analog switch 41 to select the MHL+ and MHL- terminals, the D+ terminal is connected to the MHL+ terminal, and the D- terminal is connected to the MHL- terminal. At this time, the latch enable terminal 10 of the first attenuator is connected to its corresponding serial control interface 2, and the latch enable terminal 10 of the second attenuator is connected to its corresponding serial control interface 2, thereby enabling the first attenuator and the second attenuator to synchronously enter the serial control mode. When the mechanical switch 42 is adjusted to switch the mode selection signal LE_SEL to another level state and controls the analog switch 41 to select the USB+ and USB- terminals, the D+ terminal is connected to the USB+ terminal, and the D- terminal is connected to the USB- terminal. At this time, the latch enable terminal 10 of the first attenuator is connected to its corresponding DIP switch 3, and the latch enable terminal 10 of the second attenuator is connected to its corresponding DIP switch 3, thereby enabling the first attenuator and the second attenuator to synchronously enter the asynchronous control mode.

[0037] In this embodiment, a mode selection signal is generated by a mechanical switch 42, and the control path of the latch enable terminal 10 is switched by an analog switch 41 according to the mode selection signal. This allows for hardware-level isolation between the serial control interface 2 and the DIP switch 3, preventing the serial control signal and the asynchronous control signal from acting simultaneously on the latch enable terminal 10 of the attenuator 1. Therefore, it effectively prevents the occurrence of abnormal target attenuation values ​​due to accidental activation of the DIP switch 3 in serial control mode, improving the stability of control mode switching and the accuracy of attenuation value setting.

[0038] In some examples, the attenuator control mode isolation circuit 7 includes at least two attenuators 1, such as... Figure 4As shown, the mode switching enable switch 4 may include at least two analog switches 41, with each pair of analog switches 41 corresponding to at least two attenuators 1. Each analog switch 41 includes a selection control terminal, a common terminal, a first gating terminal, and a second gating terminal; the selection control terminal of each analog switch 41 is connected to the same mechanical switch 42 to share the mode selection signal output by the mechanical switch 42. Thus, each analog switch 41 can switch synchronously under the control of the same mode selection signal, so that the latch enable terminal 10 of the corresponding attenuator 1 is synchronously connected to the serial control interface 2 or the DIP switch 3.

[0039] For example, such as Figure 4 As shown, at least two analog switches 41 include, but are not limited to, a first analog switch SW11 and a second analog switch SW12, wherein the first analog switch SW11 corresponds to the first attenuator and the second attenuator, and the second analog switch SW12 corresponds to the third attenuator and the fourth attenuator.

[0040] Mechanical switch 42 is used to generate a mode selection signal LE_SEL, which is input to the selection control terminal of the first analog switch SW11 and the second analog switch SW12. Thus, the first analog switch SW11 and the second analog switch SW12 can switch synchronously under the control of the same mode selection signal LE_SEL.

[0041] Specifically, the first analog switch SW11 is used to switch the connection between the latch enable terminal 10 of the first and second attenuators and the serial control interface 2 or the DIP switch 3, and the second analog switch SW12 is used to switch the connection between the latch enable terminal 10 of the third and fourth attenuators and the serial control interface 2 or the DIP switch 3.

[0042] For example, the common terminals of the first analog switch SW11 include a D+ terminal and a D- terminal. The D+ terminal is connected to the latch enable terminal 1 of the first attenuator (RFOUTB_LE1 in the figure is the connecting line connected to the latch enable terminal 10 of the first attenuator), and the D- terminal is connected to the latch enable terminal 1 of the second attenuator (RFOUTA_LE1 in the figure is the connecting line connected to the latch enable terminal 10 of the second attenuator). Thus, the two switching channels of the first analog switch SW11 can respectively switch the connection path of the latch enable terminal 10 of the first attenuator 1 and the second attenuator 1. The common terminals of the second analog switch SW12 include D+ and D- terminals. The D+ terminal is connected to RFOUTB_LE2, which is a connection line connected to the latch enable terminal 10 of the third attenuator. The D- terminal is connected to RFOUTA_LE2, which is a connection line connected to the latch enable terminal 10 of the fourth attenuator. Thus, the two switching channels of the second analog switch SW12 can switch the connection path of the latch enable terminal 10 of the third and fourth attenuators respectively.

[0043] When the mode selection signal LE_SEL is in the first level state, the first analog switch SW11 and the second analog switch SW12 are both switched to the selection path corresponding to the serial control interface 2, so that the latch enable terminals 10 of the first attenuator 1 and the second attenuator 1 are respectively connected to the corresponding serial control interface 2; when the mode selection signal LE_SEL is in the second level state, the first analog switch SW11 and the second analog switch SW12 are both switched to the selection path corresponding to the DIP switch 3, so that the latch enable terminals 10 of the first attenuator 1 and the second attenuator 1 are respectively connected to the corresponding DIP switch 3.

[0044] Therefore, the mode selection signal LE_SEL generated by the same mechanical switch 42 can simultaneously control the first analog switch SW11 and the second analog switch SW12 to complete the synchronous switching of the connection relationship of the latch enable terminal 10 corresponding to different attenuators 1, so that multiple attenuators 1 can enter the serial control mode or the asynchronous control mode synchronously.

[0045] It should be noted that the above embodiment uses one mechanical switch 42 controlling one or two analog switches 41 as an example. In practical applications, the number of analog switches 41 can be determined according to the number of chips under test. One mechanical switch 42 can control one, two or more analog switches 41 to switch synchronously through the same mode selection signal, so that one or more attenuators 1 can be switched synchronously to serial control mode or asynchronous control mode, thereby testing multiple chips under test.

[0046] In this embodiment, by sharing a mode selection signal generated by a single mechanical switch 42, multiple analog switches 41 are simultaneously controlled to switch synchronously, enabling the latch enable terminal 10 of the corresponding attenuator 1 to be synchronously connected to the serial control interface 2 or the DIP switch 3. This not only simplifies the mode switching circuit and reduces the number of independent switches, but also ensures that multiple attenuators 1 enter the same control mode at the same time, avoiding inconsistencies in the control modes of different attenuators 1, and preventing control signals from non-current control modes from interfering with the latch enable terminal 10, thereby improving the consistency, stability, and reliability of the control mode switching of multiple attenuators 1.

[0047] Based on the same concept, this application provides a radio frequency attenuation circuit 5, such as Figure 5 As shown, the RF attenuation circuit 5 includes a wideband signal generation unit 6 and an attenuator control mode isolation circuit 7 as described in any of the above embodiments; the output terminal of the wideband signal generation unit 6 is connected to the attenuator 1 in the attenuator control mode isolation circuit 7, and the attenuator control mode isolation circuit 7 is used to adjust the attenuation of the wideband signal output by the wideband signal generation unit 6.

[0048] Specifically, attenuator 1 can set the attenuation value according to the serial control signal input from serial control interface 2, or according to the asynchronous control signal output from DIP switch 3. Mode switching enable switch 4 is used to select one path between serial control interface 2 and DIP switch 3 to be connected to the latch enable terminal 10 of attenuator 1, and to disconnect the other path from the latch enable terminal 10, thereby realizing the isolation switching between serial control mode and asynchronous control mode.

[0049] In some examples, when the RF attenuation circuit 5 is in serial control mode, the latch enable terminal 10 of the attenuator 1 is connected to the serial control interface 2 and disconnected from the DIP switch 3. At this time, the target attenuation value can be written to the attenuator 1 through the serial control interface 2 via the controller, host computer 8, or test main control unit, so that the attenuator 1 attenuates the broadband RF signal according to the target attenuation value.

[0050] In some examples, when the RF attenuation circuit 5 is in asynchronous control mode, the latch enable terminal 10 of the attenuator 1 is connected to the DIP switch 3 and disconnected from the serial control interface 2. At this time, the corresponding asynchronous control signal can be generated by adjusting the DIP switch 3, so that the attenuator 1 attenuates the broadband RF signal according to the attenuation value corresponding to the DIP switch state.

[0051] In some examples, the wideband signal generation unit 6 may include a wideband signal generation chip. The wideband signal generation chip is used to generate a radio frequency signal at a target frequency and can adjust the output power of the radio frequency signal.

[0052] For example, the wideband signal generation chip can be packaged in a VQFN or similar form. The OUTA and OUTB pins of the wideband signal generation chip can serve as RF output terminals, outputting a wideband RF signal. The RF output terminals can be connected to attenuator 1 via a switch isolation circuit, a matching circuit, and / or RF traces, allowing attenuator 1 to adjust the attenuation of the wideband RF signal. The RF signal attenuated by attenuator 1 can then be further output via an RF connector, such as an SMP connector, to an external test device or the chip under test.

[0053] In some examples, the wideband signal generation unit 6 can adjust the output frequency and output power through its own register configuration or control interface; the attenuator 1 in the attenuator control mode isolation circuit 7 can be used to further adjust the attenuation of the wideband RF signal. Thus, the wideband signal generation unit 6 can be used to generate the target frequency RF signal, and the attenuator 1 can be used to achieve more flexible output power control.

[0054] In this embodiment, by setting the attenuator control mode isolation circuit 7 at the output of the broadband signal generation unit 6, hardware isolation switching between serial control mode and asynchronous control mode can be achieved while adjusting the power of the broadband radio frequency signal. This satisfies both the serial attenuation control requirements in automated testing or program-controlled scenarios and the DIP switch attenuation control requirements in debugging, manual configuration, or offline use scenarios. Furthermore, it avoids mutual interference between the control signals of the two control modes, improving the control reliability and attenuation value setting accuracy of the radio frequency attenuation circuit 5.

[0055] In some examples, the RF attenuation circuit 5 also includes a reference clock circuit; the reference clock circuit is connected to the wideband signal generation unit 6 and is used to provide a reference clock signal to the wideband signal generation unit 6; the wideband signal generation unit 6 is used to generate a wideband RF signal based on the reference clock signal.

[0056] Specifically, the reference clock circuit includes a crystal oscillator and peripheral matching circuitry connected to the crystal oscillator, such as... Figure 6 As shown, the power supply terminal of the crystal oscillator can be connected to a 3.3V power supply terminal, and power supply filtering can be performed through a filter capacitor. For example, a 10μF capacitor and a 0.1μF capacitor can be configured at the power supply terminal of the crystal oscillator to reduce the impact of power supply ripple on the stability of the reference clock signal. The differential output terminal of the crystal oscillator can be connected to the OSCinP and OSCinM pins of the broadband signal generation chip through an impedance matching resistor, an AC coupling capacitor, and / or a differential termination resistor, thereby providing a reference clock signal to the broadband signal generation chip.

[0057] For example, the crystal oscillator can output a 100MHz differential reference clock signal. This 100MHz differential reference clock signal, after passing through a series resistor, an AC coupling capacitor, and a differential matching network, is input to the OSCinP and OSCinM pins of the broadband signal generation chip, respectively. The broadband signal generation chip can perform phase-locked loop, frequency multiplication, frequency division, or frequency synthesis based on the 100MHz differential reference clock signal to generate a broadband radio frequency signal at the target frequency.

[0058] Therefore, by setting a reference clock circuit, a stable reference clock signal can be provided for the wideband signal generation unit 6, thereby improving the frequency stability and output reliability of the wideband radio frequency signal generation.

[0059] In some examples, the RF attenuation circuit 5 also includes a power supply module connected to the attenuator 1 for providing positive and negative operating voltages to the attenuator 1.

[0060] The power supply module includes a positive power supply unit and a negative power supply unit. The positive power supply unit includes a linear regulator for providing a positive operating voltage to the attenuator 1. The negative power supply unit includes a DC-DC converter for providing a negative operating voltage to the attenuator 1. For example, the positive operating voltage can be +5V and the negative operating voltage can be -5V.

[0061] In some examples, such as Figure 7 As shown, the positive power supply unit may include a linear regulator, the output of which is connected to the positive power supply pin of attenuator 1 to provide a positive operating voltage to attenuator 1. For example, the VDD pin and / or VDD1 pin of attenuator 1 may be connected to the output of the linear regulator to receive a +5V power supply. Because the linear regulator has the characteristics of low output ripple, low noise, and good output voltage stability, it can reduce the impact of power supply noise on the RF performance and attenuation stability of attenuator 1.

[0062] In some examples, such as Figure 8 As shown, the negative power supply unit may include a DC-DC converter, the output of which is connected to the negative power supply pin of attenuator 1 to provide a negative operating voltage to attenuator 1. Exemplarily, the VSS pin of attenuator 1 may be connected to the output of the DC-DC converter to receive a -5V power supply. The DC-DC converter can generate a negative operating voltage based on the input power supply, featuring a wide input voltage adaptability range, high conversion efficiency, and ease of integration, thereby simplifying the negative power supply generation circuit.

[0063] Therefore, in this embodiment, the positive and negative power supply units provide positive and negative operating voltages to the attenuator 1 respectively, which can meet the dual power supply requirements of the attenuator 1. At the same time, the positive operating voltage is provided by a linear regulator and the negative operating voltage is provided by a DC-DC converter, which can balance low-noise power supply and negative voltage generation efficiency, thereby improving the power supply stability, integration and reliability of the RF attenuation circuit 5.

[0064] Based on the same concept, this application provides a chip testing device, such as... Figure 9 As shown, the chip testing device includes the RF attenuation circuit 5 and the host computer 8 in the above embodiment; the host computer 8 is communicatively connected to the wideband signal generation unit 6 in the RF attenuation circuit 5, and is used to send signal generation control commands to the wideband signal generation unit 6; the wideband signal generation unit 6 is used to generate a wideband signal with corresponding frequency parameters according to the signal generation control commands; the attenuator control mode isolation circuit 7 in the RF attenuation circuit 5 is used to attenuate and adjust the wideband signal, and is used to provide the attenuated wideband signal to the chip under test.

[0065] The signal generation control commands may include frequency parameters, sweep parameters, output enable parameters, and / or output power parameters. The wideband signal generation unit 6 can generate a wideband RF signal of the corresponding frequency according to the frequency parameters and output the wideband RF signal to the attenuator 1 in the attenuator control mode isolation circuit 7. The attenuator 1 attenuates the wideband RF signal according to the set attenuation value to obtain an RF test signal that meets the testing requirements of the chip under test.

[0066] In some examples, the host computer 8 can communicate with the wideband signal generation unit 6 through a serial communication interface, USB interface, network interface or other communication interface to configure the output frequency of the wideband signal generation unit 6. For example, when performing chip RF performance testing, the host computer 8 can send a target frequency configuration command, a frequency step configuration command or a frequency sweep control command to the wideband signal generation unit 6 so that the wideband signal generation unit 6 outputs a wideband RF signal at the corresponding frequency or within the corresponding frequency range.

[0067] In some examples, the attenuator control mode isolation circuit 7 can select either serial or asynchronous control mode depending on the test scenario. In serial control mode, the latch enable terminal 10 of attenuator 1 is connected to the serial control interface 2 and disconnected from the DIP switch 3. Testers can write the target attenuation value to attenuator 1 via the host computer 8, the test main control unit, or other controllers through the serial control interface 2, thereby achieving automated attenuation control. In asynchronous control mode, the latch enable terminal 10 of attenuator 1 is connected to the DIP switch 3 and disconnected from the serial control interface 2. Testers can set the attenuation value by adjusting the DIP switch 3, thereby achieving manual debugging or offline testing.

[0068] In some examples, the output of the RF attenuation circuit 5 can be connected to the RF input of the chip under test (DUT) via an RF connector, RF cable, probe holder, or test fixture to provide the DUT with an attenuated, wideband signal. This allows for RF performance testing of the DUT under different frequencies and input power conditions, such as gain testing, sensitivity testing, linearity testing, frequency response testing, or input power sweep testing.

[0069] In this embodiment, by setting the aforementioned RF attenuation circuit 5 in the chip testing device 9, the host computer 8 can control the wideband signal generation unit 6 to output a wideband signal at the target frequency. The attenuation of the wideband signal is then adjusted by the attenuator control mode isolation circuit 7 before being provided to the chip under test. This satisfies the configurable frequency and power requirements during automated chip testing, and allows for rapid setting of the attenuation value via DIP switches in debugging or offline testing scenarios. Simultaneously, it avoids interference between serial and asynchronous control signals, improving the testing flexibility, control reliability, and test result stability of the chip testing device 9.

[0070] In some examples, the chip testing device 9 further includes a daughter board and a load board. The radio frequency attenuation circuit 5 is disposed on the daughter board, and the radio frequency output terminal of the daughter board is connected to the load board through a coaxial connector and a coaxial line. The load board is provided with a power divider circuit and multiple chips under test. The input terminal of the power divider circuit is connected to the coaxial line, and the multiple output terminals are respectively connected to the multiple chips under test.

[0071] During the test, the RF attenuation circuit 5 adjusts the attenuation of the wideband RF signal and transmits the attenuated wideband RF signal to the load board. The power divider circuit distributes the received wideband RF signal into multiple RF test signals and provides them to multiple chips under test, thereby realizing parallel testing of multiple chips under test. Thus, multiple chips under test can be tested in parallel using the same wideband RF signal, improving chip testing efficiency and ensuring good consistency of the RF test signals received by each chip under test.

[0072] Based on the same concept, this application also provides a chip testing method, such as... Figure 10 As shown, the method includes: S1001. Send signal generation control commands to the broadband signal generation unit via the host computer; The signal generation control commands may include frequency parameters, frequency step parameters, sweep range parameters, output enable parameters, and / or output power parameters. For example, when performing RF performance testing on the chip under test, the host computer can generate corresponding signal generation control commands based on preset test items or user-input test parameters, and send these commands to the broadband signal generation unit.

[0073] S1002. A wideband signal with corresponding frequency parameters is generated by the wideband signal generation unit according to the signal generation control command. Specifically, the wideband signal generation unit can generate a wideband radio frequency signal corresponding to the target frequency based on the frequency parameters in the signal generation control command; or, based on the sweep range parameters and frequency step parameters in the signal generation control command, it can sequentially generate wideband radio frequency signals corresponding to multiple frequency points. The wideband signal generated by the wideband signal generation unit can be output to the attenuator in the attenuator control mode isolation circuit.

[0074] S1003. Select the control mode of the attenuator by switching the mode enable switch, so that the latch enable terminal of the attenuator is connected to either the serial control interface or the DIP switch, and configure the attenuation value of the attenuator according to the control mode of the attenuator. The attenuator's control modes can include serial control mode and asynchronous control mode. The mode switching enable switch can, based on user operation or mode selection signal, select one path between the serial control interface and the DIP switch to connect to the attenuator's latch enable terminal, and disconnect the other path from the latch enable terminal.

[0075] In some examples, when the mode switching enable switch selects the serial control mode, the attenuator's latch enable terminal is connected to the serial control interface and disconnected from the DIP switch. At this time, a target attenuation value can be written to the attenuator via the serial control interface through a host computer, test control unit, or controller, causing the attenuator to operate according to the target attenuation value. Because the DIP switch is disconnected from the latch enable terminal, the current DIP switch state does not affect the attenuation value setting in serial control mode.

[0076] In some examples, when the mode switching enable switch selects asynchronous control mode, the attenuator's latch enable terminal is connected to the DIP switch and disconnected from the serial control interface. At this time, the corresponding asynchronous control signal can be generated by adjusting the DIP switch's DIP state, causing the attenuator to operate according to the attenuation value corresponding to the DIP state. Because the serial control interface is disconnected from the latch enable terminal, the serial control signal output by the serial control interface will not affect the attenuation value setting in asynchronous control mode.

[0077] S1004. The attenuation of the wideband signal is adjusted by the attenuator, and the attenuated wideband signal is provided to the chip under test for testing.

[0078] Specifically, the attenuator can attenuate the wideband RF signal output by the wideband signal generation unit according to the attenuation value configured in step S803, thereby obtaining an RF test signal that meets the testing requirements of the chip under test. The attenuated wideband signal can be input to the RF input terminal of the chip under test through an RF connector, RF cable, probe holder, or test fixture for testing the chip under test.

[0079] In some examples, frequency response testing, gain testing, sensitivity testing, linearity testing, or input power sweep testing can be performed on the chip under test based on different combinations of frequency parameters and attenuation values. This allows for testing of the RF performance of the chip under test under wide bandwidth and multiple power conditions.

[0080] In this embodiment, a broadband signal with corresponding frequency parameters is generated by a broadband signal generation unit controlled by a host computer. The control mode of the attenuator is selected between the serial control interface and the DIP switch via a mode switching enable switch. Attenuation values ​​can be configured via serial control in automated testing scenarios, or via DIP switches in debugging or offline testing scenarios. Simultaneously, since the control path corresponding to a different control mode is disconnected, interference between serial and asynchronous control signals is avoided, improving the accuracy of attenuation value configuration and the stability of chip test results.

[0081] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0082] If an integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program may include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. A computer-readable medium may include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in a computer-readable medium can be appropriately added to or subtracted according to the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0083] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An attenuator control mode isolation circuit for chip testing, characterized in that, The circuit includes: an attenuator, a serial control interface, a DIP switch, and a mode switching enable switch; the attenuator includes a latch enable terminal; wherein: The mode switching enable switch is connected between the latch enable terminal, the serial control interface and the DIP switch, and has a first connection state and a second connection state. When the mode switching enable switch is in the first connection state, the latch enable terminal is connected to the serial control interface and disconnected from the DIP switch, so that the attenuator sets the attenuation value according to the serial control signal input by the serial control interface; When the mode switching enable switch is in the second connection state, the latch enable terminal is connected to the DIP switch and disconnected from the serial control interface, so that the attenuator sets the attenuation value according to the asynchronous control signal output by the DIP switch. The attenuator is used to attenuate the radio frequency signal used for chip testing according to a set attenuation value, so as to obtain an attenuated radio frequency signal to be provided to the chip under test.

2. The circuit according to claim 1, characterized in that, The mode switching enable switch includes a mechanical switch and an analog switch; The mechanical switch is used to generate a mode selection signal; The analog switch includes a selection control terminal, a common terminal, a first strobe terminal, and a second strobe terminal. The selection control terminal is connected to the mechanical switch, the common terminal is connected to the latch enable terminal, the first strobe terminal is connected to the serial control interface, and the second strobe terminal is connected to the DIP switch. The analog switch connects the common terminal to either the first strobe terminal or the second strobe terminal according to the mode selection signal.

3. The circuit according to claim 2, characterized in that, The mechanical switch has a first switching state and a second switching state; When the mechanical switch is in the first switch state, the mechanical switch outputs a first level signal to the selection control terminal of the analog switch, so that the analog switch is in the first connection state; When the mechanical switch is in the second switch state, the mechanical switch outputs a second level signal to the selection control terminal of the analog switch, so that the analog switch is in the second connection state.

4. The circuit according to claim 2, characterized in that, The circuit includes at least two attenuators, and the mode switching enable switch may include at least two analog switches, with each of the at least two analog switches corresponding to one of the attenuators. Each of the analog switches includes a selection control terminal, a common terminal, a first gating terminal, and a second gating terminal; the selection control terminal of each of the analog switches is connected to the same mechanical switch to share the mode selection signal output by the mechanical switch.

5. A radio frequency attenuation circuit, characterized in that, The radio frequency attenuation circuit includes a wideband signal generation unit and an attenuator control mode isolation circuit as described in any one of claims 1-4. The output of the broadband signal generation unit is connected to the attenuator in the attenuator control mode isolation circuit. The attenuator control mode isolation circuit is used to adjust the attenuation of the broadband signal output by the broadband signal generation unit.

6. The circuit according to claim 5, characterized in that, The radio frequency attenuation circuit also includes a reference clock circuit; The reference clock circuit is connected to the wideband signal generation unit and is used to provide a reference clock signal to the wideband signal generation unit; The wideband signal generation unit is used to generate the wideband signal based on the reference clock signal.

7. The circuit according to claim 5, characterized in that, The radio frequency attenuation circuit also includes a power supply module connected to the attenuator, which is used to provide the attenuator with a positive operating voltage and a negative operating voltage.

8. The circuit according to claim 7, characterized in that, The power module includes a positive power supply unit and a negative power supply unit; The positive power supply unit includes a linear regulator for providing the positive operating voltage to the attenuator; The negative power supply unit includes a DC-DC converter for providing the negative operating voltage to the attenuator.

9. A chip testing device, characterized in that, The device includes the radio frequency attenuation circuit and the host computer as described in any one of claims 5 to 8; The host computer is communicatively connected to the wideband signal generation unit in the radio frequency attenuation circuit and is used to send signal generation control commands to the wideband signal generation unit. The wideband signal generation unit is used to generate a wideband signal with corresponding frequency parameters according to the signal generation control command; The attenuator control mode isolation circuit in the radio frequency attenuation circuit is used to adjust the attenuation of the wideband signal and to provide the attenuated wideband signal to the chip under test.

10. A chip testing method, characterized in that, The method includes: The host computer sends signal generation control commands to the broadband signal generation unit. The broadband signal generation unit generates a broadband signal with corresponding frequency parameters according to the signal generation control command. The control mode of the attenuator is selected by the mode switching enable switch, so that the latch enable terminal of the attenuator is connected to either the serial control interface or the DIP switch, and the attenuation value of the attenuator is configured according to the control mode of the attenuator. The attenuator is used to adjust the attenuation of the wideband signal, and the attenuated wideband signal is provided to the chip under test for testing.

Images