Multi-bit digital attenuator structure and control method thereof, radio frequency attenuator

Abstract

This invention provides a multi-bit digitally controlled attenuation structure and its control method, as well as an RF attenuator. The digitally controlled attenuation structure includes a main switch branch, at least one parallel attenuation branch, and multiple first attenuation adjustment branches. The main switch branch includes a first transistor switch, and the parallel attenuation branch includes multiple stacked and sequentially connected second transistor switches. The drains of the remaining second transistor switches, except for the first second transistor switch, are each connected to a first attenuation adjustment branch to access a reference ground. By controlling the on or off state of the first and second transistor switches, the attenuation structure operates in a reference state or an attenuation state. When the first transistor switch is off, the state combination of each second transistor switch is controlled to output the bit attenuation corresponding to different preset attenuation requirements. Multiple attenuation level functions are integrated into a single attenuation unit, realizing multi-bit attenuation function while effectively reducing insertion loss and chip area.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a multi-bit numerically controlled attenuation structure and its control method, and a radio frequency attenuator. Background Technology

[0002] In active phased array systems, the radio frequency (RF) attenuator is one of the core modules of the transmit / receive (T / R) assembly. It is used to precisely adjust the signal amplitude of each channel, enabling functions such as amplitude weighting, sidelobe suppression, and inter-channel gain calibration. To meet the accuracy requirements of beam control, the RF attenuator needs to provide multi-bit attenuation adjustment capability.

[0003] Traditional numerically controlled attenuation units often employ T-type or π-type numerically controlled attenuation structures. Their core principle is to control the connection or bypass of a resistor network via transistor switches, achieving signal attenuation while maintaining impedance matching. However, this traditional structure has significant technical bottlenecks: traditional numerically controlled attenuation units only have a single transistor switch controlled by a single switching circuit in the parallel branch, allowing for only one attenuation state. To achieve multi-bit (e.g., 2-bit, 3-bit, or higher) attenuation control, multiple basic attenuation units (e.g., 1dB, 2dB, 4dB units) typically need to be cascaded. This cascading method causes the chip area to increase linearly with the number of bits. More critically, the total insertion loss of the attenuator is mainly determined by the cumulative insertion loss of the series transistor switches in each unit under the reference state. Each additional attenuation bit requires one or more transistor switches in the signal path, introducing additional insertion loss and increasing the system's link budget pressure and power consumption.

[0004] Therefore, how to reduce the insertion loss and chip area of ​​multi-bit RF attenuators while maintaining attenuation accuracy and attenuation range is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] This invention provides a multi-bit numerically controlled attenuation structure and its control method, as well as an RF attenuator, to reduce the insertion loss and chip area of ​​the multi-bit RF attenuator while maintaining attenuation accuracy and attenuation range.

[0006] On one hand, the present invention provides a multi-bit numerically controlled attenuation structure, comprising: The main switch branch includes the first transistor switch; At least one parallel attenuation branch is connected between the main switch branch and the reference ground; Multiple first attenuation adjustment branches are connected between the parallel attenuation branches and the reference ground; The parallel attenuation branch includes multiple stacked and connected in series second transistor switches; the drains of all second transistor switches except the first second transistor switch are respectively connected to a first attenuation adjustment branch and connected to a reference ground via the first attenuation adjustment branch; wherein the first second transistor switch is the second transistor switch closest to the main switch branch. The numerically controlled attenuation structure is configured to operate in a reference state or an attenuation state by controlling the operating states of the first transistor switch and the second transistor switch. Specifically, when the first transistor switch is off, the numerically controlled attenuation structure outputs a bit attenuation amount corresponding to different preset attenuation requirements by controlling the operating state of the second transistor switch in each of the parallel attenuation branches. The operating states of the first transistor switch and the second transistor switch include on or off.

[0007] On the other hand, the present invention also provides an RF attenuator, which includes at least one of the multi-bit digitally controlled attenuation structures described above. When there are multiple numerically controlled attenuation structures for the multi-bit bits, the numerically controlled attenuation structures for each multi-bit bit are cascaded sequentially.

[0008] On the other hand, the present invention also provides a control method for the above-described multi-bit numerically controlled attenuation structure, comprising: Determine the operating state of the numerically controlled attenuation structure; wherein the operating state includes a reference state or an attenuation state; When the numerically controlled attenuation structure is operating in the attenuation state, the numerically controlled attenuation structure outputs the corresponding bit attenuation amount according to the preset attenuation requirements.

[0009] The present invention provides a multi-bit digitally controlled attenuation structure and its control method, as well as an RF attenuator. The multi-bit digitally controlled attenuation structure includes a main switch branch, at least one parallel attenuation branch, and multiple first attenuation adjustment branches. Each parallel attenuation branch comprises multiple stacked and sequentially connected second transistor switches. The drains of all second transistor switches except the first are connected to a first attenuation adjustment branch to access a reference ground. By controlling the on / off states of the first and second transistor switches, the digitally controlled attenuation structure operates in either a reference state or an attenuation state. When the first transistor switch is off, the operating state combination of the second transistor switches in each parallel attenuation branch is controlled to output a bit attenuation corresponding to different preset attenuation requirements. This integrates the functions of multiple attenuation levels into a single attenuation unit, achieving multi-bit attenuation while effectively reducing insertion loss and chip area. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a traditional T-type numerical control attenuation structure; Figure 2 This is a schematic diagram of a traditional π-type numerically controlled attenuation structure; Figure 3 The equivalent circuit for the decay state and reference state of a traditional T-type numerically controlled attenuation structure; Figure 4 The equivalent circuit for the decay state and reference state of a traditional π-type numerically controlled attenuation structure; Figure 5 This is a schematic diagram of the first structure of the numerically controlled attenuation structure provided in the embodiments of the present invention; Figure 6 This is a schematic diagram of the second type of numerically controlled attenuation structure provided in the embodiments of the present invention. Figures 7a to 7d Equivalent circuit diagrams for the reference state and different decay states; Figure 8 This is a schematic diagram of the third structure of the numerically controlled attenuation structure provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of the fourth structure of the numerically controlled attenuation structure provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of the fifth type of numerically controlled attenuation structure provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of the sixth type of numerically controlled attenuation structure provided in the embodiments of the present invention; Figure 12 This is a schematic diagram of the seventh structure of the numerically controlled attenuation structure provided in the embodiments of the present invention; Figure 13 This is a flowchart illustrating the control method of the multi-bit numerically controlled attenuation structure of the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0013] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0014] Figure 1 This is a schematic diagram of a traditional T-type numerically controlled attenuation structure. Figure 2 This is a schematic diagram of a traditional π-type numerically controlled attenuation structure, as shown below. Figures 1 to 2 As shown, traditional T-type and π-type digitally controlled attenuation structures are symmetrical networks composed of resistors and transistor switches. Their core principle is to achieve precise attenuation of signal power by voltage division or current division of resistors with specific structures while maintaining precise impedance matching between the source and load ends (e.g., 50Ω).

[0015] The T-type network uses two series resistors ( Figure 1 R1 in the series), and a series switch ( Figure 1 Add a parallel resistor to M1 (in the middle) Figure 1 The structure of R2 in the parallel switch and the parallel switch ( Figure 1 In the M2), while the π-type network uses two parallel resistors ( Figure 2 R2' in the middle) and parallel switching transistors ( Figure 2 Add a series resistor to M2' (in the middle) Figure 2 R1' in the series switch and series switch ( Figure 2 The structure of M1' in the attenuator allows the attenuator to switch between the reference state and the attenuation state by controlling the opening and closing of the corresponding switching transistor.

[0016] Figure 3 The equivalent circuit for the decay state and reference state of a traditional T-type digitally controlled attenuation structure, such as Figure 3 As shown, in the reference state (left side), the series switch M1 in the T-type RF attenuator is in the on state (equivalent to Ron1), and the parallel switch M2 is in the off state (equivalent to Coff2). Its equivalent circuit is as follows: a low-impedance path is formed between the input terminal Rfin and the output terminal Rfout through two series resistors R1 and the on-state series switch M1. The parallel branch is a high-impedance open circuit due to the parallel switch M2; that is, there is no conductive path between the connection point of the two series resistors R1 and ground. The signal is transmitted through the series path with almost no attenuation; the insertion loss mainly comes from the on-resistance of the series switch M1 and the series resistor R1. The attenuation in the reference state is 0 dB.

[0017] In the attenuation state (right side diagram), the series switch M1 in the T-type numerically controlled attenuation structure is off (equivalent to Coff1), and the parallel switch M2 is on (equivalent to Ron2). Its equivalent circuit is as follows: the series path between the input terminal Rfin and the output terminal Rfout is interrupted, presenting a high-impedance open circuit state; the parallel branch forms a low-impedance path from the connection point of the two series resistors R1 to ground through the on-state parallel switch M2 and the parallel resistor R2. After the input signal reaches the connection point of the two series resistors R1 through the series resistor R1 on the input side, most of the signal energy flows to ground through the parallel branch, with only a small portion of the signal energy coupled to the output terminal Rfout through the series resistor R1 on the output side. This structure can also achieve signal attenuation while maintaining impedance matching.

[0018] Figure 4 This is the equivalent circuit for the decay state and reference state of a traditional π-type digitally controlled attenuation structure. For example... Figure 4 As shown, in the reference state ( Figure 4 (See the left diagram). In the π-type numerically controlled attenuation structure, the series switch M1' is in the on state, while both parallel switches M2' are in the off state. Its equivalent circuit is as follows: a low-impedance path is formed between the input terminal Rfin and the output terminal Rfout through the on-state series switch M1' and the series resistor R1'; the parallel branch from the input terminal to ground is in a high-impedance open-circuit state due to the off state of the parallel switch M2'; the parallel branch from the output terminal Rfout to ground is also in a high-impedance open-circuit state. At this time, the signal passes through the numerically controlled attenuation structure with almost no attenuation; the insertion loss mainly comes from the on-resistance of the series switch M1' and the small voltage drop across the series resistor R1'. Ideally, the attenuation in the reference state is equal to 0 dB.

[0019] In the decaying state ( Figure 4 (See the right-hand diagram). In the π-type numerically controlled attenuation structure, the series switch M1' is in the off state, while both parallel switches M2' are in the on state. Its equivalent circuit is as follows: the series path between the input terminal Rfin and the output terminal Rfout is interrupted, presenting a high-impedance open circuit state; the input terminal Rfin is connected to ground through the on-state parallel switch M2' and parallel resistor R2', forming a signal shunt path; the output terminal Rfout is also connected to ground through the on-state parallel switch M2' and parallel resistor R2', forming another shunt path. Part of the input signal energy is shunted to ground through the parallel resistor R2' on the input side, and the remaining energy is coupled to the output terminal through the series resistor R1', and then shunted to ground again through the parallel resistor R2' on the output side.

[0020] The two numerically controlled attenuation structures mentioned above are widely used in RF and microwave circuits and are the basic units of the core module of numerically controlled attenuation structures. However, traditional attenuation schemes often consist of multiple such attenuation units. This passive structure occupies a relatively large chip area. Therefore, the more compact the implementation scheme of the numerically controlled attenuation unit, the better. At the same time, a smaller insertion loss can also reduce the gain requirements of the active structure, thereby reducing system power consumption.

[0021] To address this, this invention introduces a multi-bit numerically controlled attenuation structure. This structure optimizes insertion loss and area without altering attenuation accuracy or range, integrating the functions of multiple attenuation units into a single attenuation unit. This reduces insertion loss and achieves a compact layout, thereby meeting the system's link budget requirements. The technical solution of this invention provides a numerically controlled attenuation structure implementation with low insertion loss, small area, and high integration, making it particularly suitable for active phased array systems.

[0022] Specifically, Figure 5 This is a schematic diagram of the first type of numerically controlled attenuation structure provided in an embodiment of the present invention. For example... Figure 5 As shown, the numerically controlled attenuation structure provided in this embodiment of the invention may include: Main switch branch 11 includes a first transistor switch; At least one parallel attenuation branch 12 is connected between the main switch branch 11 and the reference ground; Multiple first attenuation adjustment branches 13 are connected between the parallel attenuation branch 12 and the reference ground; The parallel attenuation branch 12 includes a plurality of stacked and connected in series second transistor switches; the drains of all second transistor switches except the first second transistor switch are respectively connected to a first attenuation adjustment branch 13 and connected to the reference ground via the first attenuation adjustment branch 13; wherein the first second transistor switch is the second transistor switch closest to the main switch branch 11. The numerically controlled attenuation structure is configured to operate in a reference state or an attenuation state by controlling the operating states of the first transistor switch and the second transistor switch. Specifically, when the first transistor switch is off, the numerically controlled attenuation structure outputs a bit attenuation amount corresponding to different preset attenuation requirements by controlling the operating state of the second transistor switch in each of the parallel attenuation branches 12. The operating states of the first transistor switch and the second transistor switch include on or off.

[0023] In detail, in this embodiment, the multi-bit digitally controlled attenuation structure comprises a main switch branch 11, at least one parallel attenuation branch 12, and multiple first attenuation adjustment branches 13. The main switch branch 11 contains a first transistor switch, the source and drain of which are connected to the signal input terminal Rfin and the signal output terminal Rfout of the digitally controlled attenuation structure, respectively. The parallel attenuation branch 12 connects the main switch branch 11 to a reference ground, and contains multiple stacked and sequentially connected second transistor switches. During assembly, the drain of the first second transistor switch (the one closest to the main switch branch 11) is connected to the main switch branch 11, the source of the first second transistor switch is connected to the drain of the second second transistor switch, the source of the second second transistor switch is connected to the drain of the third second transistor switch, and so on, with the source of the last second transistor switch connected to the reference ground. For each of the second to last second transistor switches, a first attenuation adjustment branch 13 is connected to the drain of each second transistor switch, and the other end of each first attenuation adjustment branch 13 is connected to a reference ground. Each first attenuation adjustment branch 13 is provided with a first attenuation adjustment component with a different resistance value to achieve different shunt ratios.

[0024] When the numerically controlled attenuation structure is working, the first and second transistor switches are turned on or off by applying different gate control voltages. When the first transistor switch is on, the signal is directly transmitted from the signal input terminal to the signal output terminal via the first transistor switch. At this time, the numerically controlled attenuation structure is working in the reference state, and the signal amplitude is basically not attenuated, with only minimal insertion loss caused by the on-resistance of the first transistor switch.

[0025] When the first transistor switch is turned off, the digitally controlled attenuation structure switches to the attenuation state. The signal cannot be directly transmitted through the first transistor switch, but instead enters the parallel attenuation branch 12 via the main switch branch 11. At this time, by controlling the gate voltage of each second transistor switch, different second transistor switches can be turned on or off, connecting the corresponding first attenuation adjustment branch 13 to the shunt circuit, changing the shunt impedance to ground, thereby achieving different attenuation outputs. The more second transistor switches that are turned on, the more shunt branches are connected, and the greater the attenuation.

[0026] Specifically, taking a system with three second transistor switches as an example, when the preset attenuation requirement is the minimum attenuation requirement, the first second transistor switch is turned on, and the remaining second transistor switches are turned off. At this time, the signal enters the drain of the first second transistor switch from the main switch branch 11, reaches its source through the channel of the first second transistor switch, and then reaches ground through the first attenuation adjustment branch connected to the drain of the second second transistor switch, forming the first attenuation path and outputting the minimum bit attenuation.

[0027] When the preset attenuation requirement is set to the intermediate attenuation level, the first second transistor switch is turned on, and the second second transistor switch is also turned on, while the third second transistor switch is turned off. At this time, the signal enters the drain of the first second transistor switch from the main switch branch 11, reaches its source through the channel of the first second transistor switch, and this source is simultaneously connected to the drain of the second second transistor switch. The signal travels to ground via both the first attenuation adjustment branch connected to the drain of the second second transistor switch and the source of the second second transistor switch, then to ground via the first attenuation adjustment branch connected to the drain of the third second transistor switch, forming a second attenuation path and outputting the intermediate bit attenuation level.

[0028] When the preset attenuation requirement is the maximum attenuation requirement, all second transistor switches are turned on. At this time, the signal enters the drain of the first second transistor switch from the main switch branch 11. After passing through the channel of the first second transistor switch, part of it goes to ground through the first attenuation adjustment branch connected to the drain of the second second transistor switch, and the other part continues to be transmitted through the channel of the second second transistor switch. After reaching the source of the second second transistor switch, part of it goes to ground through the first attenuation adjustment branch connected to the drain of the third second transistor switch, and the other part continues to be transmitted through the channel of the third second transistor switch to its source, which is directly connected to the reference ground, forming the third attenuation path and outputting the maximum bit attenuation.

[0029] The three attenuation states correspond to three preset attenuation values, thus achieving three bit-level attenuation levels within the same attenuation unit. Compared to the traditional approach that requires three cascaded attenuation units to achieve the three attenuation levels, this embodiment integrates multiple attenuation functions into one attenuation unit using a stacked transistor switch architecture, effectively reducing insertion loss and chip area while ensuring attenuation accuracy.

[0030] It should be noted that if there are more than three second transistor switches, as the remaining second transistor switches are turned on in sequence, the number of first attenuation adjustment branches connected in parallel to ground gradually increases, the signal shunt paths increase, the attenuation gradually increases, and multiple levels of bit attenuation are achieved.

[0031] Furthermore, such as Figure 5 As shown, the main switch branch 11 further includes an impedance sub-branch 15, which is connected in parallel with the first transistor switch; wherein, the impedance sub-branch 15 includes at least one impedance component, and if there are multiple impedance components, the multiple impedance components are connected in series; a second attenuation adjustment branch 14 is connected in series between the drain of the first second transistor switch and the main switch branch 11.

[0032] In detail, the main switch branch 11 is connected in parallel with the first transistor switch with an impedance sub-branch 15. The impedance sub-branch 15 is composed of at least one impedance component connected in series. When the first transistor switch is turned off and the structure enters the attenuation state, the impedance sub-branch 15 is connected in series in the main signal path and together with the parallel attenuation branch 12, it forms a voltage divider / current divider attenuation network to ensure port impedance matching in the attenuation state.

[0033] A second attenuation adjustment branch 14 is connected in series between the drain of the first second transistor switch and the connection node of the main switch branch 11. This second attenuation adjustment branch 14 serves as part of the series impedance of the parallel attenuation branch 12, and works in conjunction with the first attenuation adjustment branch to adjust the impedance parameters of the attenuation network, precisely setting the attenuation value for each attenuation level, while optimizing the port return loss characteristics. The impedance value of the impedance sub-branch 15 is matched with the impedance values ​​of each attenuation adjustment branch to ensure that the port impedance in the reference state and each attenuation state remains consistent with the system characteristic impedance.

[0034] In some embodiments, the number of parallel attenuation branches 12 is at least two; At least one impedance unit formed by at least one impedance component is provided between two adjacent parallel attenuation branches 12; The first end of the impedance unit is connected to the first end of the first second attenuation adjustment branch, and the second end of the impedance unit is connected to the first end of the second second attenuation adjustment branch. The second terminal of the first second attenuation adjustment branch and the second terminal of the second second attenuation adjustment branch are respectively connected to the drain of their respective first second transistor switch M121; The first second attenuation adjustment branch is one of the two adjacent parallel attenuation branches 12, and the second second attenuation adjustment branch is the other of the two adjacent parallel attenuation branches 12.

[0035] Specifically, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the second structure of the numerically controlled attenuation structure provided in the embodiments of the present invention, as shown below. Figure 6 As shown, the number of parallel attenuation branches 12 is illustrated using two as an example. Figure 6The main switch branch 11 includes a first transistor switch M11; two parallel attenuation branches 12 are connected between the main switch branch 11 and the reference ground; each parallel attenuation branch 12 includes multiple stacked and connected in series second transistor switches; the drain of the first second transistor switch M121 among all the second transistor switches is connected in series with the main switch branch 11 via a second attenuation adjustment branch 14; the drains of the remaining second transistor switches (denoted as M122 to M12n in the figure) are all connected in parallel to the first attenuation adjustment branch 13 of the reference ground.

[0036] Among them, such as Figure 6 As shown, the first attenuation adjustment branch 13 includes a first attenuation adjustment component, which serves as a shunt impedance to determine the attenuation amount for the corresponding level, and / or, each second attenuation adjustment branch includes a second attenuation adjustment component, which serves as a shunt impedance to determine the attenuation amount for the corresponding level. The first attenuation adjustment component, the second attenuation adjustment component, and the impedance component are all passive resistors; or, the first attenuation adjustment component, the second attenuation adjustment component, and the impedance component are all MOSFET impedance components; or, a portion of the first attenuation adjustment component, the second attenuation adjustment component, and the impedance component are passive resistors, and another portion are MOSFET impedance components; wherein, the MOSFET impedance component is configured to adjust the MOSFET's on-resistance by adjusting the voltage applied to the MOSFET's gate.

[0037] In other words, the various impedance elements constituting the attenuation network can be implemented in multiple ways. When using passive resistors, the resistance value is fixed, the circuit structure is simple, and the stability is high, making it suitable for scenarios with high temperature stability requirements. When using MOSFET impedance components, the on-resistance value of the MOSFET can be changed by applying an adjustable control voltage to the MOSFET gate, thereby dynamically adjusting the impedance parameters of the attenuation network.

[0038] In practical applications, passive resistors, MOSFET impedance components, or a combination thereof can be used. By adjusting the gate voltage of the MOSFET, impedance drift caused by process deviations and temperature changes can be corrected, compensating for the impact of PVT (process, voltage, temperature) fluctuations on attenuation accuracy and matching characteristics, and improving the performance stability of the attenuator under different environments.

[0039] Figure 6 The following explanation is based on the example where the first attenuation adjustment component, the second attenuation adjustment component, and the impedance component are all passive resistors. The number of impedance components is taken as two, denoted as the first passive resistor R21 and the second passive resistor R22, respectively. In practical applications, there can be one or more.

[0040] One end of the first passive resistor R21 is connected to the source of the first transistor switch M11, and also to one end of the passive resistor R121 of the second attenuation adjustment component in the first parallel attenuation branch 12 (input-side branch). The other end of the first passive resistor R21 is connected to one end of the second passive resistor R22. The other end of the second passive resistor R22 is connected to the drain of the first transistor switch M11, and also to one end of the passive resistor R121 of the second attenuation adjustment component in the second parallel attenuation branch 12. For the two parallel attenuation branches 12, their internal structure is the same: the other end of the passive resistor R121 of the second attenuation adjustment component in each branch is connected to the drain of the first second transistor switch M121 in that branch. Subsequently, multiple second transistor switches M12 in each branch are connected in series in a stacked manner, that is, the source of the first second transistor switch is connected to the drain of the second second transistor switch, the source of the second second transistor switch is connected to the drain of the third second transistor switch, and so on, which will not be described in detail here.

[0041] In these stacked transistor switches, the drain of the first second transistor switch M121 is not directly connected to the main switch branch 11, but is connected through a passive resistor R121 of a second attenuation adjustment component. Its main function is to set the basic impedance matching relationship between the signal path and the ground branch in the attenuation state, and its resistance value directly affects the starting point of the attenuation. At the same time, in the same parallel attenuation branch 12, except for the first second transistor switch M121, the drain of each of the other second transistor switches M12j (j=2,3,…,n) is connected to a passive resistor to ground through an independent passive resistor of a first attenuation adjustment component. The passive resistors of each first attenuation adjustment component in the figure can be denoted as R122, R123,…, R12n. The resistance values ​​of these passive resistors of the first attenuation adjustment components can be the same, or they can be set according to a specific rule (such as binary weight or hot code weight). They together determine the attenuation step value that can be increased by turning on each additional stacked transistor switch.

[0042] The operating mode of the entire numerically controlled attenuation structure is determined by the on / off states of all its internal transistor switches. By controlling different combinations of the first transistor switch M11 and the second transistor switch, the structure can be made to behave as a reference state with virtually no attenuation, or as an attenuation state that attenuates the signal by a specific amount. When in the attenuation state, by changing the on / off combination of the stacked second transistor switches, this single attenuation unit can produce a variety of different bit attenuation outputs.

[0043] Specifically, the operating state of the numerically controlled attenuation structure can be determined; wherein the operating state includes a reference state or an attenuation state; when the numerically controlled attenuation structure is operating in the attenuation state, the numerically controlled attenuation structure outputs the corresponding bit attenuation amount according to the preset attenuation requirements.

[0044] The process of determining the working state of the numerically controlled attenuation structure may include: The operating states of the first transistor switch M11 and the second transistor switch in the numerically controlled attenuation structure are obtained. The operating states of the first transistor switch M11 and the second transistor switch include being on and off. The operating state of the numerically controlled attenuation structure is determined based on the operating state of the first transistor switch M11 and the operating state of the second transistor switch. Specifically, when the first transistor switch M11 is turned on and all the second transistor switches are turned off, the numerically controlled attenuation structure is determined to be operating in the reference state. When the first transistor switch M11 is in the off state and at least one second transistor switch is in the on state, the numerically controlled attenuation structure is determined to be operating in the attenuation state.

[0045] Furthermore, the process of controlling the bit attenuation amount output by the numerically controlled attenuation structure according to the preset attenuation requirements may include: According to the preset attenuation requirement, at least a portion of the second transistor switches are turned on so that the numerically controlled attenuation structure outputs the corresponding bit attenuation amount.

[0046] In detail, in the reference state, the first transistor switch M11 is in the on state and all the second transistor switches are in the off state; in the attenuation state, the first transistor switch M11 is in the off state and at least one second transistor switch is in the on state, and the bit attenuation amount under different attenuation requirements corresponds to the number and combination of different on second transistor switches.

[0047] To achieve the reference state, a bias voltage is applied to the gate of the first transistor switch M11 in the main switching branch 11 to turn it on, while a bias voltage is applied to the gates of all stacked second transistor switches in all parallel attenuation branches 12 to turn them off completely. In this state, the RF signal is primarily transmitted to the output through the low-impedance main switching branch 11, while all attenuation branches connected to ground are in a high-impedance off state, thus minimizing signal loss; this is the reference state.

[0048] To achieve the attenuation state, the opposite operation is performed compared to the previous reference state: the first transistor switch M11 is turned off, forcing the signal to flow through the parallel attenuation branch 12 instead of the main switch branch 11. Simultaneously, depending on the required attenuation level, at least one stacked second transistor switch can be turned on. Different attenuation requirements correspond to different numbers and combinations of the second transistor switches that are turned on. For example, turning on a specific combination of transistor switches can produce a smaller attenuation, while turning on more or different combinations can produce a larger attenuation.

[0049] Furthermore, in the attenuation state, the first second transistor switch M121 is turned on while the remaining second transistor switches M12j (j=2, 3, ..., n) are turned off, so that the numerically controlled attenuation structure outputs the minimum attenuation requirement of bit attenuation. All second transistor switches are in the ON state, so that the numerically controlled attenuation structure outputs the maximum attenuation required bit attenuation amount. The remaining second transistor switches M12j are turned on sequentially, causing the numerically controlled attenuation structure to output the target attenuation requirement in bits; wherein, the target attenuation requirement in bits is located between the minimum attenuation requirement in bits and the maximum attenuation requirement in bits, and gradually increases with the number of remaining second transistor switches M12j that are turned on.

[0050] In detail, this embodiment further illustrates how to finely control the stacked second transistor switches to generate a series of discrete, incremental attenuation amounts. This numerically controlled attenuation structure can output a minimum attenuation amount. In this case, the first transistor switch M11 in the main switch branch 11 is turned off, and in the parallel attenuation branch 12, only the first second transistor switch M121 is turned on, while all other stacked second transistor switches M12j are turned off. This configuration provides the signal with a lowest-loss path to ground, thus generating the minimum attenuation achievable by this unit. This structure can also output a maximum attenuation amount. In this case, the first transistor switch M11 remains off, while all stacked second transistor switches M12j in a parallel attenuation branch 12 are turned on. The signal flows to ground through a low-resistance path consisting of multiple on-state transistor switches and parallel resistors, thereby obtaining the maximum attenuation achievable by this unit.

[0051] For a target attenuation amount between the minimum and maximum attenuation, this can be achieved by sequentially turning on the remaining second transistor switches M12j. Specifically, while keeping the first second transistor switch M121 on, the remaining second transistor switches M12 are turned on gradually, starting from the closest to the first switch and moving away from it. With each additional transistor switch turned on, the signal path impedance decreases, and more signal is shunted to ground. This allows the attenuation to gradually and precisely increase from its minimum value as the number of turned-on transistor switches increases, until it reaches its maximum value.

[0052] Specifically, taking a two-bit digitally controlled attenuation structure unit as an example, Figures 7a to 7d This shows the equivalent circuit diagrams for the reference state and different decay states. Figure 7a The equivalent circuit in the reference state is shown. In this state, the first transistor switch M11 is on, equivalent to the on-resistance Ron11; all second transistor switches M121, M122, and M123 are off, equivalent to the off-capacitors Coff121, Coff122, and Coff123, respectively. The passive resistors R122 and R123 of the second attenuation adjustment component are not connected to the circuit. In this state, the digitally controlled attenuation structure operates in the reference state, and the signal is transmitted through the low-impedance path formed by the first transistor switch M11, minimizing insertion loss.

[0053] Figure 7b The equivalent circuit for the first attenuation state is shown. In this state, the first transistor switch M11 is off, equivalent to a turn-off capacitor Coff11; the first second transistor switch M121 is on, equivalent to an on-resistance Ron121; the remaining second transistor switches M122 and M123 are off, equivalent to turn-off capacitors Coff122 and Coff123, respectively. This configuration corresponds to the minimum bit attenuation required by the attenuation unit.

[0054] Figure 7c The equivalent circuit for the second decay state is shown. In this state, the first transistor switch M11 is off, equivalent to a turn-off capacitor Coff11; the first and second second transistor switches M121 and M122 are on, equivalent to on-resistances Ron121 and Ron122 respectively; and the third second transistor switch M123 is off, equivalent to a turn-off capacitor Coff123. This configuration produces an intermediate bit decay amount between the minimum and maximum decay requirements.

[0055] Figure 7dThe equivalent circuit for the maximum attenuation state is shown. In this state, the first transistor switch M11 is off, equivalent to the off-state capacitor Coff11. The first second transistor switch M121, the second second transistor switch M122, and the third second transistor switch M123 are all on, equivalent to the on-resistances Ron121, Ron122, and Ron123, respectively. This configuration corresponds to the maximum bit attenuation required by the attenuation unit.

[0056] Through the above four states, this single digitally controlled attenuation structure can output multiple attenuation levels of 1dB, 2dB, and 3dB, fully realizing the function that originally required two traditional attenuation units to be cascaded. Thus, without changing the attenuation accuracy and attenuation range, the insertion loss of the multi-bit digitally controlled attenuation structure is reduced, the chip area is reduced, and the integration is improved. In one specific implementation, the first second transistor switch M121 has the largest gate width to carry higher transient currents and maintain a low bias voltage drop; the gate widths of the remaining second transistor switches decrease stepwise to reduce parasitic capacitance to ground relative to the reference ground.

[0057] In detail, in the attenuation state, when the signal flows through the parallel attenuation branch 12, the first second transistor switch M121 (the one closest to the main signal path) directly handles the vast majority of the signal current, and its voltage swing is also the largest. Therefore, this transistor switch is designed to have a relatively large gate width, making the second transistor switch M121 less affected by the voltage swing and thus improving its reliability. For the remaining second transistor switches in this branch, which are further away from the main signal path and closer to the reference ground, the signal current and voltage swing they handle decrease progressively, and the gate widths of these transistor switches are set to decrease progressively. A smaller gate width means smaller parasitic capacitance of the transistor switches, especially the parasitic capacitance to ground. Reducing these parasitic capacitances can effectively reduce high-frequency leakage of the signal path to ground in the attenuation state, thereby improving the attenuation flatness and phase characteristics of the numerically controlled attenuation structure in the high-frequency band (such as millimeter waves).

[0058] This embodiment employs a differentiated size design for the stacked transistor switches. The first transistor switch is large to optimize conduction performance and withstand high current, while subsequent transistor switches adopt progressively smaller sizes to reduce parasitic capacitance. This approach optimizes the high-frequency characteristics while ensuring the core performance (insertion loss and power capacity) of the numerically controlled attenuation structure, achieving a balance between performance and parasitic parameters.

[0059] In a specific implementation, the numerical control attenuation structure may also include a logic control drive branch (not shown in the figure). The logic control drive branch includes a logic decoding module and a level conversion module; The logic decoding module is connected to the level conversion module; The level conversion module is connected to the control electrode of the first transistor switch M11 and the control electrode of the second transistor switch; The logic decoding module is configured to receive digital control signals transmitted from the system bus and convert the digital control signals into the first transistor switch M11 and the selection signals corresponding to each of the second transistor switches. The level conversion module is configured to output a corresponding bias voltage to the first transistor switch M11 and each of the second transistor switches based on the gating signal, so that the first transistor switch M11 and each of the second transistor switches are turned on or off.

[0060] In detail, this logic control drive branch mainly consists of two parts: a logic decoding module and a level conversion module. The input of the logic decoding module is connected to the system's control bus (such as SPI, MIPI RFFE, etc.) to receive digital control signals (e.g., a string of binary code) representing the desired attenuation. The logic decoding module internally includes a lookup table or combinational logic circuit that decodes the received digital codewords into independent, active-high gating signals for each transistor switch (including the main switch and all stacked switches). These gating signals are digital logic levels (e.g., 0 / 1.2V), which are insufficient to directly drive the RF transistor switches. Therefore, these gating signals are sent to the level conversion module. The level conversion module internally includes multiple level conversion units, each of which converts the input digital logic level into a bias voltage with positive or negative voltage (e.g., +1.2V for on, -1.2V for off) that can precisely control the transistor switch's on or off state. The output of the level conversion module is directly connected to the gate (control electrode) of the first transistor switch M11 and all the second transistor switches M12. By applying the correct bias voltage, the turn-on or turn-off operation is precisely performed.

[0061] Furthermore, in active phased array systems, the numerically controlled attenuation structure is responsible for precisely adjusting the signal amplitude of each channel for amplitude weighting, thereby reducing the antenna's sidelobe level and improving anti-interference capability. Together with the numerically controlled phase shifter, it forms the core of beam control. Ideally, the numerically controlled attenuation structure only changes the signal amplitude without altering the signal phase. However, in actual physical implementation, different switching capacitors exist when transistors switch states, causing additional phase shifts. When the switching transistors of the multi-bit numerically controlled unit switch between different attenuation states, the attenuation phase state is also different. Therefore, additional phase compensation is needed for the multi-bit attenuation numerically controlled unit, which has multiple attenuation states.

[0062] Figure 8 This is a schematic diagram of the third type of numerically controlled attenuation structure provided in the embodiments of the present invention, as shown below. Figure 8 As shown, phase compensation capacitors (i.e., the second capacitor C121 corresponding to the second attenuation adjustment component and the first capacitor corresponding to each of the first attenuation adjustment components, denoted as C12j, (j=2, 3, ..., n)) can be connected in parallel to the first attenuation adjustment component and the second attenuation adjustment component connected in parallel to ground, respectively, to achieve phase balance.

[0063] Its working principle is as follows: In the decay state, when a certain second transistor switch is turned on, the corresponding branch containing the first decay adjustment component is effectively short-circuited. This second transistor switch can be abstracted as a model of a parallel connection of a conducting resistance and a conducting capacitance, that is, in the decay state, the parallel branch includes capacitance. Therefore, when the branch containing the first decay adjustment component is visible, a parallel capacitor needs to be added for phase alignment to achieve phase compensation.

[0064] This embodiment achieves phase balance of the multi-bit digital controlled attenuation unit when switching between different attenuation states by connecting phase compensation capacitors in parallel to each attenuation adjustment component connected to ground. This effectively solves the phase error caused by the parasitic capacitance change of each branch switch tube and avoids the deterioration of the phased array directivity.

[0065] Furthermore, there are multiple first capacitors C12j and multiple second capacitors C121. The first attenuation adjustment branch 13 also includes a first switch connected in series with each of the first capacitors C12j; each of the second attenuation adjustment branches also includes a second switch connected in series with each of the second capacitors C121. The first switch is configured to, when turned on, connect the corresponding first capacitor C12j in parallel to the two ends of the corresponding first attenuation adjustment branch 13, so as to adjust the total compensation capacitance value connected in parallel to the two ends of the first attenuation adjustment branch 13. The second switch is configured to, when turned on, connect the corresponding second capacitor C121 in parallel across the two ends of the corresponding second attenuation adjustment branch, so as to adjust the total compensation capacitance value connected in parallel across the two ends of the second attenuation adjustment branch.

[0066] In detail, due to process variations or parasitic effects, a fixed capacitance value may not be able to accurately compensate for phase deviations at different process angles. By setting multiple capacitor units in series with corresponding switches, different numbers of switches can be selectively turned on according to actual needs, thereby connecting different numbers of sub-capacitors in parallel across the attenuation adjustment component, achieving flexible adjustment of the total compensation capacitance value. This adjustable capacitor array structure further improves the accuracy of phase compensation and can adapt to a wider range of process variations and frequency changes. The capacitance value of each capacitor is set according to binary weights, allowing for a wider range of capacitance value settings using a small number of capacitors. For example, setting capacitance values ​​of 1fF, 2fF, 4fF, and 8fF can achieve capacitance values ​​from 1fF to 16fF.

[0067] This embodiment achieves flexible configuration of phase compensation by setting an adjustable capacitor array, further improving the phase consistency of the multi-bit digitally controlled attenuation structure under different process angles and frequencies. In active phased array systems, the digitally controlled attenuation structure needs to maintain stable attenuation accuracy under different temperature environments. Traditional temperature compensation schemes adjust the on-resistance of the series-connected and parallel-connected transistor switches using two control voltages to offset the changes in insertion loss and attenuation caused by temperature variations. However, this temperature compensation method ignores the characteristics of the passive resistors in the attenuation network that fluctuate with process, voltage, and temperature (PVT). When adjusting the on-state transistor switch voltage in the reference or attenuation state, the change in resistance on another branch is ignored, leading to a deterioration in attenuator matching, which is unacceptable in phased array systems with high matching requirements. Therefore, to solve the above problems, MOSFET impedance components can be used to replace traditional passive resistors.

[0068] Figure 9 This is a schematic diagram of the fourth type of numerically controlled attenuation structure provided in the embodiments of the present invention, as shown below. Figure 9 As shown, in this embodiment... Figure 6 Based on the above, MOSFET impedance components are used to replace traditional passive resistors. The two MOSFET impedance components in impedance sub-branch 15 are denoted as the first MOSFET impedance component MR21 and the second MOSFET impedance component MR22, respectively. The MOSFET impedance component of the second attenuation adjustment component is denoted as MR121, and the MOSFET impedance components of the first attenuation adjustment component are denoted as MR122, ..., MR12n, respectively. An independent control voltage is applied to the gate of each MOSFET impedance component. By adjusting this control voltage, the on-resistance value of the MOSFET can be changed. When the PVT condition changes, by adjusting the control voltage applied to the gate of the MOSFET impedance component, its on-resistance can be dynamically adjusted, thereby compensating for the impedance shift caused by the PVT change.

[0069] Specifically, the control voltage can be generated by an on-chip detection circuit that monitors changes in temperature, power supply voltage, or process parameters in real time and adjusts the control voltage accordingly. When the temperature rises, causing the on-resistance of the MOSFET to increase, the control voltage can be increased to reduce the on-resistance; conversely, when the temperature decreases, the control voltage can be decreased to increase the on-resistance, thereby maintaining the impedance matching and attenuation accuracy of the attenuation network.

[0070] This embodiment achieves effective compensation for PVT fluctuations by using a MOS transistor impedance component to replace the passive resistor and applying an independent control voltage for dynamic adjustment. This improves the attenuation accuracy and impedance matching performance of the numerically controlled attenuation structure under different temperature, voltage and process conditions, and enhances the environmental adaptability and reliability of the system.

[0071] Figure 10 This is a schematic diagram of the fifth type of numerically controlled attenuation structure provided in this embodiment of the invention. For example... Figure 10 As shown, the numerically controlled attenuation structure provided in this embodiment of the invention takes a T-shaped structure as an example. In this structure, the number of parallel attenuation branches 12 is 1; the number of impedance components is at least 2, and at least one node is included between the first impedance component and the last impedance component; one of the at least one nodes is connected to the first end of the second attenuation adjustment branch; the second end of the second attenuation adjustment branch is connected to the drain of the first second transistor switch.

[0072] In detail, this embodiment adopts a single parallel attenuation branch 12 architecture. The impedance sub-branch 15 is composed of at least two impedance components connected in series, and the entire series connection is connected in parallel with the first transistor switch. An intermediate node is led out between the series impedance components, and the first end of the second attenuation adjustment branch 14 is connected to this intermediate node, rather than the two ends of the main switch branch 11.

[0073] In this structure, during the attenuation state, the signal passes through the first half of the impedance component in the impedance sub-branch 15, then connects to the second attenuation adjustment branch 14 and the parallel attenuation branch 12 via an intermediate node, and is output through the second half of the impedance component in the impedance sub-branch 15. By selecting intermediate nodes at different positions, the impedance ratio connected in series in the attenuation network can be flexibly adjusted, adapting to different attenuation design requirements and optimizing the impedance matching effect during attenuation without changing the total number of impedance components.

[0074] like Figure 10As shown, the diagram illustrates a configuration with two impedance components, both of which are passive resistors (denoted as the first source resistor R21 and the second source resistor R22). The specific connections are as follows: one end of the first passive resistor R21 is connected to the source of the first transistor switch M11. The other end of the first passive resistor R21 and one end of the second passive resistor R22 serve as an intermediate node, connected to one end of the first passive resistor R21. The other end of the second passive resistor R22 is connected to the drain of the first transistor switch M11. In the parallel attenuation branch 12, the other end of the first passive resistor R21 is connected to the drain of the first second transistor switch M121. Subsequently, multiple second transistor switches M12 are connected in series in a stacked manner, i.e., the source of the first transistor switch is connected to the drain of the second transistor switch, the source of the second transistor switch is connected to the drain of the third transistor switch, and so on. The drain of each subsequent transistor switch is connected to ground through the passive resistor R12n of its respective first attenuation adjustment component.

[0075] Figure 11 This is a schematic diagram of the sixth type of numerically controlled attenuation structure provided in this embodiment of the invention. For example... Figure 11 As shown, the numerically controlled attenuation structure provided in this embodiment of the invention... Figure 10 A phase compensation capacitor was added to the original design. The component labels, connections, and operating principles in the diagram can be found in the previous section. Figure 8 and Figure 10 The relevant records will not be repeated here.

[0076] Figure 12 This is a schematic diagram of the seventh type of numerically controlled attenuation structure provided in this embodiment of the invention. For example... Figure 12 As shown, the numerically controlled attenuation structure provided in this embodiment of the invention... Figure 10 Based on this, passive resistors are replaced by MOSFET impedance components. The component labels, connection relationships, and principles in the diagram can be referred to the aforementioned... Figure 9 and Figure 11 The relevant records will not be repeated here.

[0077] Based on the same general inventive concept, this invention also protects an RF attenuator. The RF attenuator provided by this invention is described below, and the RF attenuator described below can be referred to in correspondence with the numerically controlled attenuation structure described above. The RF attenuator may include at least the multi-bit numerically controlled attenuation structure of the above embodiments. When there are multiple multi-bit numerically controlled attenuation structures, the multi-bit numerically controlled attenuation structures are cascaded sequentially.

[0078] In detail, the core component of this attenuator is at least one numerically controlled attenuation structure as described above. Different configurations can be used depending on the system's requirements for attenuation range (maximum attenuation) and attenuation step (minimum adjustment precision). If the required attenuation range and step can be provided by a single numerically controlled attenuation structure, then the RF attenuator only needs to include this one unit. If a larger attenuation range or finer step is required, multiple numerically controlled attenuation structures can be cascaded, with the output of one structure connected to the input of the next. For example, a single-stage unit providing 0-7.5dB attenuation with a 0.5dB step can be cascaded with another single-stage unit providing 0-15dB attenuation with a 1dB step, thus creating an RF attenuator with a larger total attenuation range (0-22.5dB) and finer step (0.5dB).

[0079] This embodiment allows for the easy construction of attenuator products that meet the needs of different systems, whether used individually or cascaded in multiples, covering a wide range of application scenarios from small terminals to large phased array radars.

[0080] This invention also provides a control method for a multi-bit numerically controlled attenuation structure. Figure 13 This is a flowchart illustrating the control method of the multi-bit numerically controlled attenuation structure of the present invention, as shown below. Figure 13 As shown, the control method for this multi-bit numerically controlled attenuation structure mainly includes the following steps: 1301. Determine the working state of the numerically controlled attenuation structure; The operating state includes a reference state or a decay state; this step can be implemented in the following way: The operating states of the first transistor switch and the second transistor switch in the numerically controlled attenuation structure are obtained, and the operating states of the first transistor switch and the second transistor switch include on and off. The operating state of the numerically controlled attenuation structure is determined based on the operating states of the first transistor switch and the second transistor switch. Specifically, when the first transistor switch is on and all second transistor switches are off, the numerically controlled attenuation structure is determined to be operating in the reference state. When the first transistor switch is in the off state and at least one second transistor switch is in the on state, the numerically controlled attenuation structure is determined to be operating in the attenuation state.

[0081] 1302. When the numerically controlled attenuation structure is working in the attenuation state, the numerically controlled attenuation structure is controlled to output the corresponding bit attenuation amount according to the preset attenuation requirements.

[0082] Specifically, at least a portion of the second transistor switches can be turned on according to the preset attenuation requirements, so that the numerically controlled attenuation structure outputs the corresponding bit attenuation amount.

[0083] Specifically, when the preset attenuation requirement is the minimum attenuation requirement, the first second transistor switch is turned on and the remaining second transistor switches are turned off, so that the numerically controlled attenuation structure outputs the bit attenuation amount corresponding to the minimum attenuation requirement. When the preset attenuation requirement is the maximum attenuation requirement, all second transistor switches are controlled to be turned on, so that the numerically controlled attenuation structure outputs the bit attenuation amount corresponding to the maximum attenuation requirement. When the first second transistor switch is turned on, the bit attenuation of the numerically controlled attenuation structure is gradually increased by controlling the remaining second transistor switches to turn on in sequence, and the bit attenuation gradually increases with the number of remaining second transistor switches turned on.

[0084] It should be noted that the specific implementation process of the control method of the above-mentioned multi-bit numerically controlled attenuation structure can be found in the aforementioned relevant records, and will not be repeated here.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-bit digitally controlled attenuation structure, characterized in that, include: The main switch branch includes the first transistor switch; At least one parallel attenuation branch is connected between the main switch branch and the reference ground; Multiple first attenuation adjustment branches are connected between the parallel attenuation branches and the reference ground; The parallel attenuation branch includes multiple stacked and connected in series second transistor switches; the drains of all second transistor switches except the first second transistor switch are respectively connected to a first attenuation adjustment branch and connected to a reference ground via the first attenuation adjustment branch; wherein the first second transistor switch is the second transistor switch closest to the main switch branch. The numerically controlled attenuation structure is configured to operate in a reference state or an attenuation state by controlling the operating states of the first transistor switch and the second transistor switch. Specifically, when the first transistor switch is off, the numerically controlled attenuation structure outputs a bit attenuation amount corresponding to different preset attenuation requirements by controlling the operating state of the second transistor switch in each of the parallel attenuation branches. The operating states of the first transistor switch and the second transistor switch include on or off.

2. The multi-bit numerically controlled attenuation structure according to claim 1, characterized in that, The main switch branch further includes an impedance sub-branch connected in parallel with the first transistor switch; wherein, the impedance sub-branch includes at least one impedance component, and if there are multiple impedance components, the multiple impedance components are connected in series. A second attenuation adjustment branch is connected in series between the drain of the first second transistor switch and the main switch branch.

3. The multi-bit numerically controlled attenuation structure according to claim 2, characterized in that, The number of parallel attenuation branches is 1; the number of impedance components is at least 2, and there is at least one node between the first impedance component and the last impedance component. One of the at least one nodes is connected to the first end of the second attenuation adjustment branch; The second end of the second attenuation adjustment branch is connected to the drain of the first second transistor switch.

4. The multi-bit numerically controlled attenuation structure according to claim 2, characterized in that, The number of parallel attenuation branches is at least two; At least one impedance unit formed by at least one impedance component shall be provided between two adjacent parallel attenuation branches; The first end of the impedance unit is connected to the first end of the first second attenuation adjustment branch, and the second end of the impedance unit is connected to the first end of the second second attenuation adjustment branch. The second terminal of the first second attenuation adjustment branch and the second terminal of the second second attenuation adjustment branch are respectively connected to the drain of their respective first second transistor switches; The first second attenuation adjustment branch is one of the two adjacent parallel attenuation branches, and the second second attenuation adjustment branch is the other of the two adjacent parallel attenuation branches.

5. The multi-bit numerically controlled attenuation structure according to claim 2, characterized in that, The first attenuation adjustment branch includes a first attenuation adjustment component, or a first attenuation adjustment component and at least one first capacitor connected in parallel with the first attenuation adjustment component; And / or, each of the second attenuation adjustment branches includes a second attenuation adjustment component, or, the second attenuation adjustment component and at least one second capacitor connected in parallel with the second attenuation adjustment component.

6. The multi-bit numerically controlled attenuation structure according to claim 5, characterized in that, The number of the first capacitor and the number of the second capacitor are both multiple; The first attenuation adjustment branch also includes a first switch connected in series with each of the first capacitors; Each of the second attenuation adjustment branches also includes a second switch connected in series with each of the second capacitors; The first switch is configured to, when turned on, connect the corresponding first capacitor in parallel to both ends of the corresponding first attenuation adjustment branch, so as to adjust the total compensation capacitor value connected in parallel to both ends of the first attenuation adjustment branch. The second switch is configured to, when turned on, connect the corresponding second capacitor in parallel across the two ends of the corresponding second attenuation adjustment branch, so as to adjust the total compensation capacitor value connected in parallel across the two ends of the second attenuation adjustment branch.

7. The multi-bit numerically controlled attenuation structure according to claim 5 or 6, characterized in that, The first attenuation adjustment component, the second attenuation adjustment component, and the impedance component are all passive resistors; Alternatively, the first attenuation adjustment component, the second attenuation adjustment component, and the impedance component are all MOSFET impedance components; or, a portion of the first attenuation adjustment component, the second attenuation adjustment component, and the impedance component is a passive resistor, and the other portion is a MOSFET impedance component. The MOS transistor impedance component is configured to adjust the on-resistance of the MOS transistor by adjusting the voltage applied to the gate of the MOS transistor.

8. The multi-bit numerically controlled attenuation structure according to claim 1, characterized in that, The gate width of the first second transistor switch is greater than the gate width of each of the remaining second transistor switches. The gate width of each of the remaining second transistor switches decreases progressively.

9. A radio frequency attenuator, characterized in that, Includes at least one multi-bit numerically controlled attenuation structure as described in any one of claims 1-8; When there are multiple numerically controlled attenuation structures for the multi-bit bits, the numerically controlled attenuation structures for each multi-bit bit are cascaded sequentially.

10. A control method for a multi-bit numerically controlled attenuation structure as described in any one of claims 1-8, characterized in that, include: Determine the operating state of the numerically controlled attenuation structure; wherein the operating state includes a reference state or an attenuation state; When the numerically controlled attenuation structure is operating in the attenuation state, the numerically controlled attenuation structure outputs the corresponding bit attenuation amount according to the preset attenuation requirements.

11. The control method for the multi-bit numerically controlled attenuation structure according to claim 10, characterized in that, Determining the operating state of the numerically controlled attenuation structure includes: The operating states of the first transistor switch and the second transistor switch in the numerically controlled attenuation structure are obtained, and the operating states of the first transistor switch and the second transistor switch include on and off. The operating state of the numerically controlled attenuation structure is determined based on the operating states of the first transistor switch and the second transistor switch. Specifically, when the first transistor switch is on and all second transistor switches are off, the numerically controlled attenuation structure is determined to be operating in the reference state. When the first transistor switch is in the off state and at least one second transistor switch is in the on state, the numerically controlled attenuation structure is determined to be operating in the attenuation state.

12. The control method for the multi-bit numerically controlled attenuation structure according to claim 10, characterized in that, The numerically controlled attenuation structure is controlled to output the corresponding bit attenuation amount according to the preset attenuation requirements, including: According to the preset attenuation requirement, at least some of the second transistor switches in the numerically controlled attenuation structure are turned on, so that the numerically controlled attenuation structure outputs the corresponding bit attenuation amount.

13. The control method for the multi-bit numerically controlled attenuation structure according to claim 12, characterized in that, According to the preset attenuation requirement, controlling at least a portion of the second transistor switches to be turned on includes: When the preset attenuation requirement is the minimum attenuation requirement, the first second transistor switch is turned on and the remaining second transistor switches are turned off, so that the numerically controlled attenuation structure outputs the bit attenuation amount corresponding to the minimum attenuation requirement. When the preset attenuation requirement is the maximum attenuation requirement, all second transistor switches are controlled to be turned on, so that the numerically controlled attenuation structure outputs the bit attenuation amount corresponding to the maximum attenuation requirement. When the first second transistor switch is turned on, the bit attenuation of the numerically controlled attenuation structure is gradually increased by controlling the remaining second transistor switches to turn on in sequence, and the bit attenuation gradually increases with the number of remaining second transistor switches turned on.

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