Radiation-hardened latch and successive approximation analog-to-digital converter

Abstract

This disclosure relates to the field of integrated circuit technology, and in particular to a radiation-hardened latch and a successive approximation analog-to-digital converter. The latch includes: a storage core module comprising multiple storage nodes, wherein when any one of the storage nodes fails due to a single-event upset, the non-flipped storage nodes have the ability to restore the faulty storage node to normal; an input module for configuring the level state of each storage node with the input signal; a storage node reset module for resetting the level state of each storage node under the control of a switch reset signal; a hold mode control module for controlling the latch to enter or exit hold mode; and an output module for outputting the latch signal. The latch of this disclosure embodiment has high fault tolerance and low latency, therefore, the latch of this disclosure embodiment can balance high-speed transmission and fault-tolerant storage.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a radiation-hardened latch and a successive approximation analog-to-digital converter. Background Technology

[0002] Successive Approximation Register Analog-to-Digital Converters (SAR ADCs) have become the preferred architecture for analog-to-digital conversion in space electronic equipment due to their predominantly digital circuitry and excellent energy efficiency. Figure 1 As shown. In SAR ADC, the asynchronous SAR logic circuit is the core digital control module, responsible for generating the digital-to-analog converter (DAC) switching control signal based on the comparator's decision result, and latching and transmitting the quantization result of each bit.

[0003] SAR logic circuits mainly consist of latches and D flip-flops.

[0004] In asynchronous SAR ADCs, in write mode, the latch passes the latest decision result of the comparator to the subsequent logic path, requiring low latency to accelerate the successive approximation process; in hold mode, the latch needs to stably store the determined decision result to prevent erroneous flipping due to subsequent circuit switching or noise coupling.

[0005] In the radiation environment of space, memory cells such as D flip-flops and latches face a serious threat from Single-Event Effect (SEE). Specifically, in Transparent Mode, high-energy particle incidentions may induce a Single-Event Transient (SET) pulse at the latch input. If this transient pulse arrives within the latch's transparent window, it may be incorrectly latched as valid data, causing errors in the successive approximation decisions of all subsequent bits. In Hold Mode, high-energy particles directly bombarding the latch's memory nodes may trigger a Single-Event Upset (SEU), or even a Multiple-Node Upset (MNU) due to charge-sharing effects, such as a Double-Node Upset (DNU), causing the latched decision results to be flipped.

[0006] Because the successive approximation process of SAR ADC has a causal dependency—that is, the decision of subsequent bits depends on the decision of previous bits—a single latching error will lead to an error in the quantization result of the entire conversion cycle, and the error magnitude may cover multiple most significant bits (MSB), which has a very serious impact on system performance.

[0007] Therefore, designing a fault-tolerant latch that can tolerate SET in transparent mode and SEU in hold mode is crucial for ensuring the reliable operation of SAR ADCs in radiation environments. At the same time, considering the stringent conversion speed requirements of SAR ADCs, this latch must provide fault tolerance while minimizing the delay impact on critical timing paths. Summary of the Invention

[0008] In view of this, the present disclosure proposes a radiation-hardened latch, the latch comprising:

[0009] The storage core module includes multiple storage nodes. When any one of the storage nodes fails due to a single-event flip, the storage nodes that have not flipped have the ability to restore the faulty storage node to normal.

[0010] An input module is connected to each storage node. The input module is used to receive input signals and to configure the level state of each storage node under the control of an input switch control signal.

[0011] The storage node reset module is connected to each storage node and is used to reset the level state of each storage node under the control of the switch reset signal.

[0012] A hold mode control module, connected to the storage core module, is used to control the latch to enter or exit hold mode;

[0013] An output module is connected to each storage node and the storage core module. The output module is used to output a latch signal at at least one output node according to the level state of each storage node.

[0014] In one possible implementation, the input module includes a first input unit and a second input unit, wherein the first input unit includes a first input transistor and a second input transistor, and the second input unit includes a third input transistor and a fourth input transistor, wherein...

[0015] The source of the first input transistor and the source of the third input transistor are both used to receive the negative differential signal of the input signal.

[0016] The source of the second input transistor and the source of the fourth input transistor are both used to receive the positive differential signal of the input signal.

[0017] The gates of both the first and second input transistors are used to receive the first switching control signal.

[0018] The gates of the third input transistor and the fourth input transistor are both used to receive the second switch control signal.

[0019] The drain of the first input transistor is connected to the first memory node.

[0020] The drain of the second input transistor is connected to the second memory node.

[0021] The drain of the third input transistor is connected to the third memory node.

[0022] The drain of the fourth input transistor is connected to the fourth memory node.

[0023] The first and third storage nodes are used to store the same level state, and the second and fourth storage nodes are used to store the same level state. The level states stored by the first and third storage nodes are different from the level states stored by the second and fourth storage nodes.

[0024] In one possible implementation, the storage node reset module includes a first reset transistor, a second reset transistor, a third reset transistor, and a fourth reset transistor, wherein,

[0025] The sources of the first reset transistor, the second reset transistor, the third reset transistor, and the fourth reset transistor are all used to receive the power supply voltage.

[0026] The drains of the first reset transistor, the second reset transistor, the third reset transistor, and the fourth reset transistor are respectively connected to the first memory node, the second memory node, the third memory node, and the fourth memory node.

[0027] The gates of both the first and second reset transistors are used to receive the first switch reset signal.

[0028] The gates of the third reset transistor and the fourth reset transistor are both used to receive the second switch reset signal.

[0029] In one possible implementation, the storage core module includes a first inverter, a second inverter, a third inverter, and a fourth inverter, wherein the first inverter and the fourth inverter both have pull-up active loads, and the second inverter and the third inverter both have pull-down active loads.

[0030] The positive power supply terminals of the first inverter, the second inverter, the third inverter, and the fourth inverter are all used to receive power supply voltage.

[0031] The negative power supply terminals of the first inverter, the second inverter, and the first terminal of the hold mode control module are connected together; the negative power supply terminals of the third inverter and the fourth inverter are connected to the second terminal of the hold mode control module.

[0032] The input terminal of the first inverter is connected to the second output node, the control terminal of the first inverter for the pull-up active load is connected to the second storage node, the output terminal of the first inverter is connected to the first storage node, and the control terminal of the first inverter for the pull-down path is connected to the fourth storage node.

[0033] The input terminal of the second inverter is connected to the first output node, the control terminal of the second inverter for the pull-down active load is connected to the third storage node, the output terminal of the second inverter is connected to the second storage node, and the control terminal of the second inverter for the pull-up path is connected to the first storage node.

[0034] The input terminal of the third inverter is connected to the second output node, the control terminal of the third inverter for the pull-down active load is connected to the second storage node, the output terminal of the third inverter is connected to the third storage node, and the control terminal of the third inverter for the pull-up path is connected to the fourth storage node.

[0035] The input terminal of the fourth inverter is connected to the first output node, the control terminal of the fourth inverter for pulling up the active load is connected to the third storage node, the output terminal of the fourth inverter is connected to the fourth storage node, and the control terminal of the fourth inverter for pulling down the path is connected to the first storage node.

[0036] In one possible implementation, the first inverter includes a first inverting transistor, a second inverting transistor, and a third inverting transistor. The source of the first inverting transistor serves as a negative power supply terminal, the gate of the first inverting transistor serves as a pull-down path control terminal, the common node of the drains of the first and second inverting transistors serves as an output terminal, the gate of the second inverting transistor serves as an input terminal, the gate of the third inverting transistor serves as a pull-up active load control terminal, the source of the third inverting transistor serves as a positive power supply terminal, and the source of the second inverting transistor is connected to the drain of the third inverting transistor.

[0037] The second inverter includes a fourth, a fifth, and a sixth inverting transistor. The source of the fourth inverting transistor serves as a negative power supply terminal, the gate of the sixth inverting transistor serves as a pull-up path control terminal, the common node of the drains of the fifth and sixth inverting transistors serves as an output terminal, the gate of the fifth inverting transistor serves as an input terminal, the gate of the fourth inverting transistor serves as a pull-down active load control terminal, the source of the sixth inverting transistor serves as a positive power supply terminal, and the drain of the fourth inverting transistor is connected to the source of the fifth inverting transistor.

[0038] The third inverter includes a seventh, an eighth, and a ninth inverting transistor. The source of the seventh inverting transistor serves as the negative power supply terminal, the gate of the ninth inverting transistor serves as the pull-up control terminal, the common node of the drains of the eighth and ninth inverting transistors serves as the output terminal, the gate of the eighth inverting transistor serves as the input terminal, the gate of the seventh inverting transistor serves as the pull-down control terminal for an active load, the source of the ninth inverting transistor serves as the positive power supply terminal, and the drain of the seventh inverting transistor is connected to the source of the eighth inverting transistor.

[0039] The fourth inverter includes a tenth inverter transistor, an eleventh inverter transistor, and a twelfth inverter transistor. The source of the tenth inverter transistor serves as a negative power supply terminal, the gate of the tenth inverter transistor serves as a pull-down path control terminal, the common node of the drains of the tenth and eleventh inverter transistors serves as an output terminal, the gate of the eleventh inverter transistor serves as an input terminal, the gate of the twelfth inverter transistor serves as a pull-up active load control terminal, the source of the twelfth inverter transistor serves as a positive power supply terminal, and the source of the eleventh inverter transistor is connected to the drain of the twelfth inverter transistor.

[0040] In one possible implementation, the hold mode control module includes a first hold control transistor, a second hold control transistor, a third hold control transistor, and a fourth hold control transistor, wherein,

[0041] The source of the first holding control transistor and the source of the third holding control transistor are grounded.

[0042] The drain of the first hold control transistor is connected to the source of the second hold control transistor, and the drain of the second hold control transistor serves as the first terminal of the hold mode control module.

[0043] The drain of the third hold control transistor is connected to the source of the fourth hold control transistor, and the drain of the fourth hold control transistor serves as the second terminal of the hold mode control module.

[0044] The gate of the first holding control transistor is used to receive the second switch reset signal.

[0045] The gate of the third holding control transistor is used to receive the first switch reset signal.

[0046] The gates of both the second and fourth holding control transistors are used to receive holding control signals.

[0047] In one possible implementation, the output module includes a first output unit and a second output unit.

[0048] The first input terminal and the second input terminal of the first output unit are respectively connected to the first storage node and the third storage node. The first output unit outputs a first output voltage through the first output node. When the level states of the first storage node and the third storage node are the same, the first output node follows the level states of the first storage node and the third storage node. When the level states of the first storage node and the third storage node are different, the first output node maintains the previous level state.

[0049] The first input terminal and the second input terminal of the second output unit are respectively connected to the second storage node and the fourth storage node. The second output unit outputs a second output voltage through the second output node. When the level states of the second storage node and the fourth storage node are the same, the second output node follows the level states of the second storage node and the fourth storage node. When the level states of the second storage node and the fourth storage node are different, the second output node maintains the previous level state.

[0050] In one possible implementation, the first output unit includes a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, and a sixth output transistor. The source of the first output transistor is grounded, the source of the fourth output transistor is connected to a power supply voltage, the gates of the first and third output transistors are connected to the first memory node, the gates of the second and fourth output transistors are connected to the third memory node, the drains of the first, second, and fifth output transistors are connected together, the drains of the second, third, and fifth output transistors are all connected to the second output node, the sources of the third, fourth, and sixth output transistors are connected together, the drain of the fifth output transistor is connected to a power supply voltage, and the drain of the sixth output transistor is grounded.

[0051] The second output unit includes a seventh output transistor, an eighth output transistor, a ninth output transistor, a tenth output transistor, an eleventh output transistor, and a twelfth output transistor. The source of the seventh output transistor is grounded, the source of the tenth output transistor is connected to a power supply voltage, the gates of the seventh and ninth output transistors are connected to the fourth storage node, the gates of the eighth and tenth output transistors are connected to the second storage node, the drains of the seventh, eighth, and eleventh output transistors are connected together, the drains of the eighth, ninth, eleventh, and twelfth output transistors are all connected to the first output node, the sources of the ninth, tenth, and twelfth output transistors are connected together, the drain of the eleventh output transistor is grounded, and the drain of the twelfth output transistor is connected to a power supply voltage.

[0052] In one possible implementation, the latch is applied in a successive approximation analog-to-digital converter, and the validity condition of the input switch control signal includes the validity of the output result of the comparator in the successive approximation analog-to-digital converter.

[0053] According to one aspect of this disclosure, a successive approximation analog-to-digital converter (ADC) is provided, the successive approximation ADC including a sample-and-hold circuit, a digital-to-analog converter, a comparator, and a successive approximation SAR logic circuit, wherein...

[0054] The sample-and-hold circuit is used to sample and hold the input analog signal.

[0055] The digital-to-analog converter is used to receive the intermediate digital code from the SAR logic circuit and convert it into a corresponding analog voltage.

[0056] The comparator is used to compare the amplitude of the input voltage sampled and held by the sample-and-hold circuit with the analog voltage output by the digital-to-analog converter, and output a decision result.

[0057] The SAR logic circuit is used to generate intermediate digital codes of corresponding bits based on the decision result of the comparator.

[0058] The SAR logic circuit includes multiple cascaded radiation-hardened latches.

[0059] In one possible implementation, each radiation-hardened latch includes a control signal generator, which comprises a first OR gate, a second OR gate, a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a first NOT gate, and a second NOT gate, wherein...

[0060] The two input terminals of the first OR gate are used to receive input signals. The output terminal of the first OR gate is connected to the first input terminal of the first NOR gate, and the output terminal of the first OR gate is used to output a holding control signal. The second and third input terminals of the first NOR gate are respectively connected to the first status signal output by the control signal generator of the previous stage latch and the valid signal corresponding to the decision result output by the comparator. The first NOR gate is used to output a first switch control signal.

[0061] The two inputs of the second OR gate are used to receive input signals. The output of the second OR gate is connected to the first input of the second NOR gate. The output of the second OR gate is used to output a holding control signal. The second and third inputs of the second NOR gate are respectively connected to the second status signal output by the control signal generator of the previous stage latch and the valid signal corresponding to the decision result output by the comparator. The second NOR gate is used to output a second switch control signal.

[0062] The first NOT gate is used to generate a first switch reset signal based on the first state signal output by the control signal generator of the previous stage latch.

[0063] The second NOT gate is used to generate a second switch reset signal based on the second state signal output by the control signal generator of the previous stage latch.

[0064] The first NAND gate is used to generate a first state signal for the current stage based on the output hold control signal and the first global reset signal.

[0065] The second NAND gate is used to generate a second state signal for the current stage based on the output hold control signal and the second global reset signal.

[0066] In the latch of this embodiment, when any one of the storage nodes in the storage core module fails due to a single-event flip, the storage nodes that have not flipped have the ability to restore the faulty storage node to normal. In this way, high fault tolerance can be achieved in various working states such as write mode and hold mode. Furthermore, each module of the latch of this embodiment is directly connected to each storage node, which can realize fast signal transmission and has low latency. Therefore, the latch of this embodiment can take into account both high-speed transmission and fault-tolerant storage.

[0067] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0068] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0069] Figure 1 A schematic diagram of a successive approximation analog-to-digital converter is shown;

[0070] Figure 2 This illustrates a radiation-hardened latch solution used in related technologies;

[0071] Figure 3 A schematic diagram of a radiation-hardened latch according to an embodiment of the present disclosure is shown;

[0072] Figure 4 A schematic diagram of the circuit structure of a radiation-hardened latch according to an embodiment of the present disclosure is shown;

[0073] Figure 5 A schematic diagram of a control signal generator according to an embodiment of the present disclosure is shown;

[0074] Figure 6 The diagram shows the working logic of the SAR logic circuit in the SAR ADC. Detailed Implementation

[0075] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0076] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0077] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0078] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are used only to distinguish one element / operation from another. Therefore, without departing from the teachings of the conception of embodiments of this disclosure, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0079] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0080] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0081] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant regions.

[0082] As described in the background section, designing a fault-tolerant latch that can tolerate SET in transparent mode and SEU in hold mode is crucial for ensuring the reliable operation of SAR ADC in a radiation environment. It is also of great significance to minimize the delay impact on critical timing paths while providing fault tolerance.

[0083] like Figure 2As shown in Scheme 1, the most widely used radiation-hardened latch design is to use Triple Modular Redundancy (TMR) for the latch. This involves using three identical latches to operate in parallel and outputting the final result through a majority voter. When a single latch is affected by radiation and flips, the correct outputs of the other two latches win the vote, thus shielding the error.

[0084] like Figure 2 As shown in Scheme 2, DICE (Dual Interlocked Storage Cell) is a classic SEU-resistant storage cell structure that achieves self-recovery from single-node flip-over through cross-coupled four-node redundant interlocking. Its core idea is to store data simultaneously on four nodes, and through bidirectional feedback, the remaining three nodes can recover the data after a single node flips. The DICE structure is widely used in SRAM storage cells and register cells.

[0085] like Figure 2 As shown in Scheme 3, radiation-hardened SRAM (Static Random Access Memory) cells (such as the We-Quatro structure and the SARP12T structure) represent another important SEU-resistant design paradigm. We-Quatro employs a four-node polarity hardening strategy: two nodes are surrounded by PMOS transistors (P-polarity hardening, which can only be flipped from 0 to 1 by high-energy particles), and the other two nodes are surrounded by NMOS transistors (N-polarity hardening, which can only be flipped from 1 to 0). This polarity hardening design significantly reduces the number of actual sensitive nodes (only some nodes are in a sensitive state when storing specific data), and, combined with cross-coupling feedback, achieves effective single-node flip-over self-recovery, exhibiting good radiation resistance and process variation tolerance in SRAM arrays.

[0086] Existing scheme 1 has significant drawbacks: First, the triple redundancy increases the latch circuit area by more than 300% (three latches plus voting circuit), and power consumption increases exponentially. Second, the voter itself is combinational logic, and the additional delay introduced in high-frequency asynchronous SAR logic will directly affect the conversion speed.

[0087] Existing Solution 2: The DICE structure primarily hardens for SEU (switching) events, offering limited protection against SET (transient) events. In transparent mode, DICE cannot effectively filter transient pulses at the input. Furthermore, DICE requires four storage nodes and a complex cross-coupling network, resulting in significant area and power consumption overhead for a SAR ADC latch that only needs to hold data within a single conversion cycle. Additionally, the DICE structure cannot harden the DNU (Data Numerical Unit).

[0088] Existing Solution 3: There are fundamental architectural differences between We-Quatro and similar radiation-hardened SRAM cells and the latch requirements in SAR ADCs: First, SRAM cells are static storage devices; data writing is completed within a specific write cycle via word lines (WL) and bit lines (BL), lacking an asynchronous dynamic switching mechanism between write and hold modes. Second, the output of SRAM cells is typically read differentially via bit lines, requiring a sensitive amplifier, resulting in a significant read path delay (hundreds of picoseconds to nanoseconds), far from meeting the picosecond-level write window delay requirements of SAR ADC latches. Third, the SRAM cell write process suffers from a "write-read" contention problem—when WL is enabled and BL drives data writing to the storage node, if simultaneously affected by SET, erroneous data may be directly written to the storage core without additional filtering or recovery mechanisms.

[0089] In summary, existing radiation-hardened latch solutions suffer from insufficient high-speed applicability, unbalanced protection between write and hold modes, excessive area and power consumption, and lack of co-design with SAR logic, thus failing to meet the requirements of successive approximation logic circuits for high-speed SAR ADCs.

[0090] In view of this, the present disclosure proposes a radiation-hardened latch. In this latch, when any one of the storage nodes in the storage core module fails due to a single-event upset, the storage nodes that have not failed have the ability to restore the faulty storage node to normal. This enables high fault tolerance in various working states such as write mode and hold mode. Furthermore, each module of the latch in the present disclosure is directly connected to each storage node, enabling fast signal transmission and low latency. Therefore, the latch in the present disclosure can balance high-speed transmission and fault-tolerant storage.

[0091] Please see Figure 3 , Figure 3 A schematic diagram of a radiation-hardened latch according to an embodiment of the present disclosure is shown.

[0092] like Figure 3 As shown, the latch includes:

[0093] The storage core module 10 includes multiple storage nodes. When any one of the storage nodes fails due to a single-event flip, the storage nodes that have not flipped have the ability to restore the faulty storage node to normal.

[0094] The input module 20 is connected to each storage node. The input module 20 is used to receive input signals and to configure the level state of each storage node under the control of the input switch control signal.

[0095] The storage node reset module 30 is connected to each storage node and is used to reset the level state of each storage node under the control of the switch reset signal.

[0096] The hold mode control module 40 is connected to the storage core module 10 and is used to control the latch to enter or exit hold mode;

[0097] The output module 50 is connected to each storage node and the storage core module 10. The output module 50 is used to output latch signals at at least one output node according to the level state of each storage node.

[0098] The embodiments disclosed herein do not limit the specific implementation of the storage core module 10, input module 20, storage node reset module 30, hold mode control module 40, and output module 50. Those skilled in the art can implement them according to actual conditions and needs, referring to relevant technologies, as long as the corresponding functions can be achieved.

[0099] The present invention does not limit the number of storage nodes in the storage core module 10, and those skilled in the art can set it according to actual conditions and needs.

[0100] In this embodiment of the disclosure, an error caused by a single-event upset (SEU) in the storage node can refer to a high-energy particle incident causing a reversal in the level state of the storage node, such as changing from a high level to a low level, or vice versa. As an example, the latch in this embodiment can be applied to the SAR core logic of a SAR ADC. In the transparent mode of the SAR ADC, a high-energy particle incident may induce a single-event transient (SET) pulse at the latch input. If this transient pulse arrives within the latch's transparent window, it may be incorrectly latched as valid data, leading to errors in the successive approximation decisions of all subsequent bits. In hold mode, a high-energy particle directly bombarding the storage node of the latch may trigger a SEU, or even a multiple-node upset (MNU) due to charge sharing effects, such as a double-node upset (DNU), causing the latched decision result to be reversed. The transparent mode is the track mode of the ADC's internal sample-and-hold (S / H) circuit. In this mode, the sampling switch is closed, and the input analog signal can directly charge and discharge the holding capacitor. The capacitor voltage changes in real time with the input signal, and the signal path exhibits a "through-type" transmission characteristic, appearing transparent. In contrast, in the hold mode, the sampling switch is open, and the capacitor voltage is locked, allowing subsequent successive approximation logic to complete the analog-to-digital conversion.

[0101] The following provides an exemplary description of a preferred implementation of a latch.

[0102] Please see Figure 4 , Figure 4 A schematic diagram of the circuit structure of a radiation-hardened latch according to an embodiment of the present disclosure is shown.

[0103] In one possible implementation, such as Figure 4 As shown, the input module 20 may include a first input unit 210 and a second input unit 220. The first input unit 210 includes a first input transistor M1 and a second input transistor M2, and the second input unit 220 includes a third input transistor M3 and a fourth input transistor M4.

[0104] The source of the first input transistor M1 and the source of the third input transistor M3 are both used to receive the negative differential signal (DIN) of the input signal.

[0105] The source of the second input transistor M2 and the source of the fourth input transistor M4 are both used to receive the positive differential signal (DIP) of the input signal.

[0106] The gates of the first input transistor M1 and the second input transistor M2 are both used to receive the first switch control signal WRITEA.

[0107] The gates of the third input transistor M3 and the fourth input transistor M4 are both used to receive the second switch control signal WRITEB.

[0108] The drain of the first input transistor M1 is connected to the first memory node DON2.

[0109] The drain of the second input transistor M2 is connected to the second memory node DOP1.

[0110] The drain of the third input transistor M3 is connected to the third memory node DON1.

[0111] The drain of the fourth input transistor M4 is connected to the fourth memory node DOP2.

[0112] Specifically, the first storage node DON2 and the third storage node DON1 are used to store the same level state, and the second storage node DOP1 and the fourth storage node DOP2 are used to store the same level state. The level states stored by the first storage node DON2 and the third storage node DON1 are different from the level states stored by the second storage node DOP1 and the fourth storage node DOP2.

[0113] For example, such as Figure 4 As shown, each transistor in the first input unit 210 and the second input unit 220 can be controlled by the control signal WRITE (first switch control signal WRITEA and second switch control signal WRITEB). When WRITE=1, the input signals DIP and DIN are transmitted to the four storage nodes: the second storage node DOP1, the fourth storage node DOP2, the third storage node DON1, and the first storage node DON2. It is worth noting that due to the robustness (self-recovery capability) of the redundant storage core, if either the switch control signals WRITEA and WRITEB are flipped due to a single-event effect, the current stored signal result cannot be changed.

[0114] This disclosure does not limit the transistor type of each transistor in the input module 20. Those skilled in the art can set it according to actual conditions and needs, for example, such as... Figure 4As shown, the first input transistor M1, the second input transistor M2, the third input transistor M3, and the fourth input transistor M4 can all be NMOS transistors.

[0115] In one possible implementation, such as Figure 4 As shown, the storage node reset module 30 may include a first reset transistor M5, a second reset transistor M6, a third reset transistor M7, and a fourth reset transistor M8, wherein...

[0116] The sources of the first reset transistor M5, the second reset transistor M6, the third reset transistor M7, and the fourth reset transistor M8 are all used to receive the power supply voltage.

[0117] The drains of the first reset transistor M5, the second reset transistor M6, the third reset transistor M7, and the fourth reset transistor M8 are respectively connected to the first memory node DON2, the second memory node DOP1, the third memory node DON1, and the fourth memory node DOP2.

[0118] The gates of the first reset transistor M5 and the second reset transistor M6 are both used to receive the first switch reset signal RSTNA.

[0119] The gates of the third reset transistor M7 and the fourth reset transistor M8 are both used to receive the second switch reset signal RSTNB.

[0120] For example, such as Figure 4 As shown, the first reset transistor M5, the second reset transistor M6, the third reset transistor M7, and the fourth reset transistor M8 are used to reset the first memory node DON2, the second memory node DOP1, the third memory node DON1, and the fourth memory node DOP2, respectively.

[0121] For example, such as Figure 4 As shown, the first reset transistor M5, the second reset transistor M6, the third reset transistor M7, and the fourth reset transistor M8 can be controlled by the switch reset signal RSTN (the first switch reset signal RSTNA and the second switch reset signal RSTNB). When RSTN=0, all four storage nodes—the second storage node DOP1, the fourth storage node DOP2, the third storage node DON1, and the first storage node DON2—store a value of 1. It is worth noting that due to the robustness (self-recovery capability) of the redundant storage core, if either the switch reset signal RSTNA or RSTNB is flipped due to a single-event effect, the current stored signal result cannot be changed.

[0122] The embodiments disclosed herein do not limit the specific transistor types of the first reset transistor M5, the second reset transistor M6, the third reset transistor M7, and the fourth reset transistor M8. Those skilled in the art can set them according to actual conditions and needs. For example, the first reset transistor M5, the second reset transistor M6, the third reset transistor M7, and the fourth reset transistor M8 can all be PMOS transistors.

[0123] In one possible implementation, such as Figure 4 As shown, the storage core module 10 may include a first inverter NOT1, a second inverter NOT2, a third inverter NOT3, and a fourth inverter NOT4. The first inverter NOT1 and the fourth inverter NOT4 both have pull-up active loads, while the second inverter NOT2 and the third inverter NOT3 both have pull-down active loads.

[0124] The positive power supply terminals of the first inverter NOT1, the second inverter NOT2, the third inverter NOT3, and the fourth inverter NOT4 are all used to receive power supply voltage.

[0125] The negative power supply terminals of the first inverter NOT1 and the second inverter NOT2 are connected to the first terminal of the hold mode control module 40, and the negative power supply terminals of the third inverter NOT3 and the fourth inverter NOT4 are connected to the second terminal of the hold mode control module 40.

[0126] The input terminal of the first inverter NOT1 is connected to the second output node DOP. The control terminal of the pull-up active load of the first inverter NOT1 is connected to the second storage node DOP1. The output terminal of the first inverter NOT1 is connected to the first storage node DON2. The control terminal of the pull-down path of the first inverter NOT1 is connected to the fourth storage node DOP2.

[0127] The input terminal of the second inverter NOT2 is connected to the first output node DON. The control terminal of the pull-down active load of the second inverter NOT2 is connected to the third storage node DON1. The output terminal of the second inverter NOT2 is connected to the second storage node DOP1. The control terminal of the pull-up path of the second inverter NOT2 is connected to the first storage node DON2.

[0128] The input terminal of the third inverter NOT3 is connected to the second output node DOP. The control terminal of the pull-down active load of the third inverter NOT3 is connected to the second storage node DOP1. The output terminal of the third inverter NOT3 is connected to the third storage node DON1. The control terminal of the pull-up path of the third inverter NOT3 is connected to the fourth storage node DOP2.

[0129] The input terminal of the fourth inverter NOT4 is connected to the first output node DON, the control terminal of the pull-up active load of the fourth inverter NOT4 is connected to the third storage node DON1, the output terminal of the fourth inverter NOT4 is connected to the fourth storage node DOP2, and the control terminal of the pull-down path of the fourth inverter NOT4 is connected to the first storage node DON2.

[0130] This disclosure does not limit the specific implementation of each inverter, nor does it limit the specific implementation of the pull-up active load and pull-down active load. Those skilled in the art can implement these according to actual conditions and needs, referring to relevant technologies. For example, an inverter may include a pull-up path (pull-up transistor) and a pull-down path (pull-down transistor), with the drains of the pull-up and pull-down paths connected as the output node. When the input is high, the pull-down path is turned on, and the output node is pulled low; when the input is low, the pull-up path is turned on, and the output node is pulled high, thus achieving the logic inversion function. Exemplarily, both the pull-up and pull-down active loads can be implemented using transistors.

[0131] In one possible implementation, such as Figure 4 As shown, for the first inverter NOT1, the first inverter NOT1 may include a first inverter transistor M13, a second inverter transistor M19, and a third inverter transistor M21. The source of the first inverter transistor M13 serves as the negative power supply terminal, the gate of the first inverter transistor M13 serves as the pull-down path control terminal, the common node of the drains of the first inverter transistor M13 and the drains of the second inverter transistor M19 serves as the output terminal, the gate of the second inverter transistor M19 serves as the input terminal, the gate of the third inverter transistor M21 serves as the pull-up active load control terminal, the source of the third inverter transistor M21 serves as the positive power supply terminal, and the source of the second inverter transistor M19 is connected to the drain of the third inverter transistor M21.

[0132] For the second inverter NOT2, the second inverter NOT2 may include a fourth inverter transistor M15, a fifth inverter transistor M17, and a sixth inverter transistor M23. The source of the fourth inverter transistor M15 serves as the negative power supply terminal, the gate of the sixth inverter transistor M23 serves as the pull-up path control terminal, the common node of the drains of the fifth inverter transistor M17 and the sixth inverter transistor M23 serves as the output terminal, the gate of the fifth inverter transistor M17 serves as the input terminal, the gate of the fourth inverter transistor M15 serves as the pull-down active load control terminal, the source of the sixth inverter transistor M23 serves as the positive power supply terminal, and the drain of the fourth inverter transistor M15 is connected to the source of the fifth inverter transistor M17.

[0133] For the third inverter NOT3, NOT3 may include a seventh inverter M16, an eighth inverter M18, and a ninth inverter M24. The source of the seventh inverter M16 serves as the negative power supply terminal, the gate of the ninth inverter M24 serves as the pull-up path control terminal, the common node of the drains of the eighth inverter M18 and the ninth inverter M24 serves as the output terminal, the gate of the eighth inverter M18 serves as the input terminal, the gate of the seventh inverter M16 serves as the pull-down active load control terminal, the source of the ninth inverter M24 serves as the positive power supply terminal, and the drain of the seventh inverter M16 is connected to the source of the eighth inverter M18.

[0134] For the fourth inverter NOT4, the fourth inverter NOT4 may include a tenth inverter M14, an eleventh inverter M20, and a twelfth inverter M22. The source of the tenth inverter M14 serves as the negative power supply terminal, the gate of the tenth inverter M14 serves as the pull-down path control terminal, the common node of the drain of the tenth inverter M14 and the drain of the eleventh inverter M20 serves as the output terminal, the gate of the eleventh inverter M20 serves as the input terminal, the gate of the twelfth inverter M22 serves as the pull-up active load control terminal, the source of the twelfth inverter M22 serves as the positive power supply terminal, and the source of the eleventh inverter M20 is connected to the drain of the twelfth inverter M22.

[0135] For example, such as Figure 4As shown, the second storage node DOP1 and the fourth storage node DOP2, and the third storage node DON1 and the first storage node DON2, store the same logic value under normal holding conditions. Combined with the first output node DON and the second output node DOP of the latch, the four branches are reinforced by cross-coupling. When any one of the nodes (a total of 6 storage nodes) fails due to a single-event flip, the non-flipped node can provide feedback to drive the faulty node to recover, thereby achieving 100% single-node flip self-recovery. In addition, this storage core can tolerate some dual-node single-event flips (e.g., third storage node DON1-second storage node DOP1, third storage node DON1-fourth storage node DOP2, first storage node DON2-second storage node DOP1, first storage node DON2-fourth storage node DOP2, first output node DON-third storage node DON1, first output node DON-second storage node DOP1, first output node DON-fourth storage node DOP2). By combining the same type of sensitive node layout isolation design, it is possible to achieve nearly 100% resistance to two-node single-event flips.

[0136] The embodiments disclosed herein do not limit the specific type of transistors in each inverter. Those skilled in the art can set them according to actual conditions and needs. For example, the first inverter transistor M13, the fourth inverter transistor M15, the fifth inverter transistor M17, the seventh inverter transistor M16, the eighth inverter transistor M18, and the tenth inverter transistor M14 can all be NMOS transistors, and the second inverter transistor M19, the third inverter transistor M21, the sixth inverter transistor M23, the ninth inverter transistor M24, the eleventh inverter transistor M20, and the twelfth inverter transistor M22 can all be PMOS transistors.

[0137] In one possible implementation, such as Figure 4 As shown, the holding mode control module 40 may include a first holding control transistor M9, a second holding control transistor M11, a third holding control transistor M10, and a fourth holding control transistor M12, wherein,

[0138] The source of the first holding control transistor M9 and the source of the third holding control transistor M10 are grounded.

[0139] The drain of the first hold control transistor M9 is connected to the source of the second hold control transistor M11, and the drain of the second hold control transistor M11 serves as the first terminal of the hold mode control module 40.

[0140] The drain of the third hold control transistor M10 is connected to the source of the fourth hold control transistor M12, and the drain of the fourth hold control transistor M12 serves as the second terminal of the hold mode control module 40.

[0141] The gate of the first holding control transistor M9 is used to receive the second switch reset signal RSTNB.

[0142] The gate of the third holding control transistor M10 is used to receive the first switch reset signal RSTNA.

[0143] The gates of the second holding control transistor M11 and the fourth holding control transistor M12 are both used to receive holding control signals (RDYA / RDYB).

[0144] For example, such as Figure 4 As shown, M9 and M10 are controlled by RSTN (RSTNA and RSTNB) signals, while M11 and M12 are controlled by RDY (RDYA and RDYB) signals. When RDY=1 and RSTN=1, the core latch enters hold mode. It is worth noting that during input signal writing, M11 and M12, controlled by RDY (RDYA and RDYB) signals, are not turned on. Therefore, the memory core has no pull-down path, resulting in faster signal writing speeds.

[0145] The embodiments disclosed herein do not limit the specific transistor types of the first hold control transistor M9, the second hold control transistor M11, the third hold control transistor M10, and the fourth hold control transistor M12. Those skilled in the art can set them according to actual conditions and needs. For example, the first hold control transistor M9, the second hold control transistor M11, the third hold control transistor M10, and the fourth hold control transistor M12 can all be NMOS transistors.

[0146] In one possible implementation, such as Figure 4 As shown, the output module 50 may include a first output unit 510 and a second output unit 520.

[0147] The first input terminal and the second input terminal of the first output unit 510 are respectively connected to the first storage node DON2 and the third storage node DON1. The first output unit 510 outputs a first output voltage through the first output node DON. When the level states of the first storage node DON2 and the third storage node DON1 are the same, the first output node DON follows the level states of the first storage node DON2 and the third storage node DON1. When the level states of the first storage node DON2 and the third storage node DON1 are different, the first output node DON maintains the previous level state.

[0148] The first input terminal and the second input terminal of the second output unit 520 are respectively connected to the second storage node DOP1 and the fourth storage node DOP2. The second output unit 520 outputs a second output voltage through the second output node DOP. When the level states of the second storage node DOP1 and the fourth storage node DOP2 are the same, the second output node DOP follows the level states of the second storage node DOP1 and the fourth storage node DOP2. When the level states of the second storage node DOP1 and the fourth storage node DOP2 are different, the second output node DOP maintains the previous level state.

[0149] This disclosure does not limit the specific implementation of the first output unit 510 and the second output unit 520. Those skilled in the art can implement them according to the actual situation and needs, referring to relevant technologies. As long as the first output unit 510 and the second output unit 520 can achieve their functions, they are acceptable. For example, both the first output unit 510 and the second output unit 520 may include a Mueller unit, which is composed of paired PMOS transistors and NMOS transistors. Different types of Mueller units contain different numbers of transistors. The Mueller unit achieves resistance to single-event multi-bit node flipping through a multi-unit interlocking structure, which greatly improves the output stability of the chip in a radiation environment. The following is an exemplary description.

[0150] In one possible implementation, such as Figure 4 As shown, for the first output unit 510, the first output unit 510 includes a first output transistor M25, a second output transistor M26, a third output transistor M27, a fourth output transistor M28, a fifth output transistor M29, and a sixth output transistor M30. The source of the first output transistor M25 is grounded, and the source of the fourth output transistor M28 is connected to the power supply voltage. The gates of the first output transistor M25 and the third output transistor M27 are connected to the first memory node DON2, and the gates of the second output transistor M26 and the fourth output transistor M28 are connected to the third memory node DON2. At point DON1, the drain of the first output transistor M25, the source of the second output transistor M26, and the source of the fifth output transistor M29 are connected. The drain of the second output transistor M26, the drain of the third output transistor M27, the gate of the fifth output transistor M29, and the gate of the sixth output transistor M30 are all connected to the second output node DOP. The source of the third output transistor M27, the drain of the fourth output transistor M28, and the source of the sixth output transistor M30 are connected. The drain of the fifth output transistor M29 is connected to the power supply voltage, and the drain of the sixth output transistor M30 is grounded.

[0151] For the second output unit 520, the second output unit 520 includes a seventh output transistor M31, an eighth output transistor M32, a ninth output transistor M33, a tenth output transistor M34, an eleventh output transistor M35, and a twelfth output transistor M36. The source of the seventh output transistor M31 is grounded, and the source of the tenth output transistor M34 is connected to the power supply voltage. The gates of the seventh output transistor M31 and the ninth output transistor M33 are connected to the fourth memory node DOP2, and the gates of the eighth output transistor M32 and the tenth output transistor M34 are connected to the second memory node DOP. 1. The drain of the seventh output transistor M31, the source of the eighth output transistor M32, and the source of the eleventh output transistor M35 are connected. The drain of the eighth output transistor M32, the drain of the ninth output transistor M33, the gate of the eleventh output transistor M35, and the gate of the twelfth output transistor M36 are all connected to the first output node DON. The source of the ninth output transistor M33, the drain of the tenth output transistor M34, and the source of the twelfth output transistor M36 are connected. The drain of the eleventh output transistor M35 is grounded, and the drain of the twelfth output transistor M36 is connected to the power supply voltage.

[0152] For example, such as Figure 4 As shown, taking the first output unit 510 as an example, the first output transistor M25, the second output transistor M26, the third output transistor M27, and the fourth output transistor M28 constitute a Mueller unit. The first output transistor M25 and the third output transistor M27 are controlled by the first storage node DON2, while the second output transistor M26 and the fourth output transistor M28 are controlled by the third storage node DON1. If either the third storage node DON1 or the first storage node DON2 flips, the output voltage of the second output node DOP remains in its previous state, thus isolating the influence of internal single-node flipping on the external output. The fifth output transistor M29 and the sixth output transistor M30, together with the Mueller unit, form a Schmitt inverter structure, increasing the hysteresis voltage and further ensuring the stability of the second output node DOP. The output Schmitt Mueller unit buffers and shapes the input signal and provides a certain noise margin. For single-event transient pulses with small amplitude or narrow pulse width, this structure can provide preliminary filtering through its own switching threshold and limited bandwidth. It is worth noting that when the input signals DIP and DIN are written, they directly drive the two output Schmitt Muller units to generate outputs. Therefore, the comparator comparison result is fed back to the CDAC switch only after the Schmitt Muller unit is delayed, thus achieving high-speed transmission.

[0153] The latch in this embodiment realizes the storage core module 10 through multiple inverters connected by cross-coupling. Each storage node has single-event transient, single-event flip and dual-node protection capabilities. In cooperation with the output module 50 with Mueller unit, it can achieve 100% single-node flip self-recovery, more than 53% dual-node flip self-recovery, and single-event transient output isolation mechanism.

[0154] Furthermore, the latch in this embodiment employs a low-latency architecture that combines a read pass-through path with a redundant write path, such as... Figure 4 As shown, in write mode, the input signals DIP and DIN reach the output quickly via switches M1~M4 and the output Schmitt Muller unit inverter. On the other hand, before the outputs of the second output node DOP and the first output node DON stabilize, the pull-up and pull-down paths of the redundant storage core are turned off to improve the write speed, thus balancing high-speed transmission and fault-tolerant storage.

[0155] In one possible implementation, the latch is applied in a successive approximation analog-to-digital converter, and the validity condition of the input switch control signal includes the validity of the output result of the comparator in the successive approximation analog-to-digital converter.

[0156] The embodiments disclosed herein enable the latch write window to be opened after the comparator output is valid, and close the write window during DAC setup and subsequent bit comparisons, thereby coordinating the latch operating timing with the comparator regeneration time and successive approximation clock, reducing the probability of SET being sampled and propagated.

[0157] According to one aspect of this disclosure, a successive approximation analog-to-digital converter (ADC) is provided, the successive approximation ADC including a sample-and-hold circuit, a digital-to-analog converter, a comparator, and a successive approximation SAR logic circuit, wherein...

[0158] The sample-and-hold circuit is used to sample and hold the input analog signal.

[0159] The digital-to-analog converter is used to receive the intermediate digital code from the SAR logic circuit and convert it into a corresponding analog voltage.

[0160] The comparator is used to compare the amplitude of the input voltage sampled and held by the sample-and-hold circuit with the analog voltage output by the digital-to-analog converter, and output a decision result.

[0161] The SAR logic circuit is used to generate intermediate digital codes of corresponding bits based on the decision result of the comparator.

[0162] The SAR logic circuit includes multiple cascaded radiation-hardened latches.

[0163] This disclosure does not limit the specific implementation of the sample-and-hold circuit, digital-to-analog converter, comparator, and successive approximation SAR logic circuit. Those skilled in the art can implement these circuits according to actual conditions and needs, referring to relevant technologies. For example, ... Figure 1 As shown, the sample-and-hold circuit may include a sampling switch and a capacitor array. This capacitor array performs both sample-and-hold and digital-to-analog conversion functions. One input of the comparator is connected to the upper plate of each capacitor in the capacitor array and grounded through the sampling switch. The lower plate of each capacitor is connected to the lower plate via switches S0~S10. N-1 The input voltage VIN, positive reference voltage VREFP, and negative reference voltage VREFN are selected. The output of the comparator is connected to the SAR logic circuit, and the SAR logic circuit finally outputs the analog-to-digital conversion signal D[N:1].

[0164] For example, such as Figure 1 The workflow of the SAR ADC shown is divided into four stages:

[0165] Phase 1: Sampling Phase

[0166] Controlled by the sampling clock: Sampling switch φ sample When closed, the common upper plate node VX of the capacitor array is clamped to ground potential (0V); the lower plate switches S0~S of all capacitors in the capacitor array. N-1 All capacitors are switched to the input voltage VIN; a voltage difference VIN is established across each capacitor, and the total charge of the entire capacitor array is the total capacitance of all capacitors. This stage completes the sampling of the input analog signal and stores the input voltage in the capacitor array in the form of charge.

[0167] Phase 2: Maintenance and Transformation Start-up

[0168] Sampling switch φ sample When disconnected, the upper plate node VX enters a high-resistance floating state. Ideally, the total charge of the capacitor array remains unchanged, satisfying the charge conservation. The SAR logic initiates the conversion, using a binary search strategy from the most significant bit (MSB) to the least significant bit (LSB) to determine the value of each bit of the output digital code.

[0169] Phase 3: Successive Approximation Transformation (Core Process)

[0170] Each bit follows a unified process of bit probing, comparison and decision, and bit value correction:

[0171] 3.1 Position probing

[0172] The SAR logic switches the lower plate of the capacitor corresponding to the current bit to be decided to the positive reference voltage VREFP, while the capacitors of lower bits remain connected to the negative reference voltage VREFN, and the high bits that have already been decided maintain the previously determined connection state.

[0173] At this time, the weighted average voltage of the lower plate is equivalent to the DAC output voltage VDAC. According to the law of charge conservation, the voltage of the upper plate satisfies the relation: VX=VDAC-VIN

[0174] 3.2 Comparator decision

[0175] The comparator completes one decision under the control of the clock, comparing VX with the ground potential, which essentially is to judge the magnitude relationship between VDAC and VIN: if V_X>0→VDAC>VIN, the weight of the current trial bit is too large, this bit is cleared, and the lower plate of the corresponding capacitor is switched back to VREFN; if V_X<0→VDAC<VIN, the weight of the current trial bit is insufficient, this bit remains 1, and the corresponding capacitor is kept connected to VREFP.

[0176] 3.3 Bitwise iteration

[0177] Starting from the most significant bit (corresponding to the largest capacitor 2 N-1 ×Cu), the above process is repeated to sequentially complete the decisions of the next most significant bit, ..., and the least significant bit.

[0178] Stage 4: Result output

[0179] After all N bits are decided, the register inside the SAR logic latches the final N-bit binary result and outputs the analog-to-digital conversion result D[N:1], and one complete analog-to-digital conversion ends. Subsequently, the circuit returns to the sampling stage to prepare for the next conversion.

[0180] It should be understood that the above introduction to the working process of the SAR ADC is exemplary and should not be regarded as a limitation on the embodiments of the present disclosure.

[0181] The embodiments of the present disclosure do not limit the number of cascaded latches in the SAR logic circuit, and those skilled in the art can determine the number according to the actual situation and the required precision of the SAR ADC.

[0182] In a possible implementation manner, each radiation-hardened latch may include a control signal generator 60 to generate each control signal required by the latch. The embodiments of the present disclosure do not limit the specific implementation manner of the control signal generator 60, and those skilled in the art can refer to the related art to implement it according to the actual situation and needs. The preferred implementation manner will be described below as an example.

[0183] Please refer to Figure 5 , Figure 5 which shows a schematic diagram of the control signal generator 60 according to an embodiment of the present disclosure.

[0184] In a possible implementation manner, as shown in Figure 5As shown, the control signal generator 60 may include a first OR gate 610, a second OR gate 612, a first NOR gate 611, a second NOR gate 613, a first NAND gate 616, a second NAND gate 617, a first NOT gate 614, and a second NOT gate 615, wherein...

[0185] The two input terminals of the first OR gate 610 are used to receive input signals (the first output voltage (DON) and the second output voltage (DOP) of the latch). The output terminal of the first OR gate 610 is connected to the first input terminal of the first NOR gate 611. The output terminal of the first OR gate 610 is used to output a holding control signal (RDYA). The second and third input terminals of the first NOR gate 611 are respectively connected to the first status signal ENPREA output by the control signal generator 60 of the previous stage latch and the valid signal VALIDN corresponding to the decision result output by the comparator. The first NOR gate 611 is used to output a first switch control signal WRITEA.

[0186] The two input terminals of the second OR gate 612 are used to receive input signals (the first output voltage (DON) and the second output voltage (DOP) of the latch). The output terminal of the second OR gate 612 is connected to the first input terminal of the second NOR gate 613. The output terminal of the second OR gate 612 is used to output a holding control signal (RDYB). The second and third input terminals of the second NOR gate 613 are respectively connected to the second status signal ENPREB output by the control signal generator 60 of the previous stage latch and the valid signal VALIDN corresponding to the decision result output by the comparator. The second NOR gate 613 is used to output a second switch control signal WRITEB.

[0187] The first NOT gate 614 is used to generate a first switch reset signal RSTNA based on the first status signal ENPREA output by the control signal generator 60 of the previous stage latch.

[0188] The second NOT gate 615 is used to generate a second switch reset signal RSTNB based on the second status signal ENPREB output by the control signal generator 60 of the previous stage latch.

[0189] The first NAND gate 616 is used to generate the first state signal NEXTA of the current stage based on the output hold control signal (RDYA) and the first global reset signal GRSTNA.

[0190] The second NAND gate 617 is used to generate the second state signal NEXTB of the current stage based on the output hold control signal (RDYB) and the second global reset signal GRSTNB.

[0191] The level states of the hold control signal (RDYA) and the output hold control signal (RDYB) are the same.

[0192] For example, such as Figure 5 As shown, in the control signal generator 60, the VALIDN signal is the valid signal (valid decision signal) corresponding to the comparator output result signal, ENPREA and ENPREB are the status signals of the previous stage latch in the SAR logic (i.e., the NEXTA and NEXTB signals output by the previous stage control signal generator 60), and GRSTNA and GRSTNB are the global reset signals of the SAR logic. In this embodiment, the input switch control signal is valid when the comparator output result is valid, thereby opening the latch write window and closing the write window during DAC establishment and subsequent bit comparison. This coordinates the latch operating timing with the comparator regeneration time and successive approximation clock, reducing the probability of SET being sampled and propagated.

[0193] In this embodiment of the present disclosure, the output result of the comparator includes a high level (1) and a low level (0). This embodiment of the present disclosure does not limit the criteria for determining the validity of the output result. Those skilled in the art can set it according to the actual situation and needs. When the output result is valid, the output result valid signal VALIDN in this embodiment of the present disclosure can be a low level (0). In this case, WRITEA=1, WRITEB=1, and the latch enters the write mode.

[0194] This control method matches the latch write window (the time period corresponding to WRITEA=1 and WRITEB=1) with the comparator regeneration time and successive approximation cycle of the SAR ADC. The write window does not need to be open for a long time; it only needs to cover the time required for the transmission and storage of the valid decision result VALIDN, thereby reducing the probability that the input SET pulse is sampled into the memory core.

[0195] In addition to generating various control signals through the control signal generator 60 described above, embodiments of this disclosure can also receive external control signals or generate them using processing components. In some possible implementations, the processing components include, but are not limited to, a separate processor, discrete components, or a combination of a processor and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0196] The following describes the operating modes of the latches in the embodiments of this disclosure and the cascaded latches in the SAR logic circuit of the SAR ADC.

[0197] For example, the operating modes of a latch may include global reset mode, wait mode, write mode, and hold mode.

[0198] For example, when both global reset signals GRSTNA and GRSTNB are low (0), the latch operates in global reset mode. For instance, in global reset mode, the input GRSTNA = GRSTNB = 0, as shown below. Figure 5 As shown, NEXTA=NEXTB=1. Since the latches are cascaded in the SAR logic, i.e., ENPREA=ENPREB=1, RSTNA=RSTNB=0. The latches are in the reset phase, DON1=DON2=DOP1=DOP2=1. At this time, DOP=DON=0.

[0199] For example, when GRSTNA=GRSTNB=1 (high level) and ENPREA=ENPREB=1, the latch operates in wait mode. For instance, after a global reset, before the preceding latch has finished writing data (i.e., the current latch ENPREA=ENPREB=1), then RSTNA=RSTNB=0 and WRITEA=WRITEB=0, the latch will still be in the reset state, DON1=DON2=DOP1=DOP2=1, DOP=DON=0.

[0200] For example, when GRSTNA=GRSTNB=1 and ENPREA=ENPREB=0, the latch operates in write mode. For instance, after the preceding latch completes the data writing (i.e., the current latch ENPREA=ENPREB=0), the latch enters a write wait state, waiting for the comparator to output a valid decision result VALID=0, WRITEA=WRITEB=1, and then the data writing begins.

[0201] For example, when GRSTNA=GRSTNB=1, ENPREA=ENPREB=0, and RDYA=RDYB=1, the latch operates in hold mode. For instance, after the comparator comparison result is successfully written to the latch, the second output node DOP and the first output node DON leave the all-zero state, i.e., RDYA=RDYB=1, then WRITEA=WRITEB=0, and the latch leaves the write mode and enters the hold mode.

[0202] Please see Figure 6 , Figure 6 The diagram shows the working logic of the SAR logic circuit in the SAR ADC.

[0203] For example, such as Figure 6 As shown, multiple radiation-hardened latches (latch 1 to latch N, where N is a positive integer) are cascaded in successive approximation bit order to form an asynchronous successive approximation logic chain for the SAR ADC. The status ports of the first-stage latches receive start signals STARTA and STARTB, respectively, while the status ports of subsequent latches receive the NEXTA and NEXTB signals output from the previous stage latch. Each stage latch receives the comparator decision result (including valid decision results VALIDN, CMPP, and CMPN) or the control result from the previous stage (NEXTA and NEXTB), outputs the corresponding DAC switch control signal (second output node DOP and first output node DON), and passes the decision result VALIDN to the subsequent quantization output circuit.

[0204] For example, such as Figure 6 As shown, the working process of this successive approximation logic circuit includes:

[0205] First, quantization is initiated by the CLKS signal (STARTA=STARTB=0), the comparator is enabled during the current bit comparison cycle (CLKC=1), and the decision result VALIDN (CMPP and CMPN) is output.

[0206] Second, after the comparator decision result VALIDN is valid (VALIDN=0), the corresponding bit latch first enters the write mode, and the decision result VALIDN quickly drives the reference voltage switch of the DAC through the through path. At the same time, the decision result VALIDN is written into the redundant storage core of the latch.

[0207] Third, after the decision result VALIDN is written to the redundant storage core of the latch, the latch enters the holding mode, and the redundant storage core stably holds the decision result VALIDN. The current latch outputs the start signal of the next-level latch (NEXTA=NEXTB=0).

[0208] Fourth, subsequent bit latches are triggered sequentially, completing the approximation process from the high bit to the low bit.

[0209] Fifth, after the successive approximation process is completed, the sampling signal CLKS controls the latching result to be sent to the subsequent circuit (for lower-speed circuits, a TMR flip-flop can be used), and then all latches can be reset to wait for the next quantization.

[0210] Through the above cascading method, the radiation-resistant latch in this embodiment not only has SEE protection capability as a single storage unit, but also works in coordination with the bit order propagation, asynchronous handshake and DAC switch control timing of SAR logic, making it difficult for single-particle transients or single-node flips to propagate continuously throughout the entire successive approximation link.

[0211] For example, to further enhance the single-event immunity of actual chips, embodiments of this disclosure may also incorporate the following layout-level measures:

[0212] First, the transistors corresponding to the second storage node DOP1 (fourth storage node DOP2), the third storage node DON1 (first storage node DON2), the second output node DOP, and the first output node DON of the redundant storage core are physically separated on the layout, and a diagonal or spaced layout is preferred to reduce the probability of a single particle affecting two redundant nodes at the same time.

[0213] Second, a protective ring connected to VDD or GND is set around the active regions of PMOS and NMOS to suppress parasitic latch-up and collect substrate charge generated by radiation.

[0214] Third, when process allows, deep N-well isolation, power / ground mesh wiring, and multi-contact hole connections are used to improve power integrity and substrate isolation capabilities.

[0215] The aforementioned layout-level measures are not necessary conditions for changing the circuit topology of the embodiments of this disclosure, but rather constitute optional enhanced implementation methods together with circuit-level redundant storage, Mueller cell error isolation, and SAR timing coordination.

[0216] The SAR ADC of this disclosure can be applied to various electronic devices. This disclosure does not limit the specific type of electronic device; those skilled in the art can configure it according to actual conditions and needs. For example, the electronic device may include terminal devices and servers. The terminal device may be user equipment (UE), mobile device, user terminal, terminal, handheld device, computing device, or vehicle-mounted device, etc. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, and wireless terminals in vehicle networks, etc. For example, the server may be a local server or a cloud server.

[0217] The radiation-hardened latch and successive approximation logic circuit of the present disclosure have at least the following advantages over the prior art:

[0218] (1) Achieve dual redundancy protection in all working states. In write mode, the probability of SET being latched and propagated by error is reduced by through-path, redundant writing and SAR timing coordination; in hold mode, 100% SEU self-recovery and 53% DNU error output isolation are achieved by redundant dual-path storage core units.

[0219] (2) It has both high speed and low latency characteristics. The critical path in write mode is the write switch (M1~M4) and the output Schmitt Muller unit, which avoids the voter being connected in series with the main data path and can meet the requirement of low propagation delay for bit-by-bit decision of high-speed asynchronous SAR ADC.

[0220] (3) Lower area and power consumption overhead. Compared with triple-redundant latches, the embodiments of this disclosure only add limited redundant storage and error isolation units, without requiring three complete latches and a majority voter, making them suitable for space-constrained electronic chips with limited area and power consumption.

[0221] (4) Deep synergy with the working mechanism of SAR ADC. The embodiments disclosed in this disclosure utilize the inherent timing characteristics of SAR ADC, such as opening the write window only after the comparator regeneration is completed and the successive approximation link segmented propagation, and adopt a dual-mode redundancy method to achieve anti-single-event hardening. At the same time, a hierarchical anti-radiation logic is adopted. The high-speed latch is suitable for the high-speed dynamic decision path, and the TMR DFF (or DICE DFF) is suitable for the low-speed status register path. The two work together to form a complete SAR asynchronous logic anti-radiation protection system.

[0222] (5) It has good scalability and process adaptability. The embodiments of this disclosure can adjust the number of redundant nodes, output buffer structure and layout hardening strength according to radiation level, speed index and area constraints, and are suitable for SAR ADCs with different resolutions and sampling rates or other digital control circuits that require high-speed latching.

[0223] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A radiation-hardened latch, characterized in that, The latch includes: The storage core module includes multiple storage nodes. When any one of the storage nodes fails due to a single-event flip, the storage nodes that have not flipped have the ability to restore the faulty storage node to normal. An input module is connected to each storage node. The input module is used to receive input signals and to configure the level state of each storage node under the control of an input switch control signal. The storage node reset module is connected to each storage node and is used to reset the level state of each storage node under the control of the switch reset signal. A hold mode control module, connected to the storage core module, is used to control the latch to enter or exit hold mode; An output module, connected to the storage core module, is used to output latch signals at at least one output node according to the level state of each storage node.

2. The radiation-hardened latch according to claim 1, characterized in that, The input module includes a first input unit and a second input unit. The first input unit includes a first input transistor and a second input transistor, and the second input unit includes a third input transistor and a fourth input transistor. The source of the first input transistor and the source of the third input transistor are both used to receive the negative differential signal of the input signal. The source of the second input transistor and the source of the fourth input transistor are both used to receive the positive differential signal of the input signal. The gates of both the first and second input transistors are used to receive the first switching control signal. The gates of the third input transistor and the fourth input transistor are both used to receive the second switch control signal. The drain of the first input transistor is connected to the first memory node. The drain of the second input transistor is connected to the second memory node. The drain of the third input transistor is connected to the third memory node. The drain of the fourth input transistor is connected to the fourth memory node. The first and third storage nodes are used to store the same level state, and the second and fourth storage nodes are used to store the same level state. The level states stored by the first and third storage nodes are different from the level states stored by the second and fourth storage nodes.

3. The radiation-hardened latch according to claim 1, characterized in that, The storage node reset module includes a first reset transistor, a second reset transistor, a third reset transistor, and a fourth reset transistor, wherein, The sources of the first reset transistor, the second reset transistor, the third reset transistor, and the fourth reset transistor are all used to receive the power supply voltage. The drains of the first reset transistor, the second reset transistor, the third reset transistor, and the fourth reset transistor are respectively connected to the first memory node, the second memory node, the third memory node, and the fourth memory node. The gates of both the first and second reset transistors are used to receive the first switch reset signal. The gates of the third reset transistor and the fourth reset transistor are both used to receive the second switch reset signal.

4. The radiation-hardened latch according to claim 1, characterized in that, The storage core module includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The first inverter and the fourth inverter both have pull-up active loads, while the second inverter and the third inverter both have pull-down active loads. The positive power supply terminals of the first inverter, the second inverter, the third inverter, and the fourth inverter are all used to receive power supply voltage. The negative power supply terminals of the first inverter, the second inverter, and the first terminal of the hold mode control module are connected together; the negative power supply terminals of the third inverter and the fourth inverter are connected to the second terminal of the hold mode control module. The input terminal of the first inverter is connected to the second output node, the control terminal of the first inverter for the pull-up active load is connected to the second storage node, the output terminal of the first inverter is connected to the first storage node, and the control terminal of the first inverter for the pull-down path is connected to the fourth storage node. The input terminal of the second inverter is connected to the first output node, the control terminal of the second inverter for the pull-down active load is connected to the third storage node, the output terminal of the second inverter is connected to the second storage node, and the control terminal of the second inverter for the pull-up path is connected to the first storage node. The input terminal of the third inverter is connected to the second output node, the control terminal of the third inverter for the pull-down active load is connected to the second storage node, the output terminal of the third inverter is connected to the third storage node, and the control terminal of the third inverter for the pull-up path is connected to the fourth storage node. The input terminal of the fourth inverter is connected to the first output node, the control terminal of the fourth inverter for pulling up the active load is connected to the third storage node, the output terminal of the fourth inverter is connected to the fourth storage node, and the control terminal of the fourth inverter for pulling down the path is connected to the first storage node.

5. The radiation-hardened latch according to claim 4, characterized in that, The first inverter includes a first inverting transistor, a second inverting transistor, and a third inverting transistor. The source of the first inverting transistor serves as a negative power supply terminal, the gate of the first inverting transistor serves as a pull-down path control terminal, the common node of the drains of the first and second inverting transistors serves as an output terminal, the gate of the second inverting transistor serves as an input terminal, the gate of the third inverting transistor serves as a pull-up active load control terminal, and the source of the third inverting transistor serves as a positive power supply terminal. The source of the second inverting transistor is connected to the drain of the third inverting transistor. The second inverter includes a fourth, a fifth, and a sixth inverting transistor. The source of the fourth inverting transistor serves as a negative power supply terminal, the gate of the sixth inverting transistor serves as a pull-up path control terminal, the common node of the drains of the fifth and sixth inverting transistors serves as an output terminal, the gate of the fifth inverting transistor serves as an input terminal, the gate of the fourth inverting transistor serves as a pull-down active load control terminal, the source of the sixth inverting transistor serves as a positive power supply terminal, and the drain of the fourth inverting transistor is connected to the source of the fifth inverting transistor. The third inverter includes a seventh, an eighth, and a ninth inverting transistor. The source of the seventh inverting transistor serves as the negative power supply terminal, the gate of the ninth inverting transistor serves as the pull-up control terminal, the common node of the drains of the eighth and ninth inverting transistors serves as the output terminal, the gate of the eighth inverting transistor serves as the input terminal, the gate of the seventh inverting transistor serves as the pull-down control terminal for an active load, the source of the ninth inverting transistor serves as the positive power supply terminal, and the drain of the seventh inverting transistor is connected to the source of the eighth inverting transistor. The fourth inverter includes a tenth inverter transistor, an eleventh inverter transistor, and a twelfth inverter transistor. The source of the tenth inverter transistor serves as a negative power supply terminal, the gate of the tenth inverter transistor serves as a pull-down path control terminal, the common node of the drains of the tenth and eleventh inverter transistors serves as an output terminal, the gate of the eleventh inverter transistor serves as an input terminal, the gate of the twelfth inverter transistor serves as a pull-up active load control terminal, the source of the twelfth inverter transistor serves as a positive power supply terminal, and the source of the eleventh inverter transistor is connected to the drain of the twelfth inverter transistor.

6. The radiation-hardened latch according to claim 4 or 5, characterized in that, The hold mode control module includes a first hold control transistor, a second hold control transistor, a third hold control transistor, and a fourth hold control transistor, wherein, The source of the first holding control transistor and the source of the third holding control transistor are grounded. The drain of the first hold control transistor is connected to the source of the second hold control transistor, and the drain of the second hold control transistor serves as the first terminal of the hold mode control module. The drain of the third hold control transistor is connected to the source of the fourth hold control transistor, and the drain of the fourth hold control transistor serves as the second terminal of the hold mode control module. The gate of the first holding control transistor is used to receive the second switch reset signal. The gate of the third holding control transistor is used to receive the first switch reset signal. The gates of both the second and fourth holding control transistors are used to receive holding control signals.

7. The radiation-hardened latch according to claim 1, characterized in that, The output module includes a first output unit and a second output unit. The first input terminal and the second input terminal of the first output unit are respectively connected to the first storage node and the third storage node. The first output unit outputs a first output voltage through the first output node. When the level states of the first storage node and the third storage node are the same, the first output node follows the level states of the first storage node and the third storage node. When the level states of the first storage node and the third storage node are different, the first output node maintains the previous level state. The first input terminal and the second input terminal of the second output unit are respectively connected to the second storage node and the fourth storage node. The second output unit outputs a second output voltage through the second output node. When the level states of the second storage node and the fourth storage node are the same, the second output node follows the level states of the second storage node and the fourth storage node. When the level states of the second storage node and the fourth storage node are different, the second output node maintains the previous level state.

8. The radiation-hardened latch according to claim 7, characterized in that, For the first output unit, the first output unit includes a first output transistor, a second output transistor, a third output transistor, a fourth output transistor, a fifth output transistor, and a sixth output transistor. The source of the first output transistor is grounded, the source of the fourth output transistor is connected to a power supply voltage, the gates of the first and third output transistors are connected to the first memory node, the gates of the second and fourth output transistors are connected to the third memory node, the drains of the first, second, and fifth output transistors are connected together, the drains of the second, third, and fifth output transistors, and the gates of the sixth output transistor are all connected to the second output node, the sources of the third, fourth, and sixth output transistors are connected together, the drain of the fifth output transistor is connected to a power supply voltage, and the drain of the sixth output transistor is grounded. The second output unit includes a seventh output transistor, an eighth output transistor, a ninth output transistor, a tenth output transistor, an eleventh output transistor, and a twelfth output transistor. The source of the seventh output transistor is grounded, the source of the tenth output transistor is connected to a power supply voltage, the gates of the seventh and ninth output transistors are connected to the fourth storage node, the gates of the eighth and tenth output transistors are connected to the second storage node, the drains of the seventh, eighth, and eleventh output transistors are connected together, the drains of the eighth, ninth, eleventh, and twelfth output transistors are all connected to the first output node, the sources of the ninth, tenth, and twelfth output transistors are connected together, the drain of the eleventh output transistor is grounded, and the drain of the twelfth output transistor is connected to a power supply voltage.

9. The radiation-hardened latch according to any one of claims 1-8, characterized in that, The latch is used in a successive approximation analog-to-digital converter, and the valid condition of the input switch control signal includes that the output result of the comparator in the successive approximation analog-to-digital converter is valid.

10. A successive approximation analog-to-digital converter, characterized in that, The successive approximation analog-to-digital converter includes a sample-and-hold circuit, a digital-to-analog converter, a comparator, and a successive approximation SAR logic circuit, wherein... The sample-and-hold circuit is used to sample and hold the input analog signal. The digital-to-analog converter is used to receive the intermediate digital code from the SAR logic circuit and convert it into a corresponding analog voltage. The comparator is used to compare the amplitude of the input voltage sampled and held by the sample-and-hold circuit with the analog voltage output by the digital-to-analog converter, and output a decision result. The SAR logic circuit is used to generate intermediate digital codes of corresponding bits based on the decision result of the comparator. The SAR logic circuit includes a plurality of cascaded radiation-hardened latches as described in any one of claims 1-9.

11. The successive approximation analog-to-digital converter according to claim 10, characterized in that, Each radiation-hardened latch includes a control signal generator, which comprises a first OR gate, a second OR gate, a first NOR gate, a second NOR gate, a first NAND gate, a second NAND gate, a first NOT gate, and a second NOT gate, wherein... The two input terminals of the first OR gate are used to receive input signals. The output terminal of the first OR gate is connected to the first input terminal of the first NOR gate, and the output terminal of the first OR gate is used to output a holding control signal. The second and third input terminals of the first NOR gate are respectively connected to the first status signal output by the control signal generator of the previous stage latch and the valid signal corresponding to the decision result output by the comparator. The first NOR gate is used to output a first switch control signal. The two inputs of the second OR gate are used to receive input signals. The output of the second OR gate is connected to the first input of the second NOR gate. The output of the second OR gate is used to output a holding control signal. The second and third inputs of the second NOR gate are respectively connected to the second status signal output by the control signal generator of the previous stage latch and the valid signal corresponding to the decision result output by the comparator. The second NOR gate is used to output a second switch control signal. The first NOT gate is used to generate a first switch reset signal based on the first state signal output by the control signal generator of the previous stage latch. The second NOT gate is used to generate a second switch reset signal based on the second state signal output by the control signal generator of the previous stage latch. The first NAND gate is used to generate a first state signal for the current stage based on the output hold control signal and the first global reset signal. The second NAND gate is used to generate a second state signal for the current stage based on the output hold control signal and the second global reset signal.

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