A pulse signal protection circuit and protection method based on hardware real-time monitoring

Abstract

This invention belongs to the field of pulse signal monitoring and protection technology, and discloses a pulse signal protection circuit and method based on real-time hardware monitoring. The circuit includes a monitoring path, a threshold configuration register group, a comparator array, and an exception arbitration logic unit. The monitoring path monitors the time interval between adjacent same-direction transition edges, the time interval between adjacent opposite-direction transition edges, and the silence duration of the input pulse signal in real time. The comparator array compares the monitored values ​​with the corresponding thresholds and outputs an exception flag. When any exception flag is valid, the exception arbitration logic unit outputs a hardware trigger signal within a single system clock cycle, which is directly transmitted to the pulse signal generator via dedicated wiring, triggering it to stop pulse signal output. This invention achieves zero CPU intervention and nanosecond-level fast shutdown protection, and can simultaneously cover multiple fault modes such as periodic anomalies, duty cycle anomalies, and edge loss. It is suitable for industrial control and power electronics applications such as motor control and digital power supplies.

Description

Technical Field

[0001] This invention belongs to the field of pulse signal monitoring and protection technology, and specifically relates to a pulse signal protection circuit and protection method based on hardware real-time monitoring. Background Technology

[0002] Pulse signals are widely used information carriers in industrial control and power electronic systems. Their time characteristic parameters, such as the time interval between inverse and opposite transition edges and the signal activity, directly reflect the operating status of the controlled object. Taking motor control as an example, the period of the pulse signal output by the Hall sensor reflects the motor speed, and the duration of the high-level signal reflects the rotor position. If an abnormal sensor signal is not detected and protected in time, it may lead to overcurrent damage to power switching devices or even system burnout. Therefore, real-time abnormal monitoring of the time characteristic parameters of pulse signals and timely triggering of protection are crucial to ensuring the safe operation of the system.

[0003] In existing technologies, monitoring the time characteristic parameters of pulse signals typically relies on a CPU software polling scheme. This scheme involves the CPU periodically reading the timestamp register of the capture module, calculating and determining whether the time characteristic parameters of the pulse signal exceed limits using software, and then executing protective actions upon confirmation of an anomaly. However, the aforementioned software polling scheme has the following shortcomings: First, the response delay is large. From the occurrence of an abnormal pulse signal to the software's recognition and execution of protective actions, it typically takes tens to hundreds of microseconds. In applications such as motor control and digital power supplies, power switching devices may be damaged within a few microseconds when a short circuit or overcurrent occurs. The response speed of software solutions cannot meet the hardware protection requirements at the microsecond or even nanosecond level.

[0004] Secondly, it consumes CPU resources. High-frequency polling severely consumes CPU computing power, affecting the real-time performance and execution efficiency of the main control task.

[0005] Third, the monitoring dimensions are limited. Conventional watchdog circuits can only monitor signal timeouts and cannot monitor other time characteristic parameters of the pulse signal, such as the time interval between adjacent same-direction transition edges and the time interval between adjacent opposite-direction transition edges, making it difficult to comprehensively reflect the abnormal state of the pulse signal.

[0006] In summary, the existing technology lacks a hardware protection scheme that can perform real-time hardware monitoring of multiple time characteristic parameters of pulse signals and directly shut down the pulse signal output at a nanosecond speed when an anomaly occurs. Summary of the Invention

[0007] To address the aforementioned technical problems, this invention provides a pulse signal protection circuit and method based on real-time hardware monitoring. This allows for real-time hardware monitoring of multiple time characteristic parameters of the input pulse signal, such as the time interval between adjacent same-direction transition edges, the time interval between adjacent opposite-direction transition edges, and the duration of silence. When any parameter is abnormal, a hardware trigger signal is directly output through dedicated wiring within a single system clock cycle to shut down the pulse signal output, thereby achieving zero CPU intervention and nanosecond-level rapid protection.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows: A pulse signal protection circuit based on hardware real-time monitoring includes: The monitoring channel is configured to receive input pulse signals and monitor the time characteristic parameters of the input pulse signals in real time. A threshold configuration register group is used to configure the monitoring threshold of the time feature parameter; A comparator array, connected to the monitoring path and the threshold configuration register group, is used to compare the monitored value of the time feature parameter obtained by the monitoring path with the corresponding monitoring threshold in the threshold configuration register group, and output an abnormal flag when the monitored value exceeds the monitoring threshold; An exception arbitration logic unit, connected to the comparator array, is used to receive the exception flags and output a hardware trigger signal when any of the exception flags is valid; The hardware trigger signal is transmitted directly to the control input terminal of the pulse signal generator through a dedicated wiring to trigger the pulse signal generator to stop outputting pulse signals.

[0009] In the above scheme, the monitoring pathway includes: A time base counter is configured to count when the protection circuit is in operation; The edge detection unit is configured to capture the rising or falling edge of the input pulse signal and generate a valid edge flag when a rising edge is captured. A timestamp register, connected to the edge detection unit and the time base counter, is configured to latch the current count value of the time base counter in response to the valid edge flag.

[0010] In the above scheme, the timestamp register includes a first timestamp register and a second timestamp register; The edge detection unit is configured to: generate a first valid edge flag when a first edge is detected, triggering the first timestamp register to latch the current count value of the time base counter; and generate a second valid edge flag when a second edge is detected, triggering the second timestamp register to latch the current count value of the time base counter.

[0011] In the above scheme, the monitoring path also includes a same-direction interval latch, an opposite-direction interval latch, and a monitoring type configuration terminal; The monitoring type configuration terminal is used to configure the type of edge detected by the edge detection unit. The edge type includes adjacent same-direction edge and adjacent opposite-direction edge. The same-direction interval latch is connected to the first timestamp register, the second timestamp register and the transition edge detection unit. It is configured to respond to the second valid edge flag and, according to the configuration of the monitoring type configuration terminal, when the monitoring type is configured to monitor adjacent same-direction transition edges, latch the difference between the count values ​​of the second timestamp register and the first timestamp register as the first time interval between adjacent same-direction transition edges. The anisotropic interval latch is connected to the first timestamp register, the second timestamp register, and the transition edge detection unit. It is configured to respond to the second valid edge flag and, according to the configuration of the monitoring type configuration terminal, when the monitoring type is configured to monitor adjacent anisotropic transition edges, latch the difference between the count values ​​of the second timestamp register and the first timestamp register as the second time interval between adjacent anisotropic transition edges.

[0012] In a further technical solution, the monitoring path also includes a working enable terminal; The enable terminal is used to control the opening and closing of the protection circuit; when the hardware trigger signal is valid, the enable terminal is closed. When the enable terminal is turned on, the time base counter and the silence counter start counting, and the edge detection unit starts detecting the edge of the input pulse signal; when the enable terminal is turned off, the time base counter, the silence counter, and the edge detection unit stop working.

[0013] In a further technical solution, the monitoring thresholds configured by the threshold configuration register group include: the upper limit threshold and the lower limit threshold of the first time interval, and the upper limit threshold and the lower limit threshold of the second time interval; The comparator array includes: A first comparator, connected to the same-direction interval latch, is used to compare the first time interval with a lower limit threshold of the first time interval, and output a first time interval out-of-bounds flag 1 when the first time interval is less than the lower limit threshold. The second comparator, connected to the same-direction interval latch, is used to compare the first time interval with the upper limit threshold of the first time interval, and output the first time interval out-of-bounds flag 2 when the first time interval is greater than the upper limit threshold; The third comparator, connected to the opposite interval latch, is used to compare the second time interval with the lower limit threshold of the second time interval, and output the second time interval out-of-bounds flag 1 when the second time interval is less than the lower limit threshold. The fourth comparator, connected to the opposite interval latch, is used to compare the second time interval with the upper limit threshold of the second time interval, and output the second time interval out-of-bounds flag 2 when the second time interval is greater than the upper limit threshold.

[0014] In a further technical solution, the monitoring path also includes a silent counter, configured to start counting when the protection circuit is in operation, and to be reset after the edge detection unit generates a valid edge flag; The threshold configuration register group is also configured with a silent timeout threshold. The comparator array further includes a fifth comparator connected to the silent counter, used to compare the count value of the silent counter with the silent timeout threshold, and output a silent timeout exception flag when the count value of the silent counter exceeds the silent timeout threshold.

[0015] Further technical solutions also include: A first AND gate, connected to the monitoring type configuration terminal and the edge detection unit, is configured to output a valid control signal to start the first comparator and the second comparator when the monitoring type configuration terminal is configured to monitor adjacent edge transitions in the same direction and the edge detection unit generates the second valid edge flag. The second AND gate, connected to the monitoring type configuration terminal and the edge detection unit, is configured to output a valid control signal to start the third comparator and the fourth comparator when the monitoring type configuration terminal is configured to monitor adjacent opposite edge transitions and the edge detection unit generates the second valid edge flag.

[0016] In a further technical solution, the exception arbitration logic unit includes an OR gate, the multiple input terminals of the OR gate respectively receive the exception flag, and the output terminal of the OR gate outputs the hardware trigger signal within a single system clock cycle when any of the exception flags is valid; the transmission path of the hardware trigger signal does not pass through the system bus and does not depend on CPU operation.

[0017] A pulse signal protection method based on real-time hardware monitoring includes the following steps: Step 1: Configure monitoring parameters: Configure the monitoring thresholds for time characteristic parameters through the threshold configuration register group. The monitoring thresholds include the upper and lower thresholds of the first time interval, the upper and lower thresholds of the second time interval, and the silent timeout threshold. Configure the type of edge detected by the edge detection unit through the monitoring type configuration terminal. The edge type includes adjacent same-direction edge edges and adjacent opposite-direction edge edges. Enable the working state of the protection circuit through the working enable terminal. Step 2, Start Counting and Detection: After the enable terminal is turned on, the time base counter starts counting, the silence counter starts counting, and the rising edge detection unit starts detecting the rising edge of the input pulse signal; Step 3: Capture the transition edge and latch the timestamp: When the transition edge detection unit detects the first transition edge, it generates a first valid edge flag and latches the current count value of the time base counter to the first timestamp register; when the transition edge detection unit detects the second transition edge, it generates a second valid edge flag and latches the current count value of the time base counter to the second timestamp register. Step 4: Calculate and latch the time interval: In response to the second valid edge flag, the difference between the count values ​​of the second timestamp register and the first timestamp register is output to the same-direction interval latch and the opposite-direction interval latch, respectively; the same-direction interval latch latches the difference as the first time interval between adjacent same-direction transition edges when the monitoring type is configured to monitor adjacent same-direction transition edges, according to the configuration of the monitoring type configuration terminal; the opposite-direction interval latch latches the difference as the second time interval between adjacent opposite-direction transition edges when the monitoring type is configured to monitor adjacent opposite-direction transition edges, according to the configuration of the monitoring type configuration terminal. Step 5, Multi-parameter Comparison: When the monitoring type is configured as adjacent same-direction transition edges and the second valid edge flag is generated, the first AND gate outputs a valid control signal, activating the first and second comparators. The first time interval is compared with the lower and upper thresholds of the first time interval, respectively. If the first time interval is less than the lower threshold, a first time interval out-of-bounds flag 1 is output; if the first time interval is greater than the upper threshold, a first time interval out-of-bounds flag 2 is output. When the monitoring type is configured as adjacent opposite-direction transition edges and the second valid edge flag is generated, the second AND gate outputs a valid control signal, activating the third and fourth comparators. The second time interval is compared with the lower and upper thresholds of the second time interval, respectively. If the second time interval is less than the lower threshold, a second time interval out-of-bounds flag 1 is output; if the second time interval is greater than the upper threshold, a second time interval out-of-bounds flag 2 is output. Simultaneously, the fifth comparator compares the count value of the silent counter with the silent timeout threshold. If the count value of the silent counter is greater than the silent timeout threshold, a silent timeout exception flag is output. The silent counter is reset once each time the transition edge detection unit generates a valid edge flag. Step 6, Hardware Arbitration and Trigger Protection: The abnormal arbitration logic unit receives the first time interval out-of-bounds flag 1, the first time interval out-of-bounds flag 2, the second time interval out-of-bounds flag 1, the second time interval out-of-bounds flag 2, and the silent timeout abnormal flag. When any one of the abnormal flags is valid, a hardware trigger signal is output within a single system clock cycle. Step 7, Zero CPU Intervention Shutdown: The hardware trigger signal is transmitted directly to the control input terminal of the pulse signal generator through a dedicated wiring. The transmission path does not pass through the system bus and does not depend on CPU operation. After receiving the valid hardware trigger signal, the pulse signal generator immediately stops outputting pulse signals and simultaneously turns off the enable terminal.

[0018] Through the above technical solution, the pulse signal protection circuit and protection method based on real-time hardware monitoring provided by the present invention have the following beneficial effects: 1. This invention outputs a hardware trigger signal within a single system clock cycle when any exception flag is valid through an exception arbitration logic unit, and transmits it directly to the pulse signal generator through dedicated wiring without going through the system bus and CPU operation. This achieves a nanosecond-level fast protection effect, where the time from the occurrence of an exception to the cessation of pulse signal output is only about 80ns, which is far superior to the tens to hundreds of microsecond delays of software polling schemes.

[0019] 2. This invention enables the entire process of monitoring, comparison, arbitration, and triggering protection to be completed autonomously by hardware through the monitoring path, comparator array, and abnormal arbitration logic unit. It eliminates the need for CPU polling, calculation, or execution of protection actions, achieving the effect of zero CPU load, unaffected by system bus congestion, and allowing the main control CPU to focus on other real-time control tasks.

[0020] 3. By setting up a co-directional interval latch, an anti-directional interval latch, a silence counter, and first to fifth comparators, this invention simultaneously monitors three types of time characteristic parameters in real time: the time interval between adjacent co-directional transition edges, the time interval between adjacent anti-directional transition edges, and the silence duration without transition edges. This achieves the effect of covering various fault modes such as abnormal pulse signal period, abnormal duty cycle, and missing edges, and significantly improving the completeness and reliability of anomaly detection.

[0021] 4. This invention uses an abnormal arbitration logic unit to immediately output a hardware trigger signal when any abnormal flag is valid. After receiving the valid hardware trigger signal, the pulse signal generator immediately stops outputting the pulse signal. This achieves the effect of avoiding the impact of software delay, bus arbitration delay, or CPU load fluctuation on protection actions, effectively preventing power switching devices from being damaged by overcurrent or abnormal pulse signals, and improving system safety.

[0022] 5. This invention flexibly configures the upper and lower thresholds of the first time interval and the second time interval, as well as the silent timeout threshold, through the threshold configuration register group. It also allows selection of monitoring adjacent same-direction transition edges or adjacent opposite-direction transition edges through the monitoring type configuration terminal. This achieves the effect of adapting to different pulse signal periods, duty cycles and tolerance requirements, and is widely applicable to industrial control and power electronics application scenarios such as motor control and digital power supply. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0024] Figure 1 This is a schematic diagram of a pulse signal protection circuit based on real-time hardware monitoring disclosed in an embodiment of the present invention; Figure 1 A black dot marks the intersection of conductors, indicating that the conductors at the intersection are electrically connected; intersections without a black dot indicate that the conductors cross but are not connected. Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0026] I. Overall Circuit Structure See Figure 1This invention provides a pulse signal protection circuit based on real-time hardware monitoring, comprising the following five main parts: (a) Monitoring channel, configured to receive input pulse signals and monitor the time characteristic parameters of the input pulse signals in real time; (ii) Threshold configuration register group, used to configure the monitoring threshold of time feature parameters; (iii) Comparator array, connected to the monitoring path and threshold configuration register group, is used to compare the monitoring value of the time feature parameter obtained by the monitoring path with the corresponding monitoring threshold in the threshold configuration register group, and output an abnormal flag when the monitoring value exceeds the monitoring threshold; (iv) An exception arbitration logic unit, connected to the comparator array, is used to receive exception flags and output a hardware trigger signal when any exception flag is valid; (v) AND gate control logic, including a first AND gate and a second AND gate, used to configure the startup of the corresponding comparator in the control comparator array according to the monitoring type.

[0027] II. Specific Components and Functions of Each Part (a) Monitoring pathway The monitoring pathway includes the following sub-units: 1. Time base counter A count is performed when the protection circuit starts working, and the count value is used as a reference for the timestamp.

[0028] 2. Edge detection unit Depending on the monitoring type configuration, the rising or falling edge of the input pulse signal is captured, and a valid edge flag is generated when a transition edge is captured. Specifically, a first valid edge flag is generated when a first transition edge is detected, and a second valid edge flag is generated when a second transition edge is detected.

[0029] 3. First timestamp register Connected to the edge detection unit and the time base counter, configured to latch the current count value of the time base counter in response to the first valid edge flag.

[0030] 4. Second timestamp register Connected to the edge detection unit and the time base counter, configured to latch the current count value of the time base counter in response to the second valid edge flag.

[0031] 5. Co-directional interval latch Connected to the first timestamp register, the second timestamp register, and the transition edge detection unit, and configured to respond to the second valid edge flag, according to the configuration of the monitoring type configuration terminal, when the monitoring type is configured to monitor adjacent same-direction transition edges, the difference between the count values ​​of the second timestamp register and the first timestamp register is latched as the first time interval between adjacent same-direction transition edges.

[0032] 6. Opposite-direction interval latch Connected to the first timestamp register, the second timestamp register, and the edge detection unit, and configured to respond to the second valid edge flag, according to the configuration of the monitoring type configuration terminal, when the monitoring type is configured to monitor adjacent opposite edge transitions, the difference between the count values ​​of the second timestamp register and the first timestamp register is latched as the second time interval between adjacent opposite edge transitions.

[0033] 7. Silent Counter The counting begins when the protection circuit is in operation, and is reset after each valid edge flag is generated by the edge detection unit.

[0034] 8. Enable terminal This is used to control the on / off state of the protection circuit. When the hardware trigger signal is valid, the enable pin is turned off. When the enable pin is turned on, the time base counter starts counting, the edge detection unit starts detecting the edge of the input pulse signal, and the silence counter starts counting. When the enable pin is turned off, the time base counter, the edge detection unit, and the silence counter stop working.

[0035] 9. Monitoring Type Configuration Terminal This is used to configure the edge detection unit to detect edge types. Edge types include adjacent same-direction edge transitions and adjacent opposite-direction edge transitions. Adjacent same-direction edge transitions can be configured as rising edge to rising edge or falling edge to falling edge; adjacent opposite-direction edge transitions can be configured as rising edge to falling edge or falling edge to rising edge. The monitoring type configuration terminal simultaneously controls the operation of the first AND gate and the second AND gate.

[0036] (ii) Threshold configuration register group The threshold configuration register group includes the following subgroups: 1. A first time interval upper limit threshold register, used to store the upper limit threshold of the first time interval; 2. A first time interval lower limit threshold register, used to store the lower limit threshold of the first time interval; 3. Second time interval upper limit threshold register, used to store the upper limit threshold of the second time interval; 4. Second time interval lower limit threshold register, used to store the lower limit threshold of the second time interval; 5. Silent Timeout Threshold Register, used to store the timeout threshold of the silent counter.

[0037] (III) Comparator Array The comparator array consists of the following sub-units: 1. First comparator C1 Connected to the same-direction interval latch, it is used to compare the first time interval with the lower limit threshold of the first time interval, and output the first time interval out-of-bounds flag 1 when the first time interval is less than the lower limit threshold.

[0038] 2. Second comparator C2 Connected to the same-direction interval latch, it is used to compare the first time interval with the upper limit threshold of the first time interval, and output the first time interval out-of-bounds flag 2 when the first time interval is greater than the upper limit threshold.

[0039] 3. Third comparator C3 Connected to the opposite interval latch, it is used to compare the second time interval with the lower limit threshold of the second time interval, and output the second time interval out-of-bounds flag 1 when the second time interval is less than the lower limit threshold.

[0040] 4. Fourth comparator C4 Connected to the opposite interval latch, it is used to compare the second time interval with the upper limit threshold of the second time interval, and output the second time interval out-of-bounds flag 2 when the second time interval is greater than the upper limit threshold.

[0041] 5. Fifth comparator C5 Connected to a silent counter, it compares the count value of the silent counter with the silent timeout threshold and outputs a silent timeout exception flag when the count value of the silent counter exceeds the silent timeout threshold.

[0042] (iv) Abnormal Arbitration Logic Unit An exception arbitration logic unit is connected to a comparator array and includes an OR gate. The multiple inputs of the OR gate receive all exception flags, including a first time interval out-of-bounds flag 1, a first time interval out-of-bounds flag 2, a second time interval out-of-bounds flag 1, a second time interval out-of-bounds flag 2, and a silence timeout exception flag. When any exception flag is valid, the output of the OR gate outputs a hardware trigger signal within a single system clock cycle. The hardware trigger signal is transmitted directly to the control input of the pulse signal generator via dedicated wiring; this transmission path does not pass through the system bus and is independent of CPU operation. Upon receiving a valid hardware trigger signal, the pulse signal generator immediately stops outputting pulse signals and simultaneously disables its enable pin.

[0043] (v) AND gate control logic AND gate control logic includes the following sub-units: 1. First AND gate Connected to the monitoring type configuration terminal and the edge detection unit, it is configured to output a valid control signal to start the first comparator and the second comparator when the monitoring type configuration terminal is configured to monitor adjacent edge transitions in the same direction and the edge detection unit generates a second valid edge flag.

[0044] 2. Second AND gate Connected to the monitoring type configuration terminal and the edge detection unit, it is configured to output a valid control signal to start the third and fourth comparators when the monitoring type configuration terminal is configured to monitor adjacent opposite edge transitions and the edge detection unit generates a second valid edge flag.

[0045] III. Work Process The working process of the protection circuit of this invention is as follows: Step 1: Configure monitoring parameters. Configure the monitoring thresholds for time characteristic parameters through the threshold configuration register group, including the upper and lower thresholds for the first time interval, the upper and lower thresholds for the second time interval, and the silent timeout threshold; configure the type of edge detected by the edge detection unit through the monitoring type configuration terminal; enable the working state of the protection circuit through the working enable terminal.

[0046] Step 2: Start Counting and Detection. After the enable pin is turned on, the time base counter starts counting, the silence counter starts counting, and the edge detection unit starts detecting the edge of the input pulse signal.

[0047] Step 3: Capture the transition edge and latch the timestamp. When the transition edge detection unit detects the first transition edge, it generates a first valid edge flag and latches the current count value of the time base counter to the first timestamp register; when the transition edge detection unit detects the second transition edge, it generates a second valid edge flag and latches the current count value of the time base counter to the second timestamp register.

[0048] Step 4: Calculate and latch the time interval. In response to the second valid edge flag, the difference between the count values ​​of the second timestamp register and the first timestamp register is output to the same-direction interval latch and the opposite-direction interval latch, respectively. The same-direction interval latch, according to the monitoring type configuration terminal, latches the difference as the first time interval between adjacent same-direction edges when the monitoring type is configured to monitor adjacent same-direction edges. The opposite-direction interval latch, according to the monitoring type configuration terminal, latches the difference as the second time interval between adjacent opposite-direction edges when the monitoring type is configured to monitor adjacent opposite-direction edges.

[0049] Step 5: Multi-parameter comparison. When the monitoring type is configured as adjacent same-direction transition edges and a second valid edge flag is generated, the first AND gate outputs a valid control signal, activating the first and second comparators. The first time interval is compared with its lower and upper threshold values, respectively. If the first time interval is less than the lower threshold, a first time interval out-of-bounds flag 1 is output; if the first time interval is greater than the upper threshold, a first time interval out-of-bounds flag 2 is output. When the monitoring type is configured as adjacent opposite-direction transition edges and a second valid edge flag is generated, the second AND gate outputs a valid control signal, activating the third and fourth comparators. The second time interval is compared with its lower and upper threshold values, respectively. If the second time interval is less than the lower threshold, a second time interval out-of-bounds flag 1 is output; if the second time interval is greater than the upper threshold, a second time interval out-of-bounds flag 2 is output. Simultaneously, the fifth comparator compares the count value of the silence counter with the silence timeout threshold. If the count value of the silence counter is greater than the silence timeout threshold, a silence timeout exception flag is output. The silence counter is reset once each time a valid edge flag is generated by the transition edge detection unit.

[0050] Step Six: Hardware Arbitration and Trigger Protection. The exception arbitration logic unit receives the first time interval out-of-bounds flag 1, the first time interval out-of-bounds flag 2, the second time interval out-of-bounds flag 1, the second time interval out-of-bounds flag 2, and the silent timeout exception flag. When any one of the exception flags is valid, a hardware trigger signal is output within a single system clock cycle.

[0051] Step 7: Zero CPU Intervention Shutdown. The hardware trigger signal is transmitted directly to the control input of the pulse signal generator via dedicated wiring. The transmission path does not pass through the system bus and does not depend on CPU operation. After receiving a valid hardware trigger signal, the pulse signal generator immediately stops outputting pulse signals and simultaneously turns off the enable terminal. IV. Specific Implementation Examples The following example, using the time interval between adjacent edges of a pulse signal in the same direction as monitoring, illustrates the specific implementation process of this invention. Assume the input pulse signal period is 2μs, the duty cycle is 50%, the system clock is 100MHz, and the tolerance is 1%.

[0053] First, the monitoring type is configured as adjacent same-direction edge—rising edge to rising edge. Since the input pulse signal period is 2μs and the system clock period is 10ns, 2μs / 10ns=200. Based on a tolerance of 1%, the lower limit threshold of the first time interval is configured as 198 and the upper limit threshold of the first time interval is configured as 202.

[0054] When the protection circuit is enabled, the monitoring path and the rising edge detection unit begin to operate. When the rising edge detection unit detects the first rising edge, it outputs a first valid edge flag and latches the current time base counter count value (e.g., 158) into the first timestamp register; when the rising edge detection unit detects the second rising edge, it outputs a second valid edge flag and latches the current time base counter count value (e.g., 358) into the second timestamp register.

[0055] After outputting the second valid edge flag, the count value 358 of the second timestamp register is subtracted from the count value 158 of the first timestamp register, and the resulting count value 200 is latched into the same-direction interval latch.

[0056] At this point, the output of the first AND gate is valid, comparing the count value 200 of the same-direction interval latch with the upper and lower limits of the first time interval. Because 200 > 198, the first time interval out-of-bounds flag 1 is invalid; 200 < 202, so the first time interval out-of-bounds flag 2 is invalid. This indicates that the input pulse signal is within the tolerance range and is normal.

[0057] If the pulse signal is abnormal, for example, the count value latched by the first timestamp register is 160 and the count value latched by the second timestamp register is 400, after outputting the second valid edge flag, the count value of the second timestamp register 400 is subtracted from the count value of the first timestamp register 160, and the resulting count value 240 is latched into the same direction interval latch.

[0058] At this point, the output of the first AND gate is valid, comparing the count value 240 of the same-direction interval latch with the upper and lower thresholds of the first time interval. Because 240 > 198, the first time interval out-of-bounds flag 1 is invalid; 240 > 202, so the first time interval out-of-bounds flag 2 is valid. This indicates that the input pulse signal exceeds the tolerance range and is abnormal.

[0059] When the exception arbitration logic unit receives a valid first time interval out-of-bounds flag 2, it immediately outputs a valid hardware trigger signal to the pulse signal generator and generates an interrupt notification to the CPU. Upon receiving the valid hardware trigger signal, the pulse signal generator immediately stops outputting pulse signals; the CPU jumps to the interrupt service routine for relevant processing. From the time the hardware trigger signal becomes valid until the pulse signal generator stops outputting pulse signals, actual measurements show that 8 system clock cycles, or 80 ns, are consumed.

[0060] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A pulse signal protection circuit based on real-time hardware monitoring, characterized in that, include: The monitoring channel is configured to receive input pulse signals and monitor the time characteristic parameters of the input pulse signals in real time. A threshold configuration register group is used to configure the monitoring threshold of the time feature parameter; A comparator array, connected to the monitoring path and the threshold configuration register group, is used to compare the monitored value of the time feature parameter obtained by the monitoring path with the corresponding monitoring threshold in the threshold configuration register group, and output an abnormal flag when the monitored value exceeds the monitoring threshold; An exception arbitration logic unit, connected to the comparator array, is used to receive the exception flags and output a hardware trigger signal when any of the exception flags is valid; The hardware trigger signal is transmitted directly to the control input terminal of the pulse signal generator through a dedicated wiring to trigger the pulse signal generator to stop outputting pulse signals.

2. The pulse signal protection circuit based on real-time hardware monitoring according to claim 1, characterized in that, The monitoring pathways include: A time base counter is configured to count when the protection circuit is in operation; The edge detection unit is configured to capture the rising or falling edge of the input pulse signal and generate a valid edge flag when a rising edge is captured. A timestamp register, connected to the edge detection unit and the time base counter, is configured to latch the current count value of the time base counter in response to the valid edge flag.

3. The pulse signal protection circuit based on real-time hardware monitoring according to claim 2, characterized in that, The timestamp register includes a first timestamp register and a second timestamp register; The edge detection unit is configured to: generate a first valid edge flag when a first edge is detected, triggering the first timestamp register to latch the current count value of the time base counter; and generate a second valid edge flag when a second edge is detected, triggering the second timestamp register to latch the current count value of the time base counter.

4. The pulse signal protection circuit based on real-time hardware monitoring according to claim 3, characterized in that, The monitoring path also includes a same-direction interval latch, an opposite-direction interval latch, and a monitoring type configuration terminal; The monitoring type configuration terminal is used to configure the type of edge detected by the edge detection unit. The edge type includes adjacent same-direction edge and adjacent opposite-direction edge. The same-direction interval latch is connected to the first timestamp register, the second timestamp register and the transition edge detection unit. It is configured to respond to the second valid edge flag and, according to the configuration of the monitoring type configuration terminal, when the monitoring type is configured to monitor adjacent same-direction transition edges, latch the difference between the count values ​​of the second timestamp register and the first timestamp register as the first time interval between adjacent same-direction transition edges. The anisotropic interval latch is connected to the first timestamp register, the second timestamp register, and the transition edge detection unit. It is configured to respond to the second valid edge flag and, according to the configuration of the monitoring type configuration terminal, when the monitoring type is configured to monitor adjacent anisotropic transition edges, latch the difference between the count values ​​of the second timestamp register and the first timestamp register as the second time interval between adjacent anisotropic transition edges.

5. The pulse signal protection circuit based on real-time hardware monitoring according to claim 4, characterized in that, The monitoring path also includes a working enable terminal; The enable terminal is used to control the opening and closing of the protection circuit; when the hardware trigger signal is valid, the enable terminal is closed. When the enable terminal is turned on, the time base counter and the silence counter start counting, and the edge detection unit starts detecting the edge of the input pulse signal; when the enable terminal is turned off, the time base counter, the silence counter, and the edge detection unit stop working.

6. The pulse signal protection circuit based on real-time hardware monitoring according to claim 5, characterized in that, The monitoring thresholds configured in the threshold configuration register group include: the upper and lower thresholds of the first time interval, and the upper and lower thresholds of the second time interval; The comparator array includes: A first comparator, connected to the same-direction interval latch, is used to compare the first time interval with a lower limit threshold of the first time interval, and output a first time interval out-of-bounds flag 1 when the first time interval is less than the lower limit threshold. The second comparator, connected to the same-direction interval latch, is used to compare the first time interval with the upper limit threshold of the first time interval, and output the first time interval out-of-bounds flag 2 when the first time interval is greater than the upper limit threshold; The third comparator, connected to the opposite interval latch, is used to compare the second time interval with the lower limit threshold of the second time interval, and output the second time interval out-of-bounds flag 1 when the second time interval is less than the lower limit threshold. The fourth comparator, connected to the opposite interval latch, is used to compare the second time interval with the upper limit threshold of the second time interval, and output the second time interval out-of-bounds flag 2 when the second time interval is greater than the upper limit threshold.

7. The pulse signal protection circuit based on real-time hardware monitoring according to claim 6, characterized in that, The monitoring path also includes a silent counter, configured to start counting when the protection circuit is in operation and to be reset after the edge detection unit generates a valid edge flag. The threshold configuration register group is also configured with a silent timeout threshold. The comparator array further includes a fifth comparator connected to the silent counter, used to compare the count value of the silent counter with the silent timeout threshold, and output a silent timeout exception flag when the count value of the silent counter exceeds the silent timeout threshold.

8. The pulse signal protection circuit based on real-time hardware monitoring according to claim 7, characterized in that, Also includes: A first AND gate, connected to the monitoring type configuration terminal and the edge detection unit, is configured to output a valid control signal to start the first comparator and the second comparator when the monitoring type configuration terminal is configured to monitor adjacent edge transitions in the same direction and the edge detection unit generates the second valid edge flag. The second AND gate, connected to the monitoring type configuration terminal and the edge detection unit, is configured to output a valid control signal to start the third comparator and the fourth comparator when the monitoring type configuration terminal is configured to monitor adjacent opposite edge transitions and the edge detection unit generates the second valid edge flag.

9. The pulse signal protection circuit based on real-time hardware monitoring according to any one of claims 1 to 8, characterized in that, The exception arbitration logic unit includes an OR gate, the multiple inputs of which receive the exception flags respectively, and the output of the OR gate outputs the hardware trigger signal within a single system clock cycle when any of the exception flags is valid; the transmission path of the hardware trigger signal does not pass through the system bus and does not depend on CPU operation.

10. A pulse signal protection method based on real-time hardware monitoring, characterized in that, Includes the following steps: Step 1: Configure monitoring parameters: Configure the monitoring thresholds for time characteristic parameters through the threshold configuration register group. The monitoring thresholds include the upper and lower thresholds of the first time interval, the upper and lower thresholds of the second time interval, and the silent timeout threshold. Configure the type of edge detected by the edge detection unit through the monitoring type configuration terminal. The edge type includes adjacent same-direction edge edges and adjacent opposite-direction edge edges. Enable the working state of the protection circuit through the working enable terminal. Step 2, Start Counting and Detection: After the enable terminal is turned on, the time base counter starts counting, the silence counter starts counting, and the rising edge detection unit starts detecting the rising edge of the input pulse signal; Step 3: Capture the transition edge and latch the timestamp: When the transition edge detection unit detects the first transition edge, it generates the first valid edge flag and latches the current count value of the time base counter into the first timestamp register; When the edge detection unit detects the second edge, it generates a second valid edge flag and latches the current count value of the time base counter into the second timestamp register. Step 4: Calculate and latch the time interval: In response to the second valid edge flag, the difference between the count values ​​of the second timestamp register and the first timestamp register is output to the same-direction interval latch and the opposite-direction interval latch, respectively; the same-direction interval latch latches the difference as the first time interval between adjacent same-direction transition edges when the monitoring type is configured to monitor adjacent same-direction transition edges, according to the configuration of the monitoring type configuration terminal; the opposite-direction interval latch latches the difference as the second time interval between adjacent opposite-direction transition edges when the monitoring type is configured to monitor adjacent opposite-direction transition edges, according to the configuration of the monitoring type configuration terminal. Step 5, Multi-parameter Comparison: When the monitoring type is configured as adjacent same-direction transition edges and the second valid edge flag is generated, the first AND gate outputs a valid control signal, activating the first and second comparators. The first time interval is compared with the lower and upper thresholds of the first time interval, respectively. If the first time interval is less than the lower threshold, a first time interval out-of-bounds flag 1 is output; if the first time interval is greater than the upper threshold, a first time interval out-of-bounds flag 2 is output. When the monitoring type is configured as adjacent opposite-direction transition edges and the second valid edge flag is generated, the second AND gate outputs a valid control signal, activating the third and fourth comparators. The second time interval is compared with the lower and upper thresholds of the second time interval, respectively. If the second time interval is less than the lower threshold, a second time interval out-of-bounds flag 1 is output; if the second time interval is greater than the upper threshold, a second time interval out-of-bounds flag 2 is output. Simultaneously, the fifth comparator compares the count value of the silent counter with the silent timeout threshold. If the count value of the silent counter is greater than the silent timeout threshold, a silent timeout exception flag is output. The silent counter is reset once each time the transition edge detection unit generates a valid edge flag. Step 6, Hardware Arbitration and Trigger Protection: The abnormal arbitration logic unit receives the first time interval out-of-bounds flag 1, the first time interval out-of-bounds flag 2, the second time interval out-of-bounds flag 1, the second time interval out-of-bounds flag 2, and the silent timeout abnormal flag. When any one of the abnormal flags is valid, a hardware trigger signal is output within a single system clock cycle. Step 7, Zero CPU Intervention Shutdown: The hardware trigger signal is transmitted directly to the control input terminal of the pulse signal generator through a dedicated wiring. The transmission path does not pass through the system bus and does not depend on CPU operation. After receiving the valid hardware trigger signal, the pulse signal generator immediately stops outputting pulse signals and simultaneously turns off the enable terminal.

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