Deep N-well bootstrap bias circuits, circuit boards, devices and systems

Abstract

This application discloses a deep N-well bootstrap bias circuit, circuit board, device, and system, relating to the field of semiconductor integrated circuit technology. The deep N-well bootstrap bias circuit includes a potential selection module, a bootstrap energy storage module, and a charging module. The potential selection module includes a first unidirectional conductive unit and a second unidirectional conductive unit, with the output terminal of the first unidirectional conductive unit connected to the output terminal of the second unidirectional conductive unit. The bootstrap energy storage module includes a bootstrap capacitor, one end of which is the bootstrap terminal, connected to the input terminal of the second unidirectional conductive unit via the bootstrap terminal. The other end of the bootstrap capacitor is used for electrical connection to an external power stage circuit via a switching node. The charging module is electrically connected to the bootstrap capacitor via the bootstrap terminal. This application, through the first guiding conductive unit and the second unidirectional conductive unit, ensures that the potential of the deep N-well is always the higher of the driving voltage terminal and the bootstrap terminal, thereby preventing the deep N-well potential from becoming negative and causing the bootstrap capacitor to fail.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a deep N-well bootstrap bias circuit, circuit board, device and system. Background Technology

[0002] In the classic scheme of monolithically integrated high-side NOMS (N-channel Metal-Oxide-Semiconductor) gate drive circuit, two techniques are usually used simultaneously: an external bootstrap capacitor is set across the BST (Bootstrap) node and SW (Switch) node to provide the operating voltage for the high-side floating circuit; and a fully isolated MOS transistor isolation ring structure is used internally. Specifically, the isolation ring structure of the fully isolated MOS transistor is as follows: a deep N-well (DNW) is formed in the P-type substrate (PSUB), and a deep P-well (DPW) is formed inside the deep N-well. The NMOS is directly fabricated in this deep P-well, and an N-well (NWELL) is formed inside the deep P-well. The PMOS is directly fabricated in this N-well. Both the P-type substrate and the deep P-well have P+ regions (heavily doped P-type regions). The P+ region of the P-type substrate is grounded (GND). The P+ region of the deep P-well is electrically connected to the external power stage circuit through the SW node. Both the deep N-well and the N-well have N+ regions (heavily doped N-type regions). The N+ regions of both the deep N-well and the N-well are connected to the BST node.

[0003] A parasitic PN junction exists between the P-type substrate and the deep N-well. The anode of this parasitic PN junction is located on the P-type substrate, and the cathode is located in the deep N-well. In conventional technology, the N+ region of the deep N-well is usually connected to the BST node, and a fixed voltage is applied to the BST node to prevent the parasitic PN junction from conducting when the SW node voltage is positive. However, the potential of the SW node is determined by the external power stage circuit and is not always non-negative. Under certain operating conditions, such as inductive load freewheeling, parasitic parameter resonance, body diode conduction, or external load voltage intervention, the voltage of the SW node can momentarily swing to a negative value. When the voltage of the SW node is negative, the voltage of the BST node will also decrease due to the influence of the bootstrap capacitor. When the voltage of the SW node becomes negative to a certain extent, the voltage of the BST node will also become negative, which may cause the parasitic PN junction between the P-type substrate and the deep N-well to conduct. This will cause the voltage across the bootstrap capacitor to gradually increase, and eventually the voltage across the bootstrap capacitor will exceed the margin, causing the bootstrap capacitor and the chip to fail. Summary of the Invention

[0004] This application aims to at least solve one of the technical problems existing in the prior art. To this end, this application proposes a deep N-well bootstrap bias circuit, circuit board, device, and system, which, through a first guiding conductive unit and a second unidirectional conductive unit, ensures that the potential of the deep N-well is always the higher of the driving voltage terminal and the bootstrap terminal, thereby avoiding the deep N-well potential from being negative and causing the bootstrap capacitor to fail.

[0005] A deep N-well bootstrap bias circuit according to a first aspect of this application includes a potential selection module, a bootstrap energy storage module, and a charging module. The potential selection module includes a first unidirectional conductive unit and a second unidirectional conductive unit. The input terminal of the first unidirectional conductive unit is connected to a driving voltage terminal, and the output terminal of the first unidirectional conductive unit is connected to the output terminal of the second unidirectional conductive unit. The output terminal of the first unidirectional conductive unit is also electrically connected to the deep N-well. The bootstrap energy storage module includes a bootstrap capacitor. One end of the bootstrap capacitor is a bootstrap terminal, which is connected to the input terminal of the second unidirectional conductive unit. The other end of the bootstrap capacitor is electrically connected to an external power stage circuit through a switching node. The bootstrap capacitor provides an operating voltage to the external power stage circuit. The first unidirectional conductive unit and the second unidirectional conductive unit are used to make the higher potential between the driving voltage terminal and the bootstrap terminal the bias potential of the deep N-well. The charging module is electrically connected to the bootstrap capacitor through the bootstrap terminal, and the charging module is used to charge the bootstrap capacitor.

[0006] The deep N-well bootstrap bias circuit according to the embodiments of this application has at least the following beneficial effects: by setting a bootstrap capacitor, a floating gate drive voltage is provided for the high-side power transistor in the external power stage circuit, and it is also used to maintain a certain voltage difference between the bootstrap terminal and the SW node; the setting of the charging module is used to charge the bootstrap capacitor to ensure that the bootstrap capacitor can work normally; the setting of the first unidirectional conductive unit and the second unidirectional conductive unit is used to make the higher potential between the driving voltage terminal and the bootstrap terminal the bias potential of the deep N-well; so that when the SW node swings to a negative value instantaneously, and the potential of the bootstrap terminal also drops to a negative value, since the potential of the driving voltage terminal is fixed, at this time, the first unidirectional conductive unit is turned on and the second unidirectional conductive unit is turned off, so that the value of the driving voltage terminal potential minus the forward conduction voltage drop of the first unidirectional conductive unit is used as the bias potential of the deep N-well, thereby avoiding the deep N-well bias potential being negative, which would cause the parasitic PN junction between the deep N-well and the P-type substrate to conduct, causing the bootstrap capacitor and the chip to fail.

[0007] According to some embodiments of this application, the potential selection module further includes a bleed resistor, one end of which is connected to the input terminal of the first unidirectional conductive unit, and the other end of which is connected to the output terminal of the first unidirectional conductive unit.

[0008] According to some embodiments of this application, the charging module includes a controllable switch transistor and a switch control unit. The first conductive terminal of the controllable switch transistor is connected to the driving voltage terminal, and the second conductive terminal of the controllable switch transistor is connected to the bootstrap capacitor through the bootstrap terminal. The bootstrap capacitor is connected to the input terminal of the switch control unit through the bootstrap terminal, and the output terminal of the switch control unit is connected to the control terminal of the controllable switch transistor. The switch control unit is used to control the controllable switch transistor to be turned on or off.

[0009] According to some embodiments of this application, the switch control unit includes a comparator and a level shifter. A bootstrap capacitor is connected to the first input terminal of the comparator through the bootstrap terminal. The output terminal of the comparator is connected to the control terminal of the controllable switch through the level shifter. The second input terminal of the comparator is used to connect to a reference voltage.

[0010] According to some embodiments of this application, the charging module further includes a third unidirectional conductive unit, the input terminal of which is connected to the second conductive terminal of the controllable switch transistor, and the output terminal of which is connected to the bootstrap capacitor via a bootstrap terminal.

[0011] According to some embodiments of this application, both the first unidirectional conductive unit and the second unidirectional conductive unit are Schottky diodes.

[0012] According to some embodiments of this application, the controllable switch is a P-channel MOSFET.

[0013] The circuit board according to a second aspect embodiment of this application includes: The deep N-well bootstrap bias circuit of the first aspect of this application.

[0014] The device according to the embodiments of this application has at least the following beneficial effects: by setting a bootstrap capacitor, a floating gate drive voltage is provided for the high-side power transistor in the external power stage circuit, and it is also used to maintain a certain voltage difference between the bootstrap terminal and the SW node; the setting of the charging module is used to charge the bootstrap capacitor to ensure that the bootstrap capacitor can work normally; the setting of the first unidirectional conductive unit and the second unidirectional conductive unit is used to make the higher potential of the driving voltage terminal and the bootstrap terminal the bias potential of the deep N-well; so that when the SW node swings to a negative value instantaneously, and the potential of the bootstrap terminal also drops to a negative value, since the potential of the driving voltage terminal is fixed, at this time, the first unidirectional conductive unit is turned on and the second unidirectional conductive unit is turned off, so that the value of the driving voltage terminal potential minus the forward conduction voltage drop of the first unidirectional conductive unit is used as the bias potential of the deep N-well, thereby avoiding the deep N-well bias potential being negative, which would cause the parasitic PN junction between the deep N-well and the P-type substrate to conduct, causing the bootstrap capacitor and the chip to fail. By introducing the deep N-well bootstrap bias circuit of this application, it is possible to effectively deal with the scenario where the SW node swings between positive and negative values, and to prevent the parasitic PN junction between the P-type substrate and the deep N-well from conducting due to the negative potential of the SW node, which would cause the bootstrap capacitor and the chip to fail.

[0015] The device according to a third aspect embodiment of this application includes: The circuit board of the second aspect of this application.

[0016] The system according to a fourth aspect embodiment of this application includes: The device according to the third aspect of this application.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a deep N-well bootstrap bias circuit according to an embodiment of this application; Figure 2 This is a schematic diagram of a classic scheme for integrating a high-side NMOS gate drive circuit on a single chip. Figure 3 This is a timing diagram of the potential of each node in the deep N-well bootstrap bias circuit of this application during the charging phase and bootstrap phase. Figure 4 This is a schematic diagram of a deep N-well bootstrap bias circuit applied to a monolithically integrated high-side NMOS gate drive circuit, according to an embodiment of this application. Detailed Implementation

[0019] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0020] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0021] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0022] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0023] Currently, in classic monolithically integrated high-side NOMS (N-channel Metal-Oxide-Semiconductor) gate drive circuits, two techniques are typically employed simultaneously: an external bootstrap capacitor is used across the BST (Bootstrap) node and SW (Switch) node to provide the operating voltage for the high-side floating circuit; internally, a fully isolated MOS transistor isolation ring structure is used. (Refer to...) Figure 2 The isolation ring structure of the fully isolated MOSFET is as follows: a deep N-well (DNW) is formed in the P-type substrate (PSUB), and a deep P-well (DPW) is formed inside the deep N-well. The NMOS is directly fabricated in this deep P-well, and an N-well (NWELL) is formed inside the deep P-well. The PMOS is directly fabricated in this N-well. Both the P-type substrate and the deep P-well have P+ regions (heavily doped P-type regions). The P+ region of the P-type substrate is grounded (GND). The P+ region of the deep P-well is electrically connected to the external power stage circuit through the SW node. Both the deep N-well and the N-well have N+ regions (heavily doped N-type regions). The N+ regions of both the deep N-well and the N-well are connected to the BST node.

[0024] A parasitic PN junction exists between the P-type substrate and the deep N-well. The anode of this parasitic PN junction is located on the P-type substrate, and the cathode is located in the deep N-well. In conventional technology, the N+ region of the deep N-well is usually connected to the BST node, and a fixed voltage is applied to the BST node to prevent the parasitic PN junction from conducting when the SW node voltage is positive. However, the potential of the SW node is determined by the external power stage circuit and is not always non-negative. Under certain operating conditions, such as inductive load freewheeling, parasitic parameter resonance, body diode conduction, or external load voltage intervention, the voltage of the SW node can momentarily swing to a negative value. When the voltage of the SW node is negative, the voltage of the BST node will also decrease due to the influence of the bootstrap capacitor. When the voltage of the SW node becomes negative to a certain extent, the voltage of the BST node will also become negative, which may cause the parasitic PN junction between the P-type substrate and the deep N-well to conduct. This will cause the voltage across the bootstrap capacitor to gradually increase, and eventually the voltage across the bootstrap capacitor will exceed the margin, causing the bootstrap capacitor and the chip to fail.

[0025] Existing technologies also include solutions that use MOS well switches or charge pumps to dynamically switch the deep N-well bias to address the above problems, but these solutions increase area, timing complexity, and failure modes, thereby raising costs and barriers to entry.

[0026] Based on this, this application proposes a deep N-well bootstrap bias circuit, circuit board, device, and system. The aim is to ensure that the potential of the deep N-well is always the higher of the driving voltage terminal and the bootstrap terminal through the first guiding conductive unit and the second unidirectional conductive unit, thereby avoiding the deep N-well potential from being negative and causing the bootstrap capacitor to fail. At the same time, compared with the existing technology, the setting of the first guiding conductive unit and the second unidirectional conductive unit does not require additional devices such as well switches, charge pumps, and comparators, resulting in lower cost and a lower design threshold, thus making it applicable to a wider range of scenarios.

[0027] It is understood that the deep N-well bootstrap bias circuit of the first aspect embodiment of this application includes a potential selection module, a bootstrap energy storage module, and a charging module. The potential selection module includes a first unidirectional conductive unit DL and a second unidirectional conductive unit DH. The input terminal of the first unidirectional conductive unit DL is connected to the driving voltage terminal VDRV, and the output terminal of the first unidirectional conductive unit DL is connected to the output terminal of the second unidirectional conductive unit DH. The output terminal of the first unidirectional conductive unit DL is also electrically connected to the deep N-well. The bootstrap energy storage module includes a bootstrap capacitor C_Boot, one end of which is the bootstrap terminal BST. The bootstrap capacitor C_Boot is connected to the input terminal of the second unidirectional conductive unit DH via the bootstrap terminal BST. The other end of the bootstrap capacitor C_Boot is used to electrically connect to the external power stage circuit through the switching node. The bootstrap capacitor C_Boot is used to provide the operating voltage for the external power stage circuit. The first unidirectional conductive unit DL and the second unidirectional conductive unit DH are used to make the higher potential between the drive voltage terminal VDRV and the bootstrap terminal BST serve as the bias potential for the deep N-well. The charging module is electrically connected to the bootstrap capacitor C_Boot via the bootstrap terminal BST and is used to charge the bootstrap capacitor C_Boot.

[0028] The beneficial effects of the deep N-well bootstrap bias circuit in this application embodiment can be manifested as follows: by setting the bootstrap capacitor C_Boot, a floating gate drive voltage is provided for the high-side power transistor in the external power stage circuit, and it is also used to maintain a certain voltage difference between the bootstrap terminal BST and the SW node; the charging module is set to charge the bootstrap capacitor C_Boot to ensure that the bootstrap capacitor C_Boot can work normally; the first unidirectional conductive unit DL and the second unidirectional conductive unit DH are set to make the higher potential in the drive voltage terminal VDRV and the bootstrap terminal BST, as the deep N-well bootstrap bias circuit. The bias potential of the N-well causes the BST potential at the bootstrap terminal to drop to a negative value when the SW node momentarily swings to a negative value. Since the VDRV potential at the drive voltage terminal is constant, the first unidirectional conductive unit DL is turned on and the second unidirectional conductive unit DH is turned off. This results in the value of the VDRV potential minus the forward conduction voltage drop of the first unidirectional conductive unit DL being used as the bias potential of the deep N-well. This avoids the deep N-well bias potential being negative, which would cause the parasitic PN junction between the deep N-well and the P-type substrate to conduct, resulting in the failure of the bootstrap capacitor C_Boot and the chip.

[0029] For example, in some embodiments, reference is made to Figure 1 , Figure 2 and Figure 4 In this embodiment, Figure 2This is a classic scheme for monolithically integrating a high-side NMOS gate drive circuit under traditional technology. In this scheme, the parasitic PN junction between the P-type substrate and the deep N-well is D1. The anode of D1 is located on the P-type substrate, and the cathode is located in the deep N-well. This application is mainly used in the classic operating scenario where the SW node swings positive and negative. The external power stage circuit connected to the SW node falls under the scope of external circuit design and is not the subject of this application, therefore it will not be discussed further. Both the first unidirectional conducting unit DL and the second unidirectional conducting unit DH are diodes. The anode (input) of the first unidirectional conducting unit DL is connected to the drive voltage terminal VDRV, and the anode (input) of the second unidirectional conducting unit DH is connected to the bootstrap terminal BST. The cathode (output) of the first unidirectional conducting unit DL is connected to the cathode (output) of the second unidirectional conducting unit DH. Compared to the traditional deep N-well where the N+ region is connected to the BST node and a fixed voltage (e.g., ...) is applied at the BST node, this approach... Figure 2 The N+ region of the deep N-well in this application is connected between the cathode of the first unidirectional conductive unit DL and the cathode of the second unidirectional conductive unit DH, i.e., node DNW (e.g. Figure 4 This causes the potential between the cathode of the first unidirectional conductive unit DL and the cathode of the second unidirectional conductive unit DH to be the greater of the difference between the potential of the driving voltage terminal VDRV and the forward conduction voltage drop of the first unidirectional conductive unit DL and the potential of the bootstrap terminal BST and the forward conduction voltage drop of the second unidirectional conductive unit DH. This value is used as the bias voltage of the deep N-well. This causes the potential of the SW node to become negative. When the potential of the bootstrap terminal BST node also becomes negative due to the influence of the bootstrap capacitor C_Boot, the bias potential of the deep N-well will only reach the difference between the potential of the driving voltage terminal VDRV and the forward conduction voltage drop of the first unidirectional conductive unit DL, and will not become negative. This effectively avoids the parasitic PN junction D1 between the P-type substrate and the deep N-well from conducting, which would cause the voltage across the bootstrap capacitor C_Boot to exceed the margin and cause the bootstrap capacitor C_Boot and the chip to fail. Meanwhile, in the deep N-well bootstrap bias circuit of this application, the bootstrap capacitor C_Boot is still connected across the SW node and the bootstrap terminal BST. That is, due to the influence of the bootstrap capacitor C_Boot, the potential of the bootstrap terminal BST is always greater than the potential of the SW node. This causes the parasitic PN junction D2 between the deep N-well and the deep P-well, and the parasitic PN junction D3 between the deep P-well and the N-well, to remain in a reverse-biased state. Specifically, the anode of D2 is located in the deep P-well, and the cathode of D2 is located in the deep N-well; the anode of D3 is located in the deep P-well, and the cathode of D3 is located in the N-well. The bootstrap capacitor C_Boot is still used to provide the floating gate drive voltage for devices such as high-side power transistors in the external power stage circuit. The charging module is used to charge the bootstrap capacitor C_Boot, compensating for the charge loss of the bootstrap capacitor C_Boot to maintain the voltage difference between the bootstrap terminal BST and the SW node.

[0030] It is understood that the potential selection module also includes a bleed resistor R, one end of which is connected to the input terminal of the first unidirectional conductive unit DL, and the other end of which is connected to the output terminal of the first unidirectional conductive unit DL.

[0031] For example, in some embodiments, reference is made to Figure 1 In this embodiment, the discharge resistor R is designed to provide a discharge path to discharge excess charge when the potential between the cathode of the first unidirectional conductive unit DL and the cathode of the second unidirectional conductive unit DH, i.e., the potential of node DNW, is too high.

[0032] It is understood that the charging module includes a controllable switch Q1 and a switch control unit. The first conductive terminal of the controllable switch Q1 is connected to the drive voltage terminal VDRV. The second conductive terminal of the controllable switch Q1 is connected to the bootstrap capacitor C_Boot through the bootstrap terminal BST. The bootstrap capacitor C_Boot is connected to the input terminal of the switch control unit through the bootstrap terminal BST. The output terminal of the switch control unit is connected to the control terminal of the controllable switch Q1. The switch control unit is used to control the controllable switch Q1 to be turned on or off.

[0033] For example, in some embodiments, reference is made to Figure 1 In this embodiment, the switch control unit is used to control the turn-on or turn-off of the controllable switch Q1. This causes the controllable switch Q1 to turn on during each switching cycle if the BST-SW voltage is lower than the threshold voltage. During the time window when the SW node potential is approximately zero, the switch control unit controls the controllable switch Q1 to turn on, causing the drive voltage terminal VDRV to conduct with the bootstrap capacitor C_Boot. This allows the bootstrap capacitor C_Boot to be charged through the drive voltage terminal VDRV to replenish its charge.

[0034] It is understandable that the switch control unit includes a comparator Comp and a level shifter. The bootstrap capacitor C_Boot is connected to the first input terminal of the comparator Comp through the bootstrap terminal BST. The output terminal of the comparator Comp is connected to the control terminal of the controllable switch Q1 through the level shifter. The second input terminal of the comparator Comp is used to connect to the reference voltage.

[0035] For example, in some embodiments, reference is made to Figure 1 and Figure 3In this embodiment, the non-inverting input (first input) of comparator Comp is connected to the bootstrap capacitor C_Boot via the bootstrap terminal BST, and the inverting input (second input) of comparator Comp is used to connect the reference voltage (i.e., the threshold voltage mentioned earlier), which is typically 5V. The comparator Comp operates as follows: when the potential of the bootstrap terminal BST is greater than the reference voltage, it outputs a high level; when the potential of the bootstrap terminal BST is less than the reference voltage, it outputs a low level. A level shifter is used to convert the voltage to the voltage range of the controllable switch Q1, ensuring that the potential does not exceed the operating range of the controllable switch Q1 and preventing damage to Q1. This causes comparator Comp to turn off the controllable switch Q1 when it outputs a high level and turn on the controllable switch Q1 when it outputs a low level, thus maintaining the voltage of the bootstrap capacitor C_Boot.

[0036] It is understandable that the charging module also includes a third unidirectional conductive unit DH2. The input terminal of the third unidirectional conductive unit DH2 is connected to the second conductive terminal of the controllable switch Q1, and the output terminal of the third unidirectional conductive unit DH2 is connected to the bootstrap capacitor C_Boot through the bootstrap terminal BST.

[0037] For example, in some embodiments, reference is made to Figure 1 In this embodiment, the third unidirectional conductive unit DH2 is also a diode. The input terminal of the third unidirectional conductive unit DH2 is the anode terminal, and the output terminal is the cathode terminal. The third unidirectional conductive unit DH2 is set to prevent the charge of the bootstrap capacitor C_Boot from flowing back to Q1.

[0038] It is understandable that both the first unidirectional conductive unit DL and the second unidirectional conductive unit DH are Schottky diodes.

[0039] For example, in some embodiments, reference is made to Figure 1 In this embodiment, both the first unidirectional conductive unit DL and the second unidirectional conductive unit DH are Schottky diodes. Compared with ordinary diodes, Schottky diodes have a lower forward voltage drop to ensure a higher deep N-well bias potential. At the same time, the switching response speed is also faster, making them more suitable for the main application scenarios of this application.

[0040] It is understandable that the controllable switch Q1 is a P-channel MOSFET.

[0041] For example, in some embodiments, reference is made to Figure 1 In this embodiment, the controllable switch Q1 is a P-channel MOS transistor. The source (first conductive terminal) of the controllable switch Q1 is connected to the driving voltage terminal VDRV, the drain (second conductive terminal) of the controllable switch Q1 is connected to the bootstrap capacitor C_Boot through the bootstrap terminal BST, and the gate of the controllable switch Q1 is connected to the output terminal of the level shifter.

[0042] The specific working principle of the deep N-well bootstrap bias circuit in this application is as follows: During the charging phase, the external power stage circuit pulls SW to -5V, and the drive voltage terminal VDRV (5V) charges the bootstrap capacitor C_Boot through the third unidirectional conductive unit DH2. The current path is sequentially: drive voltage terminal VDRV, third unidirectional conductive unit DH2, bootstrap terminal BST, bootstrap capacitor C_Boot, and SW node. This causes the potential of the bootstrap terminal BST to be raised to 0V. At this time, the voltage of the bootstrap capacitor C_Boot = 0 - (-5) = 5V. The potential of the deep N-well, that is, the potential of the DNW node, is equal to the potential of the drive voltage terminal VDRV - the forward conduction voltage drop of the first unidirectional conductive unit DL = 5V - 0.7V = 4.3V. Since the P-type substrate potential is 0 (grounded) < 4.3V, the parasitic PN junction D1 between the P-type substrate and the deep N-well is reverse-biased and cut off. Simultaneously, the deep N-well potential is equal to the driving voltage terminal VDRV potential minus the forward conduction voltage drop of the first unidirectional conductive unit DL = 5V - 0.7V = 4.3V. The deep P-well potential is the SW node potential - 5V < 4.3V; therefore, the parasitic PN junction D2 between the deep N-well and the deep P-well is also reverse-biased and cut off. Similarly, the parasitic PN junction D3 between the deep P-well (-5V) and the N-well (0V) is also reverse-biased and cut off.

[0043] During the bootstrap phase, the external power stage switches the SW node from -5V to +5V. The voltage across the bootstrap capacitor C_Boot remains constant at 5V, and the bootstrap terminal BST boots to 10V. The potential of the deep N-well, i.e., the potential of the DNW node, is equal to the potential of the bootstrap terminal minus the forward conduction voltage drop of the second unidirectional conductive unit DH = 10V - 0.7V = 9.3V. Since the potential of the P-type substrate is 0 (grounded) < 9.3V, the parasitic PN junction D1 between the P-type substrate and the deep N-well is reverse-biased and cut off. Similarly, the parasitic PN junction D2 between the deep N-well and the deep P-well, and the parasitic PN junction D3 between the deep P-well and the N-well are also reverse-biased and cut off.

[0044] It should be noted that the forward conduction voltage drop of the first unidirectional conductive unit DL and the forward conduction voltage drop of the second unidirectional conductive unit DH are selected from conventional typical values, namely 0.7V. The specific values ​​can be assigned according to the forward conduction voltage drop corresponding to the actual selected type of unidirectional conductive unit.

[0045] The potential timing diagrams of the relevant nodes in the charging phase and bootstrap phase mentioned above are referenced. Figure 3 Where VDNW represents the potential of the DNW node, and V_Cboot is the voltage across the bootstrap capacitor C_Boot.

[0046] The circuit board according to the second aspect of the application includes the deep N-well bootstrap bias circuit of the first aspect of the application described above.

[0047] According to the circuit board of this application embodiment, the application provides a floating gate drive voltage for the high-side power transistor in the external power stage circuit by setting a bootstrap capacitor C_Boot, and also uses it to maintain a certain voltage difference between the bootstrap terminal BST and the SW node; the charging module is set to charge the bootstrap capacitor C_Boot to ensure that the bootstrap capacitor C_Boot can work normally; the first unidirectional conductive unit DL and the second unidirectional conductive unit DH are set to make the higher potential in the drive voltage terminal VDRV and the bootstrap terminal BST serve as the bias of the deep N-well. The potential is such that when the SW node momentarily swings to a negative value, the bootstrap terminal BST potential also drops to a negative value. Since the driving voltage terminal VDRV potential remains constant, the first unidirectional conductive unit DL is turned on, and the second unidirectional conductive unit DH is turned off. This causes the value of the driving voltage terminal VDRV minus the forward conduction voltage drop of the first unidirectional conductive unit DL to be used as the bias potential of the deep N-well. This avoids the deep N-well bias potential being negative, which would cause the parasitic PN junction between the deep N-well and the P-type substrate to conduct, resulting in the failure of the bootstrap capacitor C_Boot and the chip. By introducing the deep N-well bootstrap bias circuit of this application, the scenario of the SW node swinging between positive and negative values ​​can be effectively handled, preventing the parasitic PN junction between the P-type substrate and the deep N-well from conducting due to the negative potential of the SW node, thus preventing the failure of the bootstrap capacitor C_Boot and the chip.

[0048] Since the circuit board includes the deep N-well bootstrap bias circuit of the first aspect embodiment, the corresponding contents of the deep N-well bootstrap bias circuit of the first aspect embodiment can be applied to the circuit board of the second aspect, and have the same implementation principle and technical effect. To avoid redundancy, it will not be described in detail here.

[0049] The device according to the third aspect of the application includes the circuit board of the second aspect of the application described above.

[0050] The system according to the fourth aspect of the application includes the device described in the third aspect of the application above.

[0051] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0052] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0053] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0054] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0055] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0057] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0058] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0059] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0060] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0061] Furthermore, it should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent will be obtained first. Moreover, the collection, use, and processing of this data will comply with relevant laws, regulations, and standards. Additionally, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user will be obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent will the necessary user-related data for the proper functioning of these embodiments be acquired.

[0062] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A deep N-well bootstrap bias circuit, characterized in that, include: A potential selection module includes a first unidirectional conductive unit and a second unidirectional conductive unit. The input terminal of the first unidirectional conductive unit is connected to the driving voltage terminal, and the output terminal of the first unidirectional conductive unit is connected to the output terminal of the second unidirectional conductive unit. The output terminal of the first unidirectional conductive unit is also used to be electrically connected to a deep N-well. The bootstrap energy storage module includes a bootstrap capacitor. One end of the bootstrap capacitor is a bootstrap terminal, which is connected to the input terminal of the second unidirectional conductive unit. The other end of the bootstrap capacitor is used to electrically connect to an external power stage circuit through a switching node. The bootstrap capacitor is used to provide an operating voltage to the external power stage circuit. The first unidirectional conductive unit and the second unidirectional conductive unit are used to make the higher potential between the driving voltage terminal and the bootstrap terminal serve as the bias potential of the deep N-well. A charging module is provided, which is electrically connected to the bootstrap capacitor via the bootstrap terminal, and is used to charge the bootstrap capacitor.

2. The deep N-well bootstrap bias circuit according to claim 1, characterized in that, The potential selection module further includes a bleed resistor, one end of which is connected to the input terminal of the first unidirectional conductive unit, and the other end of which is connected to the output terminal of the first unidirectional conductive unit.

3. The deep N-well bootstrap bias circuit according to claim 1, characterized in that, The charging module includes a controllable switch transistor and a switch control unit. The first conductive terminal of the controllable switch transistor is connected to the driving voltage terminal, and the second conductive terminal of the controllable switch transistor is connected to the bootstrap capacitor through the bootstrap terminal. The bootstrap capacitor is connected to the input terminal of the switch control unit through the bootstrap terminal, and the output terminal of the switch control unit is connected to the control terminal of the controllable switch transistor. The switch control unit is used to control the controllable switch transistor to be turned on or off.

4. The deep N-well bootstrap bias circuit according to claim 3, characterized in that, The switch control unit includes a comparator and a level shifter. The bootstrap capacitor is connected to the first input terminal of the comparator through the bootstrap terminal. The output terminal of the comparator is connected to the control terminal of the controllable switch through the level shifter. The second input terminal of the comparator is used to connect to a reference voltage.

5. The deep N-well bootstrap bias circuit according to claim 3, characterized in that, The charging module further includes a third unidirectional conductive unit, the input terminal of which is connected to the second conductive terminal of the controllable switch tube, and the output terminal of which is connected to the bootstrap capacitor through the bootstrap terminal.

6. The deep N-well bootstrap bias circuit according to claim 1, characterized in that, Both the first unidirectional conductive unit and the second unidirectional conductive unit are Schottky diodes.

7. The deep N-well bootstrap bias circuit according to claim 3, characterized in that, The controllable switch is a P-channel MOSFET.

8. A circuit board, characterized in that, include: The deep N-well bootstrap bias circuit according to any one of claims 1 to 7.

9. A device, characterized in that, include: The circuit board as described in claim 8.

10. A system, characterized in that, include: The device as described in claim 9.

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