Drive circuit and power device

Abstract

This application provides a driving circuit and a power device. The driving circuit includes a first switching transistor, a second switching transistor, a first control module, and a second control module. The switching loss of the first switching transistor is greater than that of the second switching transistor. When the control signal is active, the first control module outputs a turn-on enable signal after the second control module, so that the first switching transistor turns on after the second switching transistor. When the control signal is active, the first control module outputs a turn-off enable signal before the second control module, so that the first switching transistor turns off before the second switching transistor. In this application, the switching loss of the driving circuit during the turn-on and turn-off control processes is mainly the switching loss of the second switching transistor. Since the switching loss of the first switching transistor is greater than that of the second switching transistor, it is beneficial to improve the power efficiency of the device.

Description

Technical Field

[0001] This application relates to the field of switch control technology, specifically to a drive circuit and power equipment. Background Technology

[0002] Currently, because IGBTs (Insulated-Gate Bipolar Transistors) can withstand high currents, they are widely used as power switches in high-voltage, high-current power control scenarios such as photovoltaic power generation, wind power generation, new energy vehicles, and industrial control.

[0003] However, IGBTs are bipolar devices. When an IGBT is turned on, both electrons and holes participate in conduction. When an IGBT is turned off, electrons can be quickly drawn away through the channel, while holes can only be slowly cleared through recombination. This results in a significant tail current in the IGBT, which increases switching losses. Summary of the Invention

[0004] This application provides a drive circuit and a power device, which aim to solve the above-mentioned technical problems.

[0005] In a first aspect, this application provides a driving circuit, comprising:

[0006] A first switching transistor and a second switching transistor, wherein the first terminal of the first switching transistor is connected to the first terminal of the second switching transistor, and the second terminal of the first switching transistor is connected to the second terminal of the second switching transistor.

[0007] The first control module has an input terminal for receiving control signals and an output terminal connected to the control terminal of the first switching transistor.

[0008] The second control module has an input terminal for receiving control signals and an output terminal connected to the control terminal of the second switching transistor.

[0009] Among them, the switching loss of the first switching transistor is greater than that of the second switching transistor.

[0010] When the control signal is active, the first control module outputs an enable signal after the second control module, so that the first switching transistor is turned on after the second switching transistor.

[0011] When the control signal is enabled for shutdown, the first control module outputs a shutdown enable signal before the second control module, so that the first switching transistor is turned off before the second switching transistor.

[0012] In some embodiments, the first control module includes a first delay unit with signal delay function, and the second control module includes a second delay unit with signal delay function;

[0013] When the control signal is active, the signal delay function of the first delay unit is activated and the signal delay function of the second delay unit is disabled, so that the first control module outputs the enable signal after the second control module.

[0014] When the control signal is enabled, the signal delay function of the second delay unit is activated and the signal delay function of the first delay unit is disabled, so that the first control module outputs the shutdown enable signal before the second control module.

[0015] In some embodiments, the first control module further includes a first switching unit;

[0016] The first switching unit is connected to the first delay unit. When the control signal is turned on, the first switching unit controls the signal delay function of the first delay unit to take effect. When the control signal is turned off, the first switching unit disables the signal delay function of the first delay unit.

[0017] In some embodiments, the first delay unit includes a first capacitor and a first resistor, and the first switching unit includes a first transistor;

[0018] The first terminal of the first capacitor is connected to the control terminal of the first switching transistor, and the second terminal of the first capacitor is connected to the first terminal of the first switching transistor.

[0019] The first end of the first resistor is connected to the first end of the first capacitor, and the second end of the first resistor is connected to the control signal.

[0020] The first terminal of the first transistor is connected to the first terminal of the first capacitor, the second terminal of the first transistor is connected to the first terminal of the first switching transistor, and the control terminal of the first transistor is connected to a control signal.

[0021] In some embodiments, the second control module further includes a second switching unit;

[0022] The second switching unit is connected to the second delay unit. When the control signal is on, the second switching unit disables the signal delay function of the second delay unit. When the control signal is off, the second switching unit controls the signal delay function of the second delay unit to take effect.

[0023] In some embodiments, the second delay unit includes a second capacitor and a second resistor, and the second switching unit includes a second transistor;

[0024] The first terminal of the second capacitor is connected to the control terminal of the second switching transistor, the second terminal of the second capacitor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is connected to the control signal.

[0025] The first terminal of the second transistor is connected to the control terminal of the second switching transistor, the second terminal of the second transistor is connected to the control signal, and the control terminal of the second transistor is connected to the first node between the second capacitor and the second resistor.

[0026] In some embodiments, the second switching unit further includes a third transistor and a third resistor;

[0027] The first end of the third resistor is connected to the control terminal of the second switching transistor, and the second end of the third resistor is connected to the first end of the second capacitor.

[0028] The first terminal of the third transistor is connected to the control terminal of the second switching transistor, the second terminal of the third transistor is connected to the first terminal of the second switching transistor, and the control terminal of the third transistor is connected to the first terminal of the second transistor.

[0029] In some embodiments, the second switching unit further includes a fourth resistor and a third capacitor;

[0030] The first end of the fourth resistor is connected to the control terminal of the second switching transistor, the second end of the fourth resistor is connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the first end of the second switching transistor.

[0031] In some embodiments, the second switching unit further includes a fifth resistor and a first diode;

[0032] The first terminal of the fifth resistor is connected to the first terminal of the third capacitor, the second terminal of the fifth resistor is connected to the positive terminal of the first diode, and the negative terminal of the first diode is connected to the first terminal of the third transistor.

[0033] The resistance value of the fifth resistor is less than that of the fourth resistor.

[0034] In a second aspect, this application provides an electrical device including the drive circuit described in the first aspect.

[0035] When the control signal is active, the first control module can output an enable signal after the second control module, thus enabling the first switching transistor to turn on after the second switching transistor. When the control signal is inactive, the first control module can output an enable signal before the second control module, thus enabling the first switching transistor to turn off before the second switching transistor.

[0036] In other words, during the turn-on process, the second switching transistor turns on before the first switching transistor, and the switching loss during the turn-on process is the switching loss of the second switching transistor; conversely, during the turn-off process, the second switching transistor turns off after the first switching transistor, and the switching loss during the turn-off process is also the switching loss of the second switching transistor. It can be seen that during both the turn-on and turn-off control processes, the switching losses of the drive circuit are mainly the switching losses of the second switching transistor. Since the switching losses of the first switching transistor are greater than those of the second switching transistor, this application helps to reduce the switching losses of the drive circuit, thereby achieving the goal of improving power supply efficiency. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a schematic diagram showing a driving circuit in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram illustrating a related signal in an embodiment of this application;

[0040] Figure 3 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0041] Figure 4 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0042] Figure 5 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0043] Figure 6 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0044] Figure 7 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0045] Figure 8 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0046] Figure 9 This is another schematic diagram showing the driving circuit in an embodiment of this application;

[0047] Figure 10 This is another schematic diagram showing the driving circuit in an embodiment of this application.

[0048] Among them, 10 is the first control module, 20 is the second control module, 11 is the first delay unit, 12 is the first switch unit, 21 is the second delay unit, and 22 is the second switch unit;

[0049] First switching transistor Q1, second switching transistor Q2, first resistor R1, first capacitor C1, second resistor R2, second capacitor C2, first transistor M1, second transistor M2, third transistor M3, third resistor R3, fourth resistor R4, fifth resistor R5, third capacitor C3, first diode D1. Detailed Implementation

[0050] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] In the description of this invention, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0052] This application provides a driving circuit and a power device, which will be described in detail below.

[0053] First, refer to Figure 1 , Figure 1 A schematic diagram of a driving circuit in an embodiment of this application is shown, wherein the driving circuit includes a first switching transistor Q1, a second switching transistor Q2, a first control module 10, and a second control module 20.

[0054] Specifically, the first terminal of the first switching transistor Q1 is connected to the first terminal of the second switching transistor Q2, and the second terminal of the first switching transistor Q1 is connected to the second terminal of the second switching transistor Q2. The first terminals of the first switching transistor Q1 and the second switching transistor Q2 can be connected to the ground terminal GND, and the second terminals of the first switching transistor Q1 and the second switching transistor Q2 can be connected to the power supply terminal VDD. Since the first switching transistor Q1 and the second switching transistor Q2 are connected in parallel, when at least one of the first switching transistor Q1 and the second switching transistor Q2 is turned on, the path between the power supply terminal VDD and the ground terminal GND is turned on; and when the first switching transistor Q1 and the second switching transistor Q2 are turned off at the same time, the path between the power supply terminal VDD and the ground terminal GND is turned off.

[0055] It should be noted that the switching loss of the first switching transistor Q1 is greater than that of the second switching transistor Q2. For example, taking the first switching transistor Q1 as an IGBT and the second switching transistor Q2 as a SiC-MOSFET (Silicon Carbide-Metal Oxide-Semiconductor Field-Effect Transistor), since the IGBT is a bipolar device and the SiC-MOSFET is a unipolar device, the holes in the IGBT can only be slowly cleared through recombination at the moment of turn-off, while only electrons participate in conduction in the SiC-MOSFET, so there is no tail current when it is turned off. Therefore, the switching loss of the IGBT is greater than that of the SiC-MOSFET.

[0056] Understandably, the first switching transistor Q1 and the second switching transistor Q2 are not limited to the transistors described above. For example, in some possible embodiments, the second switching transistor Q2 may also be a GaN MOSFET (gallium nitride-metal oxide semiconductor field-effect transistor).

[0057] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0058] It should also be noted that each transistor used in the embodiments of this application has a first terminal, a second terminal, and a control terminal. The first terminal and the second terminal refer to the emitter and collector, respectively, or the first terminal and the second terminal refer to the source and drain, respectively, and the control terminal refers to the gate or the base. For example, when the transistor is a bipolar junction transistor (BJT), the first terminal of the transistor is one of the emitter and the collector, the second terminal of the transistor is the other of the emitter and the collector, and the control terminal of the transistor is the base; as another example, when the transistor is a field effect transistor (FET), the first terminal of the transistor is one of the source and the drain, the second terminal of the transistor is the other of the source and the drain, and the control terminal of the transistor is the gate.

[0059] Since the source and drain (emitter and collector) of a transistor can be structurally symmetrical, they can also be structurally indistinguishable. In other words, the first and second terminals of the transistor in the embodiments of this application can be structurally indistinguishable. For example, when the transistor is a P-type transistor, the first terminal is the source (or emitter), and the second terminal is the drain (or collector); for example, when the transistor is an N-type transistor, the first terminal is the source (or emitter), and the second terminal is the drain (or collector).

[0060] The input terminal of the first control module 10 is used to receive the control signal PWM, and the output terminal of the first control module 10 is connected to the control terminal of the first switching transistor Q1. The first control module 10 can respond to the control signal PWM by outputting an enable signal to the control terminal of the first switching transistor Q1, thereby controlling the first switch to be turned on or off. For example, taking the first switching transistor Q1 as an N-type transistor, when the control signal PWM is active, the first control module 10 can output a high-level signal to the control terminal of the first switching transistor Q1 as an enable signal, thereby turning on the first switching transistor Q1; conversely, when the control signal PWM is active deactivation, the first control module 10 can output a low-level signal to the control terminal of the first switching transistor Q1 as a deactivation enable signal, thereby turning off the first switching transistor Q1.

[0061] The input terminal of the second control module 20 is used to receive the control signal PWM, and the output terminal of the second control module 20 is connected to the control terminal of the second switching transistor Q2. The second control module 20 can respond to the control signal PWM by outputting an enable signal to the control terminal of the second switching transistor Q2, thereby controlling the second switch to be turned on or off. For example, taking the second switching transistor Q2 as a P-type transistor, when the control signal PWM is active, the second control module 20 can output a low-level signal to the control terminal of the second switching transistor Q2 as an enable signal, thereby turning on the second switching transistor Q2; conversely, when the control signal PWM is active deactivation, the second control module 20 can output a high-level signal to the control terminal of the second switching transistor Q2 as a deactivation enable signal, thereby turning off the second switching transistor Q2.

[0062] It should be noted that whether the control signal PWM is active or inactive refers to the current level state of the control signal PWM. A high level and a low level of the control signal PWM correspond to active conduction and active inactive deactivation, respectively. For example, in an embodiment where the first and second switching transistors are P-type transistors, the control signal PWM is active when it is high and inactive when it is low. As another example, in an embodiment where the first and second switching transistors are N-type transistors, the control signal PWM is active when it is low and inactive when it is high.

[0063] In this embodiment, when the control signal PWM is active, the first control module 10 outputs a conduction enable signal (e.g., a high-level signal) after the second control module 20. That is, the second control module 20 first outputs a conduction enable signal to the control terminal of the second switching transistor Q2, and the first control module 10 then outputs a conduction enable signal to the control terminal of the first switching transistor Q1. Therefore, the first switching transistor Q1 can be turned on after the second switching transistor Q2. When the control signal PWM is off, the first control module 10 outputs a shutdown enable signal (e.g., a low-level signal) before the second control module 20. That is, the first control module 10 first outputs a shutdown enable signal to the control terminal of the first switching transistor Q1, and the second control module 20 then outputs a shutdown enable signal to the control terminal of the second switching transistor Q2. Therefore, the second switching transistor Q2 is turned off before the second switching transistor Q2.

[0064] For example, taking the case where both the first switching transistor Q1 and the second switching transistor Q2 are N-type transistors, see [reference needed]. Figure 2 , Figure 2The diagram shows a schematic of the relevant signals in an embodiment of this application. At time t1, the control signal PWM is high (active). The second control module 20 outputs a high-level signal to the second switching transistor Q2 as a turn-on enable signal close to time t1. The first control module 10 outputs a high-level signal to the first switching transistor Q1 as a turn-on enable signal at time t2 after time t1. Therefore, the second switching transistor Q2 turns on first, and the first switching transistor Q1 turns on later.

[0065] At time t3, the control signal PWM is low (off enabled). The first control module 10 outputs a low-level signal to the first switching transistor Q1 as a turn-off enable signal close to time t3. The second control module 20 outputs a low-level signal to the second switching transistor Q2 as a turn-off enable signal at time t4 after time t3. Therefore, the first switching transistor Q1 is turned off first, and the second switching transistor Q2 is turned off later.

[0066] It can be seen that during the turn-on process, the second switching transistor Q2 is turned on before the first switching transistor Q1; while during the turn-off process, the second switching transistor Q2 is turned off after the first switching transistor Q1. Therefore, during both the turn-on and turn-off control processes, the switching losses of the drive circuit are mainly the switching losses of the second switching transistor Q2. Considering that the switching losses of the first switching transistor Q1 are greater than those of the second switching transistor Q2, it can be concluded that this application can reduce the switching losses of the drive circuit, thereby improving the power conversion efficiency and reducing the system heat generation.

[0067] It should also be noted that when the first switching transistor Q1 is an IGBT and the second switching transistor Q2 is a SiC-MOSFET, since the SiC-MOSFET does not have a tail current during the turn-on and turn-off control processes, the turn-on and turn-off control processes of the drive circuit in this application are not limited by the tail current of the IGBT, which is beneficial for increasing the switching frequency. Furthermore, since the conduction loss of the IGBT is less than that of the SiC-MOSFET under high current (e.g., exceeding 100A), the current can pass through the IGBT during conduction, resulting in a smaller conduction loss. Therefore, when the first switching transistor Q1 is an IGBT and the second switching transistor Q2 is a SiC-MOSFET, the conduction loss of the drive circuit can be reduced, thereby further improving power efficiency.

[0068] In some embodiments of this application, see Figure 3 , Figure 3 Another schematic diagram of the driving circuit in an embodiment of this application is shown, wherein the first control module 10 includes a first delay unit 11 and the second control module 20 includes a second delay unit 21.

[0069] Specifically, the first delay unit 11 and the second delay unit 21 have signal delay functions. For example, the first delay unit 11 and the second delay unit 21 may include an RC delay circuit composed of a resistor and a capacitor. The duration for which the capacitor charges and discharges through the resistor is the delay duration of the signal provided by the first delay unit 11 and the second delay unit 21. For another example, the first delay unit 11 and the second delay unit 21 may include a counter. The counter starts counting after receiving a high or low level of the control signal PWM, and outputs a corresponding signal when it counts to a pre-designed value. Therefore, the time for the counter to count to the pre-designed value is the delay duration of the signal provided by the first delay unit 11 and the second delay unit 21.

[0070] It should be noted that the signal delay functions of the first delay unit 11 and the second delay unit 21 can be enabled or disabled by the control signal PWM. For example, in an embodiment where the first delay unit 11 and the second delay unit 21 include an RC delay circuit, when the resistor is not short-circuited, the capacitor in the RC delay circuit can normally charge and discharge through the charging and discharging current and realize the signal delay function because the magnitude of the capacitor's charging and discharging current is limited by the resistor; however, when the resistor is short-circuited, the capacitor in the RC delay circuit will instantly complete the charging or discharging process because the magnitude of the capacitor's charging and discharging current is not limited by the resistor, thus disabling the signal delay function.

[0071] In the above embodiment, since the signal delay functions of the first delay unit 11 and the second delay unit 21 can be controlled by the control signal PWM to be enabled or disabled, when the control signal PWM is enabled, if the signal delay function of the first delay unit 11 is enabled and the signal delay function of the second delay unit 21 is disabled, then the first control module 10 can perform signal delay through the first delay unit 11, and the second control module 20 cannot perform signal delay. Therefore, the first control module 10 can output a turn-on enable signal after the second control module 20.

[0072] When the control signal PWM is enabled, if the signal delay function of the second delay unit 21 is enabled and the signal delay function of the first delay unit 11 is disabled, then the second control module 20 can delay the signal through the second delay unit 21, while the first control module 10 cannot delay the signal. Therefore, the first control module 10 can output the shutdown enable signal before the second control module 20.

[0073] As can be seen, the above embodiment enables the signal delay function of the first delay unit 11 to take effect during the conduction process, thereby disabling the signal delay function of the second delay unit 21. The first switching transistor Q1 is turned on with a delay, while the second switching transistor Q2 is turned on normally. Therefore, the second switching transistor Q2 can be turned on before the first switching transistor Q1. During the turn-off process, the signal delay function of the second delay unit 21 takes effect, thereby disabling the signal delay function of the first delay unit 11. The first switching transistor Q1 is turned off normally, while the second switching transistor Q2 is turned off with a delay. Therefore, the second switching transistor Q2 can be turned off before the first switching transistor Q1, ultimately achieving the goal of reducing the switching losses of the drive circuit.

[0074] In some embodiments of this application, see Figure 4 , Figure 4 Another schematic diagram of the driving circuit in an embodiment of this application is shown, wherein the first control module 10 further includes a first switch unit 12; the first switch unit 12 is connected to the first delay unit 11, and the first switch unit 12 controls the signal delay function of the first delay unit 11 to take effect when the control signal PWM is turned on, and the first switch unit 12 disables the signal delay function of the first delay unit 11 when the control signal PWM is turned off.

[0075] It should be noted that the first switching unit 12 can control whether the electronic components in the first delay unit 11 are short-circuited, thereby enabling or disabling the signal delay function of the first delay unit 11. For example, taking the first delay unit 11 as including an RC delay circuit, the first switching unit 12 is connected in parallel with a resistor. When the first switching unit 12 is conducting across the resistor, the resistor is short-circuited. At this time, the charging and discharging current of the capacitor is not limited by the resistor, so the capacitor will instantly complete the charging or discharging process, thus disabling the signal delay function. Conversely, when the first switching unit 12 is conducting across the resistor, the charging and discharging current of the capacitor is limited by the resistor, so the signal delay function can be realized normally.

[0076] Understandably, in some possible embodiments, the first switching unit 12 may also be connected in parallel with the capacitor in the RC delay circuit. The first switching unit 12 controls whether the capacitor is short-circuited, thereby enabling or disabling the signal delay function of the first delay unit 11.

[0077] As an exemplary embodiment, see [reference] Figure 5 , Figure 5Another schematic diagram of the driving circuit in an embodiment of this application is shown, wherein the first delay unit 11 includes a first capacitor C1 and a first resistor R1, and the first switching unit 12 includes a first transistor M1; the first end of the first capacitor C1 is connected to the control terminal of the first switching transistor Q1, and the second end of the first capacitor C1 is connected to the first end of the first switching transistor Q1; the first end of the first resistor R1 is connected to the first end of the first capacitor C1, and the second end of the first resistor R1 is connected to the control signal PWM; the first end of the first transistor M1 is connected to the first end of the first capacitor C1, and the second end of the first transistor M1 is connected to the second end of the second capacitor C2, and the control terminal of the first transistor M1 is connected to the control signal PWM.

[0078] For example, assuming the control signal PWM is active when high and active when low, the first transistor M1 is a P-type transistor (e.g., a PNP transistor). When the control signal PWM is high, the first transistor M1 is in the off state. At this time, the first capacitor C1 is charged through the charging current provided by the first resistor R1, so the signal delay function of the first delay unit 11 is activated. When the first capacitor C1 is charged to a level above the turn-on voltage of the first switching transistor Q1, the first switching transistor Q1 can be turned on with a delay. When the control signal PWM is low, the first switching transistor Q1 is in the on state, which is equivalent to short-circuiting the two ends of the first capacitor C1. The first capacitor C1 does not discharge through the first resistor R1, but discharges rapidly through the first switching transistor Q1. Therefore, the signal delay function of the first delay unit 11 is disabled. When the first capacitor C1 discharges to a level below the turn-on voltage of the first switching transistor Q1, the first switching transistor Q1 can be turned off quickly.

[0079] It is understandable that the aforementioned first transistor M1 in Figure 5 The first transistor M1 is a PNP transistor, but in practice, the implementation of the first transistor M1 is not limited to this. In some possible embodiments, the first transistor M1 can also be a PMOS transistor, an NMOS transistor, or an NPN transistor, etc.

[0080] It should be noted that the implementation methods for disabling the signal delay function of the first delay unit 11 or controlling the signal delay function of the first delay unit 11 are not limited to this. For example, see [link to relevant documentation]. Figure 6 , Figure 6Another schematic diagram of the driving circuit in this application embodiment is shown. A diode D0 can also be connected in parallel across the first resistor R1. When the control signal PWM is high, the diode D0 is cut off. At this time, the first capacitor C1 is charged normally through the charging current provided by the first resistor R1, so the signal delay function of the first delay unit 11 is effective. When the control signal PWM is low, the diode D0 is turned on. At this time, the first capacitor C1 discharges quickly through the diode D0. Since the discharge process of the first capacitor C1 is not limited by the first resistor R1, the signal delay function of the first delay unit 11 is shielded at this time.

[0081] In some embodiments of this application, see Figure 7 , Figure 7 Another schematic diagram of the driving circuit in this application embodiment is shown. The second control module 20 further includes a second switching unit 22. The second switching unit 22 is connected to the second delay unit 21. When the control signal PWM is turned on, the second switching unit 22 disables the signal delay function of the second delay unit 21. When the control signal PWM is turned off, the second switching unit 22 controls the signal delay function of the second delay unit 21 to take effect.

[0082] Similarly, the second switching unit 22 can control whether the electronic components in the second delay unit 21 are short-circuited to enable or disable the signal delay function of the second delay unit 21. For example, taking the second delay unit 21 as including an RC delay circuit, the second switching unit 22 is connected in parallel with a capacitor. When the second switching unit 22 turns on the capacitor, the capacitor will not charge, so the RC delay circuit does not have a signal delay function, which is equivalent to disabling the signal delay function of the second delay unit 21. Conversely, when the second switching unit 22 does not turn on the capacitor, the capacitor will charge normally, and the charging and discharging current of the capacitor is limited by the resistor, so the signal delay function can be realized normally.

[0083] As an example, see Figure 8 , Figure 8 Another schematic diagram of the driving circuit in an embodiment of this application is shown. The second delay unit 21 includes a second capacitor C2 and a second resistor R2, and the second switching unit 22 includes a second transistor M2. The first end of the second capacitor C2 is connected to the control terminal of the second switching transistor Q2, and the second end of the second capacitor C2 is connected to the first end of the second resistor R2. The second end of the second resistor R2 is connected to the control signal PWM. The first end of the second transistor M2 is connected to the control terminal of the second switching transistor Q2, and the second end of the second transistor M2 is connected to the control signal PWM. The control terminal of the second transistor M2 is connected to the first node m1 between the second capacitor C2 and the second resistor R2.

[0084] Taking a PMOS transistor where the control signal PWM is high and low, and the second transistor M2 is low and active, as an example, when the control signal PWM is high, although the second transistor M2 is in the off state, due to the presence of the body diode of the PMOS transistor, the current of the control signal PWM can flow into the control terminal of the second switching transistor Q2 through the body diode of the PMOS transistor. At this time, the voltage across the second capacitor C2 is equal and will not be charged. The signal delay function of the second delay unit 21 is shielded, so the second switching transistor Q2 can be quickly turned on, so that the second switching transistor Q2 is turned on before the first switching transistor Q1.

[0085] When the control signal PWM switches from high to low, the body diode of the PMOS transistor is cut off. Due to the presence of the second resistor R2 and the second capacitor C2, a voltage difference exists across the second capacitor C2, causing it to charge. This activates the signal delay function of the second delay unit 21. Simultaneously, the voltage at the first node m1 decreases as the second capacitor C2 charges. In other words, the voltage at the first node m1 does not drop instantaneously. Therefore, the second transistor M2 does not turn on instantaneously. Instead, it turns on and pulls down the control terminal voltage of the second switching transistor Q2 only after the second capacitor C2 has finished charging (or has reached a certain voltage). This ultimately achieves the purpose of delaying the turn-off of the second switching transistor Q2.

[0086] It is understood that the above embodiment is illustrated by taking the control signal PWM as an example, where the transistor is turned on when it is high and turned off when it is low, and the second transistor M2 is a PMOS transistor that is turned on when it is low. In fact, the second transistor Q2 is not limited to a PMOS transistor. For example, when the control signal PWM is turned on when it is low and turned off when it is high, the second transistor M2 can also be an NMOS transistor that is turned on when it is high.

[0087] In some embodiments of this application, see further reference. Figure 9 , Figure 9 Another schematic diagram of the driving circuit in an embodiment of this application is shown, wherein the second switching unit 22 further includes a third transistor M3 and a third resistor R3; the first end of the third resistor R3 is connected to the control terminal of the second switching transistor Q2, and the second end of the third resistor R3 is connected to the first end of the second capacitor C2; the first end of the third transistor M3 is connected to the control terminal of the second switching transistor Q2, the second end of the third transistor M3 is connected to the first end of the second switching transistor Q2, and the control terminal of the third transistor M3 is connected to the first end of the second transistor M2.

[0088] For example, taking a PMOS transistor where the control signal PWM is high and the transistor is low, and the second transistor M2 is low and the transistor is active, as an example, in... Figure 9 The third transistor M3 corresponds to a low-level conducting transistor (such as a PNP transistor or a PMOS transistor). When the control signal PWM is high, the second transistor M2 outputs a high-level signal through its body diode, so the third transistor M3 is in the off state. This ensures that the control terminal voltage of the second switching transistor Q2 is quickly pulled up, and the second switching transistor Q2 is turned on before the first switching transistor Q1 is turned on. When the control signal PWM is low, after the second transistor M2 is turned on with a delay and outputs a low-level signal, the third transistor M3 is in the conducting state. Therefore, the third transistor M3 can quickly pull down the control terminal voltage of the second switching transistor Q2, and finally achieve the purpose of quickly turning off the second switching transistor Q2 after a delay.

[0089] In some embodiments of this application, see Figure 10 , Figure 10 Another schematic diagram of the driving circuit in an embodiment of this application is shown, wherein the second switching unit 22 further includes a fourth resistor R4 and a third capacitor C3; the first end of the fourth resistor R4 is connected to the control terminal of the second switching transistor Q2, the second end of the fourth resistor R4 is connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is connected to the first end of the second switching transistor Q2.

[0090] Specifically, the third capacitor C3 can act as an energy storage element to stabilize the control terminal voltage of the second switching transistor Q2, and the fourth resistor R4 acts as a current-limiting resistor for charging the third capacitor C3. When the second transistor M2 outputs a high-level signal, since the fourth resistor R4 does not limit the current input to the control terminal of the second switching transistor Q2, it will not have a delay effect on the conduction of the second switching transistor Q2. Thus, the third capacitor C3 and the fourth resistor R4 can stabilize the control terminal voltage of the second switching transistor Q2 while ensuring that the second switching transistor Q2 conducts before the first switching transistor Q1, thus avoiding the phenomenon that the second switching transistor Q2 will malfunction due to voltage fluctuations.

[0091] In some embodiments of this application, see further reference. Figure 10 The second switching unit 22 further includes a fifth resistor R5 and a first diode D1; the first end of the fifth resistor R5 is connected to the first end of the third capacitor C3, the second end of the fifth resistor R5 is connected to the positive end of the first diode D1, the negative end of the first diode D1 is connected to the first end of the third transistor M3, and the resistance value of the fifth resistor R5 is less than the resistance value of the fourth resistor R4.

[0092] It should be noted that when the second transistor M2 outputs a low-level signal, since the third transistor M3 is turned on, the third capacitor C3 can discharge quickly through the fifth resistor R5 with a smaller resistance, the first diode D1, and the third transistor M3, avoiding the fifth resistor R5 with a relatively larger resistance affecting the discharge speed of the third capacitor C3. This quickly lowers the control terminal voltage of the second switching transistor Q2, ultimately achieving the purpose of quickly turning off the second switching transistor Q2.

[0093] Furthermore, to better implement the drive circuit in the embodiments of this application, based on the drive circuit, this application also provides a power device including the drive circuit as described in any of the above embodiments. Exemplarily, the power device may be, but is not limited to, an inverter, a frequency converter, a charging pile, a traction converter, a converter valve, a converter transformer, etc. Since the power device in the embodiments of this application has all the beneficial effects of the drive circuit described in the above embodiments due to the inclusion of the drive circuit, it will not be elaborated further here.

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the detailed descriptions of other embodiments above, which will not be repeated here.

[0095] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0096] The foregoing has provided a detailed description of a driving circuit and power device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A driving circuit, characterized in that, include: A first switching transistor and a second switching transistor, wherein a first terminal of the first switching transistor is connected to a first terminal of the second switching transistor, and a second terminal of the first switching transistor is connected to a second terminal of the second switching transistor. The first control module has an input terminal for receiving control signals and an output terminal connected to the control terminal of the first switching transistor. The second control module has an input terminal for receiving control signals and an output terminal connected to the control terminal of the second switching transistor. Wherein, the switching loss of the first switching transistor is greater than the switching loss of the second switching transistor; When the control signal is active, the first control module outputs an enable signal after the second control module, so that the first switching transistor is turned on after the second switching transistor. When the control signal is enabled for shutdown, the first control module outputs a shutdown enable signal before the second control module, so that the first switching transistor is turned off before the second switching transistor.

2. The driving circuit as described in claim 1, characterized in that, The first control module includes a first delay unit with signal delay function, and the second control module includes a second delay unit with signal delay function; When the control signal is active, the signal delay function of the first delay unit is activated and the signal delay function of the second delay unit is disabled, so that the first control module outputs an enable signal after the second control module. When the control signal is enabled, the signal delay function of the second delay unit is activated and the signal delay function of the first delay unit is disabled, so that the first control module outputs the shutdown enable signal before the second control module.

3. The driving circuit as described in claim 2, characterized in that, The first control module also includes a first switching unit; The first switching unit is connected to the first delay unit. When the control signal is turned on, the first switching unit controls the signal delay function of the first delay unit to be activated, and when the control signal is turned off, the first switching unit disables the signal delay function of the first delay unit.

4. The driving circuit as described in claim 3, characterized in that, The first delay unit includes a first capacitor and a first resistor, and the first switching unit includes a first transistor; The first terminal of the first capacitor is connected to the control terminal of the first switching transistor, and the second terminal of the first capacitor is connected to the first terminal of the first switching transistor. The first end of the first resistor is connected to the first end of the first capacitor, and the second end of the first resistor is connected to the control signal; The first terminal of the first transistor is connected to the first terminal of the first capacitor, the second terminal of the first transistor is connected to the second terminal of the first capacitor, and the control terminal of the first transistor is connected to the control signal.

5. The driving circuit as described in claim 2, characterized in that, The second control module also includes a second switching unit; The second switching unit is connected to the second delay unit. When the control signal is turned on, the second switching unit disables the signal delay function of the second delay unit. When the control signal is turned off, the second switching unit controls the signal delay function of the second delay unit to take effect.

6. The driving circuit as described in claim 5, characterized in that, The second delay unit includes a second capacitor and a second resistor, and the second switching unit includes a second transistor; The first terminal of the second capacitor is connected to the control terminal of the second switching transistor, the second terminal of the second capacitor is connected to the first terminal of the second resistor, and the second terminal of the second resistor is connected to the control signal. The first terminal of the second transistor is connected to the control terminal of the second switching transistor, the second terminal of the second transistor is connected to the control signal, and the control terminal of the second transistor is connected to the first node between the second capacitor and the second resistor.

7. The driving circuit as described in claim 6, characterized in that, The second switching unit also includes a third transistor and a third resistor; The first end of the third resistor is connected to the control terminal of the second switching transistor, and the second end of the third resistor is connected to the first end of the second capacitor; The first terminal of the third transistor is connected to the control terminal of the second switching transistor, the second terminal of the third transistor is connected to the first terminal of the second switching transistor, and the control terminal of the third transistor is connected to the first terminal of the second transistor.

8. The driving circuit as described in claim 7, characterized in that, The second switching unit also includes a fourth resistor and a third capacitor; The first end of the fourth resistor is connected to the control terminal of the second switching transistor, the second end of the fourth resistor is connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the first end of the second switching transistor.

9. The driving circuit as described in claim 8, characterized in that, The second switching unit also includes a fifth resistor and a first diode; The first end of the fifth resistor is connected to the first end of the third capacitor, the second end of the fifth resistor is connected to the positive end of the first diode, and the negative end of the first diode is connected to the first end of the third transistor. The resistance value of the fifth resistor is less than the resistance value of the fourth resistor.

10. An electrical device, characterized in that, Includes the drive circuit as described in any one of claims 1 to 9.

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