Non-integer frequency divider

Abstract

This invention discloses a non-integer frequency divider, comprising a mixer unit, a buffer unit, a first integer frequency divider unit, and a second integer frequency divider unit. The mixer unit mixes the input radio frequency signal with the feedback frequency-divided signal output from the second integer frequency divider unit to obtain a mixed signal. The buffer unit filters and amplifies the mixed signal output from the mixer unit to form a buffered signal. The first integer frequency divider unit divides the buffered signal output from the buffer unit to obtain an output frequency-divided signal. The second integer frequency divider unit divides the output frequency-divided signal to obtain a feedback frequency-divided signal, which is then output to the mixer unit. The division coefficient of the second integer frequency divider unit is an integer. The non-integer frequency divider of this invention has the advantages of high operating frequency, high reliability, low coupling, and low spurious emissions.

Description

Technical Field

[0001] This invention relates to the field of integrated electronic circuit technology, and in particular to a non-integer frequency divider. Background Technology

[0002] Frequency dividers are an important component of radio frequency synthesizers. Based on their circuit implementation principles, they can be divided into digital frequency dividers and analog frequency dividers. Digital frequency dividers are widely used in lower frequency bands. In high-frequency communication fields such as radio frequency / millimeter wave, due to the speed bottleneck of digital frequency dividers, analog frequency dividers are used more often to process high-speed signals.

[0003] Existing high-speed analog frequency dividers can be broadly categorized into: current-mode logic (CML), injection-locked loop (ILFD), and regenerative frequency divider (Miller). Among these, regenerative frequency dividers have extremely high operating frequencies, and their inherent low phase noise characteristics can reduce the phase noise contributed by the frequency divider module, thus improving the phase noise of the input signal.

[0004] Existing frequency dividers can be categorized based on the difference in division factors into integer dividers (where the division factor is an integer), half-integer dividers (where the division factor is N+0.5, and N is an integer), and fractional dividers (where the division factor is a fraction, such as 8.56654 or 5 / 4). Existing integer dividers are often implemented using cascaded multi-mode dividers or swallowing pulse counters. Their advantages include simple design, low division spurious emissions, and high operating frequency; their disadvantage is low frequency resolution. Existing half-integer dividers often use dual-edge triggers or dual-mode dividers with control logic. Their advantages include relatively high resolution and moderate complexity; their disadvantage is decreased reliability at high frequencies. Existing fractional dividers often use Delta-Sigma modulators to control multi-mode dividers. Their advantages include high resolution; their disadvantages include division spurious emissions and complex design.

[0005] In view of the above problems, this invention proposes a novel non-integer frequency divider that addresses the shortcomings of existing half-integer and fractional frequency dividers, which can maintain high operational reliability in high-frequency operating scenarios. Summary of the Invention

[0006] The purpose of this invention is to provide a novel non-integer frequency divider that can maintain high operational reliability in high-frequency operating scenarios.

[0007] To achieve the above objectives, the solution of the present invention is: A non-integer frequency divider includes a mixer unit, a buffer unit, a first integer frequency divider unit, and a second integer frequency divider unit. The mixer unit mixes an input radio frequency signal with a feedback frequency-divided signal output from the second integer frequency divider unit to obtain a mixed signal. The buffer unit is connected to the mixer unit and filters and amplifies the mixed signal output from the mixer unit to form a buffered signal. The first integer frequency divider unit is connected to the buffer unit and divides the buffered signal output from the buffer unit to obtain an output frequency-divided signal. The division coefficient of the first integer frequency divider unit is an integer. The second integer frequency divider unit is connected to the first integer frequency divider unit and the mixer unit. The second integer frequency divider unit divides the output frequency-divided signal to obtain a feedback frequency-divided signal, which is then output to the mixer unit. The division coefficient of the second integer frequency divider unit is an integer.

[0008] The mixer unit has an LC resonant load, and the inductor used in the LC resonant load is a figure-eight inductor.

[0009] The mixing unit includes MOSFETs M1, M2, M3, M4, M5, and M6, capacitors C1, C2, C3, C4, and C5, inductor L1, and current source I1. The first terminals of capacitors C3 and C4 are connected to the RF+ and RF- ports of the mixing unit, respectively. The second terminals of capacitors C3 and C4 are connected to the gates of MOSFETs M1 and M2, respectively. The sources of MOSFETs M1 and M2 are connected to the first terminal of current source I1, and the second terminal of current source I1 is grounded. The drain of MOSFET M1 is connected to the sources of MOSFETs M3 and M4, the drain of MOSFET M2 is connected to the sources of MOSFETs M5 and M6, and the gates of MOSFETs M3 and M6 are connected to each other. The first terminal of capacitor C2 is connected to the gate of MOSFET M4 and the gate of MOSFET M5. The second terminals of capacitor C2 and C5 are connected to the LO+ and LO- ports of the mixer unit, respectively. The drains of MOSFET M3 and M5, the first terminal of capacitor C1, and the first terminal of inductor L1 are connected to the IF+ port of the mixer unit. The drains of MOSFET M4 and M6, the second terminal of capacitor C1, and the second terminal of inductor L1 are connected to the IF- port of the mixer unit. The middle node of inductor L1 is connected to power supply VDD. Inductor L1 is a figure-eight inductor. The IF+ and IF- ports of the mixer unit are used to output the mixing signal. The RF+ and RF- ports of the mixer unit are used to input the radio frequency signal. The LO+ and LO- ports of the mixer unit are used to input the feedback frequency division signal.

[0010] The buffer unit has an LC resonant load, and the inductor used in the LC resonant load is a figure-eight inductor.

[0011] The buffer unit includes MOSFETs M7, M8, M9, and M10, resistors R1, R2, and R3, capacitors C6, C7, and C8, inductor L2, and current source I2. The first terminals of capacitors C7 and C8 are connected to the IN+ and IN- terminals of the buffer unit, respectively. The second terminals of capacitors C7 and C8 are connected to the gates of MOSFETs M7 and M8, respectively. The gates of MOSFETs M7 and M8 are connected to the first terminal of resistor R3, and the second terminal of resistor R3 is connected to power supply VCC3. The sources of MOSFETs M7 and M8 are connected to the first terminal of current source I2, and the second terminal of current source I2 is grounded. The drain of MOSFET M8 and the drain of MOSFET M9 are connected to the source of MOSFET M10 and the source of MOSFET M9, respectively. The gates of MOSFET M9 and MOSFET M10 are connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to power supply VCC2. The drain of MOSFET M9, the first terminal of capacitor C6, and the first terminal of inductor L2 are connected to the OUT+ terminal of the buffer unit. The drain of MOSFET M10, the second terminal of capacitor C6, and the second terminal of inductor L2 are connected to the OUT- terminal of the buffer unit. The middle node of inductor L2 is connected to power supply VCC1 through resistor R1. Inductor L2 is a figure-eight inductor. The IN+ and IN- terminals of the buffer unit are used to input the mixing signal, and the OUT+ and OUT- terminals of the buffer unit are used to output the buffered signal.

[0012] The figure-eight inductor's coil forms two nested loops with opposite winding directions.

[0013] After adopting the above scheme, the working principle of the non-integer frequency divider of the present invention is as follows: The mixer unit converts the input radio frequency signal F IN The feedback frequency division signal F output by the second integer frequency division unit D Mixing is performed to obtain the mixed signal F MIX The buffer unit is used to process the mixing signal F output by the mixing unit. MIX Filtering and amplification are performed to form a buffered signal F. BUF The first integer frequency divider unit outputs the buffer signal F from the buffer unit. BUF The output frequency-divided signal F is obtained by frequency division. OUT The second integer frequency divider unit is used to divide the output frequency signal F. OUT The feedback frequency division signal F is obtained by frequency division. DThe output is then sent to the mixing unit. Specifically, this invention achieves a non-integer multiple division coefficient for the entire non-integer frequency divider by selecting the division coefficient N of the first integer division unit and the division coefficient M of the second integer division unit. Furthermore, the non-integer frequency divider of this invention employs a regenerative division structure (due to the high-frequency operating characteristics and low phase noise of regenerative division), and the first and second integer division units use integer division (enabling high-speed frequency division signal processing and low spurious emissions). This allows the non-integer frequency divider of this invention to meet the requirements of high-frequency, low-spurious-emission operating scenarios while ensuring operational reliability. Additionally, the mixing unit and buffer unit of this invention use LC resonant loads, and the inductor element of the LC resonant load is an 8-shaped inductor, which effectively reduces coupling and meets the requirements of low-coupling operating scenarios. Moreover, the mixing unit, buffer unit, first integer division unit, and second integer division unit of this invention can all be implemented using analog circuits, thereby avoiding the use of high-frequency clocks and complex logic control in digital circuits, further ensuring operational reliability. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the principle of the present invention.

[0015] Figure 2 This is a circuit diagram of the mixer unit of the present invention.

[0016] Figure 3 This is a circuit diagram of the buffer unit of the present invention.

[0017] Figure 4 This is a schematic diagram of the structure of the figure-eight shaped inductor of the present invention.

[0018] Label Explanation: Mixing unit 1, buffer unit 2, first integer frequency divider unit 3, and second integer frequency divider unit 4. Detailed Implementation

[0019] To further explain the technical solution of the present invention, the present invention will be described in detail below through specific embodiments.

[0020] like Figures 1 to 3 As shown, this invention discloses a non-integer frequency divider, which includes a mixer unit 1, a buffer unit 2, a first integer frequency divider unit 3, and a second integer frequency divider unit 4; wherein, the mixer unit 1 is used to divide the input radio frequency signal F in The feedback frequency division signal F output by the second integer frequency division unit 4 D Mixing is performed to obtain the mixed signal F MIX Buffer unit 2 is connected to mixer unit 1, and buffer unit 2 is used to process the mixing signal F output by mixer unit 1. MIXFiltering and amplification are performed to form a buffered signal F. BUF The first integer frequency divider unit 3 is connected to the buffer unit 2, and the first integer frequency divider unit 3 is used to process the buffered signal F output by the buffer unit 2. BUF The output frequency-divided signal F is obtained by frequency division. OUT The division coefficient of the first integer frequency divider unit 3 is an integer; the second integer frequency divider unit 4 is connected to the first integer frequency divider unit 3 and the mixer unit 1, and the second integer frequency divider unit 4 is used to divide the output frequency-divided signal F. OUT The feedback frequency division signal F is obtained by frequency division. D The output is given to the mixing unit 1, and the division coefficient of the second integer division unit 4 is an integer.

[0021] The working principle of the non-integer frequency divider of this invention is as follows: Mixer unit 1 converts the input radio frequency signal F IN The feedback frequency division signal F output by the second integer frequency division unit 4 D Mixing is performed to obtain the mixed signal F MIX Buffer unit 2 is used to process the mixing signal F output by mixing unit 1. MIX Filtering and amplification are performed to form a buffered signal F. BUF The first integer frequency division unit 3 buffers the output signal F of the buffer unit 2. BUF The output frequency-divided signal F is obtained by frequency division. OUT The second integer frequency divider unit 4 is used to divide the output frequency signal F. OUT The feedback frequency division signal F is obtained by frequency division. D To output to mixer unit 1; Among them, the radio frequency signal F is set. IN The frequency is f IN Mixing signal F MIX The frequency is f MIX Buffer signal F BUF The frequency is f BUF Output frequency division signal F OUT The frequency is f OUT Feedback frequency division signal F D The frequency is f D The division coefficient of the first integer frequency divider unit 3 is N, and the division coefficient of the second integer frequency divider unit 4 is M, where N and M are integers. Then we have: f MIX = f IN -f D ; f BUF =f MIX ; f OUT = f BUF ×(1 / N); fD = f OUT ×(1 / M); f OUT / f IN =N+1 / M; As described above, this invention achieves non-integer multiples of the division coefficient of the entire non-integer frequency divider by selecting the division coefficient N of the first integer frequency divider unit 3 and the division coefficient M of the second integer frequency divider unit 4. Furthermore, the non-integer frequency divider of this invention employs a regenerative frequency divider structure (due to the high-frequency operating characteristics and low phase noise of regenerative frequency dividers), and the first integer frequency divider unit 3 and the second integer frequency divider unit 4 use integer frequency division (enabling high-speed frequency division signal processing and low frequency division spurious signals). This allows the non-integer frequency divider of this invention to meet the requirements of high-frequency, low-spurious-sound operating scenarios while ensuring operational reliability. Additionally, the mixing unit and buffer unit of this invention use LC resonant loads, and the inductor element of the LC resonant load is an 8-shaped inductor, which effectively reduces coupling and meets the requirements of low-coupling operating scenarios. Moreover, the mixing unit 1, buffer unit 2, first integer frequency divider unit 3, and second integer frequency divider unit 4 of this invention can all be implemented using analog circuits, thereby avoiding the use of high-frequency clocks and complex logic control in digital circuits, further ensuring operational reliability.

[0022] In an embodiment of the present invention, the mixing unit 1 may include MOSFETs M1, M2, M3, M4, M5, and M6, capacitors C1, C2, C3, C4, and C5, inductor L1, and current source I1. The first terminals of capacitors C3 and C4 are respectively connected to the RF+ and RF- ports of the mixing unit. The second terminals of capacitors C3 and C4 are respectively connected to the gates of MOSFETs M1 and M2. The gates of MOSFETs M1 and M2 are connected to power supply VDD1. The sources of MOSFETs M1 and M2 are connected to the first terminal of current source I1, and the second terminal of current source I1 is grounded. The drain of MOSFET M1 is connected to the sources of MOSFETs M3 and M4, and the drain of MOSFET M2 is connected to the sources of MOSFETs M5 and M6. The source, gate of MOSFET M3, and gate of MOSFET M6 are connected to the first terminal of capacitor C2. The gates of MOSFET M4 and M5 are connected to the first terminal of capacitor C5. The second terminals of capacitor C2 and C5 are connected to the LO+ and LO- ports of the mixer unit, respectively. The gates of MOSFETs M3, M4, M5, and M6 are connected to power supply VDD2. The drains of MOSFETs M3 and M5, the first terminal of capacitor C1, and the first terminal of inductor L1 are connected to the IF+ port of the mixer unit. The drains of MOSFETs M4 and M6, the second terminal of capacitor C1, and the second terminal of inductor L1 are connected to the IF- port of the mixer unit. The middle node of inductor L1 is connected to power supply VDD3. Inductor L1 is a figure-eight inductor. The IF+ and IF- ports of mixer unit 1 are used to output the mixing signal F. MIX The RF+ and RF- ports of mixer unit 1 are used to receive radio frequency signal F. IN The LO+ and LO- ports of mixer unit 1 are used to receive the feedback frequency division signal F. D As described above, the mixer unit 1 of the present invention has an LC resonant load (i.e., an LC resonant load composed of inductor L1 and capacitor C1), and the inductor element (i.e., inductor L1) used in the LC resonant load is a figure-eight inductor; wherein, the LC resonant load can provide suppression of undesired frequencies, while the figure-eight inductor can reduce coupling (in conjunction with...). Figure 4 As shown, the coil of the figure-eight inductor forms two nested loops with opposite winding directions. When current flows through the figure-eight inductor, the magnetic fields generated by the two loops are in opposite directions, and the magnetic lines of force of the magnetic fields generated by the two loops cancel each other out outside the figure-eight inductor. Conversely, when the external electromagnetic field changes and causes the figure-eight inductor to generate an induced current, the induced currents of the two loops will also cancel each other out, thereby reducing coupling. This can further improve the overall circuit's working stability.

[0023] In an embodiment of the present invention, the buffer unit 2 may include MOSFETs M7, M8, M9, and M10, resistors R1, R2, and R3, capacitors C6, C7, and C8, inductor L2, and current source I2. The first terminals of capacitors C7 and C8 are respectively connected to the IN+ and IN- terminals of the buffer unit 2. The second terminals of capacitors C7 and C8 are respectively connected to the gates of MOSFETs M7 and M8. The gates of MOSFETs M7 and M8 are connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to power supply VCC3. The sources of MOSFETs M7 and M8 are connected to the first terminal of current source I2. The second terminal of current source I2 is grounded. The drains of MOSFETs M7 and M8 are connected to the sources of MOSFETs M9 and M10, respectively. The gates of MOSFETs M9 and M10 are connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to power supply VCC2. The drain of MOSFET M9, the first terminal of capacitor C6, and the first terminal of inductor L2 are connected to the OUT+ terminal of buffer unit 2. The drain of MOSFET M10, the second terminal of capacitor C6, and the second terminal of inductor L2 are connected to the OUT- terminal of buffer unit 2. The middle node of inductor L2 is connected to power supply VCC1 through resistor R1. Inductor L2 is a figure-eight inductor. The IN+ and IN- terminals of buffer unit 2 are used to input the mixing signal F. MIX The OUT+ and OUT- terminals of buffer unit 2 are used to output the buffered signal F. BUF As can be seen from the foregoing, the buffer unit 2 of the present invention also has an LC resonant load (i.e., an LC resonant load composed of inductor L2 and capacitor C6), and the inductor element (i.e., inductor L2) used in the LC resonant load is a figure-eight inductor; wherein, the LC resonant load can provide suppression of non-desired frequency points, and the figure-eight inductor can reduce coupling, thus further improving the overall circuit's working stability.

[0024] The above embodiments and figures are not intended to limit the product form and style of the present invention. Any appropriate changes or modifications made by those skilled in the art should be considered as not departing from the patent scope of the present invention.

Claims

1. A non-integer frequency divider, characterized in that: It includes a mixer unit, a buffer unit, a first integer frequency divider unit, and a second integer frequency divider unit; The mixing unit is used to mix the input radio frequency signal with the feedback frequency division signal output by the second integer frequency division unit to obtain a mixed signal; The buffer unit is connected to the mixer unit. The buffer unit is used to filter and amplify the mixed signal output by the mixer unit to form a buffered signal. The first integer frequency divider unit is connected to the buffer unit. The first integer frequency divider unit is used to divide the buffered signal output by the buffer unit to obtain the output frequency divided signal. The frequency division coefficient of the first integer frequency divider unit is an integer. The second integer frequency divider unit connects the first integer frequency divider unit and the mixing unit. The second integer frequency divider unit is used to divide the output frequency divider signal to obtain a feedback frequency divider signal, which is then output to the mixing unit. The frequency division coefficient of the second integer frequency divider unit is an integer.

2. The non-integer frequency divider as described in claim 1, characterized in that: The mixer unit has an LC resonant load, and the inductor used in the LC resonant load is a figure-eight inductor.

3. The non-integer frequency divider as described in claim 1 or 2, characterized in that: The mixer unit includes MOSFETs M1, M2, M3, M4, M5, and M6, capacitors C1, C2, C3, C4, and C5, inductor L1, and current source I1. The first terminals of capacitors C3 and C4 are connected to the RF+ and RF- ports of the mixer unit, respectively. The second terminals of capacitors C3 and C4 are connected to the gates of MOSFETs M1 and M2, respectively. The gates of MOSFETs M1 and M2 are connected to power supply VDD1. The sources of MOSFETs M1 and M2 are connected to the first terminal of current source I1, and the second terminal of current source I1 is grounded. The drain of MOSFET M1 is connected to the sources of MOSFETs M3 and M4, and the drain of MOSFET M2 is connected to the sources of MOSFETs M5 and M6. The source of MOSFET M6, the gate of MOSFET M3, and the gate of MOSFET M6 are connected to the first terminal of capacitor C2. The gates of MOSFET M4 and MOSFET M5 are connected to the first terminal of capacitor C5. The second terminals of capacitor C2 and capacitor C5 are connected to the LO+ and LO- ports of the mixer unit, respectively. The gates of MOSFET M3, MOSFET M4, MOSFET M5, and MOSFET M6 are connected to power supply VDD2. The drains of MOSFET M3 and MOSFET M5, the first terminal of capacitor C1, and the first terminal of inductor L1 are connected to the IF+ port of the mixer unit. The drains of MOSFET M4 and MOSFET M6, the second terminal of capacitor C1, and the second terminal of inductor L1 are connected to the IF- port of the mixer unit. The middle node of inductor L1 is connected to power supply VDD3. Inductor L1 is a figure-eight inductor. The IF+ and IF- ports of the mixer unit are used to output the mixer signal, the RF+ and RF- ports of the mixer unit are used to receive the radio frequency signal, and the LO+ and LO- ports of the mixer unit are used to receive the feedback frequency division signal.

4. The non-integer frequency divider as described in claim 1, characterized in that: The buffer unit has an LC resonant load, and the inductor used in the LC resonant load is a figure-eight inductor.

5. The non-integer frequency divider as described in claim 1 or 4, characterized in that: The buffer unit includes MOSFETs M7, M8, M9, and M10, resistors R1, R2, and R3, capacitors C6, C7, and C8, inductor L2, and current source I2. The first terminals of capacitors C7 and C8 are connected to the IN+ and IN- terminals of the buffer unit, respectively. The second terminals of capacitors C7 and C8 are connected to the gates of MOSFETs M7 and M8, respectively. The gates of MOSFETs M7 and M8 are connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to power supply VCC3. The sources of MOSFETs M7 and M8 are connected to current source I2. The first terminal of the current source I2 is grounded. The drain of MOSFET M7 and the drain of MOSFET M8 are connected to the source of MOSFET M9 and the source of MOSFET M10, respectively. The gate of MOSFET M9 and the gate of MOSFET M10 are connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to power supply VCC2. The drain of MOSFET M9, the first terminal of capacitor C6 and the first terminal of inductor L2 are connected to the OUT+ terminal of the buffer unit. The drain of MOSFET M10, the second terminal of capacitor C6 and the second terminal of inductor L2 are connected to the OUT- terminal of the buffer unit. The middle node of inductor L2 is connected to power supply VCC1 through resistor R1. Inductor L2 is a figure-eight inductor. The IN+ and IN- terminals of the buffer unit are used to input the mixing signal, and the OUT+ and OUT- terminals of the buffer unit are used to output the buffered signal.

6. The non-integer frequency divider as described in claim 2 or 4, characterized in that: The figure-eight inductor's coil forms two nested loops with opposite winding directions.

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