A frequency self-following control system and method for a radio frequency power supply
Patent Information
- Application Number
- CN202611120924.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-27
- Publication Date
- 2026-10-20
Smart Images
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Abstract
Description
Technical Field
[0001] This invention relates to the field of radio frequency power source technology, and in particular to a frequency self-following control system and method for radio frequency power supplies, which is especially suitable for industrial application scenarios with stringent requirements for long-term frequency stability, such as plasma etching equipment, PECVD (plasma-enhanced chemical vapor deposition) devices, radio frequency sputtering systems, synthesis systems with multiple power supplies working together, and medical radio frequency ablation equipment. Background Technology
[0002] In industrial production fields such as semiconductor etching, plasma deposition, and radio frequency induction heating, the frequency (RF) power supply serves as the core of energy supply. The frequency synchronization accuracy of its output signal is a key indicator for ensuring the stability of production processes, the reliability of load operation, and the efficiency of energy transmission. To adapt to the dynamic resonance characteristics of plasma loads or the collaborative operation requirements of multiple devices, the RF power supply must have a frequency synchronization tracking function. That is, the frequency of its output RF fundamental signal must track the external reference signal in real time and accurately, ensuring that it maintains the same frequency as the external reference signal (such as the plasma resonant frequency or the main equipment synchronization trigger signal). This avoids problems such as impedance mismatch, energy reflection, and abnormal load discharge caused by frequency deviation, and ensures the consistency of process parameters. Currently, the frequency synchronization and following technology of radio frequency power supplies used in the industrial field is generally based on the frequency measurement-tuning closed-loop approach of local clock reference. Its core design logic is as follows: the crystal oscillator (hereinafter referred to as crystal) integrated inside the radio frequency power supply is used as the core frequency reference. The frequency of the external reference signal is detected by a digital frequency measurement module (such as a digital frequency counter) or an analog sampling module (such as ADC sampling combined with FFT operation). The detection result is compared with the local crystal oscillator reference frequency. Then, the internal output frequency is fine-tuned through a feedback adjustment mechanism to finally achieve frequency following with the external reference signal.
[0003] However, in practical industrial applications, RF power supplies often operate in environments with drastic temperature fluctuations. The internal temperature of the chassis is affected by factors such as ambient temperature and the heat generated by the components themselves. Engineering practice shows that the internal temperature of an RF power supply often varies from approximately 25°C to 70°C depending on the power output, and this temperature variation leads to a significant decrease in frequency accuracy. The crystal oscillator on the control board of the RF power supply, as the core frequency reference in traditional solutions, will shift its oscillation frequency with temperature changes, exhibiting a temperature drift phenomenon: the temperature drift coefficient of ordinary industrial-grade crystal oscillators is typically between ±20ppm and ±50ppm. Even when using a temperature-compensated crystal oscillator (TCXO), its temperature drift coefficient can only be controlled within ±1ppm to ±5ppm. While temperature-controlled crystal oscillators (OCXOs) offer higher precision, their high cost, high power consumption, and large size make them unsuitable for the miniaturization and low-cost design requirements of industrial RF power supplies, hindering their widespread application. Temperature drift is a key factor limiting the frequency synchronization accuracy of crystal oscillators. Frequency deviation caused by temperature drift is directly transmitted to the RF power supply output. For example, for a 60MHz RF output signal, if a standard crystal oscillator with a temperature drift coefficient of ±30ppm is used, a 10℃ change in ambient temperature can cause a frequency drift of up to 18kHz. Even if the external reference signal frequency remains stable, this drift will still lead to a significant deviation between the power supply output frequency and the external reference signal, disrupting the impedance matching of the plasma load and affecting process repeatability. Some solutions compensate for temperature drift errors using software algorithms, but software compensation suffers from response lag and limitations in accuracy due to algorithm complexity, making it unsuitable for the real-time requirements of high-frequency synchronization in RF power supplies. Other solutions employ a multi-crystal redundancy design, reducing the impact of temperature drift through comparison and calibration of multiple crystals. However, this approach not only increases circuit design complexity and hardware cost but also fails to completely eliminate the frequency drift caused by crystal temperature drift.
[0004] Therefore, existing technologies lack a method for achieving the same frequency output without relying on the absolute accuracy of the crystal oscillator, unaffected by temperature drift, and directly achieving the goal of equal frequency. Summary of the Invention
[0005] This application provides a frequency self-following control system and method for radio frequency power supplies, which solves the problem in existing radio frequency power supply frequency synchronization technology where the temperature drift characteristics of the crystal oscillator cause a significant deviation between the power supply output frequency and the external reference signal during long-term operation, and achieves frequency synchronization following that is immune to temperature drift.
[0006] This application provides a frequency self-following control system for radio frequency power supplies, including: An external reference signal input module is used to receive an external reference sinusoidal signal Sref(t) as a reference source for frequency tracking. The DDS module, or Digital Frequency Synthesizer module, is used to generate an internally adjustable sine wave signal Svco(t), whose output frequency is determined by the frequency control word F. TW Decide; A dual-channel comparator includes a first comparator and a second comparator, wherein the first comparator shapes the external reference sinusoidal signal Sref(t) into a first square wave pulse sequence, and the second comparator shapes the internal sinusoidal signal Svco(t) into a second square wave pulse sequence; A pulse counter is used to set a fixed number of pulse counts N, and to count the first square wave pulse sequence and the second square wave pulse sequence respectively; A dual-channel time measurement unit is used to measure, based on the system's high-frequency clock, the time T1 required for the first square wave pulse sequence to generate N pulses, and the time T2 required for the second square wave pulse sequence to generate N pulses, respectively. A closed-loop feedback control unit is used to dynamically adjust the frequency control word F of the DDS module based on the difference between time T1 and time T2. TW This forms a negative feedback closed loop, making the difference between time T1 and time T2 less than a set threshold, thereby achieving synchronous output.
[0007] The beneficial effects of the above embodiments are as follows: This system constructs a dual-channel time comparison closed-loop architecture with a fixed number of pulses N as the dimension. By measuring the time required for the external reference signal and the internal DDS signal to generate the same fixed number of pulses, and using the time difference as an error signal for closed-loop feedback control, the two times are forced to approach equality, thereby achieving synchronous output in the frequency domain. This system transforms the frequency comparison problem into a time comparison problem, so that the system clock frequency is completely canceled out in the expression of the steady-state output frequency, thus theoretically eliminating the impact of crystal oscillator temperature drift on frequency synchronization accuracy and achieving temperature drift-immune frequency synchronization following.
[0008] Based on the above embodiments, this application can be further improved as follows: In one embodiment of this application, the system clock of the DDS module and the time measurement clock of the dual-channel time measurement unit use the same clock source, which is selected from any one of a common crystal oscillator, a temperature-compensated crystal oscillator, or a temperature-controlled crystal oscillator.
[0009] Technical effect: By sharing the same clock source, the time measurement value M2 obtained by the dual-channel time measurement unit is equal to N·2. M / F TW In the expression, the system clock frequency fclk The M2 and M1 are completely canceled out, ensuring that the equality relationship remains unchanged regardless of the temperature drift of the system clock.
[0010] In one embodiment of this application, the times T1 and T2 measured by the dual-channel time measurement unit are quantized in units of system clock cycles Tclk, where Tclk = 1 / fclk , fclk The system's high-frequency clock frequency is used to obtain time measurements M1 = T1 / Tclk and M2 = T2 / Tclk. The closed-loop feedback control unit compares M1 and M2 instead of directly comparing T1 and T2.
[0011] Technical benefits: By quantizing continuous time into discrete clock cycle count values, it is easier to implement time comparison and closed-loop control in the FPGA digital domain, simplifying the design of digital logic circuits.
[0012] In one embodiment of this application, the closed-loop feedback control unit updates the frequency control word F using adaptive step control. TW The updated formula is: ; F TW (k+1) = F TW (k) ± ΔF TW ; in Δlarge, Δmedium, Δsmall, θ high and θ low All are preset values, ΔF TW The step size is dynamically selected based on the size of |M1-M2|.
[0013] Technical benefits: Through adaptive step control, a large step size is used to achieve fast acquisition when the frequency difference is large, and a small step size is used to achieve fine adjustment when the frequency difference is small. This balances locking speed and steady-state accuracy, and avoids overshoot or slow convergence caused by fixed step size.
[0014] In one embodiment of this application, the closed-loop feedback control unit is further used to determine the locking state. When |M1-M2| ≤ ΔMth is satisfied for K consecutive measurement cycles, the system is determined to enter the locking state and the locking state flag is set, where ΔMth is a preset locking threshold and K is an integer greater than 1.
[0015] Technical benefits: The multi-cycle continuous judgment mechanism avoids false locking caused by noise from a single measurement, thus improving the reliability of locking judgment; the locking status flag can be read by external systems, facilitating system status monitoring and interlocking control.
[0016] In one embodiment of the present application, the closed-loop feedback control unit continuously monitors |M1-M2| in the locked state. When |M1-M2| ≥ ΔMunlock is detected for L consecutive measurement cycles, it is determined that the system is out of lock, the lock status flag bit is cleared, and the measurement and adjustment process is automatically restarted, where ΔMunlock>ΔMth, and L is an integer greater than or equal to 1.
[0017] Technical effects: By setting an out-of-lock threshold greater than the lock threshold, a hysteresis comparison interval is formed, which prevents the system from frequently switching between the locked and out-of-lock states near the lock boundary; automatic re-locking after losing lock realizes long-term stable operation without on-site attendance.
[0018] An embodiment of the present application provides a frequency self-tracking control method for a radio frequency power supply, which is based on the aforementioned frequency self-tracking control system and includes the following steps: S1: Receive an external reference sine signal Sref(t), and convert it into a first square wave pulse sequence through a first comparator; S2: Generate an internal sine signal Svco(t) by a DDS module, and convert it into a second square wave pulse sequence through a second comparator, where the first comparator and the second comparator are two comparison channels of the dual-channel comparator; S3: Set a fixed number of pulse counts N, and separately measure, by a dual-channel time measurement unit, the time T1 required for the first square wave pulse sequence to generate N pulses and the time T2 required for the second square wave pulse sequence to generate N pulses; S4: Compare the time T1 and the time T2 obtained in step S3. If |T1 - T2| >ΔTth and T1>T2, it is determined that the external reference frequency fref is lower than the internal DDS output frequency fvco , and the current DDS frequency control word F TW is decreased to reduce the internal DDS output frequency fvco ; if |T1 - T2| >ΔTth and T1<T2, it is determined that the external reference frequency fref is higher than the internal DDS output frequency fvco , and the current DDS frequency control word F TW is increased to raise the internal DDS output frequency fvco ; if |T1 -T2| ≤ ΔTth, the current frequency control word F TW remains unchanged; ΔTth is a set threshold; S5: Repeat step S3 to step S4 until |T1 - T2| ≤ ΔTth, at which point the system achieves same-frequency output.
[0019] Technical effect: By using time comparison closed-loop control under fixed pulse counting, frequency synchronization is achieved without relying on the absolute accuracy of the crystal oscillator. The system clock frequency in the steady-state output frequency expression is completely eliminated, and the crystal oscillator temperature drift does not enter the steady-state error, fundamentally breaking through the limitations of traditional frequency measurement schemes.
[0020] In one embodiment of this application, in step S4, the time T1 and the time T2 are quantized using a system high-frequency clock, and the quantized time measurements are M1 = T1 / Tclk and M2 = T2 / Tclk, respectively, where Tclk = 1 / fclk For the system clock cycle, fclk The system clock frequency is used; the comparison of time T1 and time T2 is replaced by the comparison of M1 and M2.
[0021] Technical benefits: By implementing time quantization and comparison in the digital domain, the impact of analog device drift on comparison accuracy is eliminated, while simplifying digital logic implementation.
[0022] In one embodiment of this application, in step S4, the frequency control word F TW The adjustment step size is adaptively selected based on the magnitude of |T1-T2| or |M1-M2|. When |T1-T2|| or |M1-M2| is large, a large step size is selected to speed up the convergence speed. When |T1-T2|| or |M1-M2| is small, a small step size is selected to ensure steady-state accuracy.
[0023] Technical effect: By adaptively adjusting the step size, a phased optimization control of "coarse adjustment and fast acquisition, fine adjustment and stable locking" is achieved, which takes into account both the dynamic response speed and steady-state accuracy of the system.
[0024] In one embodiment of this application, in step S5, when multiple consecutive measurement cycles satisfy |T1 - T2|≤ ΔTth or |M1-M2|≤ΔMth, the system is determined to enter a locked state, and |T1 - T2| or |M1-M2| is continuously monitored in the locked state; if |T1 - T2|≥ ΔTunlock or |M1-M2|≥ ΔMunlock is detected in multiple consecutive measurement cycles in the locked state, the system is determined to be unlocked and steps S3 to S5 are automatically re-executed.
[0025] Technical benefits: By using multi-cycle continuous locking determination and lock loss determination with hysteresis, the locking stability of the system in noisy environments is improved, avoiding false locking and false lock loss. Attached Figure Description
[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale.
[0027] Figure 1 This is a structural block diagram of a frequency self-following control system for radio frequency power supply in an embodiment of this application; Figure 2 This is a flowchart illustrating a frequency self-following control method for an RF power supply in an embodiment of this application. Detailed Implementation
[0028] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0029] Example: like Figure 1 As shown, a frequency self-following control system for radio frequency power supplies includes the following components: The external reference signal input module is used to receive an external reference sine signal Sref(t) as a reference source for frequency following.
[0030] The internal DDS module, controlled by an FPGA, generates a frequency-adjustable sinusoidal signal Svco(t) based on the phase accumulation principle. Its output frequency is controlled by the frequency control word F. TW The decision is based on the following relationship: ;in fclk M is the system clock frequency, and M is the bit width of the phase accumulator.
[0031] The dual-channel comparator comprises two high-speed comparators. The first channel shapes an external reference sine wave signal Sref(t) into a first square wave pulse sequence of the same frequency, and the second channel shapes a sine wave signal Svco(t) output from an internal DDS into a second square wave pulse sequence of the same frequency. This dual-channel comparator preferably uses dual-channel comparator devices in the same chip package to ensure the symmetry of the propagation delays of the two channels.
[0032] The pulse counter is set to a fixed number of pulses N. It counts the first square wave pulse sequence and the second square wave pulse sequence respectively. When any channel counts N pulses, it immediately latches the time measurement value of that channel and waits for the other channel to complete counting.
[0033] The dual-channel time measurement unit, based on the system's high-frequency clock, measures the time T1 required for the external reference signal to generate N pulses, and the time T2 required for the internal DDS signal to generate N pulses.
[0034] The closed-loop feedback control unit dynamically adjusts the frequency control word F of the DDS based on the time difference signal output by the dual-channel time measurement unit. TW This forms a negative feedback closed loop, ultimately forcing the difference between the time T1 and T2 used by the external reference signal and the internal DDS signal to generate the same number of pulses to be less than a set threshold (approaching equality), thereby achieving synchronous output.
[0035] The principle of temperature-drift immunoassay in this system is explained as follows: The frequency of the external reference signal is fref (Unknown, may change slowly over time and with varying environments), the internal DDS output signal frequency is... fvco If the preset fixed number of pulse counts is N, then the following basic relationship exists: ; Where T1 is the time required for the external reference signal to generate N pulses, and T2 is the time required for the internal DDS signal to generate N pulses.
[0036] The judgment criteria are: T1 = T2 fref = fvco (Same frequency, target state); T1>T2 fref < fvco (Internal frequency is too high and needs to be reduced); T1 <T2 fref > fvco (Internal frequency is too low and needs to be increased).
[0037] In this embodiment, time measurement is quantized using the FPGA's internal high-frequency clock. Let the system clock frequency be... fclk The clock period is Tclk = 1 / fclk The system time measurement resolution is: δT = Tclk = 1 / fclk In this embodiment, δT can be used as a set threshold ΔTth; the time measurement value (clock cycle count) is defined as: ; ; Comparing T1 and T2 is equivalent to comparing M1 and M2.
[0038] Mathematical proof of the immunity of temperature drift: Let the DDS frequency control word be F. TW If the phase accumulator has a bit width of M, then the DDS output frequency is: ; The time T2 required for the internal DDS signal to generate N pulses is: ; The time is measured using the system clock count value M2 as follows: ; As can be seen, the system clock frequency in the expression for M2 fclk They were completely taken away.
[0039] Similarly, the time measurement value M1 of the external reference signal is: ; When the system reaches steady state, the closed-loop control ensures that |T1 - T2| ≤ δT, meaning that in the ideal case, M1 = M2. Substituting this into the expression: ; Cancel N on both sides simultaneously: ; Right now: ; F TW Substitute back into the DDS output frequency formula: ; From the above derivation, it can be concluded that in steady state... fvco = fref The result is exactly true. Throughout the derivation, the system clock frequency... fclk It is eliminated in the expression of M2, and the final result contains no such expression. fclk Therefore, regardless of the temperature drift of the crystal oscillator (i.e., ... fclk (Regardless of how it changes), as long as the measurement clock and the DDS clock are from the same source, the steady-state accuracy of the system will not be affected.
[0040] Furthermore, to improve the convergence speed while ensuring steady-state accuracy, this invention employs an adaptive step control strategy to adjust F. TW ,as follows: Define normalized frequency offset estimation: ; Step size ΔF TW Adaptive adjustment based on frequency difference: ; in Δlarge, Δmedium, Δsmall, θ high and θ low All are preset values, ΔFTW is a step size dynamically selected according to the magnitude of |M1-M2|.
[0041] This strategy achieves optimized control of "fast capture via coarse adjustment and stable locking via fine adjustment".
[0042] Embodiment 2: As shown in Figure 2 the figure, a frequency self-following control method for a radio frequency power supply is based on the system described in Embodiment 1, and includes the following steps: In S1, an external reference sine signal Sref(t) is received and converted into a first square wave pulse sequence by a first comparator.
[0043] In S2, an internal sine signal Svco(t) is generated by a DDS module, and converted into a second square wave pulse sequence by a second comparator. The first comparator and the second comparator are two comparison channels of a dual-channel comparator.
[0044] In S3, a fixed number of pulse counts N is set, and a dual-channel time measurement unit is used to respectively measure the time T1 required for the first square wave pulse sequence to generate N pulses, and the time T2 required for the second square wave pulse sequence to generate N pulses.
[0045] In S4, the time T1 and the time T2 obtained in step S3 are compared. If |T1 - T2| >ΔTth and T1>T2, it is determined that the external reference frequency fref is lower than the internal DDS output frequency fvco , and the current DDS frequency control word F TW is decreased to reduce the internal DDS output frequency fvco ; if |T1 - T2| >ΔTth and T1<T2, it is determined that the external reference frequency fref is higher than the internal DDS output frequency fvco , and the current DDS frequency control word F TW is increased to raise the internal DDS output frequency fvco ; if |T1 - T2| ≤ΔTth, the current frequency control word remains unchanged; ΔTth is a set threshold.
[0046] Further, the time T1 and the time T2 are quantized by using a system high-frequency clock, and the quantized time measurement values are respectively M1 = T1 / Tclk and M2 = T2 / Tclk, where Tclk = 1 / fclk is the system clock period, fclk is the system clock frequency; comparing T1 and T2 is replaced by comparing M1 and M2. By implementing time quantization and comparison in the digital domain, the influence of analog device drift on comparison accuracy is eliminated, and the digital logic implementation is simplified at the same time.
[0047] Furthermore, the frequency control word F TW The adjustment step size is adaptively selected based on the magnitude of |T1 - T2|| or |M1 - M2|. When |T1 - T2|| or |M1 - M2| is large, a large step size is selected to speed up the convergence speed. When |T1 - T2|| or |M1 - M2| is small, a small step size is selected to ensure steady-state accuracy.
[0048] Technical effect: By adaptively adjusting the step size, a phased optimization control of "coarse adjustment and fast acquisition, fine adjustment and stable locking" is achieved, which takes into account both the dynamic response speed and steady-state accuracy of the system.
[0049] S5. Repeat steps S3 to S4 until |T1 - T2| ≤ ΔTth, at which point the system achieves synchronous output.
[0050] Furthermore, when |T1 - T2| ≤ ΔTth or |M1 - M2| ≤ ΔMth is satisfied for multiple consecutive measurement cycles, the system is determined to enter a locked state, and |T1 - T2| or |M1 - M2| is continuously monitored in the locked state. If |T1 - T2| ≥ ΔTunlock or |M1 - M2| ≥ ΔMunlock is detected for multiple consecutive measurement cycles in the locked state, the system is determined to have lost lock and steps S3 to S5 are automatically re-executed. Through multi-cycle continuous lock determination and lock loss determination with hysteresis, the locking stability of the system in noisy environments is improved, avoiding false locking and false lock loss.
[0051] Example 3: The effectiveness of the frequency self-following method described in this invention was verified using an RF power supply operating in the 13.56MHz industrial frequency band.
[0052] System Configuration: The external reference frequency is set to 13.56MHz, which is a standard industrial frequency band. It is provided by a high-precision signal source and its own frequency error is less than 0.1Hz. It serves as the reference for this embodiment.
[0053] The system clock frequency is 50MHz, generated by frequency multiplication of the onboard crystal oscillator by the FPGA's internal phase-locked loop (PLL). A standard crystal oscillator is used as the clock source, with a temperature drift coefficient of approximately ±50ppm, requiring no temperature compensation. The corresponding clock period is 20ns, which determines the basic resolution of the time measurement.
[0054] The pulse counter has a fixed pulse count N of 65536, which is an integer power of 2. This facilitates digital logic implementation while balancing measurement accuracy and response speed.
[0055] The DDS phase accumulator has a bit width of 48 bits, which ensures that the fine adjustment capability of the frequency control word is far superior to the target accuracy of this invention.
[0056] The dual comparator uses the ADCMP602 dual high-speed comparator. This device is packaged in a dual package, with both comparators integrated into the same chip. It has symmetrical propagation delay characteristics with a delay time of less than 2.5ns, which can ensure the relative accuracy of the pulse edges of the two channels.
[0057] The two thresholds for adaptive step control are set to 100 and 10 respectively, and the step size is preset to three levels: 32, 8 and 1, which correspond to three working modes: fast acquisition of large frequency difference, smooth convergence of medium frequency difference and fine adjustment of small frequency difference.
[0058] Workflow: 1. System Power-On and FPGA Configuration Loading: After the system powers on, the FPGA completes the loading and configuration of the logic circuits. The configuration includes the frequency self-following master control logic, DDS phase accumulator configuration, dual-channel pulse counter configuration, time counter configuration, adaptive step control logic, and lock judgment logic. After the configuration loading is completed, each functional module inside the FPGA enters a standby state.
[0059] 2. DDS Initial Frequency Setting: The FPGA writes an initial frequency control word to the DDS module, outputting a frequency of 13.56MHz, making the DDS output frequency close to the target frequency of the external reference signal. The DDS module then outputs a sinusoidal signal Svco(t), which, after being shaped by the second comparator, serves as an internal feedback pulse sequence for subsequent measurements.
[0060] 3. Counter and Status Flag Reset: The system clears the external reference pulse counter and the internal DDS pulse counter; clears both time counters; clears the lock status flag, indicating that the system has not yet entered the same-frequency lock state; and clears the iteration count counter. Simultaneously, the relevant parameters for adaptive step control are initialized, with the large step size (32), medium step size (8), small step size (1), and discrimination thresholds (100 and 10) all written to their respective registers. At this point, system initialization is complete, and the system enters the ready state.
[0061] 4. External Reference Signal Detection and Measurement Startup: The system continuously monitors the external reference signal input module to detect whether a valid sine wave signal is input. When the external reference signal amplitude is stable and the frequency is within the valid range, the system determines that the reference signal is valid. At this time, the system simultaneously starts two independent measurement processes: the first process counts the external reference square wave pulse sequence shaped by the first comparator, and the second process counts the internal DDS square wave pulse sequence shaped by the second comparator. The two measurements share the same system clock source to ensure the consistency of the time base.
[0062] 5. First Measurement and Time Latching: The external reference sine wave signal Sref(t) is shaped into a square wave pulse sequence by the first high-speed comparator. A pulse counter begins counting the rising edges of this square wave pulse sequence one by one. Simultaneously, a time counter begins accumulating the system clock cycle, with each clock cycle being 20 nanoseconds. When the pulse count reaches the preset value of 65536, the pulse counter automatically stops and triggers the time counter latching operation. At this time, the current value of the time counter is latched as M1, which represents the time elapsed for the external reference signal to generate 65536 pulses. After the first measurement is completed, the system marks it as complete and waits for the second measurement to complete.
[0063] 6. Second Measurement and Time Latching: The sinusoidal signal Svco(t) output from the internal DDS module is shaped into a square wave pulse sequence by a second high-speed comparator. A pulse counter begins counting the rising edges of this square wave pulse sequence one by one, while a time counter increments by the same system clock. When the pulse count reaches the preset value of 65536, the pulse counter automatically stops and triggers a time counter latching operation. At this point, the current value of the time counter is latched as M2, which represents the time elapsed for the internal DDS signal to generate 65536 pulses. After the second measurement is completed, the system marks it as complete. Once both measurements are complete, the system proceeds to the next processing step.
[0064] 7. Time Difference Calculation and Frequency Deviation Determination: The system reads the latched values M1 and M2 and calculates the difference ΔM = M1 - M2. The sign and magnitude of this difference reflect the frequency deviation relationship between the external reference signal and the internal DDS signal.
[0065] If ΔM is greater than zero, it indicates that the time required for the external reference to generate 65536 pulses is longer. According to the relationship T = N / f, the longer the time, the lower the frequency. Therefore, it is determined that the external reference frequency is lower than the internal DDS output frequency, that is, the internal frequency is too high and needs to be reduced.
[0066] If ΔM is less than zero, it indicates that the time required for the external reference to generate 65536 pulses is shorter. Therefore, it is determined that the external reference frequency is higher than the internal DDS output frequency, that is, the internal frequency is too low and needs to be increased.
[0067] If ΔM equals zero, it indicates that the two paths have the same time. According to T = N / f, the two paths have the same frequency. The system is already in an ideal state of synchronized frequency and no adjustment is needed.
[0068] 8. Adaptive Step Selection: Based on the absolute value of ΔM calculated in step S7, the system dynamically selects the step size for this frequency adjustment. This adaptive strategy aims to balance both rapid acquisition and fine-grained locking.
[0069] When |ΔM|>100, the frequency difference is considered large, and the system is in the fast acquisition phase. A large step size of 32 is selected. This step size allows the DDS output frequency to change significantly in a single adjustment, effectively narrowing the frequency gap.
[0070] When 10 < |ΔM| ≤ 100, the frequency difference is considered moderate, and the system is in a moderate convergence phase. A medium step size of 8 is selected. This step size allows the frequency to gradually approach the target, avoiding overshoot.
[0071] When 1 < |ΔM| ≤ 10, the frequency difference is considered small, and the system is in the fine-tuning stage, so a small step size of 1 is selected. This step size enables fine-tuning of the frequency, ensuring the final convergence accuracy.
[0072] When |ΔM| ≤ 1 or even |ΔM| = 0, the system is already in the same frequency state, the step size is chosen to be zero, and the current state remains unchanged.
[0073] 9. Frequency Control Word Update and DDS Output Adjustment: Based on the deviation direction determined in process 7 and the step size selected in process 8, the system performs a frequency control word update operation. If ΔM is greater than zero (internal frequency too high), a subtraction update is performed, subtracting the selected step size from the current frequency control word to lower the DDS output frequency; if ΔM is less than zero (internal frequency too low), an addition update is performed, adding the selected step size to the current frequency control word to increase the DDS output frequency; if ΔM equals zero (frequency equal), the frequency control word remains unchanged. The updated frequency control word is immediately written to the DDS phase accumulator, and the DDS output frequency changes continuously accordingly without frequency jumps or phase discontinuities.
[0074] 10. Convergence Judgment and Lock-in Maintenance: After the system completes one frequency adjustment, it is determined whether the convergence condition is met. The convergence condition is that |ΔM| ≤ 1 for three consecutive measurement cycles.
[0075] If the convergence condition is met, the system enters a locked state, setting the locked state flag to a high level for external systems to read. In the locked state, the system continuously monitors the ΔM value, calculating it once per measurement cycle. If the absolute value of ΔM remains less than or equal to 1, the system maintains the locked state and holds the current frequency control word.
[0076] If |ΔM| ≥ 3 is detected for two consecutive measurement cycles while in the locked state, the system determines that the lock has been lost, clears the lock status flag, and automatically returns to process 4 to restart the measurement and adjustment process. If the convergence condition has not yet been met, the system returns to process 4 and begins the next round of measurement, comparison, and adjustment iterations.
[0077] In this embodiment, the single measurement period is: T2 = N / fvcoThe lock time is approximately 4.83 ms (13.56MHz, N=65536), typically 3-5 measurement cycles, i.e., <25ms, which is far superior to the hundreds of milliseconds to seconds of lock time of traditional PLLs. During long-term operation, even if the crystal oscillator frequency drifts due to temperature changes, the system clock frequencies in the M2 expression cancel each other out, and the lock state is not affected by the clock drift. The system can adaptively maintain frequency synchronization without manual intervention or periodic calibration.
[0078] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages: 1. Completely immune to crystal oscillator temperature drift: The equation for steady-state output frequency does not contain any system clock frequency term. Even if the crystal oscillator drifts by tens of kHz across the entire temperature range, the steady-state synchronization accuracy remains unaffected. Ordinary ±50ppm crystal oscillators can be used to achieve long-term frequency stability exceeding that of isothermal crystal oscillators. No temperature compensation, no isothermal control, and no periodic calibration are required, significantly reducing system cost and complexity.
[0079] 2. High precision: The frequency synchronization error can be stably controlled within 12Hz, and under typical operating conditions it is better than 10Hz, which is far superior to the hundred-Hz level of traditional phase-locked loop solutions.
[0080] 3. Rapid synchronization: The single measurement cycle is approximately 4.83ms (13.56MHz, N=65536), and the lock time is typically 3 to 5 measurement cycles, i.e. less than 25ms, which is far superior to the hundreds of milliseconds to seconds of lock time of traditional phase-locked loops.
[0081] 4. Completely decoupled from RF power and load: The core comparison quantity is the time required to generate a fixed number of pulses. This quantity is only related to the frequency and is completely independent of parameters such as signal amplitude, RF power, and load impedance. The accuracy is consistent under low-power and high-power conditions. The accuracy is not affected during the matching process, and changes in plasma state do not introduce frequency errors.
[0082] 5. Full closed-loop digital domain with no analog degradation: All functions are implemented in the FPGA digital domain, with no nonlinear analog devices, no loop filter parameter drift, and no charge pump leakage current issues, making it easy to integrate, debug, maintain, and upgrade.
[0083] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. A frequency self-following control system for radio frequency power supplies, characterized in that, include: An external reference signal input module is used to receive an external reference sinusoidal signal as a reference source for frequency following. The DDS module is used to generate an internally adjustable sine wave signal, and its output frequency is controlled by the frequency control word F. TW Decide; A dual-channel comparator includes a first comparator and a second comparator, wherein the first comparator shapes the external reference sine wave signal into a first square wave pulse sequence, and the second comparator shapes the internal sine wave signal into a second square wave pulse sequence; A pulse counter is used to set a fixed number of pulse counts N, and to count the first square wave pulse sequence and the second square wave pulse sequence respectively; A dual-channel time measurement unit is used to measure, based on the system's high-frequency clock, the time T1 required for the first square wave pulse sequence to generate N pulses, and the time T2 required for the second square wave pulse sequence to generate N pulses, respectively. A closed-loop feedback control unit is used to dynamically adjust the frequency control word F of the DDS module based on the difference between time T1 and time T2. TW This forms a negative feedback closed loop, making the difference between time T1 and time T2 less than a set threshold, thereby achieving synchronous output.
2. The frequency self-following control system according to claim 1, characterized in that: The system clock of the DDS module and the time measurement clock of the dual-channel time measurement unit use the same clock source, which is selected from any one of a common crystal oscillator, a temperature-compensated crystal oscillator, or a temperature-controlled crystal oscillator.
3. The frequency self-following control system according to claim 1, characterized in that: The times T1 and T2 measured by the dual-channel time measurement unit are quantized in units of system clock cycles Tclk, where Tclk = 1 / fclk , fclk The system's high-frequency clock frequency is used to obtain time measurements M1 = T1 / Tclk and M2 = T2 / Tclk. The closed-loop feedback control unit compares M1 and M2 instead of comparing T1 and T2.
4. The frequency self-following control system according to claim 3, characterized in that: The closed-loop feedback control unit updates the frequency control word F using adaptive step control. TW The updated formula is: ； F TW (k+1) = F TW (k) ± ΔF TW ; in Δlarge, Δmedium, Δsmall, θ high and θ low All are preset values, ΔF TW The step size is dynamically selected based on the size of |M1-M2|.
5. The frequency self-following control system according to claim 3, characterized in that: The closed-loop feedback control unit is also used to determine the locking state; when |M1-M2| ≤ ΔMth is satisfied for K consecutive measurement cycles, the system is determined to enter the locking state and the locking state flag is set, where ΔMth is a preset locking threshold and K is an integer greater than 1.
6. The frequency self-following control system according to claim 5, characterized in that: The closed-loop feedback control unit continuously monitors |M1-M2| in the locked state. When |M1-M2| ≥ ΔMunlock is detected for L consecutive measurement cycles, the system is determined to be unlocked, the locked state flag is cleared, and the measurement and adjustment process is automatically restarted, where ΔMunlock > ΔMth and L is an integer greater than or equal to 1.
7. A frequency self-following control method for radio frequency power supplies, employing the frequency self-following control system as described in any one of claims 1-6, comprising the following steps: S1 receives an external reference sinusoidal signal, which is converted into a first square wave pulse sequence by the first comparator; S2, an internal sine wave signal is generated by the DDS module and converted into a second square wave pulse sequence by the second comparator. The first comparator and the second comparator are the two comparison channels of the dual comparator. S3, set a fixed number of pulse counts N, and measure the time T1 required for the first square wave pulse sequence to generate N pulses and the time T2 required for the second square wave pulse sequence to generate N pulses respectively through the dual-channel time measurement unit; S4. Compare the time T1 obtained in step S3 with the time T2. If |T1 - T2| > ΔTth and T1 > T2, then determine the external reference frequency. fref Lower than the internal DDS output frequency fvco The current DDS frequency control word F TW Reduce to lower the internal DDS output frequency fvco If |T1 - T2| > ΔTth and T1 < T2, then determine the external reference frequency. fref Higher than the internal DDS output frequency fvco The current DDS frequency control word F TW Increase to improve the internal DDS output frequency fvco If |T1 - T2| ≤ ΔTth, then maintain the current frequency control word F. TW Unchanged; ΔTth is the set threshold; S5. Repeat steps S3 to S4 until |T1 - T2| ≤ ΔTth, at which point the system achieves synchronous output.
8. The frequency self-following control method according to claim 7, characterized in that: In step S4, time T1 and time T2 are quantized using the system's high-frequency clock, and the quantized time measurements are M1 = T1 / Tclk and M2 = T2 / Tclk, respectively, where Tclk = 1 / fclk For the system clock cycle, fclk The system clock frequency is used; the comparison of times T1 and T2 is replaced by the comparison of M1 and M2.
9. The frequency self-following control method according to claim 8, characterized in that: In step S4, the frequency control word F TW The adjustment step size is adaptively selected based on the magnitude of |T1 - T2| or |M1 - M2|. When |T1 - T2|| or |M1 - M2| is large, a large step size is selected to speed up the convergence speed. When |T1 - T2|| or |M1 - M2| is small, a small step size is selected to ensure steady-state accuracy.
10. The frequency self-following control method according to claim 9, characterized in that: In step S5, when |T1 - T2| ≤ ΔTth or |M1 - M2| ≤ ΔMth is satisfied for multiple consecutive measurement cycles, the system is determined to enter a locked state, and |T1 - T2| or |M1 - M2| is continuously monitored in the locked state; if |T1 - T2| ≥ ΔTunlock or |M1 - M2| ≥ ΔMunlock is detected for multiple consecutive measurement cycles in the locked state, the system is determined to be unlocked and steps S3 to S5 are automatically re-executed.