A programmable frequency division clock generation circuit and method

Abstract

This application discloses a programmable frequency divider clock generation circuit and method. The circuit includes: a signal conditioning module, whose input terminal receives a high-frequency clock signal and whose output terminal outputs a conditioned analog signal; a voltage comparison module, whose first input terminal is connected to the output terminal of the signal conditioning module, whose second input terminal is connected to an adjustable reference voltage source, and whose output terminal outputs a square wave pulse signal; and a digital synchronous sampling module, including a cascaded first D flip-flop and a second D flip-flop; the clock input terminal of the first D flip-flop is connected to the output terminal of the voltage comparison module, its data input terminal is connected to its own inverting output terminal, and its positive output terminal outputs an intermediate clock signal; the clock input terminal of the second D flip-flop is connected to the intermediate clock signal, its data input terminal receives an external system clock signal, and its output terminal outputs a measurement clock signal. This application achieves software-adjustable comparison thresholds, capable of adapting to input signals of different amplitudes.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal circuit technology, and particularly relates to a programmable frequency divider clock generation circuit and method. Background Technology

[0002] In embedded systems, communication equipment, testing instruments, and IoT terminals, it is often necessary to divide a high-frequency reference clock (such as a crystal oscillator output or an external clock source) into a low-frequency clock signal for microcontrollers (MCUs) to perform operations such as timing capture, pulse counting, synchronous sampling, or low-power wake-up. As electronic devices become increasingly complex, multiple frequency domains often exist simultaneously in a system, placing differentiated requirements on the frequency, duty cycle, and phase relationship of the clock signal. Therefore, high-frequency to low-frequency clock generation circuits have become one of the fundamental functional modules in these systems.

[0003] Currently, high-frequency clock division technology is mainly divided into two categories: pure digital division schemes and analog-digital hybrid division schemes. Pure digital division schemes are usually based on digital counters or phase-locked loops (PLLs). Their division ratio is programmable and the output frequency stability is high. However, this scheme relies entirely on digital logic resources, requiring dedicated timer peripherals or a large number of logic gates in MCUs or FPGAs, resulting in significant hardware overhead. Furthermore, the dynamic power consumption caused by counter flipping is not negligible when the input frequency is high. Traditional analog division schemes use an "RC filter + comparator" structure. They use resistors and capacitors to form a low-pass filter to convert a high-frequency square wave into an approximate triangular wave or sine wave, and then use a comparator to shape it into a low-frequency square wave. This scheme does not require digital logic resources, but the comparison threshold is usually set by a fixed resistor voltage divider network, and once the circuit is determined, it cannot be adjusted online.

[0004] However, purely digital frequency divider schemes heavily rely on the hardware resources of the MCU's internal timers or external counters, making them difficult to deploy flexibly in resource-constrained, low-cost microcontroller systems. Furthermore, directly introducing high-frequency signals into MCU pins can easily cause sampling metastability and EMI (electromagnetic interference) problems. Traditional analog frequency divider schemes have fixed comparison thresholds, making them unable to adapt to input clock signals of varying amplitudes. When the input signal amplitude fluctuates or the level standard changes, the division point drifts, distorting the output duty cycle, and in severe cases, even failing to trigger the comparator toggles. In addition, the RC parameters are fixed once soldered, and the division frequency cannot be adjusted programmatically, lacking adaptability to various scenarios. Summary of the Invention

[0005] In view of this, the present invention provides a programmable frequency divider clock generation circuit and method, which solves the problem that the comparison threshold is fixed and cannot be adjusted in existing analog frequency divider schemes and cannot adapt to input signals of different amplitudes.

[0006] To achieve the above objectives, in a first aspect, the technical solution of the present invention to solve the technical problem is to provide a programmable frequency divider clock generation circuit, comprising: a signal conditioning module, whose input terminal is connected to a high-frequency clock signal and whose output terminal outputs a conditioned analog signal; a voltage comparison module, whose first input terminal is connected to the output terminal of the signal conditioning module, whose second input terminal is connected to an adjustable reference voltage source, and whose output terminal outputs a square wave pulse signal; and a digital synchronous sampling module, comprising a cascaded first D flip-flop and a second D flip-flop; the clock input terminal of the first D flip-flop is connected to the output terminal of the voltage comparison module, its data input terminal is connected to its own inverting output terminal, and its positive output terminal outputs an intermediate clock signal; the clock input terminal of the second D flip-flop is connected to the intermediate clock signal, its data input terminal receives an external system clock signal, and its output terminal outputs a measurement clock signal.

[0007] In one possible embodiment, the signal conditioning module includes: a first capacitor C1 connected between the input terminal of the high-frequency clock signal and the first node; a first resistor R1 connected between the first node and ground; a second resistor R2 connected between the first node and the second node; a second capacitor C2 connected between the second node and ground; a third resistor R3 connected between an external bias voltage terminal and the second node; and a fourth resistor R4 connected between the second node and ground.

[0008] In one possible embodiment, the voltage comparison module includes an operational amplifier, the inverting input of which is connected to the output of the signal conditioning module, and the non-inverting input of which is connected to the adjustable reference voltage source; the adjustable reference voltage source includes an external digital-to-analog converter and a fifth resistor R5, and the first output of the external digital-to-analog converter is connected to the non-inverting input via the fifth resistor R5.

[0009] In one possible embodiment, the voltage comparison module further includes a sixth resistor R6, which is connected between the output terminal and the non-inverting input terminal of the operational amplifier.

[0010] In one possible embodiment, the set and reset terminals of the first D flip-flop are both connected to a high-level power supply; the set and reset terminals of the second D flip-flop are both connected to a high-level power supply.

[0011] In one possible embodiment, the measurement clock signal is a level signal output by the external system clock signal after being synchronously latched under the edge triggering of the intermediate clock signal.

[0012] Secondly, the present invention provides a programmable frequency division clock generation method, comprising: performing DC blocking, filtering, and impedance matching processing on a high-frequency input clock signal to obtain a conditioned analog signal; comparing the conditioned analog signal with a reference voltage to generate a square wave pulse signal; using the edge of the square wave pulse signal as a trigger clock to drive a first D flip-flop to perform frequency division by two according to its own inverted output feedback to obtain an intermediate clock signal; using the edge of the intermediate clock signal as a trigger clock to drive a second D flip-flop to sample an external system clock signal and output a measurement clock signal.

[0013] In one possible embodiment, the reference voltage is provided by the output of an external DAC.

[0014] In one possible embodiment, the conditioned analog signal is compared with a reference voltage, and hysteresis comparison characteristics are introduced through a positive feedback network to suppress jitter when the signal flips.

[0015] In one possible embodiment, after the DC blocking process is performed on the high-frequency input clock signal, a DC bias voltage is injected into the signal path where the high-frequency input clock signal is located through an external bias voltage terminal.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: The signal conditioning module performs DC blocking, filtering, and bias settings on the high-frequency input clock, ensuring that the analog signal entering the comparator has good signal quality and a suitable DC operating point. By using an external DAC to provide a programmable reference voltage, the comparison threshold can be dynamically adjusted in software, allowing the circuit to flexibly adapt to input signals with different amplitudes and level standards, overcoming the poor adaptability of traditional fixed-threshold comparators. By introducing positive feedback hysteresis comparison characteristics, noise jitter of the input signal near the threshold is effectively suppressed, ensuring the edge steepness and phase stability of the output square wave pulse. A frequency divider circuit is constructed using the first D flip-flop to divide and reduce the frequency of the high-frequency square wave output by the comparator, reducing the processing frequency of subsequent digital logic. The frequency-divided signal is synchronously latched by the second D flip-flop, eliminating the metastability risk when asynchronous signals are transmitted across clock domains, ensuring that the final output measurement clock signal has a stable timing relationship synchronized with the system clock. The entire circuit scheme requires only a few resistor and capacitor components, one operational amplifier, and two D flip-flops. It does not require the use of internal timer resources of the MCU or logic resources of the FPGA, resulting in extremely low hardware costs. It provides an embedded system with a high-frequency to low-frequency clock generation scheme that combines high precision, low power consumption, and software programmability. Attached Figure Description

[0017] Figure 1A schematic diagram of the topology of a programmable frequency divider clock generation circuit provided in an embodiment of this application; Figure 2 This is a flowchart illustrating the steps of a programmable frequency divider clock generation method provided in an embodiment of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that all directional indications in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a specific posture. If the specific posture changes, the directional indications will also change accordingly.

[0020] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, the user should consider such a combination of technical solutions to be non-existent and not within the scope of protection claimed in this application.

[0021] like Figure 1 As shown, the programmable frequency divider clock generation circuit provided in the first embodiment of the present invention includes a signal conditioning module, a voltage comparison module, and a digital synchronous sampling module.

[0022] The input of the signal conditioning module is connected to a high-frequency clock signal, and the output is a conditioned analog signal. The first input terminal of the voltage comparison module is connected to the output terminal of the signal conditioning module, the second input terminal is connected to an adjustable reference voltage source, and the output terminal outputs a square wave pulse signal. The digital synchronous sampling module includes a cascaded first D flip-flop and a second D flip-flop; The clock input of the first D flip-flop is connected to the output of the voltage comparator module, the data input is connected to its own inverting output, and the positive output outputs the intermediate clock signal. The clock input of the second D flip-flop is connected to the intermediate clock signal, the data input receives the external system clock signal, and the output outputs the measurement clock signal.

[0023] The signal conditioning module preprocesses the input high-frequency clock signal, including removing DC components, filtering high-frequency noise, and performing impedance matching to ensure the comparator can stably identify the signal amplitude. The high-frequency clock signal first undergoes DC blocking to remove its DC bias component, preventing DC offset from affecting the comparator's switching threshold. It then undergoes low-pass filtering to remove high-frequency glitches and spikes, smoothing the signal waveform. Simultaneously, a bias network adjusts the signal's DC operating point to a suitable position within the comparator's input common-mode range. The voltage comparator module receives the conditioned analog signal and compares it to an adjustable reference voltage. When the amplitude of the conditioned analog signal is higher than the reference voltage, the comparator outputs a high level; when the amplitude is lower than the reference voltage, the comparator outputs a low level. This comparison converts the analog signal into a digitally recognizable square wave pulse signal. The voltage comparator module uses an operational amplifier to construct the comparator structure, which features fast response, high input impedance, and adaptability to input signals of different frequencies and amplitudes. The digital synchronous sampling module is used to convert the square wave pulse signal output by the comparator into a measurement clock signal that is synchronized with the system clock domain.

[0024] The first D flip-flop receives the square wave pulse signal output by the comparator at its clock input, and its data input is connected to the feedback signal of its own inverting output, forming a frequency divider structure. Each rising edge of the square wave pulse signal triggers the first D flip-flop to flip once, reducing the frequency of the intermediate clock signal output from the positive output to half the frequency of the square wave output by the comparator.

[0025] The second D flip-flop receives the intermediate clock signal at its clock input and the external system clock signal at its data input. Each rising edge of the intermediate clock signal triggers the second D flip-flop to sample and latch the current level state of the external system clock signal. The sampled level signal is output through the output of the second D flip-flop as the final measurement clock signal.

[0026] The circuit structure described above achieves a complete signal chain, from analog comparison and shaping of the high-frequency input clock signal, to first-stage frequency division downsampling, and then synchronous latching before outputting to the MCU (Microcontroller Unit) measurement interface. This circuit architecture requires only a few discrete components, eliminating the need for MCU internal timer resources or complex programmable logic devices such as FPGAs (Field-Programmable Gate Arrays). Through the collaborative work of the analog front-end and digital logic, reliable conversion from high-frequency clock to low-frequency measurement clock is achieved, significantly reducing system hardware costs and design complexity, while simultaneously improving signal stability during asynchronous cross-clock domain transmission.

[0027] In one possible implementation, the signal conditioning module includes a first capacitor C1, a first resistor R1, a second resistor R2, a second capacitor C2, a third resistor R3, and a fourth resistor R4. The first capacitor C1 is connected between the input terminal of the high-frequency clock signal and the first node; the first resistor R1 is connected between the first node and ground; the second resistor R2 is connected between the first node and the second node; the second capacitor C2 is connected between the second node and ground; the third resistor R3 is connected between an external bias voltage terminal (DAC_SET_B) and the second node; and the fourth resistor R4 is connected between the second node and ground.

[0028] The first capacitor C1 is connected in series in the input path of the high-frequency clock signal. Its function is to block the DC component of the input signal and only allow the AC component of the signal to enter the subsequent circuit.

[0029] The first resistor R1 is connected between the first node and ground. Its function is to provide a DC bias path to ensure that the input signal has a definite DC potential reference point when there is no signal input, thus avoiding the signal path from floating.

[0030] The second resistor R2 is connected between the first node and the second node. Its function is as a current-limiting resistor to limit the signal current entering the subsequent low-pass filter network. It also forms an RC low-pass filter network together with the second capacitor C2.

[0031] The second capacitor C2 is connected between the second node and ground, and together with the second resistor R2, they form a first-order low-pass filter to filter out high-frequency noise components in the high-frequency input clock signal, making the signal waveform smoother and reducing high-frequency interference at the comparator input.

[0032] The third resistor R3 is connected between the external bias voltage terminal and the second node, and the fourth resistor R4 is connected between the second node and ground. The external bias voltage terminal outputs an adjustable DC voltage, which, through a voltage divider network formed by the third resistor R3 and the fourth resistor R4, creates a stable DC bias voltage at the second node. This DC bias voltage is superimposed on the input signal path, raising or adjusting the DC operating point of the conditioned analog signal to a suitable level range.

[0033] The cutoff frequency of the aforementioned RC network can be selected and optimized according to the frequency range of the input high-frequency clock signal to ensure that high-frequency noise is effectively filtered out without excessive attenuation of the target frequency signal. The RC network, consisting of the first capacitor C1, the first resistors R1 to R4, and the second capacitor C2, achieves DC component isolation, high-frequency noise filtering, and DC operating point setting of the high-frequency input clock signal. This ensures that the analog signal entering the comparator input has good signal quality and a suitable DC level, providing a reliable signal foundation for the accurate switching of the comparator.

[0034] In one possible implementation, the voltage comparison module includes an operational amplifier, the inverting input of which is connected to the output of the signal conditioning module, and the non-inverting input of which is connected to an adjustable reference voltage source. The adjustable reference voltage source includes an external digital-to-analog converter and a fifth resistor R5. The first output of the external digital-to-analog converter (DAC_SET_A) is connected to the non-inverting input via the fifth resistor R5.

[0035] The core component of the voltage comparator module is an operational amplifier, which operates in open-loop or high-gain mode as a voltage comparator. The inverting input of the operational amplifier serves as the first input of the voltage comparator module, connected to the output of the signal conditioning module to receive the conditioned analog signal; the non-inverting input of the operational amplifier serves as the second input of the voltage comparator module, connected to an adjustable reference voltage source to receive an adjustable reference voltage.

[0036] The operational amplifier compares the analog signal voltage at the inverting input with the reference voltage at the non-inverting input in real time: when the voltage at the inverting input is higher than the reference voltage at the non-inverting input, the operational amplifier outputs a low level; when the voltage at the inverting input is lower than the reference voltage at the non-inverting input, the operational amplifier outputs a high level.

[0037] Through this comparison operation, the operational amplifier converts the analog signal into a digital square wave pulse signal. The first output of the external digital-to-analog converter outputs a programmable DC voltage, which is connected to the non-inverting input of the operational amplifier via a fifth resistor, R5. The external digital-to-analog converter's output value is configured by software using an MCU or other controller. Because the output voltage of the digital-to-analog converter can be precisely programmed, the reference voltage at the non-inverting input of the operational amplifier is also precisely set accordingly.

[0038] By changing the output value of the digital-to-analog converter, the comparator's toggle threshold can be flexibly adjusted to adapt to input signals of different amplitudes, or the duty cycle and edge position of the output square wave pulse can be changed. An external digital-to-analog converter converts the digital control word into a corresponding analog voltage, providing the comparator with a flexibly adjustable reference level.

[0039] By using an operational amplifier to build a comparator and combining it with an external DAC (Digital-to-Analog Converter) to provide a programmable reference voltage, the comparison threshold is made software adjustable. This allows the same hardware circuit to adapt to input clock signals with different amplitudes and level standards, improving the circuit's adaptability to different scenarios and its flexibility of use.

[0040] In one possible implementation, the voltage comparison module further includes a sixth resistor R6, which is connected between the output of the operational amplifier and the non-inverting input.

[0041] The sixth resistor, R6, is connected between the output terminal and the non-inverting input terminal of the operational amplifier, forming a positive feedback path. The introduction of this positive feedback resistor causes the reference voltage at the non-inverting input terminal of the operational amplifier to shift by a certain amount when the output state of the operational amplifier changes, thus creating a hysteresis interval in the transfer characteristics of the comparator.

[0042] Hysteresis comparator characteristics refer to the following: when the input signal voltage rises from low to high, the comparator's switching threshold is higher than the nominal value of the reference voltage; when the input signal voltage falls from high to low, the comparator's switching threshold is lower than the nominal value of the reference voltage. The difference between the two switching thresholds is the hysteresis width. This hysteresis width effectively prevents the comparator output from repeatedly and erroneously switching when the input signal changes slowly near the threshold point or when noise jitter exists. When the input signal fluctuates near the threshold point due to noise interference, the comparator output will remain unchanged due to the hysteresis interval until the input signal amplitude exceeds the boundary value of the hysteresis interval before switching occurs.

[0043] The value of the sixth resistor R6 determines the hysteresis width, and in practical applications, it can be reasonably selected according to the noise level and amplitude variation range of the input signal. In this embodiment, by connecting the sixth resistor R6 across the output terminal and the non-inverting input terminal of the operational amplifier to form a positive feedback hysteresis comparator, the comparator's anti-interference capability in noisy environments is improved, the output pulse jump caused by signal jitter near the threshold is avoided, and the edge steepness and phase stability of the output square wave pulse are ensured.

[0044] In one possible implementation, the set and reset terminals of the first D flip-flop are both connected to a high-level power supply; the set and reset terminals of the second D flip-flop are both connected to a high-level power supply.

[0045] Both the first and second D flip-flops have a set pin and a reset pin. These two pins are asynchronous control pins used to set the flip-flop output to a high level (set) or a low level (reset), and this operation is not controlled by the clock signal.

[0046] In this embodiment, the set and reset terminals of the first D flip-flop are both connected to a high-level power supply, and the set and reset terminals of the second D flip-flop are also connected to a high-level power supply. For the low-active set and reset terminals, when the pins are pulled high, the set and reset functions are disabled, and the flip-flops will not be abnormally set or reset due to external interference or noise. For the high-active set and reset terminals, they are also connected to a high-level power supply according to the device datasheet to disable them. By connecting both the set and reset terminals to a high-level power supply, these two asynchronous control terminals are in an inactive state. The flip-flops only respond to the edge signal of the clock input terminal to sample and latch the data input terminal, thereby ensuring that the flip-flops work normally according to the expected clock cycle, avoiding malfunctions caused by uncertain levels introduced by floating control terminals, and effectively improving the reliability and consistency of the circuit operation.

[0047] In one possible implementation, the measurement clock signal is a level signal output from an external system clock signal after being synchronously latched by the edge triggering of an intermediate clock signal.

[0048] The second D flip-flop uses an intermediate clock signal as its clock source and an external system clock signal as its data input source. Before the rising edge (or falling edge, depending on the flip-flop type) of the intermediate clock signal arrives, the second D flip-flop does not respond to changes in the external system clock signal. When the edge of the intermediate clock signal arrives, the second D flip-flop quickly samples the current level of the external system clock signal and latches the sampled level value to its output. Until the next edge of the intermediate clock signal arrives, regardless of how the external system clock signal changes, the output of the second D flip-flop maintains the latched level. In other words, the output state of the second D flip-flop indicates whether the external system clock signal is high or low at the moment the edge of the intermediate clock signal occurs.

[0049] This sampling latch operation establishes a definite temporal correspondence between the external system clock signal and the intermediate clock signal, achieving synchronous sampling of the external system clock signal. Even if the external system clock signal is completely asynchronous with respect to the intermediate clock signal, after synchronous latching by the second D flip-flop, its output signal is aligned with the edge of the intermediate clock signal, becoming a stable level signal synchronized with the intermediate clock signal.

[0050] This embodiment uses a second D flip-flop to synchronously sample and latch the external system clock signal under the triggering of the intermediate clock signal edge. This eliminates the metastability risk that may occur when asynchronous signals are transmitted across clock domains, so that the final output measurement clock signal has a stable logic level state and a definite timing relationship, providing a reliable low-frequency measurement clock source for back-end digital systems such as MCUs.

[0051] It should be noted that, in Figure 1 In this circuit, the circuit consisting of capacitor C1, resistor R1, resistor R2, capacitor C2, resistor R3, and resistor R4 constitutes the signal conditioning module; the circuit consisting of operational amplifier, resistor R5, and feedback resistor R6 constitutes the voltage comparison module; and the circuit consisting of the first D flip-flop and the second D flip-flop constitutes the digital synchronous sampling module.

[0052] like Figure 2 As shown, a second embodiment of the present invention provides a programmable frequency divider clock generation method, which includes the following steps: Step S100: The high-frequency input clock signal is subjected to DC blocking, filtering and impedance matching to obtain a conditioned analog signal; The high-frequency input clock signal first enters the signal conditioning path. DC blocking is achieved through a series capacitor, blocking the DC bias component in the input signal and allowing only the AC component to pass, thus preventing DC offset from affecting the switching accuracy of subsequent comparators. Filtering is achieved through an RC low-pass network, using a first-order low-pass filter composed of resistors and capacitors to filter out high-frequency glitches, spikes, and out-of-band noise components in the input signal, smoothing the signal waveform and reducing high-frequency interference at the comparator input. Impedance matching is achieved through a resistor network, matching the impedance of the input signal transmission path to ensure minimal signal reflection during transmission. Simultaneously, voltage dividers or pull-up / pull-down networks are used to adjust the signal's DC operating point to within the common-mode range of the subsequent comparator input. These DC blocking, filtering, and impedance matching processes together constitute the complete signal conditioning process.

[0053] Step S200: The conditioned analog signal is compared with a reference voltage to generate a square wave pulse signal; The analog signal obtained after conditioning in step 100 is fed into the first input terminal of a comparator, and a reference voltage is connected to the second input terminal of the comparator. The comparator compares the instantaneous amplitude of the conditioned analog signal with the reference voltage: when the amplitude of the analog signal is higher than the reference voltage, the comparator outputs a high level; when the amplitude of the analog signal is lower than the reference voltage, the comparator outputs a low level. The high and low level states of the comparator output alternate with the alternation of the input signal amplitude, forming a digital square wave pulse signal. The frequency of this square wave pulse signal is the same as the frequency of the input high-frequency clock signal, and its edge position depends on the intersection point of the analog signal waveform and the reference voltage.

[0054] Step S300: Using the edge of the square wave pulse signal as the trigger clock, drive the first D flip-flop to divide the frequency by two according to its own inverted output feedback to obtain the intermediate clock signal. The square wave pulse signal generated in step S200 is input to the clock input of the first D flip-flop. The data input of the first D flip-flop is connected to its own inverting output. Each rising edge of the square wave pulse signal triggers the first D flip-flop to sample the state of its data input. Since the data input is connected to the inverting output, when the first D flip-flop is triggered, the state of its positive output will flip to the opposite state before triggering. That is, with each clock edge, the output state of the first D flip-flop flips once, so the period of the intermediate clock signal output from its positive output is twice the period of the input square wave pulse signal, and the frequency is half the frequency of the input square wave pulse signal. This intermediate clock signal, as the output of the first D flip-flop, is simultaneously sent to the clock input of the subsequent second D flip-flop.

[0055] Step S400: Using the edge of the intermediate clock signal as the trigger clock, drive the second D flip-flop to sample the external system clock signal and output the measurement clock signal; The intermediate clock signal generated in step S300 is connected to the clock input of the second D flip-flop. The external system clock signal is connected to the data input of the second D flip-flop. Each rising edge of the intermediate clock signal triggers the second D flip-flop to sample the current level of the external system clock signal at its data input and latches the sampled value to the output. Between two adjacent edges of the intermediate clock signal, the output of the second D flip-flop maintains the latched level. The signal at the output of the second D flip-flop is the final measurement clock signal. This measurement clock signal has the same frequency as the intermediate clock signal, and its logic level reflects the sampled value of the external system clock signal at the instant of the intermediate clock signal edge. Through the processing of steps S100 to S400 above, the high-frequency input clock signal is converted into a measurement clock signal with a reduced frequency and synchronized with the system clock domain.

[0056] In one possible implementation, the reference voltage is provided by the output of an external DAC.

[0057] In step S200, the reference voltage used for comparison is provided by the output of an external DAC. The external DAC receives a digital control word from the MCU or controller and converts the digital value into a corresponding analog voltage output. By running a software program, the MCU can dynamically calculate and update the DAC's digital control word according to the amplitude range of the actual input signal, thereby adjusting the analog voltage value output by the DAC in real time.

[0058] The analog voltage is sent directly to the comparator's reference voltage input or buffered via the output terminal, serving as the reference voltage in step S200. Since the DAC's output voltage can be precisely programmed, the comparator's reference voltage is also software-adjustable. In practical applications, when the amplitude of the input high-frequency clock signal changes due to power fluctuations or different signal sources, only the DAC's control word needs to be updated at the software level to adjust the comparison threshold to the optimal position matching the current input signal amplitude, ensuring that the comparator's output always maintains an accurate flipping state.

[0059] This embodiment uses an external DAC to provide a programmable reference voltage, enabling dynamic software adjustment of the comparison threshold. This allows the system to adapt to different input conditions without changing the hardware circuit, significantly improving its adaptability and flexibility.

[0060] In one possible implementation, the conditioned analog signal is compared with a reference voltage, and a hysteresis comparison feature is introduced through a positive feedback network to suppress jitter when the signal flips.

[0061] In step S200, during the comparison of the conditioned analog signal with the reference voltage, the comparator introduces hysteresis comparison characteristics through a positive feedback network connected between its output and non-inverting input. When the comparator output state flips, the positive feedback network feeds back the change at the output to the non-inverting input, causing the effective reference voltage at the non-inverting input to shift with the output state.

[0062] Specifically, when the comparator output transitions from low to high, the feedback signal raises the reference voltage at the non-inverting input by a certain amount; conversely, when the comparator output transitions from high to low, the feedback signal lowers the reference voltage at the non-inverting input by a certain amount. This effect causes the comparator's actual switching threshold to switch between two different voltage values, thus creating a hysteresis interval on the transfer characteristic curve.

[0063] When the input signal fluctuates slightly near the threshold due to noise interference, the comparator's output will not repeatedly toggle with these small fluctuations due to the hysteresis interval. The comparator will only switch its output state when the amplitude of the input signal exceeds the boundary value of the hysteresis interval. The width of the hysteresis interval depends on the feedback coefficient of the positive feedback network.

[0064] This embodiment effectively suppresses the output error caused by noise jitter near the threshold by introducing positive feedback hysteresis comparison characteristics during the comparison process. This results in a clean and steep edge in the generated square wave pulse signal, which improves the anti-interference capability and waveform quality of the output signal.

[0065] In one possible implementation, after the DC blocking process is performed on the high-frequency input clock signal, a DC bias voltage is injected into the signal path where the high-frequency input clock signal is located through an external bias voltage terminal (DAC_SET_B).

[0066] After the high-frequency input clock signal is DC blocked in step S100, a DC bias voltage is injected into the signal path downstream of the DC blocking capacitor through the external bias voltage terminal and the third resistor R3. This external bias voltage terminal is driven by another DAC (or other adjustable DC voltage source) and outputs a programmable DC voltage. This DC voltage, through a voltage divider network formed by the third resistor R3 and the fourth resistor R4, forms a stable DC bias level at the signal node downstream of the DC blocking capacitor. This DC bias level is superimposed on the AC component of the input signal, raising or adjusting the DC operating point of the conditioned analog signal to a potential suitable for the comparator input common-mode range.

[0067] By adjusting the output voltage value of the external bias voltage terminal, the DC bias of the injected signal path can be flexibly controlled, thereby ensuring that the signal waveforms of input signals with different amplitudes and DC characteristics are within the common-mode voltage range of the comparator input after conditioning. This avoids the comparator failing to flip properly or the flipping delay increasing due to the DC operating point of the signal deviating from the linear region of the comparator.

[0068] This embodiment ensures that the DC level of the conditioned analog signal is within the optimal input range of the comparator by injecting a programmable DC bias voltage into the signal path after DC blocking, thus ensuring that the comparator can accurately respond to changes in the amplitude of the input signal.

[0069] The above-mentioned operation of injecting DC bias voltage through an external bias voltage terminal can also be used in conjunction with adjusting the DAC reference voltage. The two can be adjusted independently from two dimensions: the DC operating point of the signal and the comparison flip threshold. This allows the circuit to flexibly adapt to input signals with different DC levels and different AC amplitudes, further broadening the range of applicable input signals and improving the versatility of the system.

[0070] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A programmable frequency divider clock generation circuit, comprising: The signal conditioning module has a high-frequency clock signal input and a conditioned analog signal output. The voltage comparison module has its first input terminal connected to the output terminal of the signal conditioning module, its second input terminal connected to an adjustable reference voltage source, and its output terminal outputting a square wave pulse signal. The digital synchronous sampling module includes a cascaded first D flip-flop and a second D flip-flop; The clock input terminal of the first D flip-flop is connected to the output terminal of the voltage comparison module, the data input terminal is connected to its own inverting output terminal, and the positive output terminal outputs the intermediate clock signal. The clock input of the second D flip-flop is connected to the intermediate clock signal, the data input receives the external system clock signal, and the output outputs the measurement clock signal.

2. The programmable frequency divider clock generation circuit as described in claim 1, characterized in that, The signal conditioning module includes: The first capacitor C1 is connected between the input terminal of the high-frequency clock signal and the first node; The first resistor R1 is connected between the first node and ground; The second resistor R2 is connected between the first node and the second node; The second capacitor C2 is connected between the second node and ground; The third resistor R3 is connected between an external bias voltage terminal and the second node; The fourth resistor R4 is connected between the second node and ground.

3. The programmable frequency divider clock generation circuit as described in claim 1, characterized in that: The voltage comparison module includes an operational amplifier. The inverting input of the operational amplifier is connected to the output of the signal conditioning module, and the non-inverting input of the operational amplifier is connected to the adjustable reference voltage source. The adjustable reference voltage source includes an external digital-to-analog converter and a fifth resistor R5. The first output of the external digital-to-analog converter is connected to the non-inverting input via the fifth resistor R5.

4. The programmable frequency divider clock generation circuit as described in claim 3, characterized in that: The voltage comparison module also includes a sixth resistor R6, which is connected between the output terminal and the non-inverting input terminal of the operational amplifier.

5. The programmable frequency divider clock generation circuit as described in claim 1, characterized in that: The set and reset terminals of the first D flip-flop are both connected to a high-level power supply; the set and reset terminals of the second D flip-flop are both connected to a high-level power supply.

6. The programmable frequency divider clock generation circuit as described in claim 1, characterized in that: The measurement clock signal is the level signal output by the external system clock signal after being synchronously latched under the edge triggering of the intermediate clock signal.

7. A programmable frequency divider clock generation method, characterized in that, include: The high-frequency input clock signal is subjected to DC blocking, filtering, and impedance matching to obtain a conditioned analog signal. The conditioned analog signal is compared with a reference voltage to generate a square wave pulse signal; Using the edge of the square wave pulse signal as the trigger clock, the first D flip-flop is driven to divide the frequency by two according to its own inverted output feedback to obtain the intermediate clock signal. Using the edge of the intermediate clock signal as the trigger clock, the second D flip-flop is driven to sample the external system clock signal and output a measurement clock signal.

8. The programmable frequency divider clock generation method as described in claim 7, characterized in that: The reference voltage is provided by the output of an external DAC.

9. The programmable frequency divider clock generation method as described in claim 7, characterized in that: The conditioned analog signal is compared with a reference voltage, and a hysteresis comparison characteristic is introduced through a positive feedback network to suppress jitter when the signal flips.

10. The programmable frequency divider clock generation method as described in claim 7, characterized in that: After the high-frequency input clock signal is subjected to the DC blocking process, a DC bias voltage is injected into the signal path where the high-frequency input clock signal is located through an external bias voltage terminal.

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