Differential adc driving circuit for sensor

Abstract

This invention discloses a differential ADC driving circuit for sensors, comprising a pre-driver module, a driver module, and an output module arranged in series. The pre-driver module provides a differential input signal to the driver module. The driver module includes an input protection unit, a first offset adjustment unit, and a second offset adjustment unit. The output of the pre-driver module is sent to the input protection unit, where it undergoes noise reduction and interference suppression through a three-stage protection group before being output to the first offset adjustment unit. The first offset adjustment unit provides a bias voltage Vout to the second offset adjustment unit. The bias voltage Vout is superimposed on the output voltage and processed by the second offset adjustment unit before being output as a digital signal by the output module. The input protection unit suppresses interference and common-mode noise, resulting in a clean and variable bias voltage generated by the first offset adjustment unit. This bias voltage, combined with the output voltage of the input protection unit, is then superimposed on the second offset adjustment unit for signal filtering and amplification, ensuring accurate and high-quality output by the output module.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and in particular relates to a differential ADC driving circuit for sensors. Background Technology

[0002] In single-supply data acquisition systems, analog-to-digital converters (ADCs) typically require front-end driver circuitry to perform functions such as input signal level conversion, impedance matching, common-mode noise suppression, and overvoltage protection. Standard industrial signal levels are not directly compatible with the differential input range of modern high-performance single-supply SAR ADCs, necessitating appropriate interface driver circuitry for attenuation, level conversion, and single-ended to differential conversion. Furthermore, industrial sensor signals are often very weak, potentially superimposed with significant noise, and exhibit high impedance source characteristics, all of which pose challenges to accurate ADC acquisition.

[0003] Although existing circuits can basically realize the front-end driving function of ADC, they still have the following problems and shortcomings in practical applications: 1. Incomplete protection structure and weak anti-interference capability: With the advancement of semiconductor technology, the operating power supply voltage of ADCs has been decreasing, making their inputs more susceptible to input overvoltage and requiring effective protection from external circuitry. However, the protection functions of existing front-end driver circuits are often incomplete. For example, some solutions rely on the driver circuit's own power supply voltage limitation to achieve "power-level protection," ensuring that the driver circuit output does not exceed the power supply voltage, but this cannot cope with all types of overvoltage or surge events. Existing circuits lack system-level protection designs for various overvoltage conditions such as electrostatic discharge (ESD), surges, and reverse connection, and do not fully integrate anti-interference measures such as electromagnetic interference (EMI) filtering, resulting in insufficient reliability in harsh industrial environments.

[0004] 2. Poor Common-Mode Noise Suppression: In industrial environments, common-mode noise is one of the main factors affecting signal quality. Although differential circuits themselves have a certain common-mode rejection capability, existing front-end circuits still fall short in terms of common-mode rejection ratio (CMRR). Specifically: it is difficult to achieve perfect symmetry in actual circuits, resulting in the CMRR not reaching the theoretical optimal value; when converting single-ended signals to differential signals, poorly designed conversion circuits can introduce common-mode noise; furthermore, some instrumentation amplifiers lack the linearity required for high-resolution ADCs, resulting in limited common-mode rejection and making it difficult to meet the requirements of high-precision applications.

[0005] 3. Low offset adjustment accuracy and lack of fine-tuning: Offsetting the input signal to match the analog input voltage range of the ADC is one of the key functions of the front-end circuit. Existing circuits mostly use fixed resistor voltage dividers or simple external bias circuits to achieve level offset, but the ratio matching error of the resistors and the error between the amplifiers will result in errors at the final output. Especially under single power supply conditions, the input offset voltage and bias current are large, significantly affecting DC accuracy. More importantly, traditional offset adjustment methods are mostly coarse adjustments, lacking fine-tuning capabilities, and cannot be flexibly calibrated for different sensors and signal sources, limiting the DC accuracy of the system over a wide temperature range and long-term operation.

[0006] 4. Insufficient consideration of signal integrity in local design: Signal integrity is crucial for ensuring conversion accuracy in ADC front-end circuit design. Existing circuits often fail to adequately consider signal integrity in their local design. For example, the switching operation of the sampling capacitor inside the ADC input can cause charge injection, placing high demands on the transient response and settling time of the drive circuit; poor balance in the front-end circuit or an unreasonable PCB layout can generate nonlinear signals, manifesting as distortion and noise at the target frequency; furthermore, driver noise, harmonic distortion (THD), and bandwidth limitations can all become bottlenecks restricting the effective number of bits (ENOB) of the ADC. These signal integrity issues are often not systematically optimized in existing designs.

[0007] Therefore, there is an urgent need for an improved input signal protection and drive circuit that can comprehensively solve the above problems. Summary of the Invention

[0008] The purpose of this invention is to solve the above-mentioned problems existing in the prior art and to provide a differential ADC driving circuit for sensors.

[0009] The objective of this invention is achieved through the following technical solution: A differential ADC driving circuit for a sensor includes a pre-driver module, a driving module, and an output module arranged in series; the pre-driver module provides a differential input signal to the driving module. The drive module includes at least an input protection unit, a first offset adjustment unit, and a second offset adjustment unit. The differential input signal is output to the input terminal of the input protection unit, and after being processed by a three-level protection group for surge protection, noise reduction, and interference suppression, it is output to the first offset adjustment unit. The first offset adjustment unit and the input protection unit together provide a bias voltage Vout to the second offset adjustment unit. After the bias voltage Vout is amplified by the second offset adjustment unit, it outputs a high-precision signal to the output module, and finally, the output module outputs a high-precision digital signal.

[0010] Preferably, the input protection unit includes a common-mode choke L1, a capacitor C1, and a TVS1 group, which together form the three-level protection group; the common-mode choke L1 is electrically connected to the output terminal of the drive module through differential signal input terminals AIO-1 and AIO+2; the capacitor C1 and the TVS1 group are connected in parallel on the output terminal of the common-mode choke L1; the input terminals of the capacitor C1 and the TVS1 group are also connected to the first offset adjustment unit and the second offset adjustment unit.

[0011] Preferably, the TVS1 group is an array of bidirectional TVS transistors to clamp ESD, EFT, or surge voltages and protect the input of the subsequent operational amplifier; the output terminal of the TVS1 group is grounded.

[0012] Preferably, the positive output terminal of the common mode choke L1 is also connected to a resistor R2, and its negative output terminal is also connected to a resistor R1; and the output terminal of the resistor R2 and the output terminal of the first offset adjustment unit jointly supply power to the non-inverting input terminal of the second offset adjustment unit; the output terminal of the resistor R1 supplies power to the inverting input terminal of the second offset adjustment unit.

[0013] Preferably, the first offset adjustment unit includes a reference voltage Vbias, a resistor R5 connected to the output terminal of the reference voltage Vbias, a first filter and a first operational amplifier connected in parallel to the output terminal of the resistor R5, and a resistor R6 connected to the output terminal of the first operational amplifier; the output terminals of the resistor R5 and the first filter are electrically connected to the non-inverting input terminal of the first operational amplifier; the output terminal of the first operational amplifier is also connected to its inverting input terminal via a wire.

[0014] Preferably, the first filter includes a resistor R4 and a capacitor C3 connected in parallel at the output terminal of the resistor R5, and the output terminals of both are grounded.

[0015] Preferably, the second offset adjustment unit includes a supply voltage AVDD, a second operational amplifier electrically connected to the supply voltage AVDD, and a second filter connected between the output terminal of the second operational amplifier and its inverting input terminal; the supply voltage AVDD provides a power supply voltage for the second operational amplifier; the negative pin of the second operational amplifier is grounded.

[0016] Preferably, the output terminal of the power supply voltage AVDD is further provided with a decoupling capacitor C4, and the input terminal of the decoupling capacitor C4 is connected in parallel with the positive pin of the second operational amplifier; the output terminal of the decoupling capacitor C4 is grounded.

[0017] Preferably, the second filter includes a resistor R3 and a capacitor C2 connected in parallel, which are used to filter out noise and interference signals from the output signal of the second operational amplifier.

[0018] Preferably, the output module includes a resistor R7 connected in parallel with the input terminal of the resistor R3, a capacitor C5 connected in parallel with the output terminal of the resistor R7, and a sampling input pin Analog AIO; the output terminal of the capacitor C5 is grounded, and the sampling input pin Analog AIO is connected to a processing chip.

[0019] The advantages of the technical solution of this invention are mainly reflected in: In the drive module, the input protection unit is used to resist interference and suppress common-mode noise. Then, the first offset adjustment unit generates a clean and variable bias voltage. The bias voltage and the output voltage of the input protection unit are superimposed on the second offset adjustment unit for signal filtering and amplification, so that the output module can output the signal accurately and with high quality. The resistor R4 and capacitor C3 in the first offset adjustment unit form the first filter, which performs high-frequency bypass on the external adjustable bias signal, filters out control port switching spikes and power supply ripple, and outputs a stable bias voltage without jitter or high-frequency interference, thus avoiding the bias noise from being superimposed on the effective sensing signal and causing the noise floor to rise. The first offset adjustment unit performs high-precision, continuously adjustable DC bias on the signal output from the front drive module, effectively preventing the signal output from the front drive module from being too small and being overwhelmed, eliminating the inherent input imbalance of the power supply circuit, and avoiding signal distortion. A fixed and precise gain is achieved by matching resistors R1, R2, R3, and R6, while simultaneously amplifying differential sensing signals and superimposing adjustable bias. The gain can be flexibly modified by simply changing a few resistors to adapt to sensors with different output amplitudes, without the need to redesign the signal path. The input protection unit consists of a common-mode choke L1, a differential capacitor C1, and a TVS1 group, forming a three-level protection group that together achieves input protection functions such as clean analog signal input, electromagnetic interference immunity, and transient overvoltage protection. The common-mode choke L1 and the differential capacitor C1 form an LC low-pass filter network to attenuate high-frequency differential-mode noise. Attached Figure Description

[0020] Figure 1 : Schematic diagram of a preferred embodiment of the present invention; Figure 2 : Schematic diagram of the pre-drive module of a preferred embodiment of the present invention; Figure 3 Circuit diagram of the voltage regulator unit in the pre-drive module of the preferred embodiment of the present invention; Figure 4 : Circuit diagram of the sensing unit in the pre-driver module of the preferred embodiment of the present invention; Figure 5 : Circuit diagram of the differential signal generation unit in the pre-driver module of the preferred embodiment of the present invention; Figure 6 Circuit diagram of the driving module and output module of a preferred embodiment of the present invention; Figure 7 : Circuit diagram of the input protection unit in the driving module of the preferred embodiment of the present invention; Figure 8 Circuit diagram of the first offset adjustment unit in the driving module of a preferred embodiment of the present invention; Figure 9 Circuit diagram of the second offset adjustment unit in the driving module of a preferred embodiment of the present invention. Detailed Implementation

[0021] The objectives, advantages, and features of this invention will be illustrated and explained through the following non-limiting description of preferred embodiments. These embodiments are merely typical examples of applying the technical solutions of this invention, and all technical solutions formed by equivalent substitutions or equivalent transformations fall within the scope of protection claimed by this invention.

[0022] In the description of the solution, it should be noted that the terms "center," "upper," "lower," "left," "right," "front," "rear," "vertical," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Also, in the description of the solution, with the operator as a reference, the direction closer to the operator is the proximal end, and the direction farther from the operator is the distal end.

[0023] like Figure 1 As shown, this invention discloses a differential ADC driving circuit for sensors, comprising a pre-driver module 1, a driver module 2, and an output module 3 arranged in series. The pre-driver module 1 provides differential input signals to the driver module 2 via terminals AIO-1 and AIO+2.

[0024] like Figure 2 As shown, the front-end module 1 includes an input voltage, a voltage regulator unit 11 connected to the output terminal of the input voltage, a sensing unit 12 connected to the output terminal of the voltage regulator unit 11, and a differential signal generation unit 13 connected to the output terminal of the sensing unit 12. The input voltage is preferably a 24V DC voltage.

[0025] The voltage regulator unit 11 is electrically connected to the input voltage, and its specific circuit structure is as follows: Figure 3 As shown. The voltage regulator unit 11 includes a capacitor bank 111, a chip U2, a diode D3 and an inductor L1 connected in parallel at the output terminal of the chip U2, and an output bank 112. The capacitor bank 111 includes an electrolytic capacitor C1 and a high-frequency decoupling capacitor C2 connected in parallel with the input voltage. The electrolytic capacitor is preferably 470μF, but this is adjustable and not limited here. The electrolytic capacitor C1 provides a large amount of filtering capacitance to smooth the DC voltage from the input voltage, suppress low-frequency ripple in the power supply, reduce input voltage fluctuations, and provide a stable power supply voltage for the subsequent chip U2. The high-frequency decoupling capacitor C2 is preferably a 0.1μF ceramic capacitor, which is used to absorb high-frequency interference and spike pulses in the circuit, compensate for the poor high-frequency characteristics of the electrolytic capacitor C1, and filter out EMI high-frequency noise, improving the stability and reliability of the signal entering the chip U2.

[0026] The preferred model of the chip U2 is LM2596, which can be used as a step-down switching regulator. Specifically, the first pin +VIN of the chip U2 is the power input pin, connected to the output terminal of the input voltage, and is connected in parallel with the electrolytic capacitor C1 and the high-frequency decoupling capacitor C2. The second pin Output of the chip U2 is the output pin, used to output a high-frequency pulse voltage. The third pin GND of the chip U2 is the power ground pin, used for the common ground of the power supply circuit. The fourth pin Feedback of the chip U2 is the voltage feedback pin, used to collect the voltage of the output group at the back end, realize closed-loop regulation of the duty cycle inside the chip, and ensure the stability of the power supply voltage of the chip U2. The fifth pin ON / OFF of the chip U2 is the enable pin, which is grounded and keeps the chip U2 continuously powered on. Through high-frequency switching chopping by the chip U2, the 24V high-voltage DC is converted into an uncontrollable pulse voltage, realizing step-down regulation.

[0027] The diode D3 is preferably a 1N4007 Schottky / rectifier diode (freewheeling diode). Its negative terminal is connected to the second pin Output of the chip U2, and its positive terminal is grounded. The inductor L1 is preferably a 100μH power inductor, which serves as an energy storage element. When the chip U2 is working, the inductor L1 stores energy. When the chip U2 is off, the inductor L1, together with the diode D3 and the capacitor in the output group 112, completes a smooth transition. At this time, the diode D3 provides a freewheeling path for the inductor L1, preventing the inductor L1 from generating high voltage spikes that could break down the chip U2.

[0028] The output group 112 includes a power supply voltage VCC and a capacitor assembly, both connected to the second pin of the inductor L1 furthest from the chip U2. The power supply voltage VCC is preferably 5V. The capacitor assembly includes an output filter capacitor C3 and an output high-frequency decoupling capacitor C4 connected in parallel. The output filter capacitor C3 is preferably a 100μF electrolytic capacitor, used to filter out low-frequency ripple and stabilize the 5V DC output. When a load is connected to the output filter capacitor C3, it can buffer current changes; that is, a load can be selectively connected to the output filter capacitor C3. This load can include known electrical components such as resistors, and the specific configuration needs to be adjusted according to usage requirements, which is not limited here. The output high-frequency decoupling capacitor C4 is preferably a 0.1μF ceramic capacitor, used to address known high-frequency switching noise, improve the transient response of the power supply voltage, and reduce power supply interference.

[0029] Thus, the 24V DC input voltage is filtered and fed into the LM2596 chip U2. The high-frequency pulse output by the chip U2 is stored in the inductor L1, freewheeled by the diode D3, and then filtered by the capacitor assembly to finally output a stable 5V DC voltage to power the downstream sensing, operational amplifier and other circuits.

[0030] like Figure 4 As shown, the sensing unit 12 includes a chip U1 connected in parallel to the output terminal of the power supply voltage VCC and an RC oscillation circuit 121 disposed around the outer periphery of the chip U1. Preferably, the chip U1 is a 555 chip. - TIMER - The chip U1 is RATED, and it is supplied with a stable operating voltage by the power supply voltage VCC and is powered by the output of the voltage regulator unit 11. As the core oscillation component, the chip U1 has a comparator, trigger, and discharge tube inside it, which, together with the external RC charging and discharging device, continuously output a periodic square wave.

[0031] Specifically, the chip U1 includes a power supply voltage pin VCC, connected to the output terminal of the power supply voltage VCC; a ground pin GND, used for grounding to form a loop; a reset pin RST, connected in parallel with the power supply voltage pin VCC at the output terminal of the power supply voltage to maintain normal chip operation; a discharge pin DIS, which is disconnected when the capacitor in the RC oscillation circuit 121 is charging, and turns the chip internally and grounded when the capacitor is discharging; a threshold pin THR and a trigger pin TRI are connected, wherein the threshold pin THR is triggered at a high level, and the trigger pin TRI is triggered at a low level. Both detect the voltage of the oscillation timing capacitor C1 and control the output level to flip, realizing automatic reciprocating charging and discharging, and continuously outputting a square wave; a control pin CON for internal reference voltage compensation; and an output pin OUT for frequency-modulated square wave signal output.

[0032] The RC oscillation circuit includes a timing branch resistor group, specifically comprising a charging current-limiting resistor R1 and a branch resistor R2. The charging current-limiting resistor R1 is preferably 100KΩ, and it is connected in parallel with the power supply voltage pin VCC of the chip U1 at the output terminal of the power supply voltage. The branch resistor R2 is preferably 311KΩ, and it can be replaced by a resistive sensing element Rx. This branch resistor is connected in parallel with the discharge pin DIS of the chip U2 at the output terminal of the charging current-limiting resistor R1. The power supply voltage flows through the charging current-limiting resistor R1 and the branch resistor R2 to the subsequent capacitor bank, thereby determining the charging speed of the subsequent capacitor bank and participating in the charging and discharging circuit.

[0033] The capacitor bank includes an oscillation timing capacitor C1 and an oscillation capacitor C2. The capacitance of the oscillation timing capacitor C1 is, but not limited to, 1μF, and it can be replaced by a capacitive sensing element Cx, a humidity-sensitive capacitor, or a capacitive liquid level probe, allowing its capacitance to change the oscillation frequency with variations in physical quantities. The oscillation timing capacitor C1 is the core component for charging and discharging, and its capacitance determines the charging and discharging duration. Simultaneously, the input terminal of the oscillation capacitor C1 is connected in parallel with the threshold pin THR and trigger pin TRI of the chip U1, and is connected to the output terminal of the branch resistor R2, with its output terminal grounded. The capacitance of the oscillation capacitor C2 is, but not limited to, 0.01μF, and is used for filtering and voltage regulation, stabilizing the reference level of the internal comparator of the chip, suppressing high-frequency noise, and preventing waveform jitter. Simultaneously, the input terminal of the oscillation capacitor C2 is electrically connected to the control pin CON of the chip U1, and its output terminal is grounded. The oscillation capacitor C2 stabilizes the internal reference voltage of the chip U1, reducing frequency jitter.

[0034] The working relationship between the pins of chip U1 is as follows: After the power supply voltage pin VCC is energized, it outputs current and voltage to the charging current-limiting resistor R1 in the RC oscillation circuit 121. Then, the charging current-limiting resistor R1 inputs current or level signals to the branch resistor R2 and the discharge pin DIS. The branch resistor R2 outputs current to the oscillation timing capacitor C1 and charges the oscillation timing capacitor C1; at the same time, the threshold pin THR and the trigger pin TRI detect the voltage of the oscillation timing capacitor C1. When the voltage on the oscillation timing capacitor C1 reaches the threshold voltage (preferably 2 / 3VCC), the THR trigger control level flips, and at the same time, the output pin OUT outputs a low-level square wave. The level flipping also turns on the discharge pin DIS, thereby causing the oscillation timing capacitor C1 to discharge through the branch resistor R2. When the threshold pin THR and the trigger pin TRI detect that the voltage on the oscillation timing capacitor C1 has dropped to the trigger voltage (preferably 1 / 3Vcc), the TRI trigger control level flips again, and a high-level square wave is output by the output pin OUT, while the discharge pin DIS is disconnected. This cycle repeats and outputs a continuous square wave through the output pin OUT.

[0035] Simultaneously, after connecting the RC sensing element, the element parameters change with the measured physical quantity. As the charging and discharging speed changes, the output square wave frequency changes synchronously, completing the conversion from physical quantity to frequency-modulated pulse signal.

[0036] like Figure 5 As shown, the differential signal generation unit 13 is connected in parallel with U1 in the sensing unit 12 at the output terminal of the power supply voltage VCC. The differential signal generation unit 13 consists of chip U3 and its peripheral circuitry.

[0037] Specifically, the preferred model of chip U3 is LTC6400. Its first, third, and tenth pins are all connected to the output terminal of the power supply voltage VCC, and the three together form a positive power supply pin. By connecting multiple pins in parallel to the power supply voltage VCC, the impedance of the power supply traces is reduced, and the parallel efficiency is improved. The second pin of chip U3 is an output setting pin, which is connected to the power supply voltage VCC through setting resistors R1 and R2 connected in series. It is used to output common-mode voltage and can provide a midpoint voltage through voltage division. The midpoint voltage is preferably 1.65V to ensure that the differential signal is symmetrical and does not touch the power rail. The fourth pin of chip U3 is a ground pin to form a loop during the operation of chip U3. The fifth pin of chip U3 is a negative differential signal output pin, which is electrically connected to the AIOIN- pin in the driver module through a differential resistor R5. The resistance of the differential resistor R5 is preferably 12.5Ω. The sixth pin of chip U3 is a negative output feedback intermediate node, and the seventh pin is a positive output feedback intermediate node. A differential resistor R3 is connected between them to balance the differential loop. The eighth pin is a positive differential signal output pin, which is electrically connected to the AIO IN+ pin in the drive module through a differential resistor R4, the value of which is preferably 12.5Ω. The ninth and twelfth pins are both negative power supply pins or analog ground pins. The eleventh pin is an enable / reset pin, used to turn off the chip output when low level and to work normally when high level. When not in use, it is connected to the power supply voltage pin to achieve permanent enable. The thirteenth pin is the in-phase differential input channel A, and the fourteenth pin is the in-phase differential input channel B. They are shorted and connected in parallel inside chip U3 to increase input impedance, form a shunt, and reduce noise. Externally, they can be shorted to prevent floating interference. At the same time, after being shorted, they are connected in parallel with the ground to the output terminal of the sensing unit 12. The fifteenth pin is the inverting differential signal input channel A, and the sixteenth pin is the inverting differential signal input channel B. The two are shorted and connected in parallel inside the chip U3, which can be used to increase the input impedance, form a shunt, and reduce noise. Externally, the two can be shorted to prevent interference introduced by floating. At the same time, after the two are shorted, they can be grounded through the differential capacitor C2.

[0038] The operation of chip U3 is as follows: a single-ended signal is fed into pin 13 or 14 of chip U3 via differential capacitor C1, and then AC grounded via pin 15 or 16 through C2, forming a differential input difference Vin. The signal is amplified by a certain factor G through two symmetrical amplification channels inside chip U3, and positive and negative AC components are distributed to two output channels. A DC reference is provided to pin 2 of chip U3 through a voltage divider using differential resistors R1 and R2. The common-mode servo loop inside chip U3 locks the DC midpoint VOCM of the two output channels. Differential signals with the same DC level and equal AC amplitude but opposite phase are output through pins 5 and 8 of chip U3. After impedance matching by differential resistors R4 and R5, the signals are output through differential signal input terminals AIO+ and AIO-, and the back-end differential acquisition achieves signal amplification and common-mode interference suppression.

[0039] Specifically, the single-ended signal output from the sensing unit 12 is input to the thirteenth pin of the chip U3, the in-phase differential input channel A, through the differential capacitor C1. The voltage on this pin is V+IN. Simultaneously, the fifteenth pin of the chip U3 is the in-phase differential signal input channel A, and the voltage on this pin is V-IN. At this time, only the in-phase differential input channel A carries a valid AC signal, while the in-phase differential signal input channel A has no AC excitation, forming a standard single-ended input excitation condition. The differential input difference Vin is formed by AC grounding through the differential capacitor C2. The internal differential input stage of the chip detects the potential difference between the two inputs to obtain the unique valid input difference signal Vin = (V+IN) - (V-IN).

[0040] Furthermore, after acquiring the difference signal Vin, the chip U3 amplifies it by a certain factor G. Then, through the chip's internal symmetrical architecture, it automatically distributes AC fluctuations of opposite polarity to the two output branches. Specifically, the positive differential signal output channel corresponding to pin 8 of the chip U3 is superimposed with an AC component +G*Vin, and the negative differential signal output pin corresponding to pin 5 is superimposed with an AC component -G*Vin. The hardware parameters of the two amplification branches are completely symmetrical, ensuring that the amplitudes of the two AC signals are strictly equal, naturally forming a 180° phase difference.

[0041] The power supply voltage VCC is divided by differential resistors R1 and R2 to provide a fixed DC reference voltage VOCM to the second pin of chip U3. Chip U3 has a built-in independent common-mode servo feedback loop that continuously and in real-time acquires the average voltage of the outputs from pins 5 and 8 and compares and corrects it with the reference voltage VOCM. The servo loop dynamically adjusts the static DC potential of the two outputs, forcing the DC midpoint of the two outputs to always equal VOCM. Specifically, the DC midpoint of the output from pin 8 is VOUT += VOCM + G*Vin, and the DC midpoint of the output from pin 5 is VOUT -= VOCM - G*Vin. These two calculation formulas ensure that the two outputs share the same DC bias level, with only the AC signal polarity reversed, preventing signal clipping distortion that occurs with a single power supply.

[0042] The voltage difference Vdiff = VOUT+−VOUT− = 2G⋅Vin, read from the eighth and fifth pins of chip U3, completely preserves the amplified original input signal, realizing the conversion of single-ended input signal to standard differential signal. Differential acquisition mode can cancel power supply and electromagnetic common-mode interference coupled from the transmission line, effectively improving the signal-to-noise ratio of the back-end acquisition. Simultaneously, AIO+ and AIO- are led out through differential resistors R4 and R5, which serve as isolation matching resistors to complete output impedance matching, suppress self-oscillation caused by high-frequency capacitive loads, and avoid waveform distortion caused by high-frequency signal reflection.

[0043] like Figure 6 As shown, the drive module 2 includes at least an input protection unit 21, a first offset adjustment unit 22, and a second offset adjustment unit 23. The differential input signal output from the front-end module 1 is output to the input terminal of the input protection unit 21, and after undergoing surge protection, noise reduction, and interference suppression processing by a three-level protection group, it is output to the first offset adjustment unit 22. Then, the first offset adjustment unit 22 and the input protection unit 21 together provide a bias voltage V to the second offset adjustment unit 23. out The bias voltage V out After being biased and amplified by the second offset adjustment unit 23, a high-precision signal is output to the output module 3, and finally the output module 3 outputs a high-precision digital signal.

[0044] The input protection unit 21 includes, for example, the following: Figure 7The common-mode choke L1, capacitor C1, and TVS1 group shown constitute the three-level protection group, jointly achieving input protection functions such as clean analog signal input, electromagnetic interference immunity, and transient overvoltage protection. The common-mode choke L1 is electrically connected to the output terminal of the drive module 1 through differential signal input terminals AIO-1 and AIO+2; specifically, the differential signal terminals AIO-1 and AIO+2 are connected to connection points AIO IN+ and AIO IN- through the common-mode choke L1, forming a differential signal input low potential Vin+ and a differential signal input high potential Vin-. This also provides voltage and input signals to capacitor C1 and the TVS1 group.

[0045] Furthermore, the capacitor C1 and the TVS1 group are connected in parallel at the output terminal of the common-mode choke L1; that is, the positive terminals of the capacitor C1 and the TVS1 group are connected in parallel to the connection point AIO IN+, and their negative terminals are connected in parallel to the connection point AIO IN-. The capacitor C1, positioned between connection points AIO IN+ and AIO IN-, forms a low-impedance path for high-frequency differential mode signals, constituting an LC low-pass filter with the common-mode choke L1, effectively attenuating high-frequency interference signals. Simultaneously, the input terminals of the capacitor C1 and the TVS1 group are also connected to the first offset adjustment unit 22 and the second offset adjustment unit 23.

[0046] Furthermore, the TVS1 group is an array composed of bidirectional TVS transistors. The output terminal of the TVS1 group is grounded. The TVS transistors clamp ESD, EFT, or surge voltages. That is, when the surge voltage output by the common-mode choke L1 exceeds the clamping voltage, the TVS1 group will quickly conduct, discharging the high-voltage spike to ground AGND to protect the input of the subsequent operational amplifier. At the same time, it is suitable for the high-speed, high-precision analog signals required by this application and will not be significantly attenuated from the reduced useful signal output by the common-mode choke L1.

[0047] The positive output terminal of the common-mode choke L1 is connected to a resistor R2, and its negative output terminal is connected to a resistor R1. That is, the positive terminal of capacitor C1, the positive terminal of the TVS1 group, and the resistor R2 are connected in parallel at connection point AIO IN+, and the negative terminal of capacitor C1, the negative terminal of the TVS1 group, and the resistor R1 are connected in parallel at connection point AIO IN-. The output terminal of resistor R2, together with the output terminal of the first offset adjustment unit 22, supplies power to the non-inverting input terminal of the second offset adjustment unit 23, and the output terminal of resistor R1 supplies power to the inverting input terminal of the second offset adjustment unit 23. By using resistors R1 and R2 as input current limiting and impedance matching resistors, when the TVS1 is working, they can limit the current flowing into the input terminals of the first offset adjustment unit 22 and the second offset adjustment unit 23.

[0048] like Figure 6 and Figure 8 As shown, the first offset adjustment unit 22 includes a reference voltage V. bias , connected to the reference voltage V bias The output includes a resistor R5, a first filter 221 and a first operational amplifier 222 connected in parallel to the output of resistor R5, and a resistor R6 connected to the output of the first operational amplifier 222. The reference voltage V... bias The voltage is provided by the signal terminal ADC_offset, which is connected to the output of the front-end module 1. The variable voltage of the ADC_offset signal terminal is buffered with extremely high precision, and fine control of the overall bias is achieved through the fine-tuning capability of the resistor R5 and the 8.26x gain of the first operational amplifier 222 in the subsequent stage. This gain factor needs to be calculated based on the resistance values ​​in the circuit, and the resistance values ​​can be selected according to requirements; the specific calculation process will be explained later.

[0049] The signal output from the pre-drive module 1 generates an input offset voltage after passing through the common-mode choke L1, the capacitor C1, the TVS1 group, and the resistors R1 and R2. Based on this, the first offset adjustment unit 22 performs operational amplification processing and outputs a bias voltage from the resistor R6, which can effectively prevent the signal output from the resistor R2 from being submerged.

[0050] Such as 6 and Figure 8As shown, the output terminals of resistor R5 and the first filter 221 are electrically connected to the non-inverting input terminal of the first operational amplifier 222. The output terminal of the first operational amplifier 222 is also connected to its inverting input terminal via a wire. Furthermore, the fifth pin of the first operational amplifier 222 is its non-inverting input terminal, the sixth pin is its inverting input terminal, and the seventh pin is its output terminal.

[0051] Furthermore, the first filter 221 includes a resistor R4 and a capacitor C3 connected in parallel at the output terminal of the resistor R5, and the output terminals of both are grounded. The resistor R4 provides a DC path to ground for the non-inverting input terminal of the first operational amplifier 222, stabilizing the bias point and preventing the non-inverting input terminal of the first operational amplifier 222 from floating and drifting. Simultaneously, the resistor R4 and the capacitor C3 constitute a high-frequency bypass filter to filter out high-frequency switching noise from the signal terminal ADC_offset, ensuring the bias voltage V output from the resistor R6. out The purity of the signal. Resistor R6 transmits the fine-tuning bias voltage V generated by the first operational amplifier 222. out The voltage is coupled to the non-inverting input of the second operational amplifier 231 in the second offset adjustment unit 23, and forms a voltage divider with the other input resistors (i.e., the resistor R2) of the non-inverting input of the second operational amplifier 231, which determines the final contribution ratio of the bias.

[0052] The differential input signal output from the front-end module 1 generates a clean and variable bias voltage V via the first offset adjustment unit 22. out Then, the bias voltage V is adjusted by the second offset adjustment unit 23. out Amplified and superimposed on the signal output. Specifically, as follows: Figure 6 and Figure 9 As shown, the second offset adjustment unit 23 includes at least a power supply voltage AVDD and a second operational amplifier 231 electrically connected to the power supply voltage AVDD. The power supply voltage AVDD is preferably 3.3V and is connected to the eighth pin of the second operational amplifier 231 to provide power to the second operational amplifier 231. Furthermore, a decoupling capacitor C4 is provided at the output terminal of the power supply voltage AVDD, and the input terminal of the decoupling capacitor C4 is connected in parallel with the positive pin of the second operational amplifier 231; the output terminal of the decoupling capacitor C4 is grounded.

[0053] The negative terminal of the second operational amplifier 231 is connected to the fourth pin of the second operational amplifier 231 and grounded.

[0054] like Figure 9As shown, the second offset adjustment unit 23 further includes a second filter 232 connected between the output terminal and the inverting input terminal of the second operational amplifier 231. Further, the first pin of the second operational amplifier 231 is its output terminal, the second pin is its inverting input terminal, and the third pin is its non-inverting input terminal. The second filter 232 includes a resistor R3 and a capacitor C2 connected in parallel. The resistor R3 and the capacitor C2, connected between the output terminal and the inverting input terminal of the second operational amplifier 231, form a low-pass filter, which can be used to filter out noise and interference signals in the output signal of the second operational amplifier 231. Simultaneously, the capacitor C2, together with the resistor R1 and / or the resistor R2, can also form an RC low-pass filter to further filter out noise.

[0055] The resistor R3 is a feedback resistor, and its relationship with the resistor R1 output by the input protection unit is R3 / R1=0.21; the relationship between the resistor R6 and the group R2 is R6 / R2=0.21.

[0056] Simultaneously, by dividing the voltage between resistor R6 at the output terminal of the first operational amplifier 222 and resistor R2 at the output terminal of the input rainstorm unit, the output bias voltage V can be determined. out The contribution weight of the voltage at the non-inverting input terminal of the second operational amplifier 231 is calculated using the formula R2 / (R2+R6) to determine the weight of the secondary offset. The core resistor value of this application can also be calculated using this formula, and it can be seen from the formula that during operation, only a slight change in the resistance value of resistor R6 is needed to significantly change the bias amplification factor. Furthermore, the contribution weight in this application is preferably 89%, but the specific resistance values ​​can be adjusted according to requirements and are not specifically limited here.

[0057] Specifically, the voltage at the non-inverting input terminal of the second operational amplifier 231 can be obtained by formula... The calculation yielded the result. And V in this formula... p V is the voltage at the non-inverting input terminal of the second operational amplifier 231. in+ V is the potential of the connection point AIO IN +. bias This is the potential of the signal terminal ADC_offset. The voltage at the inverting input terminal of the second operational amplifier 231 can be expressed by the formula... Calculated. Where V n V is the voltage at the inverting input terminal of the second operational amplifier 231, Vin- is the potential at the connection point AIO IN-, and V outThe bias voltage output by resistor R6. Under the "virtual short" principle, the non-inverting input voltage and the inverting input voltage calculated by the above two formulas for the second operational amplifier 231 are almost equal, i.e., V. p =V n Thus, the bias voltage is obtained. That is, the second operational amplifier 231 can achieve a gain of 8.26 times, realizing the superposition amplification of differential signal gain and bias voltage. In this application, the differential input signal is provided with voltage gain through the first offset adjustment unit 22, and added to the output voltage of the input protection unit 21 to obtain the final single-ended output.

[0058] like Figure 6 As shown, the output module 3 includes a resistor R7 connected in parallel with the input terminal of the resistor R3, a capacitor C5 connected in parallel with the output terminal of the resistor R7, and a sampling input pin Analog AIO. The output terminal of the capacitor C5 is grounded, and the sampling input pin Analog AIO is connected to the processing chip. The resistor R7 and the capacitor C5 form a resistor-capacitor network for impedance matching and high-frequency filtering, and the signal is finally sent to the ADC sampling input pin of the chip.

[0059] Taking a humidity sensor as an example, the following two tables were obtained through experiments comparing different standard humidity setpoints with the actual displayed humidity values: Table 1 0%RH 8.1%RH +8.1%RH 50%RH 56.7%RH +6.7%RH 100%RH 92.8%RH -7.2%RH Table 2 0%RH 0.02%RH +0.02%RH 50%RH 50.00%RH 0.00%RH 100%RH 99.98%RH -0.02%RH Table 1 above shows the relationship between the standard humidity setpoint and the actual displayed humidity value obtained from the drive circuit designed based on the traditional offset adjustment method; Table 2 shows the relationship between the standard humidity setpoint and the actual displayed humidity value obtained from the drive circuit designed in this application. It can be clearly seen from the tables that the absolute measurement error obtained by the drive circuit disclosed in this application is much smaller than that obtained by the traditional drive circuit. Therefore, the drive circuit disclosed in this application has the ability to accurately convert the analog signal input from the sensor into a digital signal and output it with DC accuracy, significantly improving the measurement quality.

[0060] This invention has many other embodiments, and all technical solutions formed by equivalent transformation or equivalent transformation fall within the protection scope of this invention.

Claims

1. A differential ADC driving circuit for sensors, characterized in that: It includes a front-end module (1), a drive module (2) and an output module (3) arranged in series; the front-end module (1) provides a differential input signal to the drive module (2); The drive module (2) includes at least an input protection unit (21), a first offset adjustment unit (22), and a second offset adjustment unit (23). The differential input signal is output to the input terminal of the input protection unit (21), and after being processed by a three-level protection group for surge protection, noise reduction, and anti-interference, it is output to the first offset adjustment unit (22). The first offset adjustment unit (22) and the input protection unit (21) together provide a bias voltage V to the second offset adjustment unit (23). out The bias voltage V out After being biased and amplified by the second offset adjustment unit (23), a high-precision signal is output to the output module (3), and finally the output module (3) outputs a high-precision digital signal.

2. The differential ADC driving circuit for sensors according to claim 1, characterized in that: The input protection unit (21) includes a common-mode choke L1, a capacitor C1, and a TVS1 group, which together form the three-level protection group. The common-mode choke L1 is electrically connected to the output terminal of the drive module (1) through differential signal input terminals AIO-1 and AIO+2. The capacitor C1 and the TVS1 group are connected in parallel on the output terminal of the common-mode choke L1. The input terminals of the capacitor C1 and the TVS1 group are also connected to the first offset adjustment unit (22) and the second offset adjustment unit (23).

3. The differential ADC driving circuit for sensors according to claim 2, characterized in that: The TVS1 group is an array of bidirectional TVS transistors that clamps ESD, EFT, or surge voltages to protect the input of the subsequent operational amplifier; the output of the TVS1 group is grounded.

4. The differential ADC driving circuit for sensors according to claim 3, characterized in that: The positive output terminal of the common mode choke L1 is also connected to a resistor R2, and its negative output terminal is also connected to a resistor R1; and the output terminal of the resistor R2 and the output terminal of the first offset adjustment unit (22) jointly supply power to the non-inverting input terminal of the second offset adjustment unit (23); the output terminal of the resistor R1 supplies power to the inverting input terminal of the second offset adjustment unit (23).

5. The differential ADC driving circuit for sensors according to claim 4, characterized in that: The first offset adjustment unit (22) includes a reference voltage Vbias, a resistor R5 connected to the output terminal of the reference voltage Vbias, a first filter (221) and a first operational amplifier (222) connected in parallel to the output terminal of the resistor R5, and a resistor R6 connected to the output terminal of the first operational amplifier (222); the output terminal of the resistor R5 and the output terminal of the first filter (221) are electrically connected to the non-inverting input terminal of the first operational amplifier (222); the output terminal of the first operational amplifier (222) is also connected to its inverting input terminal through a wire.

6. The differential ADC driving circuit for sensors according to claim 5, characterized in that: The first filter (221) includes a resistor R4 and a capacitor C3 connected in parallel on the output terminal of the resistor R5, and the output terminals of both are grounded.

7. The differential ADC driving circuit for sensors according to claim 6, characterized in that: The second offset adjustment unit (23) includes a power supply voltage AVDD, a second operational amplifier (231) electrically connected to the power supply voltage AVDD, and a second filter (232) connected between the output terminal of the second operational amplifier (231) and its inverting input terminal; the power supply voltage AVDD provides a power supply voltage for the second operational amplifier (231); the negative pin of the second operational amplifier (231) is grounded.

8. The differential ADC driving circuit for sensors according to claim 7, characterized in that: The output terminal of the power supply voltage AVDD is also provided with a decoupling capacitor C4, and the input terminal of the decoupling capacitor C4 is connected in parallel with the positive pin of the second operational amplifier (231); the output terminal of the decoupling capacitor C4 is grounded.

9. The differential ADC driving circuit for sensors according to claim 8, characterized in that: The second filter (232) includes a resistor R3 and a capacitor C2 connected in parallel, which are used to filter out noise and interference signals from the output signal of the second operational amplifier (231).

10. The differential ADC driving circuit for sensors according to claim 9, characterized in that: The output module (3) includes a resistor R7 connected in parallel with the input terminal of the resistor R3, a capacitor C5 connected in parallel with the output terminal of the resistor R7, and a sampling input pin Analog AIO; the output terminal of the capacitor C5 is grounded, and the sampling input pin Analog AIO is connected to a processing chip.

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