Analog-to-digital converter and method of controlling an analog-to-digital converter

Abstract

This application discloses an analog-to-digital converter (ADC) and its control method, belonging to the field of equipment control technology. The ADC includes a comparator circuit module, an asynchronous clock generation module, a sample-and-hold circuit module, a capacitor array, and an encoding module. The comparator circuit module consists of three comparators connected in parallel. Each comparator includes at least a first input terminal for the input voltage and a second input terminal for the reference voltage. The first and second input terminals are connected to the output terminal of the capacitor array and to a common-mode voltage. Through this application's embodiment, an ADC can be equipped with a comparator circuit module consisting of three parallel comparators. By comparing voltage signals using the three comparators, three thermometer codes can be generated simultaneously. These three thermometer codes are then converted into two binary codes, improving the quantization speed of the comparator circuit and meeting the quantization requirements of high-speed ADCs.

Description

Technical Field

[0001] This application belongs to the field of equipment control technology, specifically relating to an analog-to-digital converter and a control method for the analog-to-digital converter. Background Technology

[0002] With the development of information technology, the application of analog-to-digital converters (ADCs) is becoming increasingly widespread. In products such as radar, ultra-wideband communication systems, and high-performance digital oscilloscopes, the speed performance of ADCs is often the bottleneck of the entire system performance. Therefore, the research on high-speed ADCs has received much attention.

[0003] Current analog-to-digital converters (ADCs) use only one comparator, which can only output one bit of binary code at a time. The accuracy of the ADC is equal to the number of times the comparator operates in each quantization cycle. Therefore, it is difficult to meet the quantization requirements of high-speed ADCs. Summary of the Invention

[0004] The purpose of this application is to provide an analog-to-digital converter and its control method, which can solve the problem of slow quantization speed in current analog-to-digital converters.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows: In a first aspect, embodiments of this application provide an analog-to-digital converter (ADC), which includes a comparator circuit module, an asynchronous clock generation module, a sample-and-hold circuit module, a capacitor array, and an encoding module. The comparator circuit module consists of three comparators connected in parallel. Each comparator includes at least a first input terminal for an input voltage and a second input terminal for a reference voltage. The first and second input terminals are connected to the output terminal of the capacitor array and are also connected to a common-mode voltage. The asynchronous clock generation module is used to generate a sampling signal based on the received clock signal, and transmit the sampling signal to the sample-and-hold circuit module for sampling; The sample-and-hold circuit module is used to sample the first input voltage and the first reference voltage of the analog-to-digital converter in response to the received sampling signal to obtain a voltage signal; The capacitor array is used to store the voltage signal and generate the second reference voltage and input signal of the comparator circuit module; The comparator circuit module is used to generate a threshold voltage based on the second reference voltage and the common-mode voltage, and compare the threshold voltage with the input signal to generate three thermometer codes; The encoding module is used to convert the three thermometer codes into two binary codes.

[0006] Optionally, the asynchronous clock generation module is further configured to generate a clock signal for the (N+1)th round in response to receiving the thermometer code output by the comparator circuit module after the Nth round of comparison.

[0007] Optionally, the asynchronous clock generation module is further configured to generate a calibration signal for the comparator, and use the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator.

[0008] Optionally, the calibration signal includes a first calibration signal and a second calibration signal that is inversely phase to the first calibration signal. When the asynchronous clock generation module uses the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator, it is specifically used for: The first calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is connected to the common-mode voltage. At the same time, the second calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is disconnected from the capacitor array.

[0009] Optionally, the operation of the analog-to-digital converter is divided into a comparison stage and a calibration stage. When the sample-and-hold circuit module is in the N+1th round of sampling, the comparator circuit module performs the Nth round of calibration.

[0010] Optionally, during the comparison phase, the first calibration signal is at a low level and the second calibration signal is at a high level; during the calibration phase, the first calibration signal is at a high level and the second calibration signal is at a low level.

[0011] Optionally, the analog-to-digital converter further includes a digital control module, which is used to perform quantization based on the binary code to obtain a quantization result.

[0012] Secondly, embodiments of this application provide a control method for an analog-to-digital converter, applied to the analog-to-digital converter described in the first aspect, the method comprising: A sampling signal is generated based on the received clock signal; In response to the received sampling signal, the first input voltage and the first reference voltage of the analog-to-digital converter are sampled to obtain a voltage signal; The voltage signal is stored in the capacitor array, and the capacitor array is used to generate the second reference voltage and input signal of the comparator circuit module; The threshold voltage of the comparator is generated based on the second reference voltage and the common-mode voltage, and the threshold voltage is compared with the input signal to generate three thermometer codes. The three thermometer codes are converted into two binary codes.

[0013] Optionally, the method includes: Generate the calibration signal for the comparator; The calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator.

[0014] Thirdly, embodiments of this application provide an electronic device including a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the method described in the first aspect.

[0015] Fourthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method described in the first aspect.

[0016] Fifthly, embodiments of this application provide a chip, the chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run programs or instructions to implement the method as described in the first aspect.

[0017] In this embodiment of the application, a comparator circuit module consisting of three comparators connected in parallel is provided in the analog-to-digital converter. By comparing the voltage signals through the three comparators, three thermometer codes can be generated simultaneously. Then, the three thermometer codes are converted into two binary codes to improve the quantization speed of the comparator circuit and meet the quantization requirements of the high-speed analog-to-digital converter. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of a data converter according to one embodiment of this application; Figure 2 This is a timing diagram of a one-step two-bit successive approximation analog-to-digital converter architecture in one embodiment of this application; Figure 3 This is another one-step two-bit successive approximation analog-to-digital converter architecture and timing diagram in one embodiment of this application; Figure 4 This is a flowchart illustrating the steps of a control method for a digital converter according to an embodiment of this application; Figure 5 This is a schematic diagram of the structure of an electronic device according to one embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] With the development of information technology, the application of analog-to-digital converters (ADCs) is becoming increasingly widespread. In products such as radar, ultra-wideband communication systems, and high-performance digital oscilloscopes, the speed performance of the ADC is often the bottleneck of the entire system's performance; therefore, research on high-speed ADCs has received considerable attention.

[0021] In the field of analog integrated circuits, a dynamic comparator and method for offset calibration of analog-to-digital converters are disclosed, comprising a first-stage preamplifier, a second-stage preamplifier, a third-stage preamplifier, a fourth-stage preamplifier, and a latch connected in sequence. The input terminal of the first-stage preamplifier is connected to an input signal switch and a first switch, and its output terminal is connected to the upper stage board of a first calibration capacitor. The input terminal of the second-stage preamplifier is connected to a second switch and the lower stage board of the first calibration capacitor, and its output terminal is connected to the upper stage board of the second calibration capacitor. The input terminal of the third-stage preamplifier is connected to a third switch and the lower stage board of the second calibration capacitor, and its output terminal is connected to the upper stage board of the third calibration capacitor. The input terminal of the fourth-stage preamplifier is connected to a fourth switch and the lower stage board of the third calibration capacitor, and its output terminal is connected to the input terminal of the latch. The output terminal of the latch is connected to a directional controller. This scheme has the advantages of low offset voltage, low noise, and high speed.

[0022] However, after each comparator cycle, the analog-to-digital converter (ADC) typically outputs only one bit of binary code. The ADC's precision is equal to the number of comparator cycles in each quantization cycle. As the ADC's precision increases, the comparator's operating time also increases; since it can only output one bit of binary code at a time, it is difficult to meet the quantization requirements of high-speed ADCs.

[0023] In another type of analog-to-digital converter (ADC), the ADC includes a comparator, a positive capacitor, and a negative capacitor. The comparator includes a positive input terminal, a negative input terminal, and an output terminal. The positive capacitor includes an upper plate and a lower plate, and the negative capacitor includes an upper plate and a lower plate. The lower plate of the negative capacitor is used to quantize the offset voltage of the ADC to obtain a quantization result. The quantization result is the voltage adjustment value of the lower plate of the negative capacitor when the voltage difference between the positive and negative input terminals approaches the compensation voltage. The quantization result is used to adjust the voltage of the lower plate of the negative capacitor to eliminate the offset voltage, thereby reducing the working complexity of the analog circuit and timing control circuit during ADC offset calibration.

[0024] However, the offset voltage is quantized and stored on a capacitor before the analog-to-digital converter (ADC) operates; meanwhile, the comparator is not operational during the ADC sampling period, failing to fully utilize this time for comparator offset calibration. Therefore, it is difficult to meet the offset calibration requirements of high-speed ADCs.

[0025] In this embodiment of the application, the comparator circuit module in the analog-to-digital converter is composed of three comparators connected in parallel. Each comparator includes at least a first input terminal for the input voltage and a second input terminal for the reference voltage. The first input terminal and the second input terminal are connected to the output terminal of the capacitor array and are connected to the common-mode voltage.

[0026] The three parallel comparators can generate three thermometer codes during the comparison phase, which are then converted into two binary codes simultaneously, thus improving the quantization speed compared to the existing technology that can only output one binary code at a time.

[0027] Furthermore, in this embodiment, an asynchronous clock generation module can generate a calibration signal for the comparator, and the calibration signal can be used to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to perform real-time calibration of the comparator.

[0028] Furthermore, the comparator input can be shorted during each analog-to-digital converter sampling period by controlling the disconnection and connection of the first input terminal and / or the second input terminal through the calibration signal, so as to perform offset calibration. After each calibration, the calibration voltage will continuously approach the optimal value until the offset voltage is eliminated.

[0029] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] The analog-to-digital converter provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0031] Reference Figure 1 The diagram illustrates the structure of a data converter according to an embodiment of this application. Specifically, the analog-to-digital converter 100 may include a comparator circuit module 101, an asynchronous clock generation module 102, a sample-and-hold circuit module 103, a capacitor array 104, and an encoding module 105. The comparator circuit module 101 consists of three comparators connected in parallel. Each comparator includes at least a first input terminal and a second input terminal. The first input terminal is connected to a common-mode voltage, which is a voltage portion that exists simultaneously on both input terminals, is equal in magnitude, and has the same phase. The second input terminal is connected to the capacitor array, which is a basic electronic component capable of storing charge and electrical energy.

[0032] The following is a description of each module in the analog-to-digital converter 100: The asynchronous clock generation module 102 can be used to generate a sampling signal based on the received clock signal and transmit the sampling signal to the sample-and-hold circuit module for sampling. The clock signal received by the asynchronous clock generation module 102 is a synchronization control signal that determines its sampling time and conversion rhythm. Specifically, the analog-to-digital converter can be connected to a clock, within which clock-related parameters, such as clock frequency and clock jitter, can be set. Each parameter can be set according to the actual required sampling signal. For example, the clock frequency can be determined based on the sampling frequency of the sampling signal. After the clock is turned on, a clock signal is generated and then sent to the asynchronous clock generation module of the analog-to-digital converter. After generating the clock signal, the asynchronous clock generation module can generate a sampling signal based on the clock signal and send the sampling signal to the sample-and-hold circuit module 103. The sampling signal can be used for voltage sampling within the analog-to-digital converter.

[0033] The sample-and-hold circuit module 103 can be used to sample the first input voltage and the first reference voltage of the analog-to-digital converter in response to the received sampling signal to obtain a voltage signal, wherein the first input voltage may include and ; and Given a pair of differential input signals, where, (Voltage Input Positive) indicates a positive-phase input signal. (Voltage Input Negative) indicates an inverted input signal; The first reference voltage may include and ,in, and Here are a pair of differential reference signals, where, Indicates a positive phase reference signal. This indicates the inverted reference signal.

[0034] The capacitor array 103 can be used to store the voltage signal sampled by the sample-and-hold circuit module 103 and generate the second reference voltage and input signal of the comparator circuit module; for example, the sampled voltage signal is stored in two sets of capacitor arrays. as well as Furthermore, by controlling the switching of the capacitor array, a second reference voltage and input signal for the comparator circuit module are generated, such as the clock signal CLKC-early (the clock signal of the previous round), which controls the internal... The switch generates a reference voltage signal. Meanwhile, the SAR logic controls the temperature code generated by the comparator output. The internal switch generates the comparator input signal. .

[0035] The comparator circuit module 101 can be used to generate a threshold voltage based on the second reference voltage and the common-mode voltage, and compare the threshold voltage with the input signal to generate three thermometer codes.

[0036] Specifically, taking three comparators as an example, the comparators in the comparator circuit module 101 can be connected to different reference voltages. , , This generates three different threshold voltages, and the clock signal CLKC controls the comparator to convert the input signal... These three threshold voltages are compared to generate three thermometer codes.

[0037] Specifically, the process of generating thermometer codes can include a synchronous comparison process and a thermometer code generation process: In synchronous comparison, at each valid edge of CLKC (such as the rising edge), all comparators are triggered simultaneously, comparing the input signal (VIN) at the same moment with the reference voltage assigned to them, and immediately outputting the comparison result (0 or 1).

[0038] During the thermometer code generation process, the outputs of all comparators are directly combined into a single thermometer code. Because the reference voltage is distributed in steps, the transition points of the "1" or "0" in this code directly correspond to the magnitude of the input signal. For example, the comparator outputs 1 for a reference voltage lower than the input signal, and outputs 0 for a reference voltage higher than the input signal, thus forming a code pattern like 000...111...

[0039] The encoding module 105 can be used to convert the three thermometer codes into two binary codes.

[0040] The characteristic of thermometer codes is a series of consecutive "1"s and consecutive "0"s. For example, in an 8-bit thermometer code 00011111, the position where it jumps from "0" to "1" is at the 5th bit (counting from the LSB). This jump position corresponds to the quantization range of the input voltage.

[0041] The encoder internally possesses dedicated gate logic that maps each transition position to its corresponding binary number. That is, the encoder can store the mapping relationship between voltage range, thermometer code, transition position, and binary code. After determining the thermometer code, a matching mapping relationship can be looked up in the mapping table to determine the corresponding binary code. For example, a thermometer code of 0000000 corresponds to a binary code of 000; 0000001 corresponds to a binary code of 001.

[0042] In one embodiment of this application, the analog-to-digital converter further includes a digital control module, which is used to perform quantization based on the binary code to obtain a quantization result.

[0043] In practical applications, the output binary codes can be concatenated to obtain the final output quantization result DIGOUT<7:0> of the digital-to-analog converter.

[0044] One quantization process in this application embodiment includes the following steps: (1) The total number of levels is determined based on the number of bits (n) of the binary code. The total number of levels = 2^n. For example, a 3-bit binary code has 2^3 = 8 levels, corresponding to 0 to 7.

[0045] (2) Define the reference voltage range (V_ref): Determine the reference voltage of the ADC, usually expressed as V_REF- to V_REF+. This range is the "scale" of the entire quantization.

[0046] (3) Calculate the quantization step size (LSB): LSB (Least Significant Bit) is the smallest voltage increment that the ADC can distinguish, which is the voltage difference between two adjacent code values.

[0047] The calculation formula is: LSB = (V_REF+ - V_REF-) / 2^n.

[0048] (4) Perform final mapping: Convert the binary code to a decimal number (D), and then substitute it into the following formula to calculate the corresponding quantized voltage value. Quantized voltage value = V_REF- + D×LSB.

[0049] Reference Figure 2 The diagram illustrates an architecture and timing diagram of a one-step two-bit successive approximation analog-to-digital converter (ADC) according to an embodiment of this application. The one-step two-bit successive approximation ADC consists of three comparators connected in parallel.

[0050] Input clock signal The sampling signal of the analog-to-digital converter is generated by the asynchronous clock generation module. This sampling signal can control the sample-and-hold circuit module at the front end of the analog-to-digital converter to control the input voltage. and and reference voltage and Sampling is performed, and the sampled voltage signals are stored in two sets of capacitor arrays. as well as superior.

[0051] The clock signal CLKC-early can control the internal... The switch generates a reference voltage signal. Meanwhile, the SAR logic (the digital control core inside the successive approximation register-type (SAR) analog-to-digital converter (ADC). It is responsible for executing the successive approximation algorithm, coordinating the internal digital-to-analog converter (DAC) and comparator to convert analog signals into digital values) controls the temperature code generated by the comparator output. The internal switch generates the comparator input signal. The four-input comparator CMP1-3 can be connected to different reference voltages. , , The system generates three different threshold voltages. The clock signal CLKC controls the comparator to compare the input signal with these three threshold voltages, ultimately generating three thermometer codes. The encoding module converts these three thermometer codes into two-bit binary codes, thus achieving the effect of the comparator generating two-bit binary codes with each comparison.

[0052] The 3-bit thermometer code OP / ON<3:1> output by the comparator is first converted into a 2-bit binary code, and then used to control... The voltage is switched to provide the input voltage for the next conversion to the comparator. This process is repeated, and the output binary code is sequentially input into the circuit. The output binary codes are concatenated to obtain the final output ADC quantization result DIGOUT<7:0>.

[0053] Specifically, the timing sequence of a one-step two-bit SAR ADC can include: sampling phase, comparison phase, and calibration phase.

[0054] During the sampling phase, When the signal is high, this sampling signal controls the sample-and-hold circuit module at the front end of the analog-to-digital converter to control the input voltage. and and reference voltage and Sampling is performed, and the sampled voltage signals are stored in two sets of capacitor arrays. as well as superior.

[0055] During the comparison phase, The voltage level is low (CLKC is high, CAL is low), and the differential input signal voltages of the three comparators are all low. The differential input reference voltage of comparator CMP1 is The differential input reference voltage of comparator CMP2 is The differential input reference voltage of comparator CMP3 is The four-input comparator CMP1-3 generates three different threshold voltages. The clock signal CLKC controls the comparator CMP1-3 to generate three thermometer codes, achieving the effect of generating two binary codes with each comparison.

[0056] During the calibration phase, When the clock signal CLKC is low, CLKC is high, and CAL is high, the inputs of the three comparators are shorted. The differential input reference voltage and signal voltage of the three comparators are both 0. The clock signal CLKC controls the comparators to perform calibration. The calibration period comparator output code OP / ON<3:1> is used to adjust the calibration voltage. This ensures that the comparator offset voltage is controlled within the target range.

[0057] In one embodiment of this application, the asynchronous clock generation module is further configured to generate a clock signal for the (N+1)th round in response to receiving the thermometer code output by the comparator circuit module after the Nth round of comparison.

[0058] In practical applications, after all comparators have completed their comparisons, an asynchronous clock CLKC (i.e., the clock signal for the (N+1)th round) is generated to control the comparators to enter the next comparison cycle, thus accelerating the signal transmission rate. The CLKC-early signal (i.e., the clock signal for the Nth round) generated by the asynchronous clock generation circuit arrives earlier than the rising edge of CLKC, thereby ensuring that the CLKC-early controlled comparator starts working before the comparator controlled by CLKC begins to operate. The voltage switching has been completed to avoid errors in the comparison results caused by incomplete establishment of the comparator input voltage.

[0059] In one embodiment of this application, the asynchronous clock generation module is further configured to generate a calibration signal for the comparator, and use the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator. In practical applications, the comparator input is short-circuited by controlling the disconnection and connection of the first and second input terminals, thereby performing calibration.

[0060] In one embodiment of this application, the calibration signal includes a first calibration signal and a second calibration signal that is inversely phase to the first calibration signal. When the asynchronous clock generation module uses the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator, it is specifically used to: use the first calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is connected to the common-mode voltage, and at the same time use the second calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is disconnected from the capacitor array.

[0061] In practical applications, the calibration signal can be set as a pair of inverted control signals, CAL and CALB, to trigger the internal calibration circuit of the chip. The first and second input terminals of the comparator can be connected to the common-mode voltage via a first switch, and connected to the capacitor array via a second switch. Specifically, the first calibration signal controls the opening or closing of the first switch, thereby controlling the connection between the comparator and the common-mode voltage; the second calibration signal controls the opening or closing of the second switch, thereby controlling the connection between the comparator and the capacitor array.

[0062] In one embodiment of this application, the operation of the analog-to-digital converter is divided into a comparison stage and a calibration stage. When the sample-and-hold circuit module is in the N+1th round of sampling, the comparator circuit module performs the Nth round of calibration.

[0063] In one embodiment of this application, during the comparison phase, the first calibration signal is at a low level and the second calibration signal is at a high level; during the calibration phase, the first calibration signal is at a high level and the second calibration signal is at a low level.

[0064] In the embodiments of this application, the one-step two-bit successive approximation analog-to-digital converter (SAR ADC) converts two bits in one comparison cycle, which improves the working speed by nearly double compared to the traditional structure. However, since the one-step two-bit SAR ADC uses three comparators, comparator offset has a significant impact on accuracy. Offset calibration technology is required to ensure that the system performance is not reduced as a result.

[0065] Reference Figure 3 This illustrates another one-step two-bit successive approximation analog-to-digital converter architecture and timing diagram in an embodiment of this application. Figure 2 The architecture is based on the addition of calibration signals CAL and CALB to control the comparator process. Specifically, the circuit structure utilizes an asynchronous clock generation circuit to receive an external input clock signal. The output code OP / ON<3:1> of the four-input comparator CMP1-3 generates an asynchronous clock CLKC after all comparators CMP1-3 have completed their comparisons. This clock controls the comparators to enter the next comparison cycle, accelerating the signal transmission rate. The CLKC-early signal generated by the asynchronous clock generation circuit switches the comparator reference voltage before the comparator operates, preparing for the next comparison cycle. After the comparator completes all comparisons, the calibration signals CAL and CALB generated by the asynchronous clock generation circuit control the switching of the comparator input terminals. The CALB signal disconnects the comparator input terminals from the DAC, while the CAL signal connects all the comparator input terminals to VCM. At this point, the comparator inputs are adjusted according to the current comparator output result. Since the calibration voltage terminals of the offset calibration module are all connected to the same VCM voltage, the comparator output voltage is only affected by the input offset voltage. The comparator is then offset calibrated.

[0066] During operation, the CALB signal is high and the CAL signal is low, at which point the differential input signal voltages of the three comparators are all... The differential input reference voltage of comparator CMP1 is The differential input reference voltage of comparator CMP2 is The differential input reference voltage of comparator CMP3 is The three comparators have three different threshold voltages, generating three thermometer codes in each operation, achieving the goal of generating a two-bit binary code in a single comparison. During the calibration phase, the CAL signal is high and the CALB signal is low. At this time, the input signal voltages of the three comparators and the reference voltage are all connected to the common-mode voltage. Above, the connections between the two CDACs and the comparator are disconnected. During this time, the sampling network can operate normally, sampling the input voltage onto the CDACs to prepare for the next conversion cycle. This technique shortens the duty cycle of the analog-to-digital converter. The offset calibration module selects the calibration cycle comparator output code OP / ON<3:1> based on the CAL signal and adjusts the calibration voltage accordingly. This ensures that the comparator offset voltage is controlled within the target range.

[0067] The timing sequence of the above one-step two-bit SAR ADC can include: sampling phase, comparison phase, and calibration phase.

[0068] During the sampling phase, the input clock signal The asynchronous clock generation module generates the analog-to-digital converter sampling signal. This signal controls the sample-and-hold circuit module at the front end of the analog-to-digital converter to control the input voltage. and and reference voltage and Sampling is performed, and the sampled voltage signals are stored in two sets of capacitor arrays. as well as superior.

[0069] During the comparison phase, CALB is low, CAL is high, and CALB is low. An improved circuit structure utilizes an asynchronous clock generator to receive an external input clock signal. The output code OP / ON<3:1> of the four-input comparator CMP1-3 generates an asynchronous clock CLKC after all comparators CMP1-3 have completed their comparisons. This clock controls the comparators to enter the next comparison cycle, accelerating the signal transmission rate. The CLKC-early signal generated by the asynchronous clock generation circuit arrives earlier than the rising edge of CLKC, ensuring that the CLKC-early controlled comparator starts operating before the CLKC-controlled comparator begins to function. Voltage switching has been completed to prevent incomplete comparator input voltage establishment, which could lead to incorrect comparison results. After the comparator completes all comparison operations, the calibration signals CAL and CALB generated by the asynchronous clock generation circuit control the comparator input switches to perform offset calibration. CLKC-early control An internal switch generates a reference voltage signal. Meanwhile, SARlogic controls the temperature code generated by the comparator output. The internal switch generates the comparator input signal. The four-input comparator CMP1-3 can be connected to different reference voltages. , , The clock signal CLKC controls the comparator to generate three different threshold voltages, producing three thermometer codes. This achieves the effect of the comparator generating two binary codes with each comparison. The comparator output code OP / ON<3:1> is input to SARLogic and passes through the encoding module to generate the final 8-bit digital code DIGOUT<7:0>.

[0070] During the calibration phase, CALB and CAL are both high, and at this time, the differential input signal voltages of the three comparators and the reference voltage are all connected to the common-mode voltage. Above, the connections between the two CDACs and the comparator are disconnected. During this time, the sampling network can operate normally, sampling the input voltage onto the CDACs to prepare for the next conversion cycle. This technique shortens the duty cycle of the analog-to-digital converter. The offset calibration module selects the calibration cycle comparator output code OP / ON<3:1> based on the CAL signal and adjusts the calibration voltage accordingly. This ensures that the comparator offset voltage is controlled within the target range.

[0071] In this embodiment of the application, a comparator circuit module consisting of three comparators connected in parallel is provided in the analog-to-digital converter. By comparing the voltage signals through the three comparators, three thermometer codes can be generated simultaneously. Then, the three thermometer codes are converted into two binary codes to improve the quantization speed of the comparator circuit and meet the quantization requirements of the high-speed analog-to-digital converter.

[0072] Meanwhile, the comparator input can be shorted during each analog-to-digital converter sampling period to perform offset calibration. After each calibration, the calibration voltage will continuously approach the optimal value until the offset voltage is eliminated. Reference Figure 4This diagram illustrates a control method for a data converter according to an embodiment of this application. The analog-to-digital converter includes a comparator circuit module, an asynchronous clock generation module, a sample-and-hold circuit module, a capacitor array, and an encoding module. The comparator circuit module consists of three comparators connected in parallel. Each comparator includes at least a first input terminal for an input voltage and a second input terminal for a reference voltage. The first and second input terminals are connected to the output terminal of the capacitor array and to a common-mode voltage. The asynchronous clock generation module generates a sampling signal based on a received clock signal and transmits the sampling signal to the sample-and-hold circuit module for sampling. The sample-and-hold circuit module samples the first input voltage and the first reference voltage of the analog-to-digital converter in response to the received sampling signal to obtain a voltage signal. The capacitor array stores the voltage signal and generates a second reference voltage and an input signal for the comparator circuit module. The comparator circuit module generates a threshold voltage based on the second reference voltage and the common-mode voltage and compares the threshold voltage with the input signal to generate three thermometer codes. The encoding module converts the three thermometer codes into two binary codes.

[0073] The control method based on this analog-to-digital converter includes the following steps: Step S401: Generate a sampling signal based on the received clock signal; In practical applications, the clock signal received by the asynchronous clock generation module 102 can be used to generate a sampling signal in response to the received clock signal.

[0074] Specifically, the analog-to-digital converter (ADC) can be connected to a clock, within which clock-related parameters, such as clock frequency and clock jitter, can be set. Each parameter can be set according to the actual sampling signal required; for example, the clock frequency can be determined based on the sampling frequency of the sampling signal. After the clock is turned on, a clock signal is generated and then sent to the asynchronous clock generation module of the ADC. After generating the clock signal, the asynchronous clock generation module can generate a sampling signal based on the clock signal and send the sampling signal to the sample-and-hold circuit module 103. The sampling signal can be used for voltage sampling within the ADC.

[0075] Step S402: In response to the received sampling signal, the first input voltage and the first reference voltage of the analog-to-digital converter are sampled to obtain a voltage signal; Within the analog-to-digital converter, the sample-and-hold circuit module 103 can sample the first input voltage and the first reference voltage of the analog-to-digital converter in response to the received sampling signal to obtain a voltage signal.

[0076] The first input voltage may include and ; and Given a pair of differential input signals, where, (Voltage Input Positive) indicates a positive-phase input signal. (Voltage Input Negative) indicates an inverted input signal; The first reference voltage may include and ,in, and Here are a pair of differential reference signals, where, Indicates a positive phase reference signal. This indicates the inverted reference signal.

[0077] Step S403: Store the voltage signal in the capacitor array, and use the capacitor array to generate the second reference voltage and input signal of the comparator circuit module; For example, the sampled voltage signal is stored in two sets of capacitor arrays. as well as Furthermore, by controlling the switching of the capacitor array, a second reference voltage and input signal for the comparator circuit module are generated, such as the clock signal CLKC-early (the clock signal of the previous round), which controls the internal... The switch generates a reference voltage signal. Meanwhile, the SAR logic controls the temperature code generated by the comparator output. The internal switch generates the comparator input signal. .

[0078] Step S404: Generate the threshold voltage of the comparator based on the second reference voltage and the common-mode voltage, and compare the threshold voltage with the input signal to generate three thermometer codes; The comparator circuit module 101 can be used to generate a threshold voltage based on the second reference voltage and the common-mode voltage, and compare the threshold voltage with the input signal to generate three thermometer codes.

[0079] Specifically, taking three comparators as an example, the comparators in the comparator circuit module 101 can be connected to different reference voltages. , , This generates three different threshold voltages, and the clock signal CLKC controls the comparator to convert the input signal... These three threshold voltages are compared to generate three thermometer codes.

[0080] Specifically, the thermometer code generation process can include a synchronous comparison process and a thermometer code generation process: In synchronous comparison, at each valid edge of CLKC (such as the rising edge), all comparators are triggered simultaneously, comparing the input signal (VIN) at the same moment with the reference voltage assigned to them, and immediately outputting the comparison result (0 or 1).

[0081] During the thermometer code generation process, the outputs of all comparators are directly combined into a single thermometer code. Because the reference voltage is distributed in steps, the transition points of the "1" or "0" in this code directly correspond to the magnitude of the input signal. For example, the comparator outputs 1 for a reference voltage lower than the input signal, and outputs 0 for a reference voltage higher than the input signal, thus forming a code pattern like 000...111...

[0082] Step S405: Convert the three thermometer codes into two binary codes.

[0083] The characteristic of thermometer codes is a series of consecutive "1"s and consecutive "0"s. For example, in an 8-bit thermometer code 00011111, the position where it jumps from "0" to "1" is at the 5th bit (counting from the LSB). This jump position corresponds to the quantization range of the input voltage.

[0084] The encoder internally possesses dedicated gate logic that maps each transition position to its corresponding binary number. That is, the encoder can store the mapping relationship between voltage range, thermometer code, transition position, and binary code. After determining the thermometer code, a matching mapping relationship can be looked up in the mapping table to determine the corresponding binary code. For example, a thermometer code of 0000000 corresponds to a binary code of 000; 0000001 corresponds to a binary code of 001.

[0085] In practical applications, after obtaining the binary code, quantization can be performed based on the binary code to obtain the quantization result.

[0086] In practical applications, the output binary codes can be concatenated to obtain the final output quantization result DIGOUT<7:0> of the digital-to-analog converter.

[0087] One quantization process in this application embodiment includes the following steps: (1) The total number of levels is determined based on the number of bits (n) of the binary code. The total number of levels = 2^n. For example, a 3-bit binary code has 2^3 = 8 levels, corresponding to 0 to 7.

[0088] (2) Define the reference voltage range (V_ref): Determine the reference voltage of the ADC, usually expressed as V_REF- to V_REF+. This range is the "scale" of the entire quantization.

[0089] (3) Calculate the quantization step size (LSB): LSB (Least Significant Bit) is the smallest voltage increment that the ADC can distinguish, which is the voltage difference between two adjacent code values.

[0090] The calculation formula is: LSB = (V_REF+ - V_REF-) / 2^n.

[0091] (4) Perform final mapping: Convert the binary code to a decimal number (D), and then substitute it into the following formula to calculate the corresponding quantized voltage value. Quantized voltage value = V_REF- + D×LSB.

[0092] In one embodiment of this application, the analog-to-digital converter can generate a calibration signal for the comparator; the calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator.

[0093] The calibration signal includes a first calibration signal and a second calibration signal that is inversely phase to the first calibration signal. When the asynchronous clock generation module uses the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator, it is specifically used for: The first calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is connected to the common-mode voltage. At the same time, the second calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is disconnected from the capacitor array.

[0094] In one embodiment of this application, a clock signal for the (N+1)th round can be generated in response to receiving the thermometer code output after the Nth round of comparison by the comparator circuit module.

[0095] The operation of the analog-to-digital converter is divided into a comparison stage and a calibration stage. When the sample-and-hold circuit module is in the N+1th round of sampling, the comparator circuit module performs the Nth round of calibration.

[0096] In a preferred embodiment, during the comparison phase, the first calibration signal is at a low level and the second calibration signal is at a high level; during the calibration phase, the first calibration signal is at a high level and the second calibration signal is at a low level.

[0097] In this embodiment of the application, a comparator circuit module consisting of three comparators connected in parallel is provided in the analog-to-digital converter. By comparing the voltage signals through the three comparators, three thermometer codes can be generated simultaneously. Then, the three thermometer codes are converted into two binary codes to improve the quantization speed of the comparator circuit and meet the quantization requirements of the high-speed analog-to-digital converter.

[0098] It should be noted that the control method for an analog-to-digital converter provided in this application can be executed by a control device for the analog-to-digital converter, or a control module within that control device for executing the control method for loading the analog-to-digital converter. This application uses the example of a control device for the analog-to-digital converter executing the control method for loading the analog-to-digital converter to illustrate the control method for the analog-to-digital converter provided in this application.

[0099] The control device for the analog-to-digital converter in this application embodiment can be a device, or a component, integrated circuit, or chip in a terminal. The device can be a mobile electronic device or a non-mobile electronic device. For example, mobile electronic devices can be mobile phones, tablets, laptops, PDAs, in-vehicle electronic devices, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc., while non-mobile electronic devices can be servers, network-attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc. This application embodiment does not impose specific limitations.

[0100] The control device for the analog-to-digital converter in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0101] The control device for the analog-to-digital converter provided in this application embodiment can achieve... Figure 4 The various processes implemented by the control device of the analog-to-digital converter in the method embodiment will not be described again here to avoid repetition.

[0102] Optionally, this application embodiment also provides an electronic device, including a processor 1010, a memory 1009, and a program or instructions stored in the memory 1009 and executable on the processor 1010. When the program or instructions are executed by the processor 1010, they implement the various processes of the above-described analog-to-digital converter control method embodiment and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0103] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0104] Figure 5 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application. The electronic device 1000 includes, but is not limited to, the following components: radio frequency unit 1001, network module 1002, audio output unit 1003, input unit 1004, sensor 1005, display unit 1006, user input unit 1007, interface unit 1008, memory 1009, and processor 1010.

[0105] The memory 1009 includes applications and an operating system; the user input unit 1007 may include a touch panel 10071 and other input devices 10072; the input unit 1004 may include an image processor 10041 and a microphone 10042; and the display unit 1006 may include a display panel 10061.

[0106] Those skilled in the art will understand that the electronic device 1000 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1010 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 5 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here. This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described control method embodiment for an analog-to-digital converter and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0107] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0108] This application embodiment also provides a chip, which includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is used to run programs or instructions to implement the various processes of the above-described control method embodiment for analog-to-digital converter, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0109] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0110] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0111] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0112] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. An analog-to-digital converter, characterized in that, The analog-to-digital converter includes a comparator circuit module, an asynchronous clock generation module, a sample-and-hold circuit module, a capacitor array, and an encoding module. The comparator circuit module consists of three comparators connected in parallel. Each comparator includes at least a first input terminal for the input voltage and a second input terminal for the reference voltage. The first and second input terminals are connected to the output terminal of the capacitor array and are also connected to the common-mode voltage. The asynchronous clock generation module is used to generate a sampling signal based on the received clock signal, and transmit the sampling signal to the sample-and-hold circuit module for sampling; The sample-and-hold circuit module is used to sample the first input voltage and the first reference voltage of the analog-to-digital converter in response to the received sampling signal to obtain a voltage signal; The capacitor array is used to store the voltage signal and generate the second reference voltage and input signal of the comparator circuit module; The comparator circuit module is used to generate a threshold voltage based on the second reference voltage and the common-mode voltage, and compare the threshold voltage with the input signal to generate three thermometer codes; The encoding module is used to convert the three thermometer codes into two binary codes.

2. The analog-to-digital converter according to claim 1, characterized in that, The asynchronous clock generation module is also used to generate a clock signal for the (N+1)th round in response to receiving the thermometer code output by the comparator circuit module after the Nth round of comparison.

3. The analog-to-digital converter according to claim 1, characterized in that, The asynchronous clock generation module is also used to generate a calibration signal for the comparator, and to use the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator.

4. The analog-to-digital converter according to claim 3, characterized in that, The calibration signal includes a first calibration signal and a second calibration signal that is inversely phase to the first calibration signal. When the asynchronous clock generation module uses the calibration signal to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator, it is specifically used for: The first calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is connected to the common-mode voltage. At the same time, the second calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal so that the comparator is disconnected from the capacitor array.

5. The analog-to-digital converter according to claim 4, characterized in that, The operation of the analog-to-digital converter is divided into a comparison stage and a calibration stage. When the sample-and-hold circuit module is in the N+1th round of sampling, the comparator circuit module performs the Nth round of calibration.

6. The analog-to-digital converter according to claim 5, characterized in that, During the comparison phase, the first calibration signal is at a low level and the second calibration signal is at a high level; during the calibration phase, the first calibration signal is at a high level and the second calibration signal is at a low level.

7. The analog-to-digital converter according to any one of claims 1 to 6, characterized in that, The analog-to-digital converter also includes a digital control module, which is used to perform quantization based on the binary code to obtain the quantization result.

8. A control method for an analog-to-digital converter, characterized in that, Applied to an analog-to-digital converter as described in any one of claims 1 to 7, the method comprises: A sampling signal is generated based on the received clock signal; In response to the received sampling signal, the first input voltage and the first reference voltage of the analog-to-digital converter are sampled to obtain a voltage signal; The voltage signal is stored in the capacitor array, and the capacitor array is used to generate the second reference voltage and input signal of the comparator circuit module; The threshold voltage of the comparator is generated based on the second reference voltage and the common-mode voltage, and the threshold voltage is compared with the input signal to generate three thermometer codes. The three thermometer codes are converted into two binary codes.

9. The method according to claim 8, characterized in that, The method includes: Generate the calibration signal for the comparator; The calibration signal is used to control the disconnection and connection of the first input terminal and / or the second input terminal in the comparator circuit module to calibrate the comparator.

10. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the control method for the analog-to-digital converter as described in claim 8 or 9.

11. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the control method for the analog-to-digital converter as described in claim 8 or 9.

Images