Error testing method for dac circuit and related methods and apparatuses

Abstract

This invention discloses an error testing method and related methods and apparatus for DAC circuits. The error testing method includes: using a DAC circuit to perform digital-to-analog conversion on multiple first input codes based on a first minimum resolution to generate a first analog quantity; using an ADC circuit to perform analog-to-digital conversion on the first analog quantity based on a second minimum resolution to generate a first digital quantity; and obtaining the error of the DAC circuit based on the correspondence between the first digital quantity and the first input codes; wherein the error of the ADC circuit in converting the first analog quantity does not exceed a first threshold. This invention utilizes the characteristic that the ADC circuit and DAC circuit have different conversion accuracies in different conversion ranges. By actively adjusting the conversion ranges of the ADC circuit and DAC circuit, a relatively accurate ADC circuit is constructed to test the DAC circuit, solving the error coupling problem of traditional on-chip inter-testing schemes.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, specifically relating to an error testing method and related methods and apparatus for DAC circuits. Background Technology

[0002] Analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are the core digital-to-analog interfaces in electronic systems and System-on-Chips (SoCs), enabling bidirectional conversion between analog and digital signals. The ADC acquires external analog signals and provides the environmental data to the CPU for processing; the DAC outputs analog signals based on the digital processing results, assisting the CPU in controlling the external environment.

[0003] With the iteration of semiconductor technology, the digital processing performance of processors has been greatly improved, and the performance bottleneck of the system has gradually shifted from digital circuits to analog conversion interfaces. Process optimization mainly targets the speed-up and integration of digital logic circuits, while performance optimization of analog circuits such as ADCs and DACs is negligible.

[0004] Current CPUs, DSPs, and other processors possess high-precision digital processing capabilities, adapting to the data processing needs of sophisticated environments. However, the conversion accuracy of ADCs and DACs has improved slowly, significantly lagging behind the performance iterations of digital systems. Relying on traditional analog circuit design to achieve high-precision conversion would substantially increase hardware costs, resulting in performance limitations and high expenses.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an error testing method and related methods and apparatus for DAC circuits, which can calibrate DAC circuits with high accuracy.

[0007] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0008] An error testing method for a DAC circuit includes: using a DAC circuit to perform digital-to-analog conversion on a plurality of first input codes based on a first minimum resolution to generate a first analog quantity; using an ADC circuit to perform analog-to-digital conversion on the first analog quantity based on a second minimum resolution to generate a first digital quantity; and obtaining the error of the DAC circuit based on the correspondence between the first digital quantity and the first input codes; wherein the error of the ADC circuit in converting the first analog quantity does not exceed a first threshold.

[0009] In one or more embodiments of the present invention, the first minimum resolution is greater than the second minimum resolution; and / or, when the DAC circuit performs digital-to-analog conversion on a plurality of first input codes based on the first minimum resolution to generate a first analog quantity, at least two first input codes are included, such that when the DAC circuit switches between these two input codes, only one or a group of resistors under test in the DAC circuit are switched.

[0010] In one or more embodiments of the present invention, the DAC circuit includes a first adjustable resistor unit and an amplification unit. The first adjustable resistor unit adjusts its resistance value based on the input code. The amplification unit is connected to the first adjustable resistor unit to generate an analog signal based on the equivalent resistance value of the first adjustable resistor unit. The error of a portion of the resistors in the first adjustable resistor unit does not exceed a second threshold, while the remaining resistors are to be tested.

[0011] In one or more embodiments of the present invention, the DAC circuit includes an adjustable gain module and a digital-to-analog converter module, the adjustable gain module being used to adjust the gain of the digital-to-analog converter module; the correction method further includes: adjusting the gain of the analog-to-digital converter module through the adjustable gain module to adjust the minimum resolution of the DAC circuit; and / or, the DAC circuit includes a first adjustable resistor unit, an amplification unit, and a correction resistor unit, the first adjustable resistor unit adjusting its own resistance value based on the input code, the correction resistor unit being connected to the first adjustable resistor unit, the correction resistor unit adjusting its own resistance value based on the correction code, and the amplification unit generating an analog quantity based on the equivalent resistance values ​​of the first adjustable resistor unit and the correction resistor unit; the error testing method further includes: generating a plurality of first analog quantities by adjusting the resistance value of the correction resistor unit.

[0012] An embodiment of the present invention also provides a calibration method for a DAC circuit, the calibration method comprising: obtaining the error of the DAC circuit based on the above-described error testing method for the DAC circuit; and calibrating the DAC circuit based on the error of the DAC circuit.

[0013] In one or more embodiments of the present invention, the DAC circuit includes a first adjustable resistor unit, an amplification unit, and a correction resistor unit. The first adjustable resistor unit adjusts its resistance value based on the input code. The correction resistor unit is connected to the first adjustable resistor unit and adjusts its resistance value based on the correction code. The amplification unit generates an analog signal based on the equivalent resistance values ​​of the first adjustable resistor unit and the correction resistor unit. The correction method further includes: correcting the DAC circuit through the correction resistor unit.

[0014] An embodiment of the present invention also provides a calibration method for a system, the system including a DAC circuit and an ADC circuit, wherein multiple DAC circuits are provided, and the calibration method includes: putting at least one DAC circuit into an idle state; and calibrating the idle DAC circuit based on the above-described calibration method for DAC circuits.

[0015] An embodiment of the present invention also provides a chip screening method, the screening method comprising: calibrating a DAC circuit based on the above-described calibration method for DAC circuits; testing the calibration error of the calibrated DAC circuit; and screening DAC circuits based on the relationship between the calibration error and a threshold.

[0016] An embodiment of the present invention also provides a DAC circuit, which is applicable to the error testing method for DAC circuits described above, or to the calibration method for DAC circuits described above; and the DAC circuit includes a first adjustable resistor unit and an amplification unit, wherein the first adjustable resistor unit adjusts its own resistance value based on the input code, and the amplification unit is connected to the first adjustable resistor unit to generate an analog quantity based on the equivalent resistance value of the first adjustable resistor unit.

[0017] In one or more embodiments of the present invention, the first adjustable resistor unit includes a first resistor unit and a second resistor unit connected together. The first resistor unit adjusts the high-order bits of the DAC circuit, and the second resistor unit adjusts the low-order bits of the DAC circuit. The ratio of the area to the resistance value of a plurality of resistors in the high-order bits of the second resistor unit is greater than the ratio of the area to the resistance value of a plurality of resistors in the low-order bits of the second resistor unit. The resistance in the first resistor unit is to be tested.

[0018] In one or more embodiments of the present invention, the DAC circuit further includes a correction resistor unit connected to a first adjustable resistor unit, the correction resistor unit adjusting its own resistance value based on a correction code, and the amplification unit generating an analog signal based on the equivalent resistance values ​​of the first adjustable resistor unit and the correction resistor unit.

[0019] An embodiment of the present invention also provides a DAC circuit, which is applicable to the error testing method for DAC circuits described above, or to the calibration method for DAC circuits described above; and the DAC circuit includes an adjustable gain module and a digital-to-analog converter module, wherein the adjustable gain module is used to adjust the gain of the digital-to-analog converter module.

[0020] An embodiment of the present invention also provides a processing module, including: at least one processor; and a memory storing instructions that, when executed by the at least one processor, cause the at least one processor to perform the above-described error testing method for a DAC circuit, or to perform the above-described calibration method for a DAC circuit.

[0021] An embodiment of the present invention also provides a processing system, including a DAC circuit, an ADC circuit, and the above-described processing module.

[0022] Compared with the prior art, the error testing method and related methods and devices for DAC circuits of the present invention utilize the characteristics of different conversion accuracies of ADC circuits and DAC circuits in different conversion ranges. By actively adjusting the conversion ranges of ADC circuits and DAC circuits, a relatively accurate ADC circuit is constructed to test the DAC circuit, which solves the error coupling problem of traditional on-chip mutual testing schemes. Furthermore, it independently configures corresponding correction bits to complete targeted adjustments, thereby achieving accurate error tracing and correction. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a circuit diagram of a DAC circuit in one embodiment of the present invention.

[0025] Figure 2 This is a flowchart of a calibration method for a DAC circuit according to an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0027] The terms "coupled," "connected," or "linked" in the specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in the invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0028] In the detailed description of this specification, reference is made to the accompanying drawings, which form a part thereof, wherein like reference numerals always denote like parts, and wherein exemplary embodiments are shown by way of example that may be implemented. It should be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of this application. Therefore, the following detailed description should not be considered limiting.

[0029] The various operations in the specification may be described sequentially as multiple discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0030] For the purposes of this application, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this application, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0031] Various components and devices may be mentioned or shown in the singular form herein, but only for the convenience of discussion, and any element mentioned in the singular form may include multiple such elements as taught herein.

[0032] The description uses the phrases "in one embodiment," "in other embodiments," or "in some embodiments," each of which can refer to one or more of the same or different embodiments. Furthermore, the terms "comprising," "including," "having," etc., used in relation to embodiments of this application are synonymous.

[0033] Digital calibration technology is currently the mainstream solution for improving the accuracy of data converters. It uses digital circuits to assist in error compensation and accuracy adjustment. The core principle is to measure the converter's conversion error during the chip manufacturing process and correct the input-output correspondence accordingly. The specific calibration and on-chip mutual testing technologies for existing mainstream ADC and DAC circuits are as follows:

[0034] 1. Off-screen calibration:

[0035] High-precision ADC circuit calibration strategy: During the chip manufacturing process, an external signal generator is connected to the ADC circuit input, and a standard test voltage is applied. The full range of the ADC circuit is segmented, and corresponding adjustment bits are configured. When the measured input-output characteristics deviate from the ideal characteristics, the adjustment bits drive the adjustment array of the DAC circuit inside the ADC circuit to generate a compensation amount in the error range, offsetting the conversion error and achieving accuracy correction.

[0036] High-precision DAC circuit calibration strategy: The MCU and DSP generate digital input code values ​​for the DAC circuit. An external high-precision multimeter is used to test the DNL error corresponding to each code value, filtering and storing error data with an absolute value greater than 0.5 LSB. During normal use, the DAC circuit sums the original input code value with the compensation and adjustment code, using this sum as the actual input to the DAC circuit, thus completing digital domain error correction. This calibration process is simpler than ADC circuit calibration.

[0037] 2. On-chip ADC and DAC circuit mutual testing scheme:

[0038] This solution eliminates the need for external testing equipment. The on-chip CPU generates the input signal for the DAC circuit, and the on-chip analog output of the DAC circuit is directly connected to the on-chip input of the ADC circuit. The CPU then analyzes the ADC circuit's output data to complete accuracy testing and error determination. Its core advantage is that the high-precision analog signal is never brought out of the chip, effectively avoiding external noise interference.

[0039] The above-mentioned correction techniques inevitably have the following drawbacks.

[0040] For off-chip calibration techniques, firstly, off-chip test paths are susceptible to external environmental interference. Noise such as PCB crosstalk, power supply disturbances, power frequency fluctuations, and electromagnetic radiation can contaminate test signals, causing the measured error to include not only the converter's inherent error but also interference components from the test environment. Calibration based on this measured error data will significantly affect the calibration effect. Especially for today's high-precision data converters, when the interference components in the test environment are too large, the error introduced by the calibration process can be greater than, or even exceed, the data converter's inherent error, resulting in the accuracy of the data converter after calibration being lower than before calibration.

[0041] Secondly, the external test path is too long, requiring auxiliary circuits such as filtering, which not only increases the test time but also increases the cost of chip peripheral hardware and mass production testing.

[0042] Finally, off-chip calibration only supports one-time factory calibration. During long-term chip operation, temperature and voltage fluctuations and device aging can cause analog process parameters to drift, resulting in continuous changes in converter errors. The factory-fixed calibration code cannot adapt to dynamic errors, leading to poor long-term calibration performance.

[0043] While this approach completely avoids external noise interference, the principle behind on-chip ADC and DAC circuit mutual testing technology has inherent accuracy limitations. Both the ADC and DAC circuits have inherent errors. Because the system can only acquire the input data of the DAC circuit and the output data of the ADC circuit during error testing, the errors of the DAC and ADC circuits are coupled and difficult to distinguish, making independent calibration of the DAC and ADC circuits impossible.

[0044] Meanwhile, in typical mixed-signal systems, the ADC and DAC circuits have the same accuracy level, which limits the mutual measurement error to within ±0.5 LSB. Even if the test system can distinguish whether the error originates from the ADC or DAC circuit, the calibration accuracy remains relatively coarse and cannot meet the requirements for high-precision conversion.

[0045] To address the aforementioned problems, this invention provides an error testing method for DAC circuits, as well as related methods and apparatus.

[0046] Example 1

[0047] like Figure 1 As shown, one embodiment of the present invention provides a DAC circuit that is applicable to the error testing and correction methods for DAC circuits provided by the present invention.

[0048] Specifically, the DAC circuit includes a digital-to-analog converter module for performing digital-to-analog conversion.

[0049] In one embodiment, the digital-to-analog conversion module includes a first adjustable resistor unit 31, an amplification unit, and a correction resistor unit 32. The first adjustable resistor unit 31 adjusts its own resistance value based on the input code. The correction resistor unit 32 is connected to the first adjustable resistor unit 31 and adjusts its own resistance value based on the correction code. The amplification unit generates an analog quantity based on the equivalent resistance values ​​of the first adjustable resistor unit 31 and the correction resistor unit 32.

[0050] For example, the amplification unit includes a first amplifier OP1, the first input terminal of which is connected to a reference voltage.

[0051] The first adjustable resistor unit 31 includes a first resistor unit and a second resistor unit. The first resistor unit adjusts the high bit of the DAC circuit, and the second resistor unit adjusts the low bit of the DAC circuit.

[0052] Specifically, the first resistor unit includes multiple first resistors, the first ends of which are all connected to the second input terminal of the amplifier, and the second ends of the first resistors are selectively connected to either the first reference voltage VrefP or the second reference voltage VrefN based on the input code.

[0053] The second resistor unit includes multiple second resistors and a third resistor. The second resistors are connected in series to the second input terminal of the amplifier. One end of the third resistor is connected to the corresponding second resistor in sequence, and the other end is selectively connected to either the first reference voltage VrefP or the second reference voltage VrefN based on the input code. The resistance of the second resistor is half the resistance of the third resistor. The second and third resistors form a standard R2R resistor network.

[0054] The first resistor unit, the second resistor unit, and the amplifier constitute a segmented digital-to-analog converter module. The first resistor unit adopts a thermometer code architecture to form the higher bits of the DAC circuit, and the second resistor unit adopts an R2R code architecture to form the lower bits of the DAC circuit.

[0055] In one specific embodiment, there are 15 first resistors, namely Rt1~Rt15, 8 second resistors Ra and 8 third resistors, namely Ra1~Ra8 and Rb1~Rb8, and the DAC circuit has a high 4-bit + low 8-bit architecture, for a total of 12 bits.

[0056] For ease of explanation, the minimum resolution of the 12-bit DAC circuit with a gain of 1 will be denoted as 1. .

[0057] Preferably, the ratio of the area to the resistance value of the higher-order resistors in the second resistor unit is greater than the ratio of the area to the resistance value of the lower-order resistors in the second resistor unit. The resistors in the first resistor unit are to be tested.

[0058] Specifically, the higher-order resistors in the second resistor unit include multiple resistors connected in parallel to increase the ratio of its area to its resistance value.

[0059] The above design reduces the mismatch of these resistors by increasing the area of ​​some resistors, while avoiding increasing the area of ​​all resistors and making the chip too large overall. It is a compromise between ensuring resistor compatibility and chip area.

[0060] In the second resistor unit, resistor array mismatch in the R2R structure of the DAC circuit can lead to a large DNL (Distance-to-Limit) output. Each resistor in the R2R array has the same degree of resistance mismatch per unit area. The lower the resistor mismatch, the smaller the DNL output by the DAC circuit, which can be ignored. In one specific embodiment, the DNL caused by the mismatch of the lowest 5 bits (bits 8 to 12), specifically the second and third resistors, is negligible; the area-to-resistance ratio of these resistors can be small. However, the second and third resistors at bits 5 to 7 are connected in parallel to increase the area-to-resistance ratio, thus preventing these resistors from causing a large DNL in the first place.

[0061] Specifically: The second resistor Ra8 is implemented by connecting three 150KΩ resistors in parallel, increasing the area by nine times.

[0062] The third resistor, Rb8, is implemented by connecting two 100KΩ resistors in parallel, which increases the area by four times.

[0063] The second resistor Ra7 is implemented by connecting two 100KΩ resistors in parallel, which increases the area by four times.

[0064] The second resistor Ra6 is implemented by connecting two 100KΩ resistors in parallel, which increases the area by four times.

[0065] With the above design, only the mismatch between the 15 first resistors in the high position will affect the DNL error of the DAC circuit. These 15 first resistors are the resistors to be tested (and also the resistors to be calibrated).

[0066] like Figure 1 As shown, the correction resistor unit 32 includes a plurality of fourth resistors. The first end of the fourth resistor is connected to the end of the second resistor unit, and the second end of the fourth resistor is selectively connected to the first reference voltage VrefP or the second reference voltage VrefN based on the correction code.

[0067] The fourth resistor can be seen as an extension of the second resistor unit. By matching the resistance values ​​of the fourth resistor with those of the second and third resistors, the DAC circuit can be seen as an extension to more bits on the basis of the original 12 bits.

[0068] For example, there are four fourth resistors, designated Rc1 to Rc4, each with a resistance value four times that of the third resistor. Therefore, connecting zero fourth resistors to the first reference voltage VrefP will increase the output voltage by 0. Connecting a fourth resistor to the first reference voltage VrefP will increase the output voltage of the DAC circuit. Connecting the four fourth resistors to the first reference voltage VrefP will increase the output voltage by 1. This allows the DAC circuit to be expanded to 14 bits, thereby increasing the resolution bit depth and changing the minimum resolution.

[0069] Preferably, the maximum change in the analog quantity generated by the DAC circuit solely through the correction resistor unit 32 is greater than or equal to the minimum voltage change that can be obtained solely through the first adjustable resistor unit 31.

[0070] Using the example above, the maximum change in the analog signal generated by the DAC circuit solely through the correction resistor unit 32 is 1. This is equal to the minimum voltage change that can be obtained solely through the first adjustable resistor unit 31. Of course, this effect can also be achieved by increasing the number of fourth resistors, adjusting their resistance values, or changing their connection method.

[0071] In one embodiment, the DAC circuit may further include an adjustable gain module 20. The adjustable gain module 20 is used to adjust the gain of the digital-to-analog conversion module.

[0072] like Figure 1 As shown, the adjustable gain module 20 includes multiple fifth resistors connected between the second input terminal and the output terminal of the first amplifier OP1. The resistance value of the fifth resistors is adjustable or selectively connected between the second input terminal and the output terminal of the first amplifier OP1, thereby realizing the adjustment of the gain of the first amplifier OP1. For example, there are four fifth resistors, namely fifth resistor Rf1a, fifth resistor Rf1b, fifth resistor Rf2 and fifth resistor Rf3. The adjustable gain module also includes a first switch GSL2.

[0073] Specifically, the fifth resistor Rf1a is connected between the second input and output terminals of the first amplifier OP1. The fifth resistor Rf1b is connected between the second input and output terminals of the first amplifier OP1. The fifth resistor Rf2 and the first switch GSL1 are connected in series between the second input and output terminals of the first amplifier OP1. The fifth resistor Rf3 and the first switch GSL2 are connected in series between the second input and output terminals of the first amplifier OP1. The fifth resistor Rf1b is an adjustable resistor, and the first switches GSL1 and GSL2 are controlled by a gain selection code.

[0074] like Figure 1As shown, in one embodiment, the fifth resistor Rf1b includes multiple sixth resistors Rf1bx connected in series and a second switch connected in parallel with the sixth resistors. For example, there are five sixth resistors, Rf1b1 to Rf1b5, and four second switches, DAGE1 to DAGE4. The second switches DAGE1 to DAGE4 are connected in parallel with the sixth resistors Rf1b2 to Rf1b5. The second switches DAGE1 to DAGE4 are controlled by a gain correction control code.

[0075] By selecting the resistor connected to the feedback loop of the first amplifier OP1 and changing its equivalent resistance, the gain of the first amplifier OP1 can be adjusted, which in turn adjusts the gain of the DAC circuit. The gain of the DAC circuit determines the width of the output analog signal range and also changes the minimum resolution.

[0076] In summary, the minimum resolution when the gain of the original 12-bit DAC circuit is 1 is denoted as 1. The minimum resolution of the extended 14-bit DAC circuit with a gain of 1 is denoted as 0.25. When the gain of the DAC circuit changes, the minimum resolution mentioned above is multiplied by the gain change factor.

[0077] like Figure 1 As shown, in one embodiment, the DAC circuit may further include a correction module 10. The correction module 10 amplifies the reference voltage to generate the reference voltage required by the digital-to-analog converter module, which performs digital-to-analog conversion based on the input code and the reference voltage to generate an analog quantity.

[0078] like Figure 1 As shown, the correction module 10 includes a second amplifier OP2 and a voltage divider unit 11.

[0079] Voltage divider unit 11 is connected to the first reference voltage VrefP and the second reference voltage VrefN, and is used to divide the first reference voltage VrefP and the second reference voltage VrefN to generate the first input voltage. The first input terminal of the second amplifier OP2 is connected to the first input voltage, and the second input terminal and the output terminal of the second amplifier OP2 are connected to generate a reference voltage.

[0080] In one embodiment, the voltage divider unit 11 includes a plurality of seventh resistors and a plurality of third switches. The plurality of seventh resistors are connected between the first reference voltage VrefP and the second reference voltage VrefN. The first terminal of the third switch is connected to the first input terminal of the second amplifier OP2, and the second terminal of the third switch is connected to the corresponding seventh resistor. The third switch is controlled by an offset correction control code.

[0081] For example, there are 19 seventh resistors, namely seventh resistor Rm1, seventh resistor Rm21~Rm216, seventh resistor Rm3, and seventh resistor Rm4. Seventh resistors Rm1, Rm21~Rm216, and Rm3 are connected in series between the first reference voltage VrefP and the second reference voltage VrefN. The first end of the seventh resistor Rm4 is connected between the voltage divider resistor Rm1 and the seventh resistor Rm21, and the second end of the seventh resistor Rm4 is connected between the seventh resistor Rm216 and the seventh resistor Rm3.

[0082] There are 16 third switches, namely DAOS1 to DAOS16. One end of the third switches DAOS1 to DAOS16 is connected to the first input terminal of the second amplifier OP2, and the other end is connected to the corresponding seventh resistors Rm21 to Rm216.

[0083] It can be seen that adjusting the resistance value of the corresponding circuit through the third switch can be reflected in the adjustment of the reference voltage. Combined with the digital-to-analog conversion module, it can be seen that the change of the reference voltage can be reflected in the final generated analog quantity. By changing the magnitude of the reference voltage, the magnitude of the voltage corresponding to the range of the analog quantity can be adjusted.

[0084] It should be noted that this application only provides specific embodiments of DAC circuits used to implement error testing and correction methods. It should not be construed as meaning that only the DAC circuits described in this invention are applicable to the error testing and correction methods described in this invention. In fact, any DAC circuit applicable to the error testing and correction methods described in this invention is sufficient as long as it can implement the above methods, regardless of whether the specific circuit structure described above is used.

[0085] Existing ADC circuit products are generally compatible with the error testing and correction methods described in this application.

[0086] For example, the ADC circuit and DAC circuit applicable to this invention use the same first reference voltage and second reference voltage, and the ADC circuit is also 12-bit resolution with a minimum resolution of 1. .

[0087] In one specific embodiment, the first reference voltage VrefP is 2.5V, and the second reference voltage VrefN is 0V. The resistance values ​​of each resistor are as follows:

[0088] First resistor Rtx: 100K, Second resistor Rax: 50K, Third resistor Rbx: 100K, Fourth resistor Rc: 400K, Fifth resistor Rf1a: 100K / 8, Fifth resistor Rf1b: 100K / 8 (default single gain mode), Sixth resistor Rf1bx: 100K / 40, Fifth resistor Rf2: 100K / 1, Fifth resistor Rf3: 100K / 48, Seventh resistor Rm1: 31k, Seventh resistor Rm3: 31k, Seventh resistor Rm2x: 1k, Seventh resistor Rm4: 2+2 / / 0.33k.

[0089] The first switches GSL1 and GSL2 are used to control the gain of the DAC circuit. The second switches DAGE1 to DAGE4 are used to fine-tune the actual gain in the single-gain mode of the DAC circuit. The third switches DAOS1 to DAOS16 are used to fine-tune the reference voltage.

[0090] Example 2

[0091] like Figure 2 As shown, one embodiment of the present invention provides an error testing method and a correction method for a DAC circuit, comprising:

[0092] Step 1 uses a DAC circuit to perform digital-to-analog conversion on multiple first input codes based on a first minimum resolution to generate a first analog quantity.

[0093] Step 2 uses the first calibrated ADC circuit to perform analog-to-digital conversion on the first analog quantity based on the second minimum resolution to generate the first digital quantity.

[0094] Step 3: Based on the correspondence between the first digital quantity and the first input code, the error of the DAC circuit is obtained; then, the DAC circuit is corrected based on the error of the DAC circuit.

[0095] Specifically, the error in the conversion of the first analog quantity by the ADC circuit does not exceed a first threshold. The first threshold can be set based on simulation, experimentation, and the experience of technical personnel, with the aim of ensuring that the ADC circuit can be considered accurate at least when converting the first analog quantity, thereby guaranteeing that the first digital quantity is accurate.

[0096] To ensure that the error of the ADC circuit in converting the first analog quantity does not exceed the first threshold, a calibrated ADC circuit can be used directly.

[0097] Preferably, the error testing and correction method for the ADC circuit further includes: step 0 performing offset error correction and gain error correction on the ADC circuit and DAC circuit before performing step 1.

[0098] Specifically, the calibration method step 0 includes steps 0.1 to 0.4:

[0099] Step 0.1 Perform offset error correction on the ADC circuit.

[0100] Specifically, the ADC circuit samples and converts the second reference voltage VrefN, iterates through the offset correction control codes of the ADC circuit, records the offset correction control code value corresponding to the digital code of the converted output being 0000_0000_0000, and immediately uses this offset correction control code.

[0101] Step 0.2 Perform gain error correction on the ADC circuit.

[0102] Specifically, the ADC circuit samples and converts the first reference voltage VrefP, iterates through the gain correction control codes of the ADC circuit, records the gain correction control code value corresponding to the converted output digital code 1111_1111_1111, and immediately uses this gain correction control code.

[0103] Existing ADC circuits generally have offset error correction and gain error correction functions. Offset error correction is used to correct the deviation where the output digital code is not zero when the input voltage is zero. Gain error correction is used to correct the deviation where the slope of the actual conversion curve of the ADC circuit is inconsistent with the ideal slope. The principles of offset and gain correction in ADC circuits are existing technologies and will not be elaborated here. It should be noted that after offset and gain error correction, the zero-point offset and slope deviation of the ADC circuit can be basically eliminated. However, the inherent errors of the ADC circuit, such as linearity error (INL) and random noise, are usually difficult to completely eliminate through simple correction.

[0104] Step 0.3 Perform offset error correction on the DAC circuit.

[0105] Specifically, the calibration module 10 is adjusted to configure the reference voltage to 1 / 2 (VrefP - VrefN) (selecting the fourth VCSL1, while the other fourth switches are off). The adjustable gain module 20 is adjusted to configure the gain of the DAC circuit to 1 (selecting the first switch GSL1, while the first switch GSL2 is off).

[0106] Set the input code of the DAC circuit to 0000_0000_0000, traverse the offset correction control switches of the DAC circuit (the third switch DAOS1~DAOS16), record the offset correction control code value corresponding to the DAC circuit output being converted to 0000_0000_0000 by the ADC circuit output, and immediately use this offset correction control code every time the DAC circuit enters the unity gain mode.

[0107] Step 0.4 Perform gain error correction on the DAC circuit.

[0108] Specifically, the calibration module 10 is adjusted to configure the reference voltage to 1 / 2 (VrefP - VrefN) (selecting the fourth VCSL1, with the other fourth switches off). The adjustable gain module 20 is adjusted to configure the gain of the DAC circuit to 1 (selecting the first switch GSL1, with the first switch GSL2 off).

[0109] Set the DAC circuit input code to 1111_1111_1111, iterate through the gain correction control switches of the DAC circuit (second switches DAGE1~DAGE4), record the gain correction control code value corresponding to when the DAC circuit output is converted to 1111_1111_1111 by the ADC circuit output, and immediately use this gain correction control code every time the DAC circuit enters unity gain mode.

[0110] It is important to note that the DAC circuit gain is adjustable. The above process only corrects the offset error of the DAC circuit under unity gain. This is because only the unity gain mode is the mode used by the DAC circuit in practical applications, so it is necessary to correct the gain and offset errors in the unity gain mode. The other two gain modes are only used in the correction method, and the correction process is not sensitive to gain and offset errors, so they do not need to be corrected.

[0111] Preferably, in steps 1 to 3, the first minimum resolution is greater than the second minimum resolution.

[0112] By making the minimum resolution of the ADC circuit smaller than that of the DAC circuit, one first input code will correspond to multiple first digital values, thus achieving fine scanning of the single symbol width of the DAC circuit.

[0113] For example, the first minimum resolution is The second minimum resolution is .

[0114] Preferably, in step 1, when the DAC circuit performs digital-to-analog conversion on multiple first input codes based on the first minimum resolution to generate a first analog quantity, at least two first input codes are included, so that when the DAC circuit switches between these two input codes, only the state of one resistor to be tested (the resistor to be calibrated) in the DAC circuit is switched.

[0115] For example, it has been assumed above that the mismatch between the lower-order second and third resistors does not affect the accuracy, and the higher-order second and third resistors avoid affecting the accuracy by increasing the area. Therefore, the resistor to be tested (the resistor to be calibrated) is 15 first resistors.

[0116] To ensure that only the state of the first resistor changes during switching, the first four bits of the two first input codes can be 0111 and 1000, respectively.

[0117] At 0111, the eight first resistors are connected to the first reference voltage VrefP, and the seven first resistors are connected to the second reference voltage VrefN.

[0118] At 1000, the seven first resistors are connected to the first reference voltage VrefP, and the eight first resistors are connected to the second reference voltage VrefN.

[0119] The above text has assumed that the second and third resistors have no error influence. Therefore, the error in these two voltage measurements is only related to the mismatch of the first resistor at the point of switching.

[0120] Preferably, step 3 includes: calibrating the DAC circuit using the calibration resistor unit 32.

[0121] In steps 1 through 3, no adjustments are needed to the ADC circuit; only basic analog-to-digital conversion is required. Below, we will explain how to operate the DAC circuit:

[0122] Furthermore, the error testing and correction method also includes: adjusting the gain of the analog-to-digital conversion module through the adjustable gain module 20 to adjust the minimum resolution of the DAC circuit. In steps 1 to 3, the first minimum resolution is made greater than the second minimum resolution.

[0123] Based on the preceding description of the DAC circuit, we know that the gain factor of the first amplifier OP1, i.e., the DAC circuit, can be changed using the adjustable gain module 20. The minimum resolution at a gain of 1x is likely 1. Therefore, when the gain increases by a factor of n, the minimum resolution will also become n. For example, the gain is 4.

[0124] Furthermore, the error testing and correction method also includes generating multiple first analog quantities by adjusting the resistance value of the correction resistor unit 32.

[0125] Because the maximum change in the analog quantity generated by the DAC circuit is only through the correction resistor unit 32 (4) ), greater than or equal to the minimum voltage change that can be obtained solely through the first adjustable resistor unit 31 (4 When multiple first analog quantities are generated in conjunction with the correction resistor unit 32, the value of the first digital quantity can be easily obtained. The principle here will be explained below with reference to specific embodiments.

[0126] Below, we will use a specific example to illustrate how steps 1 to 3 of the correction method are implemented:

[0127] First, the reference voltage of the DAC circuit is set to 1 / 2 VrefP by the calibration module 10, and the DAC circuit is configured to four times gain by the adjustable gain unit (both the first switch GSL1 and the first switch GSL2 are turned off).

[0128] Next, the input of the DAC circuit is set to the first input code 1000_0000_0000, and all four third resistors are connected to the second reference voltage VrefN; the first analog output of the DAC circuit is denoted as... This voltage is converted into a first digital quantity by the ADC circuit; if the DAC circuit has no DNL error, the first analog quantity... It should be exactly 1 / 2VrefP, corresponding to the first digital value output by the ADC circuit being 1000_0000_0000. This first digital value falls exactly in the middle of the local conversion range during the DNL correction of the ADC circuit in steps 1 to 3.

[0129] Next, the input of the DAC circuit is set to the first input code 0111_1111_1111, and all four third resistors are connected to the first reference voltage VrefP; the first analog output of the DAC circuit is denoted as... This voltage is converted into a first digital quantity by the ADC circuit. Without DNL error, the first analog quantity... It should also be exactly 1 / 2Vref, corresponding to the first digital value output by the ADC circuit being 1000_0000_0000.

[0130] Next, based on the two initial digital values, the magnitude of the DNL error of the DAC circuit can be calculated, and the formula can be written as:

[0131]

[0132]

[0133] Where k represents which of the first resistors was switched during the first digital signal switching. Based on the above method, error testing and correction can be performed on all the first resistors in turn.

[0134] Since the DAC circuit has a gain of 4, this is equivalent to using a 14-bit ADC circuit to perform a DNL measurement on a 12-bit DAC circuit, with the test result accurate to ±0.125. Within.

[0135] Finally, after completing the DNL test for each first resistor carry, corrections are made for each first resistor carry based on the DNL test results:

[0136] Correction of the integer part of the measured DNL: This can be achieved by directly adding the measured DNL to the original DAC circuit input code, which then serves as the corrected input code for the DAC circuit.

[0137] Correction for the decimal part of the measured DNL: This is achieved through correction resistor unit 32. Each third resistor can be adjusted by 0.25. The output analog signal. Therefore, the DAC circuit correction result can be accurate to ±0.125. .

[0138] As can be seen from the above process, since the maximum change in the analog quantity generated by the correction resistor unit 32 in the DAC circuit is greater than or equal to the minimum voltage change that can be obtained by the first adjustable resistor unit 31 alone, two first input codes can always be found. Combined with the correction resistor unit 32, this ensures that the theoretical values ​​of the two output first analog quantities are the same. Thus, both first analog quantities can be adjusted to be close to the range already calibrated by the ADC circuit, even if the ADC circuit's calibration range is very small. Ultimately, this allows for convenient selection of the first digital quantity.

[0139] The above method leverages the different conversion accuracies of ADC and DAC circuits across different conversion ranges. It sequentially utilizes the DAC and ADC circuits within their relatively accurate or calibrated conversion ranges to generate corresponding digital and analog signals. Correction is then performed based on these accurate digital and analog signals. This solves the error coupling problem of traditional on-chip inter-testing schemes, accurately distinguishes the individual errors of the ADC and DAC circuits, and independently configures corresponding correction bits for targeted adjustments, achieving precise error tracing and correction.

[0140] The following explains some details that may exist in steps 0 to 3 of the above method:

[0141] 1. There should be no limitations on DAC circuits:

[0142] 1) DAC circuits can adopt other architecture types; they are not limited to thermometer codes and segmented structures such as R-2R. DAC circuits can be single architectures with only resistor strings, only R2R resistors, or other single architectures, or mixed architectures with multiple resistor types.

[0143] 2) The DAC circuit may not need to include the calibration resistor unit 32. The function of the calibration resistor unit 32 is to obtain a smaller minimum voltage change by expanding the resolution bits. Its core purpose is to make the minimum voltage change of the DAC circuit smaller than that of the ADC circuit. If the resolution of the DAC circuit itself is smaller than that of the ADC circuit, or if the effect of obtaining a smaller minimum voltage change can be achieved by adjusting the gain of the DAC circuit or adjusting the reference voltage of the DAC circuit, then the calibration resistor unit 32 is not needed.

[0144] 3) The DAC circuit may not need to have an adjustable gain module 20. The function of the adjustable gain module 20 is to amplify the gain so that the minimum voltage change of the DAC circuit is greater than that of the ADC circuit. Similarly, if the resolution of the DAC circuit itself is greater than that of the ADC circuit, or if a larger minimum voltage change can be achieved by adjusting the correction resistor unit 32 or the reference voltage of the DAC circuit, then the adjustable gain module 20 is not needed.

[0145] 4) The DAC circuit may not need to have a correction module 10. The function of the correction module 10 is to correct the offset error of the DAC circuit. If it is not necessary to correct the offset error of the DAC circuit, the correction module 10 may not be set or at least the voltage divider unit 11 may not be set.

[0146] 5) The base bit depth, reference voltage, and other parameters of the DAC circuit and the ADC circuit can also be different. Based on the above explanation of the principles, those skilled in the art should be able to deduce how to adaptively adjust the specific parameter settings required by the above correction method under other base bit depth, reference voltage, and other parameters of the DAC circuit and the ADC circuit.

[0147] 6) The calibration of DAC circuits is not limited to the first resistor of the higher bits; mismatch may also exist in the R2R resistor or other resistors or devices in other structures. Based on the above calibration method, the DNL error at each carry can be found step by step. By detecting the error while calibrating, the calibration of all or part of the conversion range can be gradually completed. Therefore, the above method can also be extended to other DAC circuits.

[0148] 2. Explanation of the rationale for not correcting for gain and offset errors in the DAC circuit's four-times gain mode in step 0:

[0149] First, as long as the DAC circuit is properly designed so that its output voltage falls within the range that the ADC circuit has already calibrated when configured in four-fold gain mode and under the conditions of steps 1 to 3 mentioned above, there is no need to consider the effects of gain and offset errors.

[0150] Secondly, the gain error has a very small impact on DNL measurements, which only consider the change of a single bit.

[0151] Therefore, in practical applications, there is no need to perform gain and offset error correction on other gain modes of the DAC circuit.

[0152] In summary, we have completed the DNL correction of the DAC circuit.

[0153] Example 3

[0154] Based on the same technical concept as described above, this embodiment provides a system calibration method, wherein the system includes a DAC circuit and an ADC circuit, multiple DAC circuits are provided, and the calibration method includes:

[0155] Put at least one DAC circuit into an idle state.

[0156] Based on the calibration method for DAC circuits described in Example 2, the DAC circuit in the idle state is calibrated.

[0157] The above-described calibration method allows for the sequential calibration of multiple DAC circuits, eliminating the need to wait for system idle time and ensuring that all DAC circuits on the field are in a state of "recently calibrated" at all times.

[0158] Example 4

[0159] Based on the same technical concept as described above, this embodiment provides a method for screening chips. Specifically, the screening method includes:

[0160] The DAC circuit is calibrated based on the calibration method for the DAC circuit described in Example 2.

[0161] Test the post-correction error of the DAC circuit and select DAC circuits based on the relationship between the post-correction error and the threshold.

[0162] When testing the corrected error of the DAC circuit, the relevant steps in the error testing method for the DAC circuit in the above embodiments can be repeated.

[0163] Based on the above screening method, chips that have been calibrated but whose accuracy still does not meet the requirements can be screened out and are suitable for chip mass production testing.

[0164] Example 5

[0165] Based on the same technical concept as described above, this embodiment provides a processing module, which includes at least one processor and a memory. The memory stores instructions, and when the instructions are executed by at least one processor, the at least one processor performs the error testing and / or correction method for the DAC circuit as described in Embodiment 2.

[0166] Based on the same technical concept as described above, this embodiment provides a processing module, which includes at least one processor and a memory. The memory stores instructions, and when the instructions are executed by at least one processor, the at least one processor performs the correction method for the system as described in Embodiment 3.

[0167] Based on the same technical concept as described above, this embodiment provides a processing module, which includes at least one processor and a memory. The memory stores instructions, and when the instructions are executed by at least one processor, the at least one processor performs the chip screening method as described in Embodiment 4.

[0168] Example 6

[0169] Based on the same technical concept as described above, this embodiment provides a processing system, including a DAC circuit, an ADC circuit, and the processing module described in Embodiment 5.

[0170] In one embodiment, multiple DAC circuits are provided.

[0171] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0172] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0173] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0174] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0175] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0176] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An error testing method for DAC circuits, characterized in that, The error testing method includes: A first analog quantity is generated by performing digital-to-analog conversion on multiple first input codes based on a first minimum resolution using a DAC circuit. The first digital quantity is generated by performing analog-to-digital conversion on the first analog quantity using an ADC circuit based on the second minimum resolution. Based on the correspondence between the first digital quantity and the first input code, the error of the DAC circuit is obtained; Wherein, the error of the ADC circuit in converting the first analog quantity does not exceed the first threshold.

2. The error testing method for DAC circuits according to claim 1, characterized in that, The first minimum resolution is greater than the second minimum resolution; and / or, When a DAC circuit performs digital-to-analog conversion on multiple first input codes based on a first minimum resolution to generate a first analog quantity, it includes at least two first input codes. When the DAC circuit switches between these two input codes, only one or a group of resistors under test in the DAC circuit are switched.

3. The error testing method for DAC circuits according to claim 1, characterized in that, The DAC circuit includes a first adjustable resistor unit and an amplification unit. The first adjustable resistor unit adjusts its resistance value based on the input code. The amplification unit is connected to the first adjustable resistor unit to generate an analog signal based on the equivalent resistance value of the first adjustable resistor unit. In the first adjustable resistor unit, the error of some resistors does not exceed a second threshold, and the remaining resistors are to be tested.

4. The error testing method for DAC circuits according to claim 1, characterized in that, The DAC circuit includes an adjustable gain module and a digital-to-analog converter (DAC) module. The adjustable gain module is used to adjust the gain of the DAC module. The error testing method further includes: adjusting the gain of the DAC module through the adjustable gain module to adjust the minimum resolution of the DAC circuit; and / or, The DAC circuit includes a first adjustable resistor unit, an amplification unit, and a correction resistor unit. The first adjustable resistor unit adjusts its resistance value based on the input code. The correction resistor unit is connected to the first adjustable resistor unit and adjusts its resistance value based on the correction code. The amplification unit generates an analog quantity based on the equivalent resistance values ​​of the first adjustable resistor unit and the correction resistor unit. The error testing method further includes generating multiple first analog quantities by adjusting the resistance value of the correction resistor unit.

5. A calibration method for a DAC circuit, characterized in that, The correction method includes: Based on the error testing method for DAC circuits according to any one of claims 1 to 4, the error of the DAC circuit is obtained; The DAC circuit is corrected based on its errors.

6. The calibration method for a DAC circuit according to claim 5, characterized in that, The DAC circuit includes a first adjustable resistor unit, an amplification unit, and a correction resistor unit. The first adjustable resistor unit adjusts its resistance value based on the input code. The correction resistor unit is connected to the first adjustable resistor unit and adjusts its resistance value based on the correction code. The amplification unit generates an analog signal based on the equivalent resistance values ​​of the first adjustable resistor unit and the correction resistor unit. The correction method further includes: correcting the DAC circuit using a correction resistor unit.

7. A calibration method for a system, characterized in that, The system includes a DAC circuit and an ADC circuit, wherein multiple DAC circuits are provided, and the correction method includes: To put at least one DAC circuit into an idle state; The calibration method for DAC circuits according to any one of claims 5 to 6 is used to calibrate the DAC circuit in the idle state.

8. A method for screening chips, characterized in that, The screening method includes: The DAC circuit chip is calibrated based on the calibration method for DAC circuits according to any one of claims 5 to 6. The DAC circuit chip is tested for its post-correction error, and the DAC circuit chip is selected based on the relationship between the post-correction error and the threshold.

9. A DAC circuit, characterized in that, The DAC circuit is applicable to the error testing method for a DAC circuit as described in any one of claims 1 to 4, or to the calibration method for a DAC circuit as described in any one of claims 5 to 6; and, The DAC circuit includes a first adjustable resistor unit and an amplification unit. The first adjustable resistor unit adjusts its resistance value based on the input code. The amplification unit is connected to the first adjustable resistor unit to generate an analog signal based on the equivalent resistance value of the first adjustable resistor unit.

10. The DAC circuit according to claim 9, characterized in that, The first adjustable resistor unit includes a first resistor unit and a second resistor unit connected together. The first resistor unit adjusts the high-order position of the DAC circuit, and the second resistor unit adjusts the low-order position of the DAC circuit. The ratio of the area to the resistance value of a number of resistors in the high-order position of the second resistor unit is greater than the ratio of the area to the resistance value of a number of resistors in the low-order position of the second resistor unit. The resistance in the first resistor unit is to be tested.

11. The DAC circuit according to claim 9, characterized in that, The DAC circuit also includes a correction resistor unit connected to a first adjustable resistor unit. The correction resistor unit adjusts its resistance value based on a correction code. The amplification unit generates an analog signal based on the equivalent resistance values ​​of the first adjustable resistor unit and the correction resistor unit.

12. A DAC circuit, characterized in that, The DAC circuit is applicable to the error testing method for a DAC circuit as described in any one of claims 1 to 4, or to the calibration method for a DAC circuit as described in any one of claims 5 to 6; and, The DAC circuit includes an adjustable gain module and a digital-to-analog converter module, wherein the adjustable gain module is used to adjust the gain of the digital-to-analog converter module.

13. A processing module, characterized in that, include: At least one processor; as well as, The memory stores instructions that, when executed by the at least one of the processors, cause the at least one of the processors to perform the error testing method for a DAC circuit according to any one of claims 1 to 4, or the calibration method for a DAC circuit according to any one of claims 5 to 6.

14. A processing system, characterized in that, It includes a DAC circuit, an ADC circuit, and the processing module as described in claim 13.

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